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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
3 *
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
Hyok S. Choid090ddd2006-06-28 14:10:01 +01006 * hacked for non-paged-MM by Hyok S. Choi, 2003.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020e.
25 *
26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
27 */
28#include <linux/linkage.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <linux/init.h>
30#include <asm/assembler.h>
Sam Ravnborge6ae7442005-09-09 21:08:59 +020031#include <asm/asm-offsets.h>
Russell King5ec94072008-09-07 19:15:31 +010032#include <asm/hwcap.h>
Russell King74945c82006-03-16 14:44:36 +000033#include <asm/pgtable-hwdef.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include <asm/pgtable.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035#include <asm/ptrace.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
Russell King00eb0f62006-07-03 12:36:07 +010037#include "proc-macros.S"
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039/*
40 * This is the maximum size of an area which will be invalidated
41 * using the single invalidate entry instructions. Anything larger
42 * than this, and we go for the whole cache.
43 *
44 * This value should be chosen such that we choose the cheapest
45 * alternative.
46 */
47#define MAX_AREA_SIZE 32768
48
49/*
50 * The size of one data cache line.
51 */
52#define CACHE_DLINESIZE 32
53
54/*
55 * The number of data cache segments.
56 */
57#define CACHE_DSEGMENTS 16
58
59/*
60 * The number of lines in a cache segment.
61 */
62#define CACHE_DENTRIES 64
63
64/*
65 * This is the size at which it becomes more efficient to
66 * clean the whole cache, rather than using the individual
67 * cache line maintainence instructions.
68 */
69#define CACHE_DLIMIT 32768
70
71 .text
72/*
73 * cpu_arm1020e_proc_init()
74 */
75ENTRY(cpu_arm1020e_proc_init)
76 mov pc, lr
77
78/*
79 * cpu_arm1020e_proc_fin()
80 */
81ENTRY(cpu_arm1020e_proc_fin)
82 stmfd sp!, {lr}
83 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
84 msr cpsr_c, ip
85 bl arm1020e_flush_kern_cache_all
86 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
87 bic r0, r0, #0x1000 @ ...i............
88 bic r0, r0, #0x000e @ ............wca.
89 mcr p15, 0, r0, c1, c0, 0 @ disable caches
90 ldmfd sp!, {pc}
91
92/*
93 * cpu_arm1020e_reset(loc)
94 *
95 * Perform a soft reset of the system. Put the CPU into the
96 * same state as it would be if it had been reset, and branch
97 * to what would be the reset vector.
98 *
99 * loc: location to jump to for soft reset
100 */
101 .align 5
102ENTRY(cpu_arm1020e_reset)
103 mov ip, #0
104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
105 mcr p15, 0, ip, c7, c10, 4 @ drain WB
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100106#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100108#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
110 bic ip, ip, #0x000f @ ............wcam
111 bic ip, ip, #0x1100 @ ...i...s........
112 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
113 mov pc, r0
114
115/*
116 * cpu_arm1020e_do_idle()
117 */
118 .align 5
119ENTRY(cpu_arm1020e_do_idle)
120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
121 mov pc, lr
122
123/* ================================= CACHE ================================ */
124
125 .align 5
126/*
127 * flush_user_cache_all()
128 *
129 * Invalidate all cache entries in a particular address
130 * space.
131 */
132ENTRY(arm1020e_flush_user_cache_all)
133 /* FALLTHROUGH */
134/*
135 * flush_kern_cache_all()
136 *
137 * Clean and invalidate the entire cache.
138 */
139ENTRY(arm1020e_flush_kern_cache_all)
140 mov r2, #VM_EXEC
141 mov ip, #0
142__flush_whole_cache:
143#ifndef CONFIG_CPU_DCACHE_DISABLE
144 mcr p15, 0, ip, c7, c10, 4 @ drain WB
145 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
1461: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
1472: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
148 subs r3, r3, #1 << 26
149 bcs 2b @ entries 63 to 0
150 subs r1, r1, #1 << 5
151 bcs 1b @ segments 15 to 0
152#endif
153 tst r2, #VM_EXEC
154#ifndef CONFIG_CPU_ICACHE_DISABLE
155 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
156#endif
157 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
158 mov pc, lr
159
160/*
161 * flush_user_cache_range(start, end, flags)
162 *
163 * Invalidate a range of cache entries in the specified
164 * address space.
165 *
166 * - start - start address (inclusive)
167 * - end - end address (exclusive)
168 * - flags - vm_flags for this space
169 */
170ENTRY(arm1020e_flush_user_cache_range)
171 mov ip, #0
172 sub r3, r1, r0 @ calculate total size
173 cmp r3, #CACHE_DLIMIT
174 bhs __flush_whole_cache
175
176#ifndef CONFIG_CPU_DCACHE_DISABLE
1771: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
178 add r0, r0, #CACHE_DLINESIZE
179 cmp r0, r1
180 blo 1b
181#endif
182 tst r2, #VM_EXEC
183#ifndef CONFIG_CPU_ICACHE_DISABLE
184 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
185#endif
186 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
187 mov pc, lr
188
189/*
190 * coherent_kern_range(start, end)
191 *
192 * Ensure coherency between the Icache and the Dcache in the
193 * region described by start. If you have non-snooping
194 * Harvard caches, you need to implement this function.
195 *
196 * - start - virtual start address
197 * - end - virtual end address
198 */
199ENTRY(arm1020e_coherent_kern_range)
200 /* FALLTHROUGH */
201/*
202 * coherent_user_range(start, end)
203 *
204 * Ensure coherency between the Icache and the Dcache in the
205 * region described by start. If you have non-snooping
206 * Harvard caches, you need to implement this function.
207 *
208 * - start - virtual start address
209 * - end - virtual end address
210 */
211ENTRY(arm1020e_coherent_user_range)
212 mov ip, #0
213 bic r0, r0, #CACHE_DLINESIZE - 1
2141:
215#ifndef CONFIG_CPU_DCACHE_DISABLE
216 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
217#endif
218#ifndef CONFIG_CPU_ICACHE_DISABLE
219 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
220#endif
221 add r0, r0, #CACHE_DLINESIZE
222 cmp r0, r1
223 blo 1b
224 mcr p15, 0, ip, c7, c10, 4 @ drain WB
225 mov pc, lr
226
227/*
Russell King2c9b9c82009-11-26 12:56:21 +0000228 * flush_kern_dcache_area(void *addr, size_t size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229 *
230 * Ensure no D cache aliasing occurs, either with itself or
231 * the I cache
232 *
Russell King2c9b9c82009-11-26 12:56:21 +0000233 * - addr - kernel address
234 * - size - region size
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235 */
Russell King2c9b9c82009-11-26 12:56:21 +0000236ENTRY(arm1020e_flush_kern_dcache_area)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237 mov ip, #0
238#ifndef CONFIG_CPU_DCACHE_DISABLE
Russell King2c9b9c82009-11-26 12:56:21 +0000239 add r1, r0, r1
Linus Torvalds1da177e2005-04-16 15:20:36 -07002401: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
241 add r0, r0, #CACHE_DLINESIZE
242 cmp r0, r1
243 blo 1b
244#endif
245 mcr p15, 0, ip, c7, c10, 4 @ drain WB
246 mov pc, lr
247
248/*
249 * dma_inv_range(start, end)
250 *
251 * Invalidate (discard) the specified virtual address range.
252 * May not write back any entries. If 'start' or 'end'
253 * are not cache line aligned, those lines must be written
254 * back.
255 *
256 * - start - virtual start address
257 * - end - virtual end address
258 *
259 * (same as v4wb)
260 */
Russell King702b94b2009-11-26 16:24:19 +0000261arm1020e_dma_inv_range:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262 mov ip, #0
263#ifndef CONFIG_CPU_DCACHE_DISABLE
264 tst r0, #CACHE_DLINESIZE - 1
265 bic r0, r0, #CACHE_DLINESIZE - 1
266 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
267 tst r1, #CACHE_DLINESIZE - 1
268 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
2691: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
270 add r0, r0, #CACHE_DLINESIZE
271 cmp r0, r1
272 blo 1b
273#endif
274 mcr p15, 0, ip, c7, c10, 4 @ drain WB
275 mov pc, lr
276
277/*
278 * dma_clean_range(start, end)
279 *
280 * Clean the specified virtual address range.
281 *
282 * - start - virtual start address
283 * - end - virtual end address
284 *
285 * (same as v4wb)
286 */
Russell King702b94b2009-11-26 16:24:19 +0000287arm1020e_dma_clean_range:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288 mov ip, #0
289#ifndef CONFIG_CPU_DCACHE_DISABLE
290 bic r0, r0, #CACHE_DLINESIZE - 1
2911: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
292 add r0, r0, #CACHE_DLINESIZE
293 cmp r0, r1
294 blo 1b
295#endif
296 mcr p15, 0, ip, c7, c10, 4 @ drain WB
297 mov pc, lr
298
299/*
300 * dma_flush_range(start, end)
301 *
302 * Clean and invalidate the specified virtual address range.
303 *
304 * - start - virtual start address
305 * - end - virtual end address
306 */
307ENTRY(arm1020e_dma_flush_range)
308 mov ip, #0
309#ifndef CONFIG_CPU_DCACHE_DISABLE
310 bic r0, r0, #CACHE_DLINESIZE - 1
3111: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
312 add r0, r0, #CACHE_DLINESIZE
313 cmp r0, r1
314 blo 1b
315#endif
316 mcr p15, 0, ip, c7, c10, 4 @ drain WB
317 mov pc, lr
318
Russell Kinga9c91472009-11-26 16:19:58 +0000319/*
320 * dma_map_area(start, size, dir)
321 * - start - kernel virtual start address
322 * - size - size of region
323 * - dir - DMA direction
324 */
325ENTRY(arm1020e_dma_map_area)
326 add r1, r1, r0
327 cmp r2, #DMA_TO_DEVICE
328 beq arm1020e_dma_clean_range
329 bcs arm1020e_dma_inv_range
330 b arm1020e_dma_flush_range
331ENDPROC(arm1020e_dma_map_area)
332
333/*
334 * dma_unmap_area(start, size, dir)
335 * - start - kernel virtual start address
336 * - size - size of region
337 * - dir - DMA direction
338 */
339ENTRY(arm1020e_dma_unmap_area)
340 mov pc, lr
341ENDPROC(arm1020e_dma_unmap_area)
342
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343ENTRY(arm1020e_cache_fns)
344 .long arm1020e_flush_kern_cache_all
345 .long arm1020e_flush_user_cache_all
346 .long arm1020e_flush_user_cache_range
347 .long arm1020e_coherent_kern_range
348 .long arm1020e_coherent_user_range
Russell King2c9b9c82009-11-26 12:56:21 +0000349 .long arm1020e_flush_kern_dcache_area
Russell Kinga9c91472009-11-26 16:19:58 +0000350 .long arm1020e_dma_map_area
351 .long arm1020e_dma_unmap_area
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352 .long arm1020e_dma_flush_range
353
354 .align 5
355ENTRY(cpu_arm1020e_dcache_clean_area)
356#ifndef CONFIG_CPU_DCACHE_DISABLE
357 mov ip, #0
3581: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
359 add r0, r0, #CACHE_DLINESIZE
360 subs r1, r1, #CACHE_DLINESIZE
361 bhi 1b
362#endif
363 mov pc, lr
364
365/* =============================== PageTable ============================== */
366
367/*
368 * cpu_arm1020e_switch_mm(pgd)
369 *
370 * Set the translation base pointer to be as described by pgd.
371 *
372 * pgd: new page tables
373 */
374 .align 5
375ENTRY(cpu_arm1020e_switch_mm)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100376#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377#ifndef CONFIG_CPU_DCACHE_DISABLE
378 mcr p15, 0, r3, c7, c10, 4
379 mov r1, #0xF @ 16 segments
3801: mov r3, #0x3F @ 64 entries
3812: mov ip, r3, LSL #26 @ shift up entry
382 orr ip, ip, r1, LSL #5 @ shift in/up index
383 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
384 mov ip, #0
385 subs r3, r3, #1
386 cmp r3, #0
387 bge 2b @ entries 3F to 0
388 subs r1, r1, #1
389 cmp r1, #0
390 bge 1b @ segments 15 to 0
391
392#endif
393 mov r1, #0
394#ifndef CONFIG_CPU_ICACHE_DISABLE
395 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
396#endif
397 mcr p15, 0, r1, c7, c10, 4 @ drain WB
398 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
399 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100400#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401 mov pc, lr
402
403/*
404 * cpu_arm1020e_set_pte(ptep, pte)
405 *
406 * Set a PTE and flush it out
407 */
408 .align 5
Russell Kingad1ae2f2006-12-13 14:34:43 +0000409ENTRY(cpu_arm1020e_set_pte_ext)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100410#ifdef CONFIG_MMU
Russell Kingda091652008-09-06 17:19:08 +0100411 armv3_set_pte_ext
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412 mov r0, r0
413#ifndef CONFIG_CPU_DCACHE_DISABLE
414 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
415#endif
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100416#endif /* CONFIG_MMU */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417 mov pc, lr
418
419 __INIT
420
421 .type __arm1020e_setup, #function
422__arm1020e_setup:
423 mov r0, #0
424 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
425 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100426#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100428#endif
Russell King22b190862006-06-29 15:09:57 +0100429 adr r5, arm1020e_crval
430 ldmia r5, {r5, r6}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 mrc p15, 0, r0, c1, c0 @ get control register v4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432 bic r0, r0, r5
Russell King22b190862006-06-29 15:09:57 +0100433 orr r0, r0, r6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
435 orr r0, r0, #0x4000 @ .R.. .... .... ....
436#endif
437 mov pc, lr
438 .size __arm1020e_setup, . - __arm1020e_setup
439
440 /*
441 * R
442 * .RVI ZFRS BLDP WCAM
Catalin Marinasabaf48a2005-06-30 17:04:14 +0100443 * .011 1001 ..11 0101
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444 */
Russell King22b190862006-06-29 15:09:57 +0100445 .type arm1020e_crval, #object
446arm1020e_crval:
447 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448
449 __INITDATA
450
451/*
452 * Purpose : Function pointers used to access above functions - all calls
453 * come through these
454 */
455 .type arm1020e_processor_functions, #object
456arm1020e_processor_functions:
457 .word v4t_early_abort
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100458 .word legacy_pabort
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459 .word cpu_arm1020e_proc_init
460 .word cpu_arm1020e_proc_fin
461 .word cpu_arm1020e_reset
462 .word cpu_arm1020e_do_idle
463 .word cpu_arm1020e_dcache_clean_area
464 .word cpu_arm1020e_switch_mm
Russell Kingad1ae2f2006-12-13 14:34:43 +0000465 .word cpu_arm1020e_set_pte_ext
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466 .size arm1020e_processor_functions, . - arm1020e_processor_functions
467
468 .section ".rodata"
469
470 .type cpu_arch_name, #object
471cpu_arch_name:
472 .asciz "armv5te"
473 .size cpu_arch_name, . - cpu_arch_name
474
475 .type cpu_elf_name, #object
476cpu_elf_name:
477 .asciz "v5"
478 .size cpu_elf_name, . - cpu_elf_name
479
480 .type cpu_arm1020e_name, #object
481cpu_arm1020e_name:
Russell King264edb32006-06-29 15:03:09 +0100482 .asciz "ARM1020E"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483 .size cpu_arm1020e_name, . - cpu_arm1020e_name
484
485 .align
486
Ben Dooks02b7dd12005-09-20 16:35:03 +0100487 .section ".proc.info.init", #alloc, #execinstr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488
489 .type __arm1020e_proc_info,#object
490__arm1020e_proc_info:
491 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
492 .long 0xff0ffff0
493 .long PMD_TYPE_SECT | \
494 PMD_BIT4 | \
495 PMD_SECT_AP_WRITE | \
496 PMD_SECT_AP_READ
Russell King8799ee92006-06-29 18:24:21 +0100497 .long PMD_TYPE_SECT | \
498 PMD_BIT4 | \
499 PMD_SECT_AP_WRITE | \
500 PMD_SECT_AP_READ
Linus Torvalds1da177e2005-04-16 15:20:36 -0700501 b __arm1020e_setup
502 .long cpu_arch_name
503 .long cpu_elf_name
504 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
505 .long cpu_arm1020e_name
506 .long arm1020e_processor_functions
507 .long v4wbi_tlb_fns
508 .long v4wb_user_fns
509 .long arm1020e_cache_fns
510 .size __arm1020e_proc_info, . - __arm1020e_proc_info