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Quinn Jensen52c543f2007-07-09 22:06:53 +01001/*
Juergen Beisert259bcaa2008-07-05 10:02:54 +02002 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
Quinn Jensen52c543f2007-07-09 22:06:53 +010018 */
19
Paulius Zaleckasd7927e12008-11-14 11:01:39 +010020#include <linux/module.h>
Juergen Beisert259bcaa2008-07-05 10:02:54 +020021#include <linux/irq.h>
Shawn Guo544496a2012-06-13 10:55:46 +080022#include <linux/irqdomain.h>
Russell Kingfced80c2008-09-06 12:10:45 +010023#include <linux/io.h>
Shawn Guo544496a2012-06-13 10:55:46 +080024#include <linux/of.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010025#include <mach/common.h>
Paulius Zaleckasd7927e12008-11-14 11:01:39 +010026#include <asm/mach/irq.h>
Jason Liu98de0cb2011-11-03 17:31:26 +080027#include <asm/exception.h>
Sascha Hauera2449092008-12-18 11:51:57 +010028#include <mach/hardware.h>
Fabio Estevam66842942012-07-03 22:25:44 -030029#include <mach/irqs.h>
Quinn Jensen52c543f2007-07-09 22:06:53 +010030
Peter Hortoncdc3f102010-12-06 11:37:38 +000031#include "irq-common.h"
32
Sascha Hauer84c9fa42009-02-18 20:59:04 +010033#define AVIC_INTCNTL 0x00 /* int control reg */
34#define AVIC_NIMASK 0x04 /* int mask reg */
35#define AVIC_INTENNUM 0x08 /* int enable number reg */
36#define AVIC_INTDISNUM 0x0C /* int disable number reg */
37#define AVIC_INTENABLEH 0x10 /* int enable reg high */
38#define AVIC_INTENABLEL 0x14 /* int enable reg low */
39#define AVIC_INTTYPEH 0x18 /* int type reg high */
40#define AVIC_INTTYPEL 0x1C /* int type reg low */
41#define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */
42#define AVIC_NIVECSR 0x40 /* norm int vector/status */
43#define AVIC_FIVECSR 0x44 /* fast int vector/status */
44#define AVIC_INTSRCH 0x48 /* int source reg high */
45#define AVIC_INTSRCL 0x4C /* int source reg low */
46#define AVIC_INTFRCH 0x50 /* int force reg high */
47#define AVIC_INTFRCL 0x54 /* int force reg low */
48#define AVIC_NIPNDH 0x58 /* norm int pending high */
49#define AVIC_NIPNDL 0x5C /* norm int pending low */
50#define AVIC_FIPNDH 0x60 /* fast int pending high */
51#define AVIC_FIPNDL 0x64 /* fast int pending low */
52
Sascha Hauer5a24d692011-05-10 18:16:10 +020053#define AVIC_NUM_IRQS 64
54
Sascha Hauer12b8eb82009-05-25 10:50:52 +020055void __iomem *avic_base;
Shawn Guo544496a2012-06-13 10:55:46 +080056static struct irq_domain *domain;
Juergen Beisert259bcaa2008-07-05 10:02:54 +020057
Hui Wang3439a392011-09-22 17:40:08 +080058static u32 avic_saved_mask_reg[2];
59
Darius Augulis3f203012009-04-08 16:17:50 +030060#ifdef CONFIG_MXC_IRQ_PRIOR
Peter Hortoncdc3f102010-12-06 11:37:38 +000061static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
62{
Shawn Guo544496a2012-06-13 10:55:46 +080063 struct irq_data *d = irq_get_irq_data(irq);
Darius Augulis479c9012008-09-09 11:29:41 +020064 unsigned int temp;
65 unsigned int mask = 0x0F << irq % 8 * 4;
66
Shawn Guo544496a2012-06-13 10:55:46 +080067 irq = d->hwirq;
68
Sascha Hauer5a24d692011-05-10 18:16:10 +020069 if (irq >= AVIC_NUM_IRQS)
Jesper Juhla5a928c2012-02-26 23:09:40 +010070 return -EINVAL;
Darius Augulis479c9012008-09-09 11:29:41 +020071
Sascha Hauer84c9fa42009-02-18 20:59:04 +010072 temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
Darius Augulis479c9012008-09-09 11:29:41 +020073 temp &= ~mask;
74 temp |= prio & mask;
75
Sascha Hauer84c9fa42009-02-18 20:59:04 +010076 __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
Darius Augulis3f203012009-04-08 16:17:50 +030077
78 return 0;
Darius Augulis479c9012008-09-09 11:29:41 +020079}
Peter Hortoncdc3f102010-12-06 11:37:38 +000080#endif
Darius Augulis479c9012008-09-09 11:29:41 +020081
Paulius Zaleckasd7927e12008-11-14 11:01:39 +010082#ifdef CONFIG_FIQ
Peter Hortoncdc3f102010-12-06 11:37:38 +000083static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
Paulius Zaleckasd7927e12008-11-14 11:01:39 +010084{
Shawn Guo544496a2012-06-13 10:55:46 +080085 struct irq_data *d = irq_get_irq_data(irq);
Paulius Zaleckasd7927e12008-11-14 11:01:39 +010086 unsigned int irqt;
87
Shawn Guo544496a2012-06-13 10:55:46 +080088 irq = d->hwirq;
89
Sascha Hauer5a24d692011-05-10 18:16:10 +020090 if (irq >= AVIC_NUM_IRQS)
Paulius Zaleckasd7927e12008-11-14 11:01:39 +010091 return -EINVAL;
92
Sascha Hauer5a24d692011-05-10 18:16:10 +020093 if (irq < AVIC_NUM_IRQS / 2) {
Sascha Hauer84c9fa42009-02-18 20:59:04 +010094 irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
95 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
Paulius Zaleckasd7927e12008-11-14 11:01:39 +010096 } else {
Sascha Hauer5a24d692011-05-10 18:16:10 +020097 irq -= AVIC_NUM_IRQS / 2;
Sascha Hauer84c9fa42009-02-18 20:59:04 +010098 irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
99 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
Paulius Zaleckasd7927e12008-11-14 11:01:39 +0100100 }
101
102 return 0;
103}
Paulius Zaleckasd7927e12008-11-14 11:01:39 +0100104#endif /* CONFIG_FIQ */
105
Quinn Jensen52c543f2007-07-09 22:06:53 +0100106
Hui Wang3439a392011-09-22 17:40:08 +0800107static struct mxc_extra_irq avic_extra_irq = {
Peter Hortoncdc3f102010-12-06 11:37:38 +0000108#ifdef CONFIG_MXC_IRQ_PRIOR
109 .set_priority = avic_irq_set_priority,
110#endif
111#ifdef CONFIG_FIQ
112 .set_irq_fiq = avic_set_irq_fiq,
113#endif
Quinn Jensen52c543f2007-07-09 22:06:53 +0100114};
115
Hui Wang3439a392011-09-22 17:40:08 +0800116#ifdef CONFIG_PM
117static void avic_irq_suspend(struct irq_data *d)
118{
119 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
120 struct irq_chip_type *ct = gc->chip_types;
Shawn Guo544496a2012-06-13 10:55:46 +0800121 int idx = d->hwirq >> 5;
Hui Wang3439a392011-09-22 17:40:08 +0800122
123 avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
124 __raw_writel(gc->wake_active, avic_base + ct->regs.mask);
125}
126
127static void avic_irq_resume(struct irq_data *d)
128{
129 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
130 struct irq_chip_type *ct = gc->chip_types;
Shawn Guo544496a2012-06-13 10:55:46 +0800131 int idx = d->hwirq >> 5;
Hui Wang3439a392011-09-22 17:40:08 +0800132
133 __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
134}
135
136#else
137#define avic_irq_suspend NULL
138#define avic_irq_resume NULL
139#endif
140
Shawn Guo544496a2012-06-13 10:55:46 +0800141static __init void avic_init_gc(int idx, unsigned int irq_start)
Hui Wang3439a392011-09-22 17:40:08 +0800142{
143 struct irq_chip_generic *gc;
144 struct irq_chip_type *ct;
Hui Wang3439a392011-09-22 17:40:08 +0800145
146 gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
147 handle_level_irq);
148 gc->private = &avic_extra_irq;
149 gc->wake_enabled = IRQ_MSK(32);
150
151 ct = gc->chip_types;
152 ct->chip.irq_mask = irq_gc_mask_clr_bit;
153 ct->chip.irq_unmask = irq_gc_mask_set_bit;
154 ct->chip.irq_ack = irq_gc_mask_clr_bit;
155 ct->chip.irq_set_wake = irq_gc_set_wake;
156 ct->chip.irq_suspend = avic_irq_suspend;
157 ct->chip.irq_resume = avic_irq_resume;
158 ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
159 ct->regs.ack = ct->regs.mask;
160
161 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
162}
163
Sascha Hauerb6de9432011-09-20 14:28:17 +0200164asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
165{
166 u32 nivector;
167
168 do {
169 nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
170 if (nivector == 0xffff)
171 break;
172
Shawn Guo544496a2012-06-13 10:55:46 +0800173 handle_IRQ(irq_find_mapping(domain, nivector), regs);
Sascha Hauerb6de9432011-09-20 14:28:17 +0200174 } while (1);
175}
176
Robert Schwebel2c130fd2008-03-28 11:02:13 +0100177/*
Quinn Jensen52c543f2007-07-09 22:06:53 +0100178 * This function initializes the AVIC hardware and disables all the
179 * interrupts. It registers the interrupt enable and disable functions
180 * to the kernel for each interrupt source.
181 */
Sascha Hauerc5aa0ad2009-05-25 17:36:19 +0200182void __init mxc_init_irq(void __iomem *irqbase)
Quinn Jensen52c543f2007-07-09 22:06:53 +0100183{
Shawn Guo544496a2012-06-13 10:55:46 +0800184 struct device_node *np;
185 int irq_base;
Quinn Jensen52c543f2007-07-09 22:06:53 +0100186 int i;
Quinn Jensen52c543f2007-07-09 22:06:53 +0100187
Sascha Hauerc5aa0ad2009-05-25 17:36:19 +0200188 avic_base = irqbase;
Sascha Hauer84c9fa42009-02-18 20:59:04 +0100189
Quinn Jensen52c543f2007-07-09 22:06:53 +0100190 /* put the AVIC into the reset value with
191 * all interrupts disabled
192 */
Sascha Hauer84c9fa42009-02-18 20:59:04 +0100193 __raw_writel(0, avic_base + AVIC_INTCNTL);
194 __raw_writel(0x1f, avic_base + AVIC_NIMASK);
Quinn Jensen52c543f2007-07-09 22:06:53 +0100195
196 /* disable all interrupts */
Sascha Hauer84c9fa42009-02-18 20:59:04 +0100197 __raw_writel(0, avic_base + AVIC_INTENABLEH);
198 __raw_writel(0, avic_base + AVIC_INTENABLEL);
Quinn Jensen52c543f2007-07-09 22:06:53 +0100199
200 /* all IRQ no FIQ */
Sascha Hauer84c9fa42009-02-18 20:59:04 +0100201 __raw_writel(0, avic_base + AVIC_INTTYPEH);
202 __raw_writel(0, avic_base + AVIC_INTTYPEL);
Hui Wang3439a392011-09-22 17:40:08 +0800203
Shawn Guo544496a2012-06-13 10:55:46 +0800204 irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
205 WARN_ON(irq_base < 0);
206
207 np = of_find_compatible_node(NULL, NULL, "fsl,avic");
208 domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
209 &irq_domain_simple_ops, NULL);
210 WARN_ON(!domain);
211
212 for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
213 avic_init_gc(i, irq_base);
Quinn Jensen52c543f2007-07-09 22:06:53 +0100214
Darius Augulis479c9012008-09-09 11:29:41 +0200215 /* Set default priority value (0) for all IRQ's */
216 for (i = 0; i < 8; i++)
Sascha Hauer84c9fa42009-02-18 20:59:04 +0100217 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
Quinn Jensen52c543f2007-07-09 22:06:53 +0100218
Paulius Zaleckasd7927e12008-11-14 11:01:39 +0100219#ifdef CONFIG_FIQ
220 /* Initialize FIQ */
Shawn Guobc896632012-06-28 14:42:08 +0800221 init_FIQ(FIQ_START);
Paulius Zaleckasd7927e12008-11-14 11:01:39 +0100222#endif
223
Quinn Jensen52c543f2007-07-09 22:06:53 +0100224 printk(KERN_INFO "MXC IRQ initialized\n");
225}