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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/drivers/video/sstfb.c -- voodoo graphics frame buffer
3 *
4 * Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net>
5 *
6 * Created 15 Jan 2000 by Ghozlane Toumi
7 *
8 * Contributions (and many thanks) :
9 *
10 * 03/2001 James Simmons <jsimmons@infradead.org>
11 * 04/2001 Paul Mundt <lethal@chaoticdreams.org>
12 * 05/2001 Urs Ganse <ursg@uni.de>
13 * (initial work on voodoo2 port, interlace)
14 * 09/2002 Helge Deller <deller@gmx.de>
15 * (enable driver on big-endian machines (hppa), ioctl fixes)
16 * 12/2002 Helge Deller <deller@gmx.de>
17 * (port driver to new frambuffer infrastructure)
18 * 01/2003 Helge Deller <deller@gmx.de>
19 * (initial work on fb hardware acceleration for voodoo2)
20 *
21 */
22
23/*
24 * The voodoo1 has the following memory mapped address space:
25 * 0x000000 - 0x3fffff : registers (4MB)
26 * 0x400000 - 0x7fffff : linear frame buffer (4MB)
27 * 0x800000 - 0xffffff : texture memory (8MB)
28 */
29
30/*
31 * misc notes, TODOs, toASKs, and deep thoughts
32
33-TODO: at one time or another test that the mode is acceptable by the monitor
34-ASK: Can I choose different ordering for the color bitfields (rgba argb ...)
35 wich one should i use ? is there any preferred one ? It seems ARGB is
36 the one ...
37-TODO: in set_var check the validity of timings (hsync vsync)...
38-TODO: check and recheck the use of sst_wait_idle : we don't flush the fifo via
39 a nop command. so it's ok as long as the commands we pass don't go
40 through the fifo. warning: issuing a nop command seems to need pci_fifo
41-FIXME: in case of failure in the init sequence, be sure we return to a safe
42 state.
43-FIXME: 4MB boards have banked memory (FbiInit2 bits 1 & 20)
44 */
45
46/*
47 * debug info
48 * SST_DEBUG : enable debugging
49 * SST_DEBUG_REG : debug registers
50 * 0 : no debug
51 * 1 : dac calls, [un]set_bits, FbiInit
52 * 2 : insane debug level (log every register read/write)
53 * SST_DEBUG_FUNC : functions
54 * 0 : no debug
55 * 1 : function call / debug ioctl
56 * 2 : variables
57 * 3 : flood . you don't want to do that. trust me.
58 * SST_DEBUG_VAR : debug display/var structs
59 * 0 : no debug
60 * 1 : dumps display, fb_var
61 *
62 * sstfb specific ioctls:
63 * toggle vga (0x46db) : toggle vga_pass_through
64 * fill fb (0x46dc) : fills fb
65 * test disp (0x46de) : draws a test image
66 */
67
68#undef SST_DEBUG
69
70/* enable 24/32 bpp functions ? (completely untested!) */
71#undef EN_24_32_BPP
72
73/*
74 Default video mode .
75 0 800x600@60 took from glide
76 1 640x480@75 took from glide
77 2 1024x768@76 std fb.mode
78 3 640x480@60 glide default */
79#define DEFAULT_MODE 3
80
81/*
82 * Includes
83 */
84
85#include <linux/config.h>
86#include <linux/string.h>
87#include <linux/kernel.h>
88#include <linux/module.h>
89#include <linux/fb.h>
90#include <linux/pci.h>
91#include <linux/delay.h>
92#include <linux/init.h>
93#include <linux/slab.h>
94#include <asm/io.h>
95#include <asm/ioctl.h>
96#include <asm/uaccess.h>
97#include <video/sstfb.h>
98
99
100/* initialized by setup */
101
102static int vgapass; /* enable Vga passthrough cable */
103static int mem; /* mem size in MB, 0 = autodetect */
104static int clipping = 1; /* use clipping (slower, safer) */
105static int gfxclk; /* force FBI freq in Mhz . Dangerous */
106static int slowpci; /* slow PCI settings */
107
108static char *mode_option __devinitdata;
109
110enum {
111 ID_VOODOO1 = 0,
112 ID_VOODOO2 = 1,
113};
114
115#define IS_VOODOO2(par) ((par)->type == ID_VOODOO2)
116
117static struct sst_spec voodoo_spec[] __devinitdata = {
118 { .name = "Voodoo Graphics", .default_gfx_clock = 50000, .max_gfxclk = 60 },
119 { .name = "Voodoo2", .default_gfx_clock = 75000, .max_gfxclk = 85 },
120};
121
122static struct fb_var_screeninfo sstfb_default =
123#if ( DEFAULT_MODE == 0 )
124 { /* 800x600@60, 16 bpp .borowed from glide/sst1/include/sst1init.h */
125 800, 600, 800, 600, 0, 0, 16, 0,
126 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
127 0, 0, -1, -1, 0,
128 25000, 86, 41, 23, 1, 127, 4,
129 0, FB_VMODE_NONINTERLACED };
130#elif ( DEFAULT_MODE == 1 )
131 {/* 640x480@75, 16 bpp .borowed from glide/sst1/include/sst1init.h */
132 640, 480, 640, 480, 0, 0, 16, 0,
133 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
134 0, 0, -1, -1, 0,
135 31746, 118, 17, 16, 1, 63, 3,
136 0, FB_VMODE_NONINTERLACED };
137#elif ( DEFAULT_MODE == 2 )
138 { /* 1024x768@76 took from my /etc/fb.modes */
139 1024, 768, 1024, 768,0, 0, 16,0,
140 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
141 0, 0, -1, -1, 0,
142 11764, 208, 8, 36, 16, 120, 3 ,
143 0, FB_VMODE_NONINTERLACED };
144#elif ( DEFAULT_MODE == 3 )
145 { /* 640x480@60 , 16bpp glide default ?*/
146 640, 480, 640, 480, 0, 0, 16, 0,
147 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
148 0, 0, -1, -1, 0,
149 39721 , 38, 26 , 25 ,18 , 96 ,2,
150 0, FB_VMODE_NONINTERLACED };
151#elif
152 #error "Invalid DEFAULT_MODE value !"
153#endif
154
155
156/*
157 * debug functions
158 */
159
160static void sstfb_drawdebugimage(struct fb_info *info);
161static int sstfb_dump_regs(struct fb_info *info);
162
163
164#if (SST_DEBUG_REG > 0)
165static void sst_dbg_print_read_reg(u32 reg, u32 val) {
166 const char *regname;
167 switch (reg) {
168 case FBIINIT0: regname = "FbiInit0"; break;
169 case FBIINIT1: regname = "FbiInit1"; break;
170 case FBIINIT2: regname = "FbiInit2"; break;
171 case FBIINIT3: regname = "FbiInit3"; break;
172 case FBIINIT4: regname = "FbiInit4"; break;
173 case FBIINIT5: regname = "FbiInit5"; break;
174 case FBIINIT6: regname = "FbiInit6"; break;
175 default: regname = NULL; break;
176 }
177 if (regname == NULL)
178 r_ddprintk("sst_read(%#x): %#x\n", reg, val);
179 else
180 r_dprintk(" sst_read(%s): %#x\n", regname, val);
181}
182
183static void sst_dbg_print_write_reg(u32 reg, u32 val) {
184 const char *regname;
185 switch (reg) {
186 case FBIINIT0: regname = "FbiInit0"; break;
187 case FBIINIT1: regname = "FbiInit1"; break;
188 case FBIINIT2: regname = "FbiInit2"; break;
189 case FBIINIT3: regname = "FbiInit3"; break;
190 case FBIINIT4: regname = "FbiInit4"; break;
191 case FBIINIT5: regname = "FbiInit5"; break;
192 case FBIINIT6: regname = "FbiInit6"; break;
193 default: regname = NULL; break;
194 }
195 if (regname == NULL)
196 r_ddprintk("sst_write(%#x, %#x)\n", reg, val);
197 else
198 r_dprintk(" sst_write(%s, %#x)\n", regname, val);
199}
200#else /* (SST_DEBUG_REG > 0) */
201# define sst_dbg_print_read_reg(reg, val) do {} while(0)
202# define sst_dbg_print_write_reg(reg, val) do {} while(0)
203#endif /* (SST_DEBUG_REG > 0) */
204
205/*
206 * hardware access functions
207 */
208
209/* register access */
210#define sst_read(reg) __sst_read(par->mmio_vbase, reg)
211#define sst_write(reg,val) __sst_write(par->mmio_vbase, reg, val)
212#define sst_set_bits(reg,val) __sst_set_bits(par->mmio_vbase, reg, val)
213#define sst_unset_bits(reg,val) __sst_unset_bits(par->mmio_vbase, reg, val)
214#define sst_dac_read(reg) __sst_dac_read(par->mmio_vbase, reg)
215#define sst_dac_write(reg,val) __sst_dac_write(par->mmio_vbase, reg, val)
216#define dac_i_read(reg) __dac_i_read(par->mmio_vbase, reg)
217#define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val)
218
219static inline u32 __sst_read(u8 __iomem *vbase, u32 reg)
220{
221 u32 ret = readl(vbase + reg);
222 sst_dbg_print_read_reg(reg, ret);
223 return ret;
224}
225
226static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val)
227{
228 sst_dbg_print_write_reg(reg, val);
229 writel(val, vbase + reg);
230}
231
232static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val)
233{
234 r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val);
235 __sst_write(vbase, reg, __sst_read(vbase, reg) | val);
236}
237
238static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val)
239{
240 r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val);
241 __sst_write(vbase, reg, __sst_read(vbase, reg) & ~val);
242}
243
244/*
245 * wait for the fbi chip. ASK: what happens if the fbi is stuck ?
246 *
247 * the FBI is supposed to be ready if we receive 5 time
248 * in a row a "idle" answer to our requests
249 */
250
251#define sst_wait_idle() __sst_wait_idle(par->mmio_vbase)
252
253static int __sst_wait_idle(u8 __iomem *vbase)
254{
255 int count = 0;
256
257 /* if (doFBINOP) __sst_write(vbase, NOPCMD, 0); */
258
259 while(1) {
260 if (__sst_read(vbase, STATUS) & STATUS_FBI_BUSY) {
261 f_dddprintk("status: busy\n");
262/* FIXME basicaly, this is a busy wait. maybe not that good. oh well;
263 * this is a small loop after all.
264 * Or maybe we should use mdelay() or udelay() here instead ? */
265 count = 0;
266 } else {
267 count++;
268 f_dddprintk("status: idle(%d)\n", count);
269 }
270 if (count >= 5) return 1;
271/* XXX do something to avoid hanging the machine if the voodoo is out */
272 }
273}
274
275
276/* dac access */
277/* dac_read should be remaped to FbiInit2 (via the pci reg init_enable) */
278static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg)
279{
280 u8 ret;
281
282 reg &= 0x07;
283 __sst_write(vbase, DAC_DATA, ((u32)reg << 8) | DAC_READ_CMD );
284 __sst_wait_idle(vbase);
285 /* udelay(10); */
286 ret = __sst_read(vbase, DAC_READ) & 0xff;
287 r_dprintk("sst_dac_read(%#x): %#x\n", reg, ret);
288
289 return ret;
290}
291
292static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val)
293{
294 r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val);
295 reg &= 0x07;
296 __sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val);
297}
298
299/* indexed access to ti/att dacs */
300static u32 __dac_i_read(u8 __iomem *vbase, u8 reg)
301{
302 u32 ret;
303
304 __sst_dac_write(vbase, DACREG_ADDR_I, reg);
305 ret = __sst_dac_read(vbase, DACREG_DATA_I);
306 r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret);
307 return ret;
308}
309static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val)
310{
311 r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val);
312 __sst_dac_write(vbase, DACREG_ADDR_I, reg);
313 __sst_dac_write(vbase, DACREG_DATA_I, val);
314}
315
316/* compute the m,n,p , returns the real freq
317 * (ics datasheet : N <-> N1 , P <-> N2)
318 *
319 * Fout= Fref * (M+2)/( 2^P * (N+2))
320 * we try to get close to the asked freq
321 * with P as high, and M as low as possible
322 * range:
323 * ti/att : 0 <= M <= 255; 0 <= P <= 3; 0<= N <= 63
324 * ics : 1 <= M <= 127; 0 <= P <= 3; 1<= N <= 31
325 * we'll use the lowest limitation, should be precise enouth
326 */
327static int sst_calc_pll(const int freq, int *freq_out, struct pll_timing *t)
328{
329 int m, m2, n, p, best_err, fout;
330 int best_n = -1;
331 int best_m = -1;
332
333 best_err = freq;
334 p = 3;
335 /* f * 2^P = vco should be less than VCOmax ~ 250 MHz for ics*/
336 while (((1 << p) * freq > VCO_MAX) && (p >= 0))
337 p--;
338 if (p == -1)
339 return -EINVAL;
340 for (n = 1; n < 32; n++) {
341 /* calc 2 * m so we can round it later*/
342 m2 = (2 * freq * (1 << p) * (n + 2) ) / DAC_FREF - 4 ;
343
344 m = (m2 % 2 ) ? m2/2+1 : m2/2 ;
345 if (m >= 128)
346 break;
347 fout = (DAC_FREF * (m + 2)) / ((1 << p) * (n + 2));
348 if ((abs(fout - freq) < best_err) && (m > 0)) {
349 best_n = n;
350 best_m = m;
351 best_err = abs(fout - freq);
352 /* we get the lowest m , allowing 0.5% error in freq*/
353 if (200*best_err < freq) break;
354 }
355 }
356 if (best_n == -1) /* unlikely, but who knows ? */
357 return -EINVAL;
358 t->p = p;
359 t->n = best_n;
360 t->m = best_m;
361 *freq_out = (DAC_FREF * (t->m + 2)) / ((1 << t->p) * (t->n + 2));
362 f_ddprintk ("m: %d, n: %d, p: %d, F: %dKhz\n",
363 t->m, t->n, t->p, *freq_out);
364 return 0;
365}
366
367/*
368 * clear lfb screen
369 */
370static void sstfb_clear_screen(struct fb_info *info)
371{
372 /* clear screen */
373 fb_memset(info->screen_base, 0, info->fix.smem_len);
374}
375
376
377/**
378 * sstfb_check_var - Optional function. Validates a var passed in.
379 * @var: frame buffer variable screen structure
380 * @info: frame buffer structure that represents a single frame buffer
381 */
382static int sstfb_check_var(struct fb_var_screeninfo *var,
383 struct fb_info *info)
384{
Antonino A. Daplas72275762006-01-09 20:53:14 -0800385 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386 int hSyncOff = var->xres + var->right_margin + var->left_margin;
387 int vSyncOff = var->yres + var->lower_margin + var->upper_margin;
388 int vBackPorch = var->left_margin, yDim = var->yres;
389 int vSyncOn = var->vsync_len;
390 int tiles_in_X, real_length;
391 unsigned int freq;
392
393 if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) {
394 eprintk("Pixclock at %ld KHZ out of range\n",
395 PICOS2KHZ(var->pixclock));
396 return -EINVAL;
397 }
398 var->pixclock = KHZ2PICOS(freq);
399
400 if (var->vmode & FB_VMODE_INTERLACED)
401 vBackPorch += (vBackPorch % 2);
402 if (var->vmode & FB_VMODE_DOUBLE) {
403 vBackPorch <<= 1;
404 yDim <<=1;
405 vSyncOn <<=1;
406 vSyncOff <<=1;
407 }
408
409 switch (var->bits_per_pixel) {
410 case 0 ... 16 :
411 var->bits_per_pixel = 16;
412 break;
413#ifdef EN_24_32_BPP
414 case 17 ... 24 :
415 var->bits_per_pixel = 24;
416 break;
417 case 25 ... 32 :
418 var->bits_per_pixel = 32;
419 break;
420#endif
421 default :
422 eprintk("Unsupported bpp %d\n", var->bits_per_pixel);
423 return -EINVAL;
424 }
425
426 /* validity tests */
427 if ((var->xres <= 1) || (yDim <= 0 )
428 || (var->hsync_len <= 1)
429 || (hSyncOff <= 1)
430 || (var->left_margin <= 2)
431 || (vSyncOn <= 0)
432 || (vSyncOff <= 0)
433 || (vBackPorch <= 0)) {
434 return -EINVAL;
435 }
436
437 if (IS_VOODOO2(par)) {
438 /* Voodoo 2 limits */
439 tiles_in_X = (var->xres + 63 ) / 64 * 2;
440
441 if (((var->xres - 1) >= POW2(11)) || (yDim >= POW2(11))) {
442 eprintk("Unsupported resolution %dx%d\n",
443 var->xres, var->yres);
444 return -EINVAL;
445 }
446
447 if (((var->hsync_len-1) >= POW2(9))
448 || ((hSyncOff-1) >= POW2(11))
449 || ((var->left_margin - 2) >= POW2(9))
450 || (vSyncOn >= POW2(13))
451 || (vSyncOff >= POW2(13))
452 || (vBackPorch >= POW2(9))
453 || (tiles_in_X >= POW2(6))
454 || (tiles_in_X <= 0)) {
455 eprintk("Unsupported Timings\n");
456 return -EINVAL;
457 }
458 } else {
459 /* Voodoo limits */
460 tiles_in_X = (var->xres + 63 ) / 64;
461
462 if (var->vmode) {
463 eprintk("Interlace/Doublescan not supported %#x\n",
464 var->vmode);
465 return -EINVAL;
466 }
467 if (((var->xres - 1) >= POW2(10)) || (var->yres >= POW2(10))) {
468 eprintk("Unsupported resolution %dx%d\n",
469 var->xres, var->yres);
470 return -EINVAL;
471 }
472 if (((var->hsync_len - 1) >= POW2(8))
473 || ((hSyncOff-1) >= POW2(10))
474 || ((var->left_margin - 2) >= POW2(8))
475 || (vSyncOn >= POW2(12))
476 || (vSyncOff >= POW2(12))
477 || (vBackPorch >= POW2(8))
478 || (tiles_in_X >= POW2(4))
479 || (tiles_in_X <= 0)) {
480 eprintk("Unsupported Timings\n");
481 return -EINVAL;
482 }
483 }
484
485 /* it seems that the fbi uses tiles of 64x16 pixels to "map" the mem */
486 /* FIXME: i don't like this... looks wrong */
487 real_length = tiles_in_X * (IS_VOODOO2(par) ? 32 : 64 )
488 * ((var->bits_per_pixel == 16) ? 2 : 4);
489
490 if ((real_length * yDim) > info->fix.smem_len) {
491 eprintk("Not enough video memory\n");
492 return -ENOMEM;
493 }
494
495 var->sync &= (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT);
496 var->vmode &= (FB_VMODE_INTERLACED | FB_VMODE_DOUBLE);
497 var->xoffset = 0;
498 var->yoffset = 0;
499 var->height = -1;
500 var->width = -1;
501
502 /*
503 * correct the color bit fields
504 */
505 /* var->{red|green|blue}.msb_right = 0; */
506
507 switch (var->bits_per_pixel) {
508 case 16: /* RGB 565 LfbMode 0 */
509 var->red.length = 5;
510 var->green.length = 6;
511 var->blue.length = 5;
512 var->transp.length = 0;
513
514 var->red.offset = 11;
515 var->green.offset = 5;
516 var->blue.offset = 0;
517 var->transp.offset = 0;
518 break;
519#ifdef EN_24_32_BPP
520 case 24: /* RGB 888 LfbMode 4 */
521 case 32: /* ARGB 8888 LfbMode 5 */
522 var->red.length = 8;
523 var->green.length = 8;
524 var->blue.length = 8;
525 var->transp.length = 0;
526
527 var->red.offset = 16;
528 var->green.offset = 8;
529 var->blue.offset = 0;
530 var->transp.offset = 0; /* in 24bpp we fake a 32 bpp mode */
531 break;
532#endif
533 default:
534 return -EINVAL;
535 }
536 return 0;
537}
538
539/**
540 * sstfb_set_par - Optional function. Alters the hardware state.
541 * @info: frame buffer structure that represents a single frame buffer
542 */
543static int sstfb_set_par(struct fb_info *info)
544{
Antonino A. Daplas72275762006-01-09 20:53:14 -0800545 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700546 u32 lfbmode, fbiinit1, fbiinit2, fbiinit3, fbiinit5, fbiinit6=0;
547 struct pci_dev *sst_dev = par->dev;
548 unsigned int freq;
549 int ntiles;
550
551 par->hSyncOff = info->var.xres + info->var.right_margin + info->var.left_margin;
552
553 par->yDim = info->var.yres;
554 par->vSyncOn = info->var.vsync_len;
555 par->vSyncOff = info->var.yres + info->var.lower_margin + info->var.upper_margin;
556 par->vBackPorch = info->var.upper_margin;
557
558 /* We need par->pll */
559 sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll);
560
561 if (info->var.vmode & FB_VMODE_INTERLACED)
562 par->vBackPorch += (par->vBackPorch % 2);
563 if (info->var.vmode & FB_VMODE_DOUBLE) {
564 par->vBackPorch <<= 1;
565 par->yDim <<=1;
566 par->vSyncOn <<=1;
567 par->vSyncOff <<=1;
568 }
569
570 if (IS_VOODOO2(par)) {
571 /* voodoo2 has 32 pixel wide tiles , BUT stange things
572 happen with odd number of tiles */
573 par->tiles_in_X = (info->var.xres + 63 ) / 64 * 2;
574 } else {
575 /* voodoo1 has 64 pixels wide tiles. */
576 par->tiles_in_X = (info->var.xres + 63 ) / 64;
577 }
578
579 f_ddprintk("hsync_len hSyncOff vsync_len vSyncOff\n");
580 f_ddprintk("%-7d %-8d %-7d %-8d\n",
581 info->var.hsync_len, par->hSyncOff,
582 par->vSyncOn, par->vSyncOff);
583 f_ddprintk("left_margin upper_margin xres yres Freq\n");
584 f_ddprintk("%-10d %-10d %-4d %-4d %-8ld\n",
585 info->var.left_margin, info->var.upper_margin,
586 info->var.xres, info->var.yres, PICOS2KHZ(info->var.pixclock));
587
588 sst_write(NOPCMD, 0);
589 sst_wait_idle();
590 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
591 sst_set_bits(FBIINIT1, VIDEO_RESET);
592 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
593 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
594 sst_wait_idle();
595
596 /*sst_unset_bits (FBIINIT0, FBI_RESET); / reenable FBI ? */
597
598 sst_write(BACKPORCH, par->vBackPorch << 16 | (info->var.left_margin - 2));
599 sst_write(VIDEODIMENSIONS, par->yDim << 16 | (info->var.xres - 1));
600 sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1));
601 sst_write(VSYNC, par->vSyncOff << 16 | par->vSyncOn);
602
603 fbiinit2 = sst_read(FBIINIT2);
604 fbiinit3 = sst_read(FBIINIT3);
605
606 /* everything is reset. we enable fbiinit2/3 remap : dac acces ok */
607 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
608 PCI_EN_INIT_WR | PCI_REMAP_DAC );
609
610 par->dac_sw.set_vidmod(info, info->var.bits_per_pixel);
611
612 /* set video clock */
613 par->dac_sw.set_pll(info, &par->pll, VID_CLOCK);
614
615 /* disable fbiinit2/3 remap */
616 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
617 PCI_EN_INIT_WR);
618
619 /* restore fbiinit2/3 */
620 sst_write(FBIINIT2,fbiinit2);
621 sst_write(FBIINIT3,fbiinit3);
622
623 fbiinit1 = (sst_read(FBIINIT1) & VIDEO_MASK)
624 | EN_DATA_OE
625 | EN_BLANK_OE
626 | EN_HVSYNC_OE
627 | EN_DCLK_OE
628 /* | (15 << TILES_IN_X_SHIFT) */
629 | SEL_INPUT_VCLK_2X
630 /* | (2 << VCLK_2X_SEL_DEL_SHIFT)
631 | (2 << VCLK_DEL_SHIFT) */;
632/* try with vclk_in_delay =0 (bits 29:30) , vclk_out_delay =0 (bits(27:28)
633 in (near) future set them accordingly to revision + resolution (cf glide)
634 first understand what it stands for :)
635 FIXME: there are some artefacts... check for the vclk_in_delay
636 lets try with 6ns delay in both vclk_out & in...
637 doh... they're still there :\
638*/
639
640 ntiles = par->tiles_in_X;
641 if (IS_VOODOO2(par)) {
642 fbiinit1 |= ((ntiles & 0x20) >> 5) << TILES_IN_X_MSB_SHIFT
643 | ((ntiles & 0x1e) >> 1) << TILES_IN_X_SHIFT;
644/* as the only value of importance for us in fbiinit6 is tiles in X (lsb),
645 and as reading fbinit 6 will return crap (see FBIINIT6_DEFAULT) we just
646 write our value. BTW due to the dac unable to read odd number of tiles, this
647 field is always null ... */
648 fbiinit6 = (ntiles & 0x1) << TILES_IN_X_LSB_SHIFT;
649 }
650 else
651 fbiinit1 |= ntiles << TILES_IN_X_SHIFT;
652
653 switch (info->var.bits_per_pixel) {
654 case 16:
655 fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL;
656 break;
657#ifdef EN_24_32_BPP
658 case 24:
659 case 32:
660 /* sst_set_bits(FBIINIT1, SEL_SOURCE_VCLK_2X_DIV2 | EN_24BPP);*/
661 fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL | EN_24BPP;
662 break;
663#endif
664 default:
665 return -EINVAL;
666 }
667 sst_write(FBIINIT1, fbiinit1);
668 if (IS_VOODOO2(par)) {
669 sst_write(FBIINIT6, fbiinit6);
670 fbiinit5=sst_read(FBIINIT5) & FBIINIT5_MASK ;
671 if (info->var.vmode & FB_VMODE_INTERLACED)
672 fbiinit5 |= INTERLACE;
673 if (info->var.vmode & FB_VMODE_DOUBLE)
674 fbiinit5 |= VDOUBLESCAN;
675 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
676 fbiinit5 |= HSYNC_HIGH;
677 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
678 fbiinit5 |= VSYNC_HIGH;
679 sst_write(FBIINIT5, fbiinit5);
680 }
681 sst_wait_idle();
682 sst_unset_bits(FBIINIT1, VIDEO_RESET);
683 sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
684 sst_set_bits(FBIINIT2, EN_DRAM_REFRESH);
685 /* disables fbiinit writes */
686 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
687
688 /* set lfbmode : set mode + front buffer for reads/writes
689 + disable pipeline */
690 switch (info->var.bits_per_pixel) {
691 case 16:
692 lfbmode = LFB_565;
693 break;
694#ifdef EN_24_32_BPP
695 case 24:
696 lfbmode = LFB_888;
697 break;
698 case 32:
699 lfbmode = LFB_8888;
700 break;
701#endif
702 default:
703 return -EINVAL;
704 }
705
706#if defined(__BIG_ENDIAN)
707 /* Enable byte-swizzle functionality in hardware.
708 * With this enabled, all our read- and write-accesses to
709 * the voodoo framebuffer can be done in native format, and
710 * the hardware will automatically convert it to little-endian.
711 * - tested on HP-PARISC, Helge Deller <deller@gmx.de> */
712 lfbmode |= ( LFB_WORD_SWIZZLE_WR | LFB_BYTE_SWIZZLE_WR |
713 LFB_WORD_SWIZZLE_RD | LFB_BYTE_SWIZZLE_RD );
714#endif
715
716 if (clipping) {
717 sst_write(LFBMODE, lfbmode | EN_PXL_PIPELINE);
718 /*
719 * Set "clipping" dimensions. If clipping is disabled and
720 * writes to offscreen areas of the framebuffer are performed,
721 * the "behaviour is undefined" (_very_ undefined) - Urs
722 */
723 /* btw, it requires enabling pixel pipeline in LFBMODE .
724 off screen read/writes will just wrap and read/print pixels
725 on screen. Ugly but not that dangerous */
726 f_ddprintk("setting clipping dimensions 0..%d, 0..%d\n",
727 info->var.xres - 1, par->yDim - 1);
728
729 sst_write(CLIP_LEFT_RIGHT, info->var.xres);
730 sst_write(CLIP_LOWY_HIGHY, par->yDim);
731 sst_set_bits(FBZMODE, EN_CLIPPING | EN_RGB_WRITE);
732 } else {
733 /* no clipping : direct access, no pipeline */
734 sst_write(LFBMODE, lfbmode);
735 }
736 return 0;
737}
738
739/**
740 * sstfb_setcolreg - Optional function. Sets a color register.
741 * @regno: hardware colormap register
742 * @red: frame buffer colormap structure
743 * @green: The green value which can be up to 16 bits wide
744 * @blue: The blue value which can be up to 16 bits wide.
745 * @transp: If supported the alpha value which can be up to 16 bits wide.
746 * @info: frame buffer info structure
747 */
748static int sstfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
749 u_int transp, struct fb_info *info)
750{
Antonino A. Daplas72275762006-01-09 20:53:14 -0800751 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752 u32 col;
753
754 f_dddprintk("sstfb_setcolreg\n");
755 f_dddprintk("%-2d rgbt: %#x, %#x, %#x, %#x\n",
756 regno, red, green, blue, transp);
Antonino A. Daplas72275762006-01-09 20:53:14 -0800757 if (regno > 15)
758 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700759
760 red >>= (16 - info->var.red.length);
761 green >>= (16 - info->var.green.length);
762 blue >>= (16 - info->var.blue.length);
763 transp >>= (16 - info->var.transp.length);
764 col = (red << info->var.red.offset)
765 | (green << info->var.green.offset)
766 | (blue << info->var.blue.offset)
767 | (transp << info->var.transp.offset);
768
Antonino A. Daplas72275762006-01-09 20:53:14 -0800769 par->palette[regno] = col;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770
771 return 0;
772}
773
774static int sstfb_ioctl(struct inode *inode, struct file *file,
775 u_int cmd, u_long arg, struct fb_info *info )
776{
Antonino A. Daplas72275762006-01-09 20:53:14 -0800777 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778 struct pci_dev *sst_dev = par->dev;
779 u32 fbiinit0, tmp, val;
780 u_long p;
781
782 switch (cmd) {
783
784 /* dump current FBIINIT values to system log */
785 case _IO('F', 0xdb): /* 0x46db */
786 return sstfb_dump_regs(info);
787
788 /* fills lfb with #arg pixels */
789 case _IOW('F', 0xdc, u32): /* 0x46dc */
790 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
791 return -EFAULT;
792 if (val > info->fix.smem_len)
793 val = info->fix.smem_len;
794 printk("filling %#x \n", val);
795 for (p=0 ; p<val; p+=2)
796 writew(p >> 6, info->screen_base + p);
797 return 0;
798
799 /* change VGA pass_through mode */
800 case _IOW('F', 0xdd, u32): /* 0x46dd */
801 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
802 return -EFAULT;
803 pci_read_config_dword(sst_dev, PCI_INIT_ENABLE, &tmp);
804 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
805 tmp | PCI_EN_INIT_WR );
806 fbiinit0 = sst_read (FBIINIT0);
807 if (val) {
808 sst_write(FBIINIT0, fbiinit0 & ~EN_VGA_PASSTHROUGH);
809 iprintk("Disabling VGA pass-through\n");
810 } else {
811 sst_write(FBIINIT0, fbiinit0 | EN_VGA_PASSTHROUGH);
812 iprintk("Enabling VGA pass-through\n");
813 }
814 pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp);
815 return 0;
816
817 /* draw test image */
818 case _IO('F', 0xde): /* 0x46de */
819 f_dprintk("test color display at %d bpp\n",
820 info->var.bits_per_pixel);
821 sstfb_drawdebugimage(info);
822 return 0;
823 }
824 return -EINVAL;
825}
826
827
828/*
829 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) - Voodoo2 only
830 */
831#if 0
832static void sstfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
833{
Antonino A. Daplas72275762006-01-09 20:53:14 -0800834 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835 u32 stride = info->fix.line_length;
836
837 if (!IS_VOODOO2(par))
838 return;
839
840 sst_write(BLTSRCBASEADDR, 0);
841 sst_write(BLTDSTBASEADDR, 0);
842 sst_write(BLTROP, BLTROP_COPY);
843 sst_write(BLTXYSTRIDES, stride | (stride << 16));
844 sst_write(BLTSRCXY, area->sx | (area->sy << 16));
845 sst_write(BLTDSTXY, area->dx | (area->dy << 16));
846 sst_write(BLTSIZE, area->width | (area->height << 16));
847 sst_write(BLTCOMMAND, BLT_SCR2SCR_BITBLT | LAUNCH_BITBLT |
848 (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) );
849 sst_wait_idle();
850}
851#endif
852
853
854/*
855 * FillRect 2D command (solidfill or invert (via ROP_XOR)) - Voodoo2 only
856 */
857static void sstfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
858{
Antonino A. Daplas72275762006-01-09 20:53:14 -0800859 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860 u32 stride = info->fix.line_length;
861
862 if (!IS_VOODOO2(par))
863 return;
864
865 sst_write(BLTCLIPX, info->var.xres);
866 sst_write(BLTCLIPY, info->var.yres);
867
868 sst_write(BLTDSTBASEADDR, 0);
869 sst_write(BLTCOLOR, rect->color);
870 sst_write(BLTROP, rect->rop == ROP_COPY ? BLTROP_COPY : BLTROP_XOR);
871 sst_write(BLTXYSTRIDES, stride | (stride << 16));
872 sst_write(BLTDSTXY, rect->dx | (rect->dy << 16));
873 sst_write(BLTSIZE, rect->width | (rect->height << 16));
874 sst_write(BLTCOMMAND, BLT_RECFILL_BITBLT | LAUNCH_BITBLT
875 | (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) | BIT(16) );
876 sst_wait_idle();
877}
878
879
880
881/*
882 * get lfb size
883 */
884static int __devinit sst_get_memsize(struct fb_info *info, __u32 *memsize)
885{
886 u8 __iomem *fbbase_virt = info->screen_base;
887
888 /* force memsize */
889 if ((mem >= 1 ) && (mem <= 4)) {
890 *memsize = (mem * 0x100000);
891 iprintk("supplied memsize: %#x\n", *memsize);
892 return 1;
893 }
894
895 writel(0xdeadbeef, fbbase_virt);
896 writel(0xdeadbeef, fbbase_virt+0x100000);
897 writel(0xdeadbeef, fbbase_virt+0x200000);
898 f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
899 readl(fbbase_virt), readl(fbbase_virt + 0x100000),
900 readl(fbbase_virt + 0x200000));
901
902 writel(0xabcdef01, fbbase_virt);
903
904 f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
905 readl(fbbase_virt), readl(fbbase_virt + 0x100000),
906 readl(fbbase_virt + 0x200000));
907
908 /* checks for 4mb lfb, then 2, then defaults to 1 */
909 if (readl(fbbase_virt + 0x200000) == 0xdeadbeef)
910 *memsize = 0x400000;
911 else if (readl(fbbase_virt + 0x100000) == 0xdeadbeef)
912 *memsize = 0x200000;
913 else
914 *memsize = 0x100000;
915 f_ddprintk("detected memsize: %dMB\n", *memsize >> 20);
916 return 1;
917}
918
919
920/*
921 * DAC detection routines
922 */
923
924/* fbi should be idle, and fifo emty and mem disabled */
925/* supposed to detect AT&T ATT20C409 and Ti TVP3409 ramdacs */
926
927static int __devinit sst_detect_att(struct fb_info *info)
928{
Antonino A. Daplas72275762006-01-09 20:53:14 -0800929 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700930 int i, mir, dir;
931
932 for (i=0; i<3; i++) {
933 sst_dac_write(DACREG_WMA, 0); /* backdoor */
934 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
935 sst_dac_read(DACREG_RMR);
936 sst_dac_read(DACREG_RMR);
937 sst_dac_read(DACREG_RMR);
938 /* the fifth time, CR0 is read */
939 sst_dac_read(DACREG_RMR);
940 /* the 6th, manufacturer id register */
941 mir = sst_dac_read(DACREG_RMR);
942 /*the 7th, device ID register */
943 dir = sst_dac_read(DACREG_RMR);
944 f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
945 if ((mir == DACREG_MIR_ATT ) && (dir == DACREG_DIR_ATT)) {
946 return 1;
947 }
948 }
949 return 0;
950}
951
952static int __devinit sst_detect_ti(struct fb_info *info)
953{
Antonino A. Daplas72275762006-01-09 20:53:14 -0800954 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955 int i, mir, dir;
956
957 for (i = 0; i<3; i++) {
958 sst_dac_write(DACREG_WMA, 0); /* backdoor */
959 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
960 sst_dac_read(DACREG_RMR);
961 sst_dac_read(DACREG_RMR);
962 sst_dac_read(DACREG_RMR);
963 /* the fifth time, CR0 is read */
964 sst_dac_read(DACREG_RMR);
965 /* the 6th, manufacturer id register */
966 mir = sst_dac_read(DACREG_RMR);
967 /*the 7th, device ID register */
968 dir = sst_dac_read(DACREG_RMR);
969 f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
970 if ((mir == DACREG_MIR_TI ) && (dir == DACREG_DIR_TI)) {
971 return 1;
972 }
973 }
974 return 0;
975}
976
977/*
978 * try to detect ICS5342 ramdac
979 * we get the 1st byte (M value) of preset f1,f7 and fB
980 * why those 3 ? mmmh... for now, i'll do it the glide way...
981 * and ask questions later. anyway, it seems that all the freq registers are
982 * realy at their default state (cf specs) so i ask again, why those 3 regs ?
983 * mmmmh.. it seems that's much more ugly than i thought. we use f0 and fA for
984 * pll programming, so in fact, we *hope* that the f1, f7 & fB won't be
985 * touched...
986 * is it realy safe ? how can i reset this ramdac ? geee...
987 */
988static int __devinit sst_detect_ics(struct fb_info *info)
989{
Antonino A. Daplas72275762006-01-09 20:53:14 -0800990 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700991 int m_clk0_1, m_clk0_7, m_clk1_b;
992 int n_clk0_1, n_clk0_7, n_clk1_b;
993 int i;
994
995 for (i = 0; i<5; i++ ) {
996 sst_dac_write(DACREG_ICS_PLLRMA, 0x1); /* f1 */
997 m_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
998 n_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
999 sst_dac_write(DACREG_ICS_PLLRMA, 0x7); /* f7 */
1000 m_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
1001 n_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
1002 sst_dac_write(DACREG_ICS_PLLRMA, 0xb); /* fB */
1003 m_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
1004 n_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
1005 f_ddprintk("m_clk0_1: %#x, m_clk0_7: %#x, m_clk1_b: %#x\n",
1006 m_clk0_1, m_clk0_7, m_clk1_b);
1007 f_ddprintk("n_clk0_1: %#x, n_clk0_7: %#x, n_clk1_b: %#x\n",
1008 n_clk0_1, n_clk0_7, n_clk1_b);
1009 if (( m_clk0_1 == DACREG_ICS_PLL_CLK0_1_INI)
1010 && (m_clk0_7 == DACREG_ICS_PLL_CLK0_7_INI)
1011 && (m_clk1_b == DACREG_ICS_PLL_CLK1_B_INI)) {
1012 return 1;
1013 }
1014 }
1015 return 0;
1016}
1017
1018
1019/*
1020 * gfx, video, pci fifo should be reset, dram refresh disabled
1021 * see detect_dac
1022 */
1023
1024static int sst_set_pll_att_ti(struct fb_info *info,
1025 const struct pll_timing *t, const int clock)
1026{
Antonino A. Daplas72275762006-01-09 20:53:14 -08001027 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028 u8 cr0, cc;
1029
1030 /* enable indexed mode */
1031 sst_dac_write(DACREG_WMA, 0); /* backdoor */
1032 sst_dac_read(DACREG_RMR); /* 1 time: RMR */
1033 sst_dac_read(DACREG_RMR); /* 2 RMR */
1034 sst_dac_read(DACREG_RMR); /* 3 // */
1035 sst_dac_read(DACREG_RMR); /* 4 // */
1036 cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */
1037
1038 sst_dac_write(DACREG_WMA, 0);
1039 sst_dac_read(DACREG_RMR);
1040 sst_dac_read(DACREG_RMR);
1041 sst_dac_read(DACREG_RMR);
1042 sst_dac_read(DACREG_RMR);
1043 sst_dac_write(DACREG_RMR, (cr0 & 0xf0)
1044 | DACREG_CR0_EN_INDEXED
1045 | DACREG_CR0_8BIT
1046 | DACREG_CR0_PWDOWN );
1047 /* so, now we are in indexed mode . dunno if its common, but
1048 i find this way of doing things a little bit weird :p */
1049
1050 udelay(300);
1051 cc = dac_i_read(DACREG_CC_I);
1052 switch (clock) {
1053 case VID_CLOCK:
1054 dac_i_write(DACREG_AC0_I, t->m);
1055 dac_i_write(DACREG_AC1_I, t->p << 6 | t->n);
1056 dac_i_write(DACREG_CC_I,
1057 (cc & 0x0f) | DACREG_CC_CLKA | DACREG_CC_CLKA_C);
1058 break;
1059 case GFX_CLOCK:
1060 dac_i_write(DACREG_BD0_I, t->m);
1061 dac_i_write(DACREG_BD1_I, t->p << 6 | t->n);
1062 dac_i_write(DACREG_CC_I,
1063 (cc & 0xf0) | DACREG_CC_CLKB | DACREG_CC_CLKB_D);
1064 break;
1065 default:
1066 dprintk("%s: wrong clock code '%d'\n",
1067 __FUNCTION__, clock);
1068 return 0;
1069 }
1070 udelay(300);
1071
1072 /* power up the dac & return to "normal" non-indexed mode */
1073 dac_i_write(DACREG_CR0_I,
1074 cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED);
1075 return 1;
1076}
1077
1078static int sst_set_pll_ics(struct fb_info *info,
1079 const struct pll_timing *t, const int clock)
1080{
Antonino A. Daplas72275762006-01-09 20:53:14 -08001081 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082 u8 pll_ctrl;
1083
1084 sst_dac_write(DACREG_ICS_PLLRMA, DACREG_ICS_PLL_CTRL);
1085 pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA);
1086 switch(clock) {
1087 case VID_CLOCK:
1088 sst_dac_write(DACREG_ICS_PLLWMA, 0x0); /* CLK0, f0 */
1089 sst_dac_write(DACREG_ICS_PLLDATA, t->m);
1090 sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
1091 /* selects freq f0 for clock 0 */
1092 sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
1093 sst_dac_write(DACREG_ICS_PLLDATA,
1094 (pll_ctrl & 0xd8)
1095 | DACREG_ICS_CLK0
1096 | DACREG_ICS_CLK0_0);
1097 break;
1098 case GFX_CLOCK :
1099 sst_dac_write(DACREG_ICS_PLLWMA, 0xa); /* CLK1, fA */
1100 sst_dac_write(DACREG_ICS_PLLDATA, t->m);
1101 sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
1102 /* selects freq fA for clock 1 */
1103 sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
1104 sst_dac_write(DACREG_ICS_PLLDATA,
1105 (pll_ctrl & 0xef) | DACREG_ICS_CLK1_A);
1106 break;
1107 default:
1108 dprintk("%s: wrong clock code '%d'\n",
1109 __FUNCTION__, clock);
1110 return 0;
1111 }
1112 udelay(300);
1113 return 1;
1114}
1115
1116static void sst_set_vidmod_att_ti(struct fb_info *info, const int bpp)
1117{
Antonino A. Daplas72275762006-01-09 20:53:14 -08001118 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001119 u8 cr0;
1120
1121 sst_dac_write(DACREG_WMA, 0); /* backdoor */
1122 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
1123 sst_dac_read(DACREG_RMR);
1124 sst_dac_read(DACREG_RMR);
1125 sst_dac_read(DACREG_RMR);
1126 /* the fifth time, CR0 is read */
1127 cr0 = sst_dac_read(DACREG_RMR);
1128
1129 sst_dac_write(DACREG_WMA, 0); /* backdoor */
1130 sst_dac_read(DACREG_RMR); /* read 4 times RMR */
1131 sst_dac_read(DACREG_RMR);
1132 sst_dac_read(DACREG_RMR);
1133 sst_dac_read(DACREG_RMR);
1134 /* cr0 */
1135 switch(bpp) {
1136 case 16:
1137 sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP);
1138 break;
1139#ifdef EN_24_32_BPP
1140 case 24:
1141 case 32:
1142 sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_24BPP);
1143 break;
1144#endif
1145 default:
1146 dprintk("%s: bad depth '%u'\n", __FUNCTION__, bpp);
1147 break;
1148 }
1149}
1150
1151static void sst_set_vidmod_ics(struct fb_info *info, const int bpp)
1152{
Antonino A. Daplas72275762006-01-09 20:53:14 -08001153 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001154
1155 switch(bpp) {
1156 case 16:
1157 sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_16BPP);
1158 break;
1159#ifdef EN_24_32_BPP
1160 case 24:
1161 case 32:
1162 sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_24BPP);
1163 break;
1164#endif
1165 default:
1166 dprintk("%s: bad depth '%u'\n", __FUNCTION__, bpp);
1167 break;
1168 }
1169}
1170
1171/*
1172 * detect dac type
1173 * prerequisite : write to FbiInitx enabled, video and fbi and pci fifo reset,
1174 * dram refresh disabled, FbiInit remaped.
1175 * TODO: mmh.. maybe i shoud put the "prerequisite" in the func ...
1176 */
1177
1178
1179static struct dac_switch dacs[] __devinitdata = {
1180 { .name = "TI TVP3409",
1181 .detect = sst_detect_ti,
1182 .set_pll = sst_set_pll_att_ti,
1183 .set_vidmod = sst_set_vidmod_att_ti },
1184
1185 { .name = "AT&T ATT20C409",
1186 .detect = sst_detect_att,
1187 .set_pll = sst_set_pll_att_ti,
1188 .set_vidmod = sst_set_vidmod_att_ti },
1189 { .name = "ICS ICS5342",
1190 .detect = sst_detect_ics,
1191 .set_pll = sst_set_pll_ics,
1192 .set_vidmod = sst_set_vidmod_ics },
1193};
1194
1195static int __devinit sst_detect_dactype(struct fb_info *info, struct sstfb_par *par)
1196{
1197 int i, ret = 0;
1198
1199 for (i=0; i<sizeof(dacs)/sizeof(dacs[0]); i++) {
1200 ret = dacs[i].detect(info);
1201 if (ret) break;
1202 }
1203 if (!ret)
1204 return 0;
1205 f_dprintk("%s found %s\n", __FUNCTION__, dacs[i].name);
1206 par->dac_sw = dacs[i];
1207 return 1;
1208}
1209
1210/*
1211 * Internal Routines
1212 */
1213static int __devinit sst_init(struct fb_info *info, struct sstfb_par *par)
1214{
1215 u32 fbiinit0, fbiinit1, fbiinit4;
1216 struct pci_dev *dev = par->dev;
1217 struct pll_timing gfx_timings;
1218 struct sst_spec *spec;
1219 int Fout;
1220
1221 spec = &voodoo_spec[par->type];
1222 f_ddprintk(" fbiinit0 fbiinit1 fbiinit2 fbiinit3 fbiinit4 "
1223 " fbiinit6\n");
1224 f_ddprintk("%0#10x %0#10x %0#10x %0#10x %0#10x %0#10x\n",
1225 sst_read(FBIINIT0), sst_read(FBIINIT1), sst_read(FBIINIT2),
1226 sst_read(FBIINIT3), sst_read(FBIINIT4), sst_read(FBIINIT6));
1227 /* disable video clock */
1228 pci_write_config_dword(dev, PCI_VCLK_DISABLE, 0);
1229
1230 /* enable writing to init registers, disable pci fifo */
1231 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
1232 /* reset video */
1233 sst_set_bits(FBIINIT1, VIDEO_RESET);
1234 sst_wait_idle();
1235 /* reset gfx + pci fifo */
1236 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
1237 sst_wait_idle();
1238
1239 /* unreset fifo */
1240 /*sst_unset_bits(FBIINIT0, FIFO_RESET);
1241 sst_wait_idle();*/
1242 /* unreset FBI */
1243 /*sst_unset_bits(FBIINIT0, FBI_RESET);
1244 sst_wait_idle();*/
1245
1246 /* disable dram refresh */
1247 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
1248 sst_wait_idle();
1249 /* remap fbinit2/3 to dac */
1250 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1251 PCI_EN_INIT_WR | PCI_REMAP_DAC );
1252 /* detect dac type */
1253 if (!sst_detect_dactype(info, par)) {
1254 eprintk("Unknown dac type\n");
1255 //FIXME watch it: we are not in a safe state, bad bad bad.
1256 return 0;
1257 }
1258
1259 /* set graphic clock */
1260 par->gfx_clock = spec->default_gfx_clock;
1261 if ((gfxclk >10 ) && (gfxclk < spec->max_gfxclk)) {
1262 iprintk("Using supplied graphic freq : %dMHz\n", gfxclk);
1263 par->gfx_clock = gfxclk *1000;
1264 } else if (gfxclk) {
1265 wprintk ("%dMhz is way out of spec! Using default\n", gfxclk);
1266 }
1267
1268 sst_calc_pll(par->gfx_clock, &Fout, &gfx_timings);
1269 par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
1270
1271 /* disable fbiinit remap */
1272 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1273 PCI_EN_INIT_WR| PCI_EN_FIFO_WR );
1274 /* defaults init registers */
1275 /* FbiInit0: unreset gfx, unreset fifo */
1276 fbiinit0 = FBIINIT0_DEFAULT;
1277 fbiinit1 = FBIINIT1_DEFAULT;
1278 fbiinit4 = FBIINIT4_DEFAULT;
1279 if (vgapass)
1280 fbiinit0 &= ~EN_VGA_PASSTHROUGH;
1281 else
1282 fbiinit0 |= EN_VGA_PASSTHROUGH;
1283 if (slowpci) {
1284 fbiinit1 |= SLOW_PCI_WRITES;
1285 fbiinit4 |= SLOW_PCI_READS;
1286 } else {
1287 fbiinit1 &= ~SLOW_PCI_WRITES;
1288 fbiinit4 &= ~SLOW_PCI_READS;
1289 }
1290 sst_write(FBIINIT0, fbiinit0);
1291 sst_wait_idle();
1292 sst_write(FBIINIT1, fbiinit1);
1293 sst_wait_idle();
1294 sst_write(FBIINIT2, FBIINIT2_DEFAULT);
1295 sst_wait_idle();
1296 sst_write(FBIINIT3, FBIINIT3_DEFAULT);
1297 sst_wait_idle();
1298 sst_write(FBIINIT4, fbiinit4);
1299 sst_wait_idle();
1300 if (IS_VOODOO2(par)) {
1301 sst_write(FBIINIT6, FBIINIT6_DEFAULT);
1302 sst_wait_idle();
1303 }
1304
1305 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
1306 pci_write_config_dword(dev, PCI_VCLK_ENABLE, 0);
1307 return 1;
1308}
1309
1310static void __devexit sst_shutdown(struct fb_info *info)
1311{
Antonino A. Daplas72275762006-01-09 20:53:14 -08001312 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001313 struct pci_dev *dev = par->dev;
1314 struct pll_timing gfx_timings;
1315 int Fout;
1316
1317 /* reset video, gfx, fifo, disable dram + remap fbiinit2/3 */
1318 pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
1319 sst_set_bits(FBIINIT1, VIDEO_RESET | EN_BLANKING);
1320 sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
1321 sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
1322 sst_wait_idle();
1323 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1324 PCI_EN_INIT_WR | PCI_REMAP_DAC);
1325 /* set 20Mhz gfx clock */
1326 sst_calc_pll(20000, &Fout, &gfx_timings);
1327 par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
1328 /* TODO maybe shutdown the dac, vrefresh and so on... */
1329 pci_write_config_dword(dev, PCI_INIT_ENABLE,
1330 PCI_EN_INIT_WR);
1331 sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET | EN_VGA_PASSTHROUGH);
1332 pci_write_config_dword(dev, PCI_VCLK_DISABLE,0);
1333 /* maybe keep fbiinit* and PCI_INIT_enable in the fb_info struct
1334 * from start ? */
1335 pci_write_config_dword(dev, PCI_INIT_ENABLE, 0);
1336
1337}
1338
1339/*
1340 * Interface to the world
1341 */
1342#ifndef MODULE
1343static int __init sstfb_setup(char *options)
1344{
1345 char *this_opt;
1346
1347 if (!options || !*options)
1348 return 0;
1349
1350 while ((this_opt = strsep(&options, ",")) != NULL) {
1351 if (!*this_opt) continue;
1352
1353 f_ddprintk("option %s\n", this_opt);
1354
1355 if (!strcmp(this_opt, "vganopass"))
1356 vgapass = 0;
1357 else if (!strcmp(this_opt, "vgapass"))
1358 vgapass = 1;
1359 else if (!strcmp(this_opt, "clipping"))
1360 clipping = 1;
1361 else if (!strcmp(this_opt, "noclipping"))
1362 clipping = 0;
1363 else if (!strcmp(this_opt, "fastpci"))
1364 slowpci = 0;
1365 else if (!strcmp(this_opt, "slowpci"))
1366 slowpci = 1;
1367 else if (!strncmp(this_opt, "mem:",4))
1368 mem = simple_strtoul (this_opt+4, NULL, 0);
1369 else if (!strncmp(this_opt, "gfxclk:",7))
1370 gfxclk = simple_strtoul (this_opt+7, NULL, 0);
1371 else
1372 mode_option = this_opt;
1373 }
1374 return 0;
1375}
1376#endif
1377
1378static struct fb_ops sstfb_ops = {
1379 .owner = THIS_MODULE,
1380 .fb_check_var = sstfb_check_var,
1381 .fb_set_par = sstfb_set_par,
1382 .fb_setcolreg = sstfb_setcolreg,
1383 .fb_fillrect = cfb_fillrect, /* sstfb_fillrect */
1384 .fb_copyarea = cfb_copyarea, /* sstfb_copyarea */
1385 .fb_imageblit = cfb_imageblit,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001386 .fb_ioctl = sstfb_ioctl,
1387};
1388
1389static int __devinit sstfb_probe(struct pci_dev *pdev,
1390 const struct pci_device_id *id)
1391{
1392 struct fb_info *info;
1393 struct fb_fix_screeninfo *fix;
1394 struct sstfb_par *par;
1395 struct sst_spec *spec;
1396 int err;
1397
Linus Torvalds1da177e2005-04-16 15:20:36 -07001398 /* Enable device in PCI config. */
1399 if ((err=pci_enable_device(pdev))) {
1400 eprintk("cannot enable device\n");
1401 return err;
1402 }
1403
1404 /* Allocate the fb and par structures. */
Antonino A. Daplas72275762006-01-09 20:53:14 -08001405 info = framebuffer_alloc(sizeof(struct sstfb_par), &pdev->dev);
1406 if (!info)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407 return -ENOMEM;
Antonino A. Daplas72275762006-01-09 20:53:14 -08001408
1409 pci_set_drvdata(pdev, info);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001410
Antonino A. Daplas72275762006-01-09 20:53:14 -08001411 par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001412 fix = &info->fix;
1413
1414 par->type = id->driver_data;
1415 spec = &voodoo_spec[par->type];
1416 f_ddprintk("found device : %s\n", spec->name);
1417
1418 par->dev = pdev;
1419 pci_read_config_byte(pdev, PCI_REVISION_ID, &par->revision);
1420
1421 fix->mmio_start = pci_resource_start(pdev,0);
1422 fix->mmio_len = 0x400000;
1423 fix->smem_start = fix->mmio_start + 0x400000;
1424
1425 if (!request_mem_region(fix->mmio_start, fix->mmio_len, "sstfb MMIO")) {
1426 eprintk("cannot reserve mmio memory\n");
1427 goto fail_mmio_mem;
1428 }
1429
1430 if (!request_mem_region(fix->smem_start, 0x400000,"sstfb FB")) {
1431 eprintk("cannot reserve fb memory\n");
1432 goto fail_fb_mem;
1433 }
1434
1435 par->mmio_vbase = ioremap_nocache(fix->mmio_start,
1436 fix->mmio_len);
1437 if (!par->mmio_vbase) {
1438 eprintk("cannot remap register area %#lx\n",
1439 fix->mmio_start);
1440 goto fail_mmio_remap;
1441 }
1442 info->screen_base = ioremap_nocache(fix->smem_start, 0x400000);
1443 if (!info->screen_base) {
1444 eprintk("cannot remap framebuffer %#lx\n",
1445 fix->smem_start);
1446 goto fail_fb_remap;
1447 }
1448
1449 if (!sst_init(info, par)) {
1450 eprintk("Init failed\n");
1451 goto fail;
1452 }
1453 sst_get_memsize(info, &fix->smem_len);
1454 strlcpy(fix->id, spec->name, sizeof(fix->id));
1455
1456 iprintk("%s (revision %d) with %s dac\n",
1457 fix->id, par->revision, par->dac_sw.name);
1458 iprintk("framebuffer at %#lx, mapped to 0x%p, size %dMB\n",
1459 fix->smem_start, info->screen_base,
1460 fix->smem_len >> 20);
1461
1462 f_ddprintk("regbase_virt: %#lx\n", par->mmio_vbase);
1463 f_ddprintk("membase_phys: %#lx\n", fix->smem_start);
1464 f_ddprintk("fbbase_virt: %p\n", info->screen_base);
1465
1466 info->flags = FBINFO_DEFAULT;
1467 info->fbops = &sstfb_ops;
Antonino A. Daplas72275762006-01-09 20:53:14 -08001468 info->pseudo_palette = par->palette;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001469
1470 fix->type = FB_TYPE_PACKED_PIXELS;
1471 fix->visual = FB_VISUAL_TRUECOLOR;
1472 fix->accel = FB_ACCEL_NONE; /* FIXME */
1473 /*
1474 * According to the specs, the linelength must be of 1024 *pixels*
1475 * and the 24bpp mode is in fact a 32 bpp mode.
1476 */
1477 fix->line_length = 2048; /* default value, for 24 or 32bit: 4096 */
1478
1479 if ( mode_option &&
1480 fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 16)) {
1481 eprintk("can't set supplied video mode. Using default\n");
1482 info->var = sstfb_default;
1483 } else
1484 info->var = sstfb_default;
1485
1486 if (sstfb_check_var(&info->var, info)) {
1487 eprintk("invalid default video mode.\n");
1488 goto fail;
1489 }
1490
1491 if (sstfb_set_par(info)) {
1492 eprintk("can't set default video mode.\n");
1493 goto fail;
1494 }
1495
1496 fb_alloc_cmap(&info->cmap, 256, 0);
1497
1498 /* register fb */
1499 info->device = &pdev->dev;
1500 if (register_framebuffer(info) < 0) {
1501 eprintk("can't register framebuffer.\n");
1502 goto fail;
1503 }
1504
1505 if (1) /* set to 0 to see an initial bitmap instead */
1506 sstfb_clear_screen(info);
1507 else
1508 sstfb_drawdebugimage(info);
1509
1510 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%p\n",
1511 info->node, fix->id, info->screen_base);
1512
1513 return 0;
1514
1515fail:
1516 iounmap(info->screen_base);
1517fail_fb_remap:
1518 iounmap(par->mmio_vbase);
1519fail_mmio_remap:
1520 release_mem_region(fix->smem_start, 0x400000);
1521fail_fb_mem:
1522 release_mem_region(fix->mmio_start, info->fix.mmio_len);
1523fail_mmio_mem:
Antonino A. Daplas72275762006-01-09 20:53:14 -08001524 framebuffer_release(info);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001525 return -ENXIO; /* no voodoo detected */
1526}
1527
1528static void __devexit sstfb_remove(struct pci_dev *pdev)
1529{
1530 struct sstfb_par *par;
1531 struct fb_info *info;
1532
1533 info = pci_get_drvdata(pdev);
Antonino A. Daplas72275762006-01-09 20:53:14 -08001534 par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001535
1536 sst_shutdown(info);
1537 unregister_framebuffer(info);
1538 iounmap(info->screen_base);
1539 iounmap(par->mmio_vbase);
1540 release_mem_region(info->fix.smem_start, 0x400000);
1541 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
Antonino A. Daplas72275762006-01-09 20:53:14 -08001542 framebuffer_release(info);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001543}
1544
1545
1546static struct pci_device_id sstfb_id_tbl[] = {
1547 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO,
1548 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_VOODOO1 },
1549 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO2,
1550 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_VOODOO2 },
1551 { 0 },
1552};
1553
1554static struct pci_driver sstfb_driver = {
1555 .name = "sstfb",
1556 .id_table = sstfb_id_tbl,
1557 .probe = sstfb_probe,
1558 .remove = __devexit_p(sstfb_remove),
1559};
1560
1561
1562static int __devinit sstfb_init(void)
1563{
1564#ifndef MODULE
1565 char *option = NULL;
1566
1567 if (fb_get_options("sstfb", &option))
1568 return -ENODEV;
1569 sstfb_setup(option);
1570#endif
1571 return pci_register_driver(&sstfb_driver);
1572}
1573
1574#ifdef MODULE
1575static void __devexit sstfb_exit(void)
1576{
1577 pci_unregister_driver(&sstfb_driver);
1578}
1579#endif
1580
1581
1582/*
1583 * testing and debugging functions
1584 */
1585
1586static int sstfb_dump_regs(struct fb_info *info)
1587{
1588#ifdef SST_DEBUG
1589 static struct { u32 reg ; const char *reg_name;} pci_regs[] = {
1590 { PCI_INIT_ENABLE, "initenable"},
1591 { PCI_VCLK_ENABLE, "enable vclk"},
1592 { PCI_VCLK_DISABLE, "disable vclk"},
1593 };
1594
1595 static struct { u32 reg ; const char *reg_name;} sst_regs[] = {
1596 {FBIINIT0,"fbiinit0"},
1597 {FBIINIT1,"fbiinit1"},
1598 {FBIINIT2,"fbiinit2"},
1599 {FBIINIT3,"fbiinit3"},
1600 {FBIINIT4,"fbiinit4"},
1601 {FBIINIT5,"fbiinit5"},
1602 {FBIINIT6,"fbiinit6"},
1603 {FBIINIT7,"fbiinit7"},
1604 {LFBMODE,"lfbmode"},
1605 {FBZMODE,"fbzmode"},
1606 };
1607
1608 const int pci_s = sizeof(pci_regs)/sizeof(pci_regs[0]);
1609 const int sst_s = sizeof(sst_regs)/sizeof(sst_regs[0]);
Antonino A. Daplas72275762006-01-09 20:53:14 -08001610 struct sstfb_par *par = info->par;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611 struct pci_dev *dev = par->dev;
1612 u32 pci_res[pci_s];
1613 u32 sst_res[sst_s];
1614 int i;
1615
1616 for (i=0; i<pci_s; i++) {
1617 pci_read_config_dword(dev, pci_regs[i].reg, &pci_res[i]);
1618 }
1619 for (i=0; i<sst_s; i++) {
1620 sst_res[i] = sst_read(sst_regs[i].reg);
1621 }
1622
1623 dprintk("hardware register dump:\n");
1624 for (i=0; i<pci_s; i++) {
1625 dprintk("%s %0#10x\n", pci_regs[i].reg_name, pci_res[i]);
1626 }
1627 for (i=0; i<sst_s; i++) {
1628 dprintk("%s %0#10x\n", sst_regs[i].reg_name, sst_res[i]);
1629 }
1630 return 0;
1631#else
1632 return -EINVAL;
1633#endif
1634}
1635
1636static void sstfb_fillrect_softw( struct fb_info *info, const struct fb_fillrect *rect)
1637{
1638 u8 __iomem *fbbase_virt = info->screen_base;
1639 int x, y, w = info->var.bits_per_pixel == 16 ? 2 : 4;
1640 u32 color = rect->color, height = rect->height;
1641 u8 __iomem *p;
1642
1643 if (w==2) color |= color<<16;
1644 for (y=rect->dy; height; y++, height--) {
1645 p = fbbase_virt + y*info->fix.line_length + rect->dx*w;
1646 x = rect->width;
1647 if (w==2) x>>=1;
1648 while (x) {
1649 writel(color, p);
1650 p += 4;
1651 x--;
1652 }
1653 }
1654}
1655
1656static void sstfb_drawrect_XY( struct fb_info *info, int x, int y,
1657 int w, int h, int color, int hwfunc)
1658{
1659 struct fb_fillrect rect;
1660 rect.dx = x;
1661 rect.dy = y;
1662 rect.height = h;
1663 rect.width = w;
1664 rect.color = color;
1665 rect.rop = ROP_COPY;
1666 if (hwfunc)
1667 sstfb_fillrect(info, &rect);
1668 else
1669 sstfb_fillrect_softw(info, &rect);
1670}
1671
1672/* print some squares on the fb */
1673static void sstfb_drawdebugimage(struct fb_info *info)
1674{
1675 static int idx;
1676
1677 /* clear screen */
1678 sstfb_clear_screen(info);
1679
1680 idx = (idx+1) & 1;
1681
1682 /* white rect */
1683 sstfb_drawrect_XY(info, 0, 0, 50, 50, 0xffff, idx);
1684
1685 /* blue rect */
1686 sstfb_drawrect_XY(info, 50, 50, 50, 50, 0x001f, idx);
1687
1688 /* green rect */
1689 sstfb_drawrect_XY(info, 100, 100, 80, 80, 0x07e0, idx);
1690
1691 /* red rect */
1692 sstfb_drawrect_XY(info, 250, 250, 120, 100, 0xf800, idx);
1693}
1694
1695module_init(sstfb_init);
1696
1697#ifdef MODULE
1698module_exit(sstfb_exit);
1699#endif
1700
1701MODULE_AUTHOR("(c) 2000,2002 Ghozlane Toumi <gtoumi@laposte.net>");
1702MODULE_DESCRIPTION("FBDev driver for 3dfx Voodoo Graphics and Voodoo2 based video boards");
1703MODULE_LICENSE("GPL");
1704
1705module_param(mem, int, 0);
1706MODULE_PARM_DESC(mem, "Size of frame buffer memory in MB (1, 2, 4 MB, default=autodetect)");
1707module_param(vgapass, bool, 0);
1708MODULE_PARM_DESC(vgapass, "Enable VGA PassThrough mode (0 or 1) (default=0)");
1709module_param(clipping, bool, 0);
1710MODULE_PARM_DESC(clipping, "Enable clipping (slower, safer) (0 or 1) (default=1)");
1711module_param(gfxclk, int, 0);
1712MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)");
1713module_param(slowpci, bool, 0);
1714MODULE_PARM_DESC(slowpci, "Uses slow PCI settings (0 or 1) (default=0)");
1715