Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 ARM Ltd. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | #ifndef __ASM_FUTEX_H |
| 17 | #define __ASM_FUTEX_H |
| 18 | |
| 19 | #ifdef __KERNEL__ |
| 20 | |
| 21 | #include <linux/futex.h> |
| 22 | #include <linux/uaccess.h> |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 23 | |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 24 | #include <asm/errno.h> |
| 25 | |
| 26 | #define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \ |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 27 | do { \ |
| 28 | uaccess_enable(); \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 29 | asm volatile( \ |
Will Deacon | 0ea366f | 2015-05-29 13:31:10 +0100 | [diff] [blame] | 30 | " prfm pstl1strm, %2\n" \ |
Will Deacon | 8e86f0b | 2014-02-04 12:29:12 +0000 | [diff] [blame] | 31 | "1: ldxr %w1, %2\n" \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 32 | insn "\n" \ |
| 33 | "2: stlxr %w3, %w0, %2\n" \ |
| 34 | " cbnz %w3, 1b\n" \ |
Will Deacon | 8e86f0b | 2014-02-04 12:29:12 +0000 | [diff] [blame] | 35 | " dmb ish\n" \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 36 | "3:\n" \ |
| 37 | " .pushsection .fixup,\"ax\"\n" \ |
Will Deacon | 4da7a56 | 2013-11-06 19:31:24 +0000 | [diff] [blame] | 38 | " .align 2\n" \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 39 | "4: mov %w0, %w5\n" \ |
| 40 | " b 3b\n" \ |
| 41 | " .popsection\n" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 42 | _ASM_EXTABLE(1b, 4b) \ |
| 43 | _ASM_EXTABLE(2b, 4b) \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 44 | : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp) \ |
| 45 | : "r" (oparg), "Ir" (-EFAULT) \ |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 46 | : "memory"); \ |
| 47 | uaccess_disable(); \ |
| 48 | } while (0) |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 49 | |
| 50 | static inline int |
Jiri Slaby | 81da9f8 | 2017-08-24 09:31:05 +0200 | [diff] [blame] | 51 | arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 52 | { |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 53 | int oldval = 0, ret, tmp; |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 54 | |
David Hildenbrand | 2f09b22 | 2015-05-11 17:52:17 +0200 | [diff] [blame] | 55 | pagefault_disable(); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 56 | |
| 57 | switch (op) { |
| 58 | case FUTEX_OP_SET: |
| 59 | __futex_atomic_op("mov %w0, %w4", |
| 60 | ret, oldval, uaddr, tmp, oparg); |
| 61 | break; |
| 62 | case FUTEX_OP_ADD: |
| 63 | __futex_atomic_op("add %w0, %w1, %w4", |
| 64 | ret, oldval, uaddr, tmp, oparg); |
| 65 | break; |
| 66 | case FUTEX_OP_OR: |
| 67 | __futex_atomic_op("orr %w0, %w1, %w4", |
| 68 | ret, oldval, uaddr, tmp, oparg); |
| 69 | break; |
| 70 | case FUTEX_OP_ANDN: |
| 71 | __futex_atomic_op("and %w0, %w1, %w4", |
| 72 | ret, oldval, uaddr, tmp, ~oparg); |
| 73 | break; |
| 74 | case FUTEX_OP_XOR: |
| 75 | __futex_atomic_op("eor %w0, %w1, %w4", |
| 76 | ret, oldval, uaddr, tmp, oparg); |
| 77 | break; |
| 78 | default: |
| 79 | ret = -ENOSYS; |
| 80 | } |
| 81 | |
David Hildenbrand | 2f09b22 | 2015-05-11 17:52:17 +0200 | [diff] [blame] | 82 | pagefault_enable(); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 83 | |
Jiri Slaby | 81da9f8 | 2017-08-24 09:31:05 +0200 | [diff] [blame] | 84 | if (!ret) |
| 85 | *oval = oldval; |
| 86 | |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 87 | return ret; |
| 88 | } |
| 89 | |
| 90 | static inline int |
Will Deacon | 1cd969f | 2018-02-05 15:34:24 +0000 | [diff] [blame] | 91 | futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr, |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 92 | u32 oldval, u32 newval) |
| 93 | { |
| 94 | int ret = 0; |
| 95 | u32 val, tmp; |
Will Deacon | 1cd969f | 2018-02-05 15:34:24 +0000 | [diff] [blame] | 96 | u32 __user *uaddr; |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 97 | |
Will Deacon | 1cd969f | 2018-02-05 15:34:24 +0000 | [diff] [blame] | 98 | if (!access_ok(VERIFY_WRITE, _uaddr, sizeof(u32))) |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 99 | return -EFAULT; |
| 100 | |
Will Deacon | 1cd969f | 2018-02-05 15:34:24 +0000 | [diff] [blame] | 101 | uaddr = __uaccess_mask_ptr(_uaddr); |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 102 | uaccess_enable(); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 103 | asm volatile("// futex_atomic_cmpxchg_inatomic\n" |
Will Deacon | 0ea366f | 2015-05-29 13:31:10 +0100 | [diff] [blame] | 104 | " prfm pstl1strm, %2\n" |
Will Deacon | 8e86f0b | 2014-02-04 12:29:12 +0000 | [diff] [blame] | 105 | "1: ldxr %w1, %2\n" |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 106 | " sub %w3, %w1, %w4\n" |
| 107 | " cbnz %w3, 3f\n" |
| 108 | "2: stlxr %w3, %w5, %2\n" |
| 109 | " cbnz %w3, 1b\n" |
Will Deacon | 8e86f0b | 2014-02-04 12:29:12 +0000 | [diff] [blame] | 110 | " dmb ish\n" |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 111 | "3:\n" |
| 112 | " .pushsection .fixup,\"ax\"\n" |
| 113 | "4: mov %w0, %w6\n" |
| 114 | " b 3b\n" |
| 115 | " .popsection\n" |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 116 | _ASM_EXTABLE(1b, 4b) |
| 117 | _ASM_EXTABLE(2b, 4b) |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 118 | : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp) |
| 119 | : "r" (oldval), "r" (newval), "Ir" (-EFAULT) |
Will Deacon | 95c4189 | 2014-02-04 12:29:13 +0000 | [diff] [blame] | 120 | : "memory"); |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 121 | uaccess_disable(); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 122 | |
| 123 | *uval = val; |
| 124 | return ret; |
| 125 | } |
| 126 | |
| 127 | #endif /* __KERNEL__ */ |
| 128 | #endif /* __ASM_FUTEX_H */ |