Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Based on arch/arm/mm/proc.S |
| 3 | * |
| 4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. |
| 5 | * Copyright (C) 2012 ARM Ltd. |
| 6 | * Author: Catalin Marinas <catalin.marinas@arm.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/linkage.h> |
| 23 | #include <asm/assembler.h> |
| 24 | #include <asm/asm-offsets.h> |
| 25 | #include <asm/hwcap.h> |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 26 | #include <asm/pgtable.h> |
James Morse | cabe1c8 | 2016-04-27 17:47:07 +0100 | [diff] [blame] | 27 | #include <asm/pgtable-hwdef.h> |
Andrew Pinski | 104a0c0 | 2016-02-24 17:44:57 -0800 | [diff] [blame] | 28 | #include <asm/cpufeature.h> |
| 29 | #include <asm/alternative.h> |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 30 | |
Catalin Marinas | 35a8697 | 2014-04-02 17:55:40 +0100 | [diff] [blame] | 31 | #ifdef CONFIG_ARM64_64K_PAGES |
| 32 | #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K |
Suzuki K. Poulose | 44eaacf | 2015-10-19 14:19:37 +0100 | [diff] [blame] | 33 | #elif defined(CONFIG_ARM64_16K_PAGES) |
| 34 | #define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K |
| 35 | #else /* CONFIG_ARM64_4K_PAGES */ |
Catalin Marinas | 35a8697 | 2014-04-02 17:55:40 +0100 | [diff] [blame] | 36 | #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 37 | #endif |
| 38 | |
Catalin Marinas | 35a8697 | 2014-04-02 17:55:40 +0100 | [diff] [blame] | 39 | #define TCR_SMP_FLAGS TCR_SHARED |
Catalin Marinas | 35a8697 | 2014-04-02 17:55:40 +0100 | [diff] [blame] | 40 | |
| 41 | /* PTWs cacheable, inner/outer WBWA */ |
| 42 | #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA |
| 43 | |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 44 | #define MAIR(attr, mt) ((attr) << ((mt) * 8)) |
| 45 | |
| 46 | /* |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 47 | * cpu_do_idle() |
| 48 | * |
| 49 | * Idle the processor (wait for interrupt). |
| 50 | */ |
| 51 | ENTRY(cpu_do_idle) |
| 52 | dsb sy // WFI may enter a low-power mode |
| 53 | wfi |
| 54 | ret |
| 55 | ENDPROC(cpu_do_idle) |
| 56 | |
Lorenzo Pieralisi | af3cfdb | 2015-01-26 18:33:44 +0000 | [diff] [blame] | 57 | #ifdef CONFIG_CPU_PM |
Lorenzo Pieralisi | 6732bc6 | 2013-07-17 10:14:45 +0100 | [diff] [blame] | 58 | /** |
| 59 | * cpu_do_suspend - save CPU registers context |
| 60 | * |
| 61 | * x0: virtual address of context pointer |
| 62 | */ |
| 63 | ENTRY(cpu_do_suspend) |
| 64 | mrs x2, tpidr_el0 |
| 65 | mrs x3, tpidrro_el0 |
| 66 | mrs x4, contextidr_el1 |
James Morse | cabe1c8 | 2016-04-27 17:47:07 +0100 | [diff] [blame] | 67 | mrs x5, cpacr_el1 |
| 68 | mrs x6, tcr_el1 |
| 69 | mrs x7, vbar_el1 |
| 70 | mrs x8, mdscr_el1 |
| 71 | mrs x9, oslsr_el1 |
| 72 | mrs x10, sctlr_el1 |
Mark Rutland | 0ec3713 | 2016-11-03 20:23:09 +0000 | [diff] [blame] | 73 | mrs x11, tpidr_el1 |
| 74 | mrs x12, sp_el0 |
Lorenzo Pieralisi | 6732bc6 | 2013-07-17 10:14:45 +0100 | [diff] [blame] | 75 | stp x2, x3, [x0] |
James Morse | cabe1c8 | 2016-04-27 17:47:07 +0100 | [diff] [blame] | 76 | stp x4, xzr, [x0, #16] |
| 77 | stp x5, x6, [x0, #32] |
| 78 | stp x7, x8, [x0, #48] |
| 79 | stp x9, x10, [x0, #64] |
Mark Rutland | 0ec3713 | 2016-11-03 20:23:09 +0000 | [diff] [blame] | 80 | stp x11, x12, [x0, #80] |
Lorenzo Pieralisi | 6732bc6 | 2013-07-17 10:14:45 +0100 | [diff] [blame] | 81 | ret |
| 82 | ENDPROC(cpu_do_suspend) |
| 83 | |
| 84 | /** |
| 85 | * cpu_do_resume - restore CPU register context |
| 86 | * |
James Morse | cabe1c8 | 2016-04-27 17:47:07 +0100 | [diff] [blame] | 87 | * x0: Address of context pointer |
Lorenzo Pieralisi | 6732bc6 | 2013-07-17 10:14:45 +0100 | [diff] [blame] | 88 | */ |
Will Deacon | 574e44d | 2018-04-03 12:09:23 +0100 | [diff] [blame] | 89 | .pushsection ".idmap.text", "awx" |
Lorenzo Pieralisi | 6732bc6 | 2013-07-17 10:14:45 +0100 | [diff] [blame] | 90 | ENTRY(cpu_do_resume) |
Lorenzo Pieralisi | 6732bc6 | 2013-07-17 10:14:45 +0100 | [diff] [blame] | 91 | ldp x2, x3, [x0] |
| 92 | ldp x4, x5, [x0, #16] |
James Morse | cabe1c8 | 2016-04-27 17:47:07 +0100 | [diff] [blame] | 93 | ldp x6, x8, [x0, #32] |
| 94 | ldp x9, x10, [x0, #48] |
| 95 | ldp x11, x12, [x0, #64] |
Mark Rutland | 0ec3713 | 2016-11-03 20:23:09 +0000 | [diff] [blame] | 96 | ldp x13, x14, [x0, #80] |
Lorenzo Pieralisi | 6732bc6 | 2013-07-17 10:14:45 +0100 | [diff] [blame] | 97 | msr tpidr_el0, x2 |
| 98 | msr tpidrro_el0, x3 |
| 99 | msr contextidr_el1, x4 |
Lorenzo Pieralisi | 6732bc6 | 2013-07-17 10:14:45 +0100 | [diff] [blame] | 100 | msr cpacr_el1, x6 |
James Morse | cabe1c8 | 2016-04-27 17:47:07 +0100 | [diff] [blame] | 101 | |
| 102 | /* Don't change t0sz here, mask those bits when restoring */ |
| 103 | mrs x5, tcr_el1 |
| 104 | bfi x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH |
| 105 | |
Lorenzo Pieralisi | 6732bc6 | 2013-07-17 10:14:45 +0100 | [diff] [blame] | 106 | msr tcr_el1, x8 |
| 107 | msr vbar_el1, x9 |
James Morse | 744c6c3 | 2016-08-26 16:03:42 +0100 | [diff] [blame] | 108 | |
| 109 | /* |
| 110 | * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking |
| 111 | * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug |
| 112 | * exception. Mask them until local_dbg_restore() in cpu_suspend() |
| 113 | * resets them. |
| 114 | */ |
| 115 | disable_dbg |
Lorenzo Pieralisi | 6732bc6 | 2013-07-17 10:14:45 +0100 | [diff] [blame] | 116 | msr mdscr_el1, x10 |
James Morse | 744c6c3 | 2016-08-26 16:03:42 +0100 | [diff] [blame] | 117 | |
James Morse | cabe1c8 | 2016-04-27 17:47:07 +0100 | [diff] [blame] | 118 | msr sctlr_el1, x12 |
Mark Rutland | 0ec3713 | 2016-11-03 20:23:09 +0000 | [diff] [blame] | 119 | msr tpidr_el1, x13 |
| 120 | msr sp_el0, x14 |
Lorenzo Pieralisi | 6732bc6 | 2013-07-17 10:14:45 +0100 | [diff] [blame] | 121 | /* |
| 122 | * Restore oslsr_el1 by writing oslar_el1 |
| 123 | */ |
| 124 | ubfx x11, x11, #1, #1 |
| 125 | msr oslar_el1, x11 |
Lorenzo Pieralisi | f436b2a | 2016-01-13 14:50:03 +0000 | [diff] [blame] | 126 | reset_pmuserenr_el0 x0 // Disable PMU access from EL0 |
Lorenzo Pieralisi | 6732bc6 | 2013-07-17 10:14:45 +0100 | [diff] [blame] | 127 | isb |
| 128 | ret |
| 129 | ENDPROC(cpu_do_resume) |
James Morse | b611303 | 2016-08-24 18:27:29 +0100 | [diff] [blame] | 130 | .popsection |
Lorenzo Pieralisi | 6732bc6 | 2013-07-17 10:14:45 +0100 | [diff] [blame] | 131 | #endif |
| 132 | |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 133 | /* |
Jingoo Han | 812944e | 2014-01-27 07:19:32 +0000 | [diff] [blame] | 134 | * cpu_do_switch_mm(pgd_phys, tsk) |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 135 | * |
| 136 | * Set the translation table base pointer to be pgd_phys. |
| 137 | * |
| 138 | * - pgd_phys - physical address of new TTB |
| 139 | */ |
| 140 | ENTRY(cpu_do_switch_mm) |
Will Deacon | a72dd8a | 2017-08-10 13:19:09 +0100 | [diff] [blame] | 141 | mrs x2, ttbr1_el1 |
Will Deacon | 5aec715 | 2015-10-06 18:46:24 +0100 | [diff] [blame] | 142 | mmid x1, x1 // get mm->context.id |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 143 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 144 | bfi x0, x1, #48, #16 // set the ASID field in TTBR0 |
| 145 | #endif |
Will Deacon | a72dd8a | 2017-08-10 13:19:09 +0100 | [diff] [blame] | 146 | bfi x2, x1, #48, #16 // set the ASID |
| 147 | msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set) |
| 148 | isb |
| 149 | msr ttbr0_el1, x0 // now update TTBR0 |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 150 | isb |
Marc Zyngier | 95bfec6 | 2018-01-02 18:19:39 +0000 | [diff] [blame] | 151 | b post_ttbr_update_workaround // Back to C code... |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 152 | ENDPROC(cpu_do_switch_mm) |
| 153 | |
Will Deacon | 574e44d | 2018-04-03 12:09:23 +0100 | [diff] [blame] | 154 | .pushsection ".idmap.text", "awx" |
Will Deacon | 4025fe1 | 2018-04-03 12:09:20 +0100 | [diff] [blame] | 155 | |
| 156 | .macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2 |
| 157 | adrp \tmp1, empty_zero_page |
| 158 | msr ttbr1_el1, \tmp1 |
| 159 | isb |
| 160 | tlbi vmalle1 |
| 161 | dsb nsh |
| 162 | isb |
| 163 | .endm |
| 164 | |
Mark Rutland | 50e1881 | 2016-01-25 11:45:01 +0000 | [diff] [blame] | 165 | /* |
| 166 | * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd) |
| 167 | * |
| 168 | * This is the low-level counterpart to cpu_replace_ttbr1, and should not be |
| 169 | * called by anything else. It can only be executed from a TTBR0 mapping. |
| 170 | */ |
| 171 | ENTRY(idmap_cpu_replace_ttbr1) |
| 172 | mrs x2, daif |
| 173 | msr daifset, #0xf |
| 174 | |
Will Deacon | 4025fe1 | 2018-04-03 12:09:20 +0100 | [diff] [blame] | 175 | __idmap_cpu_set_reserved_ttbr1 x1, x3 |
Mark Rutland | 50e1881 | 2016-01-25 11:45:01 +0000 | [diff] [blame] | 176 | |
| 177 | msr ttbr1_el1, x0 |
| 178 | isb |
| 179 | |
| 180 | msr daif, x2 |
| 181 | |
| 182 | ret |
| 183 | ENDPROC(idmap_cpu_replace_ttbr1) |
| 184 | .popsection |
| 185 | |
Will Deacon | 4025fe1 | 2018-04-03 12:09:20 +0100 | [diff] [blame] | 186 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
Will Deacon | 574e44d | 2018-04-03 12:09:23 +0100 | [diff] [blame] | 187 | .pushsection ".idmap.text", "awx" |
Will Deacon | 4025fe1 | 2018-04-03 12:09:20 +0100 | [diff] [blame] | 188 | |
| 189 | .macro __idmap_kpti_get_pgtable_ent, type |
| 190 | dc cvac, cur_\()\type\()p // Ensure any existing dirty |
| 191 | dmb sy // lines are written back before |
| 192 | ldr \type, [cur_\()\type\()p] // loading the entry |
| 193 | tbz \type, #0, next_\()\type // Skip invalid entries |
| 194 | .endm |
| 195 | |
| 196 | .macro __idmap_kpti_put_pgtable_ent_ng, type |
| 197 | orr \type, \type, #PTE_NG // Same bit for blocks and pages |
Will Deacon | fb6786c | 2018-06-22 16:23:45 +0100 | [diff] [blame] | 198 | str \type, [cur_\()\type\()p] // Update the entry and ensure |
| 199 | dmb sy // that it is visible to all |
| 200 | dc civac, cur_\()\type\()p // CPUs. |
Will Deacon | 4025fe1 | 2018-04-03 12:09:20 +0100 | [diff] [blame] | 201 | .endm |
| 202 | |
| 203 | /* |
| 204 | * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper) |
| 205 | * |
| 206 | * Called exactly once from stop_machine context by each CPU found during boot. |
| 207 | */ |
| 208 | __idmap_kpti_flag: |
| 209 | .long 1 |
| 210 | ENTRY(idmap_kpti_install_ng_mappings) |
| 211 | cpu .req w0 |
| 212 | num_cpus .req w1 |
| 213 | swapper_pa .req x2 |
| 214 | swapper_ttb .req x3 |
| 215 | flag_ptr .req x4 |
| 216 | cur_pgdp .req x5 |
| 217 | end_pgdp .req x6 |
| 218 | pgd .req x7 |
| 219 | cur_pudp .req x8 |
| 220 | end_pudp .req x9 |
| 221 | pud .req x10 |
| 222 | cur_pmdp .req x11 |
| 223 | end_pmdp .req x12 |
| 224 | pmd .req x13 |
| 225 | cur_ptep .req x14 |
| 226 | end_ptep .req x15 |
| 227 | pte .req x16 |
| 228 | |
| 229 | mrs swapper_ttb, ttbr1_el1 |
| 230 | adr flag_ptr, __idmap_kpti_flag |
| 231 | |
| 232 | cbnz cpu, __idmap_kpti_secondary |
| 233 | |
| 234 | /* We're the boot CPU. Wait for the others to catch up */ |
| 235 | sevl |
| 236 | 1: wfe |
| 237 | ldaxr w18, [flag_ptr] |
| 238 | eor w18, w18, num_cpus |
| 239 | cbnz w18, 1b |
| 240 | |
| 241 | /* We need to walk swapper, so turn off the MMU. */ |
| 242 | mrs x18, sctlr_el1 |
| 243 | bic x18, x18, #SCTLR_ELx_M |
| 244 | msr sctlr_el1, x18 |
| 245 | isb |
| 246 | |
| 247 | /* Everybody is enjoying the idmap, so we can rewrite swapper. */ |
| 248 | /* PGD */ |
| 249 | mov cur_pgdp, swapper_pa |
| 250 | add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8) |
| 251 | do_pgd: __idmap_kpti_get_pgtable_ent pgd |
| 252 | tbnz pgd, #1, walk_puds |
| 253 | __idmap_kpti_put_pgtable_ent_ng pgd |
| 254 | next_pgd: |
| 255 | add cur_pgdp, cur_pgdp, #8 |
| 256 | cmp cur_pgdp, end_pgdp |
| 257 | b.ne do_pgd |
| 258 | |
| 259 | /* Publish the updated tables and nuke all the TLBs */ |
| 260 | dsb sy |
| 261 | tlbi vmalle1is |
| 262 | dsb ish |
| 263 | isb |
| 264 | |
| 265 | /* We're done: fire up the MMU again */ |
| 266 | mrs x18, sctlr_el1 |
| 267 | orr x18, x18, #SCTLR_ELx_M |
| 268 | msr sctlr_el1, x18 |
| 269 | isb |
| 270 | |
| 271 | /* Set the flag to zero to indicate that we're all done */ |
| 272 | str wzr, [flag_ptr] |
| 273 | ret |
| 274 | |
| 275 | /* PUD */ |
| 276 | walk_puds: |
| 277 | .if CONFIG_PGTABLE_LEVELS > 3 |
| 278 | pte_to_phys cur_pudp, pgd |
| 279 | add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8) |
| 280 | do_pud: __idmap_kpti_get_pgtable_ent pud |
| 281 | tbnz pud, #1, walk_pmds |
| 282 | __idmap_kpti_put_pgtable_ent_ng pud |
| 283 | next_pud: |
| 284 | add cur_pudp, cur_pudp, 8 |
| 285 | cmp cur_pudp, end_pudp |
| 286 | b.ne do_pud |
| 287 | b next_pgd |
| 288 | .else /* CONFIG_PGTABLE_LEVELS <= 3 */ |
| 289 | mov pud, pgd |
| 290 | b walk_pmds |
| 291 | next_pud: |
| 292 | b next_pgd |
| 293 | .endif |
| 294 | |
| 295 | /* PMD */ |
| 296 | walk_pmds: |
| 297 | .if CONFIG_PGTABLE_LEVELS > 2 |
| 298 | pte_to_phys cur_pmdp, pud |
| 299 | add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8) |
| 300 | do_pmd: __idmap_kpti_get_pgtable_ent pmd |
| 301 | tbnz pmd, #1, walk_ptes |
| 302 | __idmap_kpti_put_pgtable_ent_ng pmd |
| 303 | next_pmd: |
| 304 | add cur_pmdp, cur_pmdp, #8 |
| 305 | cmp cur_pmdp, end_pmdp |
| 306 | b.ne do_pmd |
| 307 | b next_pud |
| 308 | .else /* CONFIG_PGTABLE_LEVELS <= 2 */ |
| 309 | mov pmd, pud |
| 310 | b walk_ptes |
| 311 | next_pmd: |
| 312 | b next_pud |
| 313 | .endif |
| 314 | |
| 315 | /* PTE */ |
| 316 | walk_ptes: |
| 317 | pte_to_phys cur_ptep, pmd |
| 318 | add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8) |
| 319 | do_pte: __idmap_kpti_get_pgtable_ent pte |
| 320 | __idmap_kpti_put_pgtable_ent_ng pte |
| 321 | next_pte: |
| 322 | add cur_ptep, cur_ptep, #8 |
| 323 | cmp cur_ptep, end_ptep |
| 324 | b.ne do_pte |
| 325 | b next_pmd |
| 326 | |
| 327 | /* Secondary CPUs end up here */ |
| 328 | __idmap_kpti_secondary: |
| 329 | /* Uninstall swapper before surgery begins */ |
| 330 | __idmap_cpu_set_reserved_ttbr1 x18, x17 |
| 331 | |
| 332 | /* Increment the flag to let the boot CPU we're ready */ |
| 333 | 1: ldxr w18, [flag_ptr] |
| 334 | add w18, w18, #1 |
| 335 | stxr w17, w18, [flag_ptr] |
| 336 | cbnz w17, 1b |
| 337 | |
| 338 | /* Wait for the boot CPU to finish messing around with swapper */ |
| 339 | sevl |
| 340 | 1: wfe |
| 341 | ldxr w18, [flag_ptr] |
| 342 | cbnz w18, 1b |
| 343 | |
| 344 | /* All done, act like nothing happened */ |
| 345 | msr ttbr1_el1, swapper_ttb |
| 346 | isb |
| 347 | ret |
| 348 | |
| 349 | .unreq cpu |
| 350 | .unreq num_cpus |
| 351 | .unreq swapper_pa |
| 352 | .unreq swapper_ttb |
| 353 | .unreq flag_ptr |
| 354 | .unreq cur_pgdp |
| 355 | .unreq end_pgdp |
| 356 | .unreq pgd |
| 357 | .unreq cur_pudp |
| 358 | .unreq end_pudp |
| 359 | .unreq pud |
| 360 | .unreq cur_pmdp |
| 361 | .unreq end_pmdp |
| 362 | .unreq pmd |
| 363 | .unreq cur_ptep |
| 364 | .unreq end_ptep |
| 365 | .unreq pte |
| 366 | ENDPROC(idmap_kpti_install_ng_mappings) |
| 367 | .popsection |
| 368 | #endif |
| 369 | |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 370 | /* |
| 371 | * __cpu_setup |
| 372 | * |
| 373 | * Initialise the processor for turning the MMU on. Return in x0 the |
| 374 | * value of the SCTLR_EL1 register. |
| 375 | */ |
Will Deacon | 574e44d | 2018-04-03 12:09:23 +0100 | [diff] [blame] | 376 | .pushsection ".idmap.text", "awx" |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 377 | ENTRY(__cpu_setup) |
Will Deacon | fa7aae8 | 2015-10-06 18:46:22 +0100 | [diff] [blame] | 378 | tlbi vmalle1 // Invalidate local TLB |
| 379 | dsb nsh |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 380 | |
| 381 | mov x0, #3 << 20 |
| 382 | msr cpacr_el1, x0 // Enable FP/ASIMD |
Will Deacon | d8d23fa | 2015-08-20 11:47:13 +0100 | [diff] [blame] | 383 | mov x0, #1 << 12 // Reset mdscr_el1 and disable |
| 384 | msr mdscr_el1, x0 // access to the DCC from EL0 |
Will Deacon | 2ce39ad | 2016-07-19 15:07:37 +0100 | [diff] [blame] | 385 | isb // Unmask debug exceptions now, |
| 386 | enable_dbg // since this is per-cpu |
Lorenzo Pieralisi | f436b2a | 2016-01-13 14:50:03 +0000 | [diff] [blame] | 387 | reset_pmuserenr_el0 x0 // Disable PMU access from EL0 |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 388 | /* |
| 389 | * Memory region attributes for LPAE: |
| 390 | * |
| 391 | * n = AttrIndx[2:0] |
| 392 | * n MAIR |
| 393 | * DEVICE_nGnRnE 000 00000000 |
| 394 | * DEVICE_nGnRE 001 00000100 |
| 395 | * DEVICE_GRE 010 00001100 |
| 396 | * NORMAL_NC 011 01000100 |
| 397 | * NORMAL 100 11111111 |
Jonathan (Zhixiong) Zhang | 8d446c8 | 2015-08-07 09:36:59 +0100 | [diff] [blame] | 398 | * NORMAL_WT 101 10111011 |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 399 | */ |
| 400 | ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ |
| 401 | MAIR(0x04, MT_DEVICE_nGnRE) | \ |
| 402 | MAIR(0x0c, MT_DEVICE_GRE) | \ |
| 403 | MAIR(0x44, MT_NORMAL_NC) | \ |
Jonathan (Zhixiong) Zhang | 8d446c8 | 2015-08-07 09:36:59 +0100 | [diff] [blame] | 404 | MAIR(0xff, MT_NORMAL) | \ |
| 405 | MAIR(0xbb, MT_NORMAL_WT) |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 406 | msr mair_el1, x5 |
| 407 | /* |
| 408 | * Prepare SCTLR |
| 409 | */ |
| 410 | adr x5, crval |
| 411 | ldp w5, w6, [x5] |
| 412 | mrs x0, sctlr_el1 |
| 413 | bic x0, x0, x5 // clear bits |
| 414 | orr x0, x0, x6 // set bits |
| 415 | /* |
| 416 | * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for |
| 417 | * both user and kernel. |
| 418 | */ |
Catalin Marinas | 35a8697 | 2014-04-02 17:55:40 +0100 | [diff] [blame] | 419 | ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ |
Will Deacon | a72dd8a | 2017-08-10 13:19:09 +0100 | [diff] [blame] | 420 | TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1 |
Ard Biesheuvel | dd006da | 2015-03-19 16:42:27 +0000 | [diff] [blame] | 421 | tcr_set_idmap_t0sz x10, x9 |
| 422 | |
Radha Mohan Chintakuntla | 87366d8 | 2014-03-07 08:49:25 +0000 | [diff] [blame] | 423 | /* |
| 424 | * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in |
| 425 | * TCR_EL1. |
| 426 | */ |
| 427 | mrs x9, ID_AA64MMFR0_EL1 |
| 428 | bfi x10, x9, #32, #3 |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 429 | #ifdef CONFIG_ARM64_HW_AFDBM |
| 430 | /* |
| 431 | * Hardware update of the Access and Dirty bits. |
| 432 | */ |
| 433 | mrs x9, ID_AA64MMFR1_EL1 |
| 434 | and x9, x9, #0xf |
| 435 | cbz x9, 2f |
| 436 | cmp x9, #2 |
| 437 | b.lt 1f |
Suzuki K Poulose | b8c3208 | 2018-03-26 15:12:49 +0100 | [diff] [blame] | 438 | #ifdef CONFIG_ARM64_ERRATUM_1024718 |
| 439 | /* Disable hardware DBM on Cortex-A55 r0p0, r0p1 & r1p0 */ |
| 440 | cpu_midr_match MIDR_CORTEX_A55, MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(1, 0), x1, x2, x3, x4 |
| 441 | cbnz x1, 1f |
| 442 | #endif |
Catalin Marinas | 2f4b829 | 2015-07-10 17:24:28 +0100 | [diff] [blame] | 443 | orr x10, x10, #TCR_HD // hardware Dirty flag update |
| 444 | 1: orr x10, x10, #TCR_HA // hardware Access flag update |
| 445 | 2: |
| 446 | #endif /* CONFIG_ARM64_HW_AFDBM */ |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 447 | msr tcr_el1, x10 |
| 448 | ret // return to head.S |
| 449 | ENDPROC(__cpu_setup) |
| 450 | |
| 451 | /* |
Suzuki K. Poulose | 9f71ac9 | 2014-12-17 15:50:21 +0000 | [diff] [blame] | 452 | * We set the desired value explicitly, including those of the |
| 453 | * reserved bits. The values of bits EE & E0E were set early in |
| 454 | * el2_setup, which are left untouched below. |
| 455 | * |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 456 | * n n T |
| 457 | * U E WT T UD US IHBS |
| 458 | * CE0 XWHW CZ ME TEEA S |
| 459 | * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM |
Suzuki K. Poulose | 9f71ac9 | 2014-12-17 15:50:21 +0000 | [diff] [blame] | 460 | * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved |
| 461 | * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings |
Catalin Marinas | 9cce7a4 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 462 | */ |
| 463 | .type crval, #object |
| 464 | crval: |
Suzuki K. Poulose | 9f71ac9 | 2014-12-17 15:50:21 +0000 | [diff] [blame] | 465 | .word 0xfcffffff // clear |
| 466 | .word 0x34d5d91d // set |
James Morse | b611303 | 2016-08-24 18:27:29 +0100 | [diff] [blame] | 467 | .popsection |