David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 Google, Inc. |
| 3 | * Copyright (C) 2012 Intel, Inc. |
| 4 | * Copyright (C) 2013 Intel, Inc. |
Christoffer Dall | 2f3be88 | 2016-01-06 14:05:15 +0000 | [diff] [blame] | 5 | * Copyright (C) 2014 Linaro Limited |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 6 | * |
| 7 | * This software is licensed under the terms of the GNU General Public |
| 8 | * License version 2, as published by the Free Software Foundation, and |
| 9 | * may be copied, distributed, and modified under those terms. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | */ |
| 17 | |
Yurii Zubrytskyi | f910124 | 2016-07-29 10:51:46 -0700 | [diff] [blame] | 18 | /* This source file contains the implementation of the legacy version of |
| 19 | * a goldfish pipe device driver. See goldfish_pipe_v2.c for the current |
| 20 | * version. |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 21 | */ |
Yurii Zubrytskyi | f910124 | 2016-07-29 10:51:46 -0700 | [diff] [blame] | 22 | #include "goldfish_pipe.h" |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 23 | |
| 24 | /* |
| 25 | * IMPORTANT: The following constants must match the ones used and defined |
| 26 | * in external/qemu/hw/goldfish_pipe.c in the Android source tree. |
| 27 | */ |
| 28 | |
| 29 | /* pipe device registers */ |
| 30 | #define PIPE_REG_COMMAND 0x00 /* write: value = command */ |
| 31 | #define PIPE_REG_STATUS 0x04 /* read */ |
| 32 | #define PIPE_REG_CHANNEL 0x08 /* read/write: channel id */ |
Jun Tian | 49a75c4 | 2014-05-12 16:54:46 +0100 | [diff] [blame] | 33 | #define PIPE_REG_CHANNEL_HIGH 0x30 /* read/write: channel id */ |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 34 | #define PIPE_REG_SIZE 0x0c /* read/write: buffer size */ |
| 35 | #define PIPE_REG_ADDRESS 0x10 /* write: physical address */ |
Jun Tian | 49a75c4 | 2014-05-12 16:54:46 +0100 | [diff] [blame] | 36 | #define PIPE_REG_ADDRESS_HIGH 0x34 /* write: physical address */ |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 37 | #define PIPE_REG_WAKES 0x14 /* read: wake flags */ |
| 38 | #define PIPE_REG_PARAMS_ADDR_LOW 0x18 /* read/write: batch data address */ |
| 39 | #define PIPE_REG_PARAMS_ADDR_HIGH 0x1c /* read/write: batch data address */ |
| 40 | #define PIPE_REG_ACCESS_PARAMS 0x20 /* write: batch access */ |
Yu Ning | 4f42071 | 2016-01-06 14:06:40 +0000 | [diff] [blame] | 41 | #define PIPE_REG_VERSION 0x24 /* read: device version */ |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 42 | |
| 43 | /* list of commands for PIPE_REG_COMMAND */ |
| 44 | #define CMD_OPEN 1 /* open new channel */ |
| 45 | #define CMD_CLOSE 2 /* close channel (from guest) */ |
| 46 | #define CMD_POLL 3 /* poll read/write status */ |
| 47 | |
| 48 | /* List of bitflags returned in status of CMD_POLL command */ |
| 49 | #define PIPE_POLL_IN (1 << 0) |
| 50 | #define PIPE_POLL_OUT (1 << 1) |
| 51 | #define PIPE_POLL_HUP (1 << 2) |
| 52 | |
| 53 | /* The following commands are related to write operations */ |
| 54 | #define CMD_WRITE_BUFFER 4 /* send a user buffer to the emulator */ |
| 55 | #define CMD_WAKE_ON_WRITE 5 /* tell the emulator to wake us when writing |
| 56 | is possible */ |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 57 | #define CMD_READ_BUFFER 6 /* receive a user buffer from the emulator */ |
| 58 | #define CMD_WAKE_ON_READ 7 /* tell the emulator to wake us when reading |
| 59 | * is possible */ |
| 60 | |
| 61 | /* Possible status values used to signal errors - see goldfish_pipe_error_convert */ |
| 62 | #define PIPE_ERROR_INVAL -1 |
| 63 | #define PIPE_ERROR_AGAIN -2 |
| 64 | #define PIPE_ERROR_NOMEM -3 |
| 65 | #define PIPE_ERROR_IO -4 |
| 66 | |
| 67 | /* Bit-flags used to signal events from the emulator */ |
| 68 | #define PIPE_WAKE_CLOSED (1 << 0) /* emulator closed pipe */ |
| 69 | #define PIPE_WAKE_READ (1 << 1) /* pipe can now be read from */ |
| 70 | #define PIPE_WAKE_WRITE (1 << 2) /* pipe can now be written to */ |
| 71 | |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 72 | #define MAX_PAGES_TO_GRAB 32 |
| 73 | |
| 74 | #define DEBUG 0 |
| 75 | |
| 76 | #if DEBUG |
| 77 | #define DPRINT(...) { printk(KERN_ERR __VA_ARGS__); } |
| 78 | #else |
| 79 | #define DPRINT(...) |
| 80 | #endif |
| 81 | |
Yurii Zubrytskyi | f910124 | 2016-07-29 10:51:46 -0700 | [diff] [blame] | 82 | /* This data type models a given pipe instance */ |
| 83 | struct goldfish_pipe { |
| 84 | struct goldfish_pipe_dev *dev; |
| 85 | struct mutex lock; |
| 86 | unsigned long flags; |
| 87 | wait_queue_head_t wake_queue; |
| 88 | }; |
| 89 | |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 90 | struct access_params { |
Jun Tian | 49a75c4 | 2014-05-12 16:54:46 +0100 | [diff] [blame] | 91 | unsigned long channel; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 92 | u32 size; |
Jun Tian | 49a75c4 | 2014-05-12 16:54:46 +0100 | [diff] [blame] | 93 | unsigned long address; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 94 | u32 cmd; |
| 95 | u32 result; |
| 96 | /* reserved for future extension */ |
| 97 | u32 flags; |
| 98 | }; |
| 99 | |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 100 | /* Bit flags for the 'flags' field */ |
| 101 | enum { |
| 102 | BIT_CLOSED_ON_HOST = 0, /* pipe closed by host */ |
| 103 | BIT_WAKE_ON_WRITE = 1, /* want to be woken on writes */ |
| 104 | BIT_WAKE_ON_READ = 2, /* want to be woken on reads */ |
| 105 | }; |
| 106 | |
| 107 | |
| 108 | static u32 goldfish_cmd_status(struct goldfish_pipe *pipe, u32 cmd) |
Alan | a99698f | 2014-05-12 16:57:22 +0100 | [diff] [blame] | 109 | { |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 110 | unsigned long flags; |
| 111 | u32 status; |
| 112 | struct goldfish_pipe_dev *dev = pipe->dev; |
| 113 | |
| 114 | spin_lock_irqsave(&dev->lock, flags); |
Peter Senna Tschudin | 07d783f | 2015-05-19 11:44:46 +0200 | [diff] [blame] | 115 | gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL, |
| 116 | dev->base + PIPE_REG_CHANNEL_HIGH); |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 117 | writel(cmd, dev->base + PIPE_REG_COMMAND); |
| 118 | status = readl(dev->base + PIPE_REG_STATUS); |
| 119 | spin_unlock_irqrestore(&dev->lock, flags); |
| 120 | return status; |
| 121 | } |
| 122 | |
| 123 | static void goldfish_cmd(struct goldfish_pipe *pipe, u32 cmd) |
Alan | a99698f | 2014-05-12 16:57:22 +0100 | [diff] [blame] | 124 | { |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 125 | unsigned long flags; |
| 126 | struct goldfish_pipe_dev *dev = pipe->dev; |
| 127 | |
| 128 | spin_lock_irqsave(&dev->lock, flags); |
Peter Senna Tschudin | 07d783f | 2015-05-19 11:44:46 +0200 | [diff] [blame] | 129 | gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL, |
| 130 | dev->base + PIPE_REG_CHANNEL_HIGH); |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 131 | writel(cmd, dev->base + PIPE_REG_COMMAND); |
| 132 | spin_unlock_irqrestore(&dev->lock, flags); |
| 133 | } |
| 134 | |
| 135 | /* This function converts an error code returned by the emulator through |
| 136 | * the PIPE_REG_STATUS i/o register into a valid negative errno value. |
| 137 | */ |
| 138 | static int goldfish_pipe_error_convert(int status) |
| 139 | { |
| 140 | switch (status) { |
| 141 | case PIPE_ERROR_AGAIN: |
| 142 | return -EAGAIN; |
| 143 | case PIPE_ERROR_NOMEM: |
| 144 | return -ENOMEM; |
| 145 | case PIPE_ERROR_IO: |
| 146 | return -EIO; |
| 147 | default: |
| 148 | return -EINVAL; |
| 149 | } |
| 150 | } |
| 151 | |
| 152 | /* |
| 153 | * Notice: QEMU will return 0 for un-known register access, indicating |
| 154 | * param_acess is supported or not |
| 155 | */ |
| 156 | static int valid_batchbuffer_addr(struct goldfish_pipe_dev *dev, |
| 157 | struct access_params *aps) |
| 158 | { |
| 159 | u32 aph, apl; |
| 160 | u64 paddr; |
| 161 | aph = readl(dev->base + PIPE_REG_PARAMS_ADDR_HIGH); |
| 162 | apl = readl(dev->base + PIPE_REG_PARAMS_ADDR_LOW); |
| 163 | |
| 164 | paddr = ((u64)aph << 32) | apl; |
| 165 | if (paddr != (__pa(aps))) |
| 166 | return 0; |
| 167 | return 1; |
| 168 | } |
| 169 | |
| 170 | /* 0 on success */ |
| 171 | static int setup_access_params_addr(struct platform_device *pdev, |
| 172 | struct goldfish_pipe_dev *dev) |
| 173 | { |
Shraddha Barke | 1d427da | 2016-02-12 16:11:54 +0530 | [diff] [blame] | 174 | dma_addr_t dma_handle; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 175 | struct access_params *aps; |
| 176 | |
Shraddha Barke | 1d427da | 2016-02-12 16:11:54 +0530 | [diff] [blame] | 177 | aps = dmam_alloc_coherent(&pdev->dev, sizeof(struct access_params), |
| 178 | &dma_handle, GFP_KERNEL); |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 179 | if (!aps) |
Shraddha Barke | 1d427da | 2016-02-12 16:11:54 +0530 | [diff] [blame] | 180 | return -ENOMEM; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 181 | |
Shraddha Barke | 1d427da | 2016-02-12 16:11:54 +0530 | [diff] [blame] | 182 | writel(upper_32_bits(dma_handle), dev->base + PIPE_REG_PARAMS_ADDR_HIGH); |
| 183 | writel(lower_32_bits(dma_handle), dev->base + PIPE_REG_PARAMS_ADDR_LOW); |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 184 | |
| 185 | if (valid_batchbuffer_addr(dev, aps)) { |
| 186 | dev->aps = aps; |
| 187 | return 0; |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 188 | } else { |
| 189 | devm_kfree(&pdev->dev, aps); |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 190 | return -1; |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 191 | } |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 192 | } |
| 193 | |
| 194 | /* A value that will not be set by qemu emulator */ |
| 195 | #define INITIAL_BATCH_RESULT (0xdeadbeaf) |
| 196 | static int access_with_param(struct goldfish_pipe_dev *dev, const int cmd, |
| 197 | unsigned long address, unsigned long avail, |
| 198 | struct goldfish_pipe *pipe, int *status) |
| 199 | { |
| 200 | struct access_params *aps = dev->aps; |
| 201 | |
| 202 | if (aps == NULL) |
| 203 | return -1; |
| 204 | |
| 205 | aps->result = INITIAL_BATCH_RESULT; |
| 206 | aps->channel = (unsigned long)pipe; |
| 207 | aps->size = avail; |
| 208 | aps->address = address; |
| 209 | aps->cmd = cmd; |
| 210 | writel(cmd, dev->base + PIPE_REG_ACCESS_PARAMS); |
| 211 | /* |
| 212 | * If the aps->result has not changed, that means |
| 213 | * that the batch command failed |
| 214 | */ |
| 215 | if (aps->result == INITIAL_BATCH_RESULT) |
| 216 | return -1; |
| 217 | *status = aps->result; |
| 218 | return 0; |
| 219 | } |
| 220 | |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 221 | static ssize_t goldfish_pipe_read_write(struct file *filp, char __user *buffer, |
Christoffer Dall | 2f3be88 | 2016-01-06 14:05:15 +0000 | [diff] [blame] | 222 | size_t bufflen, int is_write) |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 223 | { |
| 224 | unsigned long irq_flags; |
| 225 | struct goldfish_pipe *pipe = filp->private_data; |
| 226 | struct goldfish_pipe_dev *dev = pipe->dev; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 227 | unsigned long address, address_end; |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 228 | struct page* pages[MAX_PAGES_TO_GRAB] = {}; |
Christoffer Dall | 2f3be88 | 2016-01-06 14:05:15 +0000 | [diff] [blame] | 229 | int count = 0, ret = -EINVAL; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 230 | |
| 231 | /* If the emulator already closed the pipe, no need to go further */ |
| 232 | if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags)) |
| 233 | return -EIO; |
| 234 | |
| 235 | /* Null reads or writes succeeds */ |
Joe Perches | 3411d03 | 2015-04-10 16:47:35 -0700 | [diff] [blame] | 236 | if (unlikely(bufflen == 0)) |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 237 | return 0; |
| 238 | |
| 239 | /* Check the buffer range for access */ |
| 240 | if (!access_ok(is_write ? VERIFY_WRITE : VERIFY_READ, |
| 241 | buffer, bufflen)) |
| 242 | return -EFAULT; |
| 243 | |
| 244 | /* Serialize access to the pipe */ |
| 245 | if (mutex_lock_interruptible(&pipe->lock)) |
| 246 | return -ERESTARTSYS; |
| 247 | |
| 248 | address = (unsigned long)(void *)buffer; |
| 249 | address_end = address + bufflen; |
| 250 | |
| 251 | while (address < address_end) { |
Christoffer Dall | 2f3be88 | 2016-01-06 14:05:15 +0000 | [diff] [blame] | 252 | unsigned long page_end = (address & PAGE_MASK) + PAGE_SIZE; |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 253 | unsigned long next, avail; |
| 254 | int status, wakeBit, page_i, num_contiguous_pages; |
| 255 | long first_page, last_page, requested_pages; |
| 256 | unsigned long xaddr, xaddr_prev, xaddr_i; |
Yu Ning | 4f42071 | 2016-01-06 14:06:40 +0000 | [diff] [blame] | 257 | |
Christoffer Dall | 2f3be88 | 2016-01-06 14:05:15 +0000 | [diff] [blame] | 258 | /* |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 259 | * Attempt to grab multiple physically contiguous pages. |
Christoffer Dall | 2f3be88 | 2016-01-06 14:05:15 +0000 | [diff] [blame] | 260 | */ |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 261 | first_page = address & PAGE_MASK; |
| 262 | last_page = (address_end - 1) & PAGE_MASK; |
| 263 | requested_pages = ((last_page - first_page) >> PAGE_SHIFT) + 1; |
| 264 | if (requested_pages > MAX_PAGES_TO_GRAB) { |
| 265 | requested_pages = MAX_PAGES_TO_GRAB; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 266 | } |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 267 | ret = get_user_pages_fast(first_page, requested_pages, |
| 268 | !is_write, pages); |
| 269 | |
Yurii Zubrytskyi | f910124 | 2016-07-29 10:51:46 -0700 | [diff] [blame] | 270 | DPRINT("%s: requested pages: %d %d %p\n", __FUNCTION__, |
| 271 | ret, requested_pages, first_page); |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 272 | if (ret == 0) { |
| 273 | DPRINT("%s: error: (requested pages == 0) (wanted %d)\n", |
| 274 | __FUNCTION__, requested_pages); |
Greg Hackmann | ac95768 | 2016-11-18 11:09:02 -0800 | [diff] [blame] | 275 | mutex_unlock(&pipe->lock); |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 276 | return ret; |
| 277 | } |
| 278 | if (ret < 0) { |
| 279 | DPRINT("%s: (requested pages < 0) %d \n", |
| 280 | __FUNCTION__, requested_pages); |
Greg Hackmann | ac95768 | 2016-11-18 11:09:02 -0800 | [diff] [blame] | 281 | mutex_unlock(&pipe->lock); |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 282 | return ret; |
| 283 | } |
| 284 | |
| 285 | xaddr = page_to_phys(pages[0]) | (address & ~PAGE_MASK); |
| 286 | xaddr_prev = xaddr; |
| 287 | num_contiguous_pages = ret == 0 ? 0 : 1; |
| 288 | for (page_i = 1; page_i < ret; page_i++) { |
| 289 | xaddr_i = page_to_phys(pages[page_i]) | (address & ~PAGE_MASK); |
| 290 | if (xaddr_i == xaddr_prev + PAGE_SIZE) { |
| 291 | page_end += PAGE_SIZE; |
| 292 | xaddr_prev = xaddr_i; |
| 293 | num_contiguous_pages++; |
| 294 | } else { |
| 295 | DPRINT("%s: discontinuous page boundary: %d pages instead\n", |
| 296 | __FUNCTION__, page_i); |
| 297 | break; |
| 298 | } |
| 299 | } |
| 300 | next = page_end < address_end ? page_end : address_end; |
| 301 | avail = next - address; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 302 | |
| 303 | /* Now, try to transfer the bytes in the current page */ |
| 304 | spin_lock_irqsave(&dev->lock, irq_flags); |
Alex Bennée | 23c5ee2 | 2016-01-06 14:04:31 +0000 | [diff] [blame] | 305 | if (access_with_param(dev, |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 306 | is_write ? CMD_WRITE_BUFFER : CMD_READ_BUFFER, |
| 307 | xaddr, avail, pipe, &status)) { |
Peter Senna Tschudin | 07d783f | 2015-05-19 11:44:46 +0200 | [diff] [blame] | 308 | gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL, |
| 309 | dev->base + PIPE_REG_CHANNEL_HIGH); |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 310 | writel(avail, dev->base + PIPE_REG_SIZE); |
Yu Ning | 4f42071 | 2016-01-06 14:06:40 +0000 | [diff] [blame] | 311 | gf_write_ptr((void *)xaddr, |
Peter Senna Tschudin | 07d783f | 2015-05-19 11:44:46 +0200 | [diff] [blame] | 312 | dev->base + PIPE_REG_ADDRESS, |
| 313 | dev->base + PIPE_REG_ADDRESS_HIGH); |
Alex Bennée | 23c5ee2 | 2016-01-06 14:04:31 +0000 | [diff] [blame] | 314 | writel(is_write ? CMD_WRITE_BUFFER : CMD_READ_BUFFER, |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 315 | dev->base + PIPE_REG_COMMAND); |
| 316 | status = readl(dev->base + PIPE_REG_STATUS); |
| 317 | } |
| 318 | spin_unlock_irqrestore(&dev->lock, irq_flags); |
| 319 | |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 320 | for (page_i = 0; page_i < ret; page_i++) { |
| 321 | if (status > 0 && !is_write && |
| 322 | page_i < num_contiguous_pages) { |
| 323 | set_page_dirty(pages[page_i]); |
| 324 | } |
| 325 | put_page(pages[page_i]); |
| 326 | } |
Christoffer Dall | 2f3be88 | 2016-01-06 14:05:15 +0000 | [diff] [blame] | 327 | |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 328 | if (status > 0) { /* Correct transfer */ |
Christoffer Dall | 2f3be88 | 2016-01-06 14:05:15 +0000 | [diff] [blame] | 329 | count += status; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 330 | address += status; |
| 331 | continue; |
Christoffer Dall | 2f3be88 | 2016-01-06 14:05:15 +0000 | [diff] [blame] | 332 | } else if (status == 0) { /* EOF */ |
| 333 | ret = 0; |
| 334 | break; |
| 335 | } else if (status < 0 && count > 0) { |
| 336 | /* |
| 337 | * An error occurred and we already transferred |
| 338 | * something on one of the previous pages. |
| 339 | * Just return what we already copied and log this |
| 340 | * err. |
| 341 | * |
| 342 | * Note: This seems like an incorrect approach but |
| 343 | * cannot change it until we check if any user space |
| 344 | * ABI relies on this behavior. |
| 345 | */ |
Greg Hackmann | 25dd0f4 | 2016-01-06 14:05:55 +0000 | [diff] [blame] | 346 | if (status != PIPE_ERROR_AGAIN) |
| 347 | pr_info_ratelimited("goldfish_pipe: backend returned error %d on %s\n", |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 348 | status, is_write ? "write" : "read"); |
Christoffer Dall | 2f3be88 | 2016-01-06 14:05:15 +0000 | [diff] [blame] | 349 | ret = 0; |
| 350 | break; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 351 | } |
| 352 | |
Christoffer Dall | 2f3be88 | 2016-01-06 14:05:15 +0000 | [diff] [blame] | 353 | /* |
| 354 | * If the error is not PIPE_ERROR_AGAIN, or if we are not in |
| 355 | * non-blocking mode, just return the error code. |
| 356 | */ |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 357 | if (status != PIPE_ERROR_AGAIN || |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 358 | (filp->f_flags & O_NONBLOCK) != 0) { |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 359 | ret = goldfish_pipe_error_convert(status); |
| 360 | break; |
| 361 | } |
| 362 | |
Christoffer Dall | 2f3be88 | 2016-01-06 14:05:15 +0000 | [diff] [blame] | 363 | /* |
| 364 | * The backend blocked the read/write, wait until the backend |
| 365 | * tells us it's ready to process more data. |
| 366 | */ |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 367 | wakeBit = is_write ? BIT_WAKE_ON_WRITE : BIT_WAKE_ON_READ; |
| 368 | set_bit(wakeBit, &pipe->flags); |
| 369 | |
| 370 | /* Tell the emulator we're going to wait for a wake event */ |
Alex Bennée | 23c5ee2 | 2016-01-06 14:04:31 +0000 | [diff] [blame] | 371 | goldfish_cmd(pipe, |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 372 | is_write ? CMD_WAKE_ON_WRITE : CMD_WAKE_ON_READ); |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 373 | |
| 374 | /* Unlock the pipe, then wait for the wake signal */ |
| 375 | mutex_unlock(&pipe->lock); |
| 376 | |
| 377 | while (test_bit(wakeBit, &pipe->flags)) { |
| 378 | if (wait_event_interruptible( |
| 379 | pipe->wake_queue, |
| 380 | !test_bit(wakeBit, &pipe->flags))) |
| 381 | return -ERESTARTSYS; |
| 382 | |
| 383 | if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags)) |
| 384 | return -EIO; |
| 385 | } |
| 386 | |
| 387 | /* Try to re-acquire the lock */ |
| 388 | if (mutex_lock_interruptible(&pipe->lock)) |
| 389 | return -ERESTARTSYS; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 390 | } |
| 391 | mutex_unlock(&pipe->lock); |
Christoffer Dall | 2f3be88 | 2016-01-06 14:05:15 +0000 | [diff] [blame] | 392 | |
| 393 | if (ret < 0) |
| 394 | return ret; |
| 395 | else |
| 396 | return count; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 397 | } |
| 398 | |
| 399 | static ssize_t goldfish_pipe_read(struct file *filp, char __user *buffer, |
| 400 | size_t bufflen, loff_t *ppos) |
| 401 | { |
| 402 | return goldfish_pipe_read_write(filp, buffer, bufflen, 0); |
| 403 | } |
| 404 | |
| 405 | static ssize_t goldfish_pipe_write(struct file *filp, |
| 406 | const char __user *buffer, size_t bufflen, |
| 407 | loff_t *ppos) |
| 408 | { |
| 409 | return goldfish_pipe_read_write(filp, (char __user *)buffer, |
| 410 | bufflen, 1); |
| 411 | } |
| 412 | |
| 413 | |
| 414 | static unsigned int goldfish_pipe_poll(struct file *filp, poll_table *wait) |
| 415 | { |
| 416 | struct goldfish_pipe *pipe = filp->private_data; |
| 417 | unsigned int mask = 0; |
| 418 | int status; |
| 419 | |
| 420 | mutex_lock(&pipe->lock); |
| 421 | |
| 422 | poll_wait(filp, &pipe->wake_queue, wait); |
| 423 | |
| 424 | status = goldfish_cmd_status(pipe, CMD_POLL); |
| 425 | |
| 426 | mutex_unlock(&pipe->lock); |
| 427 | |
| 428 | if (status & PIPE_POLL_IN) |
| 429 | mask |= POLLIN | POLLRDNORM; |
| 430 | |
| 431 | if (status & PIPE_POLL_OUT) |
| 432 | mask |= POLLOUT | POLLWRNORM; |
| 433 | |
| 434 | if (status & PIPE_POLL_HUP) |
| 435 | mask |= POLLHUP; |
| 436 | |
| 437 | if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags)) |
| 438 | mask |= POLLERR; |
| 439 | |
| 440 | return mask; |
| 441 | } |
| 442 | |
| 443 | static irqreturn_t goldfish_pipe_interrupt(int irq, void *dev_id) |
| 444 | { |
| 445 | struct goldfish_pipe_dev *dev = dev_id; |
| 446 | unsigned long irq_flags; |
| 447 | int count = 0; |
| 448 | |
Christoffer Dall | 2f3be88 | 2016-01-06 14:05:15 +0000 | [diff] [blame] | 449 | /* |
| 450 | * We're going to read from the emulator a list of (channel,flags) |
| 451 | * pairs corresponding to the wake events that occurred on each |
| 452 | * blocked pipe (i.e. channel). |
| 453 | */ |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 454 | spin_lock_irqsave(&dev->lock, irq_flags); |
| 455 | for (;;) { |
| 456 | /* First read the channel, 0 means the end of the list */ |
| 457 | struct goldfish_pipe *pipe; |
| 458 | unsigned long wakes; |
Jun Tian | 49a75c4 | 2014-05-12 16:54:46 +0100 | [diff] [blame] | 459 | unsigned long channel = 0; |
| 460 | |
| 461 | #ifdef CONFIG_64BIT |
| 462 | channel = (u64)readl(dev->base + PIPE_REG_CHANNEL_HIGH) << 32; |
Jun Tian | 25c72c7 | 2014-05-12 16:54:57 +0100 | [diff] [blame] | 463 | |
| 464 | if (channel == 0) |
| 465 | break; |
Jun Tian | 49a75c4 | 2014-05-12 16:54:46 +0100 | [diff] [blame] | 466 | #endif |
| 467 | channel |= readl(dev->base + PIPE_REG_CHANNEL); |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 468 | |
| 469 | if (channel == 0) |
| 470 | break; |
| 471 | |
| 472 | /* Convert channel to struct pipe pointer + read wake flags */ |
| 473 | wakes = readl(dev->base + PIPE_REG_WAKES); |
| 474 | pipe = (struct goldfish_pipe *)(ptrdiff_t)channel; |
| 475 | |
| 476 | /* Did the emulator just closed a pipe? */ |
| 477 | if (wakes & PIPE_WAKE_CLOSED) { |
| 478 | set_bit(BIT_CLOSED_ON_HOST, &pipe->flags); |
| 479 | wakes |= PIPE_WAKE_READ | PIPE_WAKE_WRITE; |
| 480 | } |
| 481 | if (wakes & PIPE_WAKE_READ) |
| 482 | clear_bit(BIT_WAKE_ON_READ, &pipe->flags); |
| 483 | if (wakes & PIPE_WAKE_WRITE) |
| 484 | clear_bit(BIT_WAKE_ON_WRITE, &pipe->flags); |
| 485 | |
| 486 | wake_up_interruptible(&pipe->wake_queue); |
| 487 | count++; |
| 488 | } |
| 489 | spin_unlock_irqrestore(&dev->lock, irq_flags); |
| 490 | |
| 491 | return (count == 0) ? IRQ_NONE : IRQ_HANDLED; |
| 492 | } |
| 493 | |
| 494 | /** |
| 495 | * goldfish_pipe_open - open a channel to the AVD |
| 496 | * @inode: inode of device |
| 497 | * @file: file struct of opener |
| 498 | * |
| 499 | * Create a new pipe link between the emulator and the use application. |
| 500 | * Each new request produces a new pipe. |
| 501 | * |
| 502 | * Note: we use the pipe ID as a mux. All goldfish emulations are 32bit |
| 503 | * right now so this is fine. A move to 64bit will need this addressing |
| 504 | */ |
| 505 | static int goldfish_pipe_open(struct inode *inode, struct file *file) |
| 506 | { |
| 507 | struct goldfish_pipe *pipe; |
| 508 | struct goldfish_pipe_dev *dev = pipe_dev; |
| 509 | int32_t status; |
| 510 | |
| 511 | /* Allocate new pipe kernel object */ |
| 512 | pipe = kzalloc(sizeof(*pipe), GFP_KERNEL); |
| 513 | if (pipe == NULL) |
| 514 | return -ENOMEM; |
| 515 | |
| 516 | pipe->dev = dev; |
| 517 | mutex_init(&pipe->lock); |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 518 | DPRINT("%s: call. pipe_dev pipe_dev=0x%lx new_pipe_addr=0x%lx file=0x%lx\n", __FUNCTION__, pipe_dev, pipe, file); |
| 519 | // spin lock init, write head of list, i guess |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 520 | init_waitqueue_head(&pipe->wake_queue); |
| 521 | |
| 522 | /* |
| 523 | * Now, tell the emulator we're opening a new pipe. We use the |
| 524 | * pipe object's address as the channel identifier for simplicity. |
| 525 | */ |
| 526 | |
| 527 | status = goldfish_cmd_status(pipe, CMD_OPEN); |
| 528 | if (status < 0) { |
| 529 | kfree(pipe); |
| 530 | return status; |
| 531 | } |
| 532 | |
| 533 | /* All is done, save the pipe into the file's private data field */ |
| 534 | file->private_data = pipe; |
| 535 | return 0; |
| 536 | } |
| 537 | |
| 538 | static int goldfish_pipe_release(struct inode *inode, struct file *filp) |
| 539 | { |
| 540 | struct goldfish_pipe *pipe = filp->private_data; |
| 541 | |
Yurii Zubrytskyi | ba574b6 | 2016-05-04 13:05:38 -0700 | [diff] [blame] | 542 | DPRINT("%s: call. pipe=0x%lx file=0x%lx\n", __FUNCTION__, pipe, filp); |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 543 | /* The guest is closing the channel, so tell the emulator right now */ |
| 544 | goldfish_cmd(pipe, CMD_CLOSE); |
| 545 | kfree(pipe); |
| 546 | filp->private_data = NULL; |
| 547 | return 0; |
| 548 | } |
| 549 | |
| 550 | static const struct file_operations goldfish_pipe_fops = { |
| 551 | .owner = THIS_MODULE, |
| 552 | .read = goldfish_pipe_read, |
| 553 | .write = goldfish_pipe_write, |
| 554 | .poll = goldfish_pipe_poll, |
| 555 | .open = goldfish_pipe_open, |
| 556 | .release = goldfish_pipe_release, |
| 557 | }; |
| 558 | |
Yurii Zubrytskyi | f910124 | 2016-07-29 10:51:46 -0700 | [diff] [blame] | 559 | static struct miscdevice goldfish_pipe_dev = { |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 560 | .minor = MISC_DYNAMIC_MINOR, |
| 561 | .name = "goldfish_pipe", |
| 562 | .fops = &goldfish_pipe_fops, |
| 563 | }; |
| 564 | |
Yurii Zubrytskyi | f910124 | 2016-07-29 10:51:46 -0700 | [diff] [blame] | 565 | int goldfish_pipe_device_init_v1(struct platform_device *pdev) |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 566 | { |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 567 | struct goldfish_pipe_dev *dev = pipe_dev; |
Yurii Zubrytskyi | f910124 | 2016-07-29 10:51:46 -0700 | [diff] [blame] | 568 | int err = devm_request_irq(&pdev->dev, dev->irq, goldfish_pipe_interrupt, |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 569 | IRQF_SHARED, "goldfish_pipe", dev); |
| 570 | if (err) { |
Yurii Zubrytskyi | f910124 | 2016-07-29 10:51:46 -0700 | [diff] [blame] | 571 | dev_err(&pdev->dev, "unable to allocate IRQ for v1\n"); |
| 572 | return err; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 573 | } |
| 574 | |
Yurii Zubrytskyi | f910124 | 2016-07-29 10:51:46 -0700 | [diff] [blame] | 575 | err = misc_register(&goldfish_pipe_dev); |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 576 | if (err) { |
Yurii Zubrytskyi | f910124 | 2016-07-29 10:51:46 -0700 | [diff] [blame] | 577 | dev_err(&pdev->dev, "unable to register v1 device\n"); |
| 578 | return err; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 579 | } |
Yurii Zubrytskyi | f910124 | 2016-07-29 10:51:46 -0700 | [diff] [blame] | 580 | |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 581 | setup_access_params_addr(pdev, dev); |
| 582 | return 0; |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 583 | } |
| 584 | |
Yurii Zubrytskyi | f910124 | 2016-07-29 10:51:46 -0700 | [diff] [blame] | 585 | void goldfish_pipe_device_deinit_v1(struct platform_device *pdev) |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 586 | { |
Yurii Zubrytskyi | f910124 | 2016-07-29 10:51:46 -0700 | [diff] [blame] | 587 | misc_deregister(&goldfish_pipe_dev); |
David 'Digit' Turner | c89f275 | 2013-01-21 23:48:21 +0000 | [diff] [blame] | 588 | } |