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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Tony Lindgren7c38cf02005-09-08 23:07:38 +01002 * linux/arch/arm/mach-omap1/irq.c
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Interrupt handler for all OMAP boards
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
Jan Engelhardt96de0e22007-10-19 23:21:04 +02008 * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
10 * Completely re-written to support various OMAP chips with bank specific
11 * interrupt handlers.
12 *
13 * Some snippets of the code taken from the older OMAP interrupt handler
14 * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
15 *
16 * GPIO interrupt handler moved to gpio.c by Juha Yrjola
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License as published by the
20 * Free Software Foundation; either version 2 of the License, or (at your
21 * option) any later version.
22 *
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
37 */
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <linux/init.h>
40#include <linux/module.h>
41#include <linux/sched.h>
42#include <linux/interrupt.h>
Russell Kingfced80c2008-09-06 12:10:45 +010043#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070044
Russell Kinga09e64f2008-08-05 16:14:15 +010045#include <mach/hardware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <asm/irq.h>
47#include <asm/mach/irq.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010048#include <mach/gpio.h>
Tony Lindgrence491cf2009-10-20 09:40:47 -070049#include <plat/cpu.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
Linus Torvalds1da177e2005-04-16 15:20:36 -070051#define IRQ_BANK(irq) ((irq) >> 5)
52#define IRQ_BIT(irq) ((irq) & 0x1f)
53
54struct omap_irq_bank {
55 unsigned long base_reg;
56 unsigned long trigger_map;
Tony Lindgren3b59b6b2005-07-10 19:58:09 +010057 unsigned long wake_enable;
Linus Torvalds1da177e2005-04-16 15:20:36 -070058};
59
Tony Lindgren120db2c2006-04-02 17:46:27 +010060static unsigned int irq_bank_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -070061static struct omap_irq_bank *irq_banks;
62
63static inline unsigned int irq_bank_readl(int bank, int offset)
64{
65 return omap_readl(irq_banks[bank].base_reg + offset);
66}
67
68static inline void irq_bank_writel(unsigned long value, int bank, int offset)
69{
70 omap_writel(value, irq_banks[bank].base_reg + offset);
71}
72
73static void omap_ack_irq(unsigned int irq)
74{
75 if (irq > 31)
76 omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
77
78 omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
79}
80
81static void omap_mask_irq(unsigned int irq)
82{
83 int bank = IRQ_BANK(irq);
84 u32 l;
85
86 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
87 l |= 1 << IRQ_BIT(irq);
88 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
89}
90
91static void omap_unmask_irq(unsigned int irq)
92{
93 int bank = IRQ_BANK(irq);
94 u32 l;
95
96 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
97 l &= ~(1 << IRQ_BIT(irq));
98 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
99}
100
101static void omap_mask_ack_irq(unsigned int irq)
102{
103 omap_mask_irq(irq);
104 omap_ack_irq(irq);
105}
106
Tony Lindgren3b59b6b2005-07-10 19:58:09 +0100107static int omap_wake_irq(unsigned int irq, unsigned int enable)
108{
109 int bank = IRQ_BANK(irq);
110
111 if (enable)
112 irq_banks[bank].wake_enable |= IRQ_BIT(irq);
113 else
114 irq_banks[bank].wake_enable &= ~IRQ_BIT(irq);
115
116 return 0;
117}
118
119
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120/*
121 * Allows tuning the IRQ type and priority
122 *
123 * NOTE: There is currently no OMAP fiq handler for Linux. Read the
124 * mailing list threads on FIQ handlers if you are planning to
125 * add a FIQ handler for OMAP.
126 */
127static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
128{
129 signed int bank;
130 unsigned long val, offset;
131
132 bank = IRQ_BANK(irq);
133 /* FIQ is only available on bank 0 interrupts */
134 fiq = bank ? 0 : (fiq & 0x1);
135 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
136 offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
137 irq_bank_writel(val, bank, offset);
138}
139
Alistair Buxton559663b2009-09-22 06:33:04 +0100140#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
Alistair Buxton7c006922009-09-22 10:02:58 +0100141static struct omap_irq_bank omap7xx_irq_banks[] = {
Tony Lindgren120db2c2006-04-02 17:46:27 +0100142 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
143 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
145};
146#endif
147
Tony Lindgren3179a012005-11-10 14:26:48 +0000148#ifdef CONFIG_ARCH_OMAP15XX
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149static struct omap_irq_bank omap1510_irq_banks[] = {
Tony Lindgren120db2c2006-04-02 17:46:27 +0100150 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
151 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152};
Tony Lindgren3179a012005-11-10 14:26:48 +0000153static struct omap_irq_bank omap310_irq_banks[] = {
Tony Lindgren120db2c2006-04-02 17:46:27 +0100154 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
155 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
Tony Lindgren3179a012005-11-10 14:26:48 +0000156};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157#endif
158
159#if defined(CONFIG_ARCH_OMAP16XX)
160
161static struct omap_irq_bank omap1610_irq_banks[] = {
Tony Lindgren120db2c2006-04-02 17:46:27 +0100162 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
163 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
Tony Lindgren3b59b6b2005-07-10 19:58:09 +0100164 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
166};
167#endif
168
David Brownell38c677c2006-08-01 22:26:25 +0100169static struct irq_chip omap_irq_chip = {
170 .name = "MPU",
Russell King2be863c2005-09-06 23:13:17 +0100171 .ack = omap_mask_ack_irq,
172 .mask = omap_mask_irq,
173 .unmask = omap_unmask_irq,
174 .set_wake = omap_wake_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175};
176
177void __init omap_init_irq(void)
178{
Tony Lindgren03a9e512010-12-09 15:49:23 -0800179 extern unsigned int omap_irq_flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180 int i, j;
181
Alistair Buxton559663b2009-09-22 06:33:04 +0100182#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
183 if (cpu_is_omap7xx()) {
Tony Lindgren03a9e512010-12-09 15:49:23 -0800184 omap_irq_flags = INT_7XX_IH2_IRQ;
Alistair Buxton7c006922009-09-22 10:02:58 +0100185 irq_banks = omap7xx_irq_banks;
186 irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187 }
188#endif
Tony Lindgren3179a012005-11-10 14:26:48 +0000189#ifdef CONFIG_ARCH_OMAP15XX
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190 if (cpu_is_omap1510()) {
Tony Lindgren03a9e512010-12-09 15:49:23 -0800191 omap_irq_flags = INT_1510_IH2_IRQ;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192 irq_banks = omap1510_irq_banks;
193 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
194 }
Tony Lindgren3179a012005-11-10 14:26:48 +0000195 if (cpu_is_omap310()) {
Tony Lindgren03a9e512010-12-09 15:49:23 -0800196 omap_irq_flags = INT_1510_IH2_IRQ;
Tony Lindgren3179a012005-11-10 14:26:48 +0000197 irq_banks = omap310_irq_banks;
198 irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
199 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200#endif
201#if defined(CONFIG_ARCH_OMAP16XX)
202 if (cpu_is_omap16xx()) {
Tony Lindgren03a9e512010-12-09 15:49:23 -0800203 omap_irq_flags = INT_1510_IH2_IRQ;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204 irq_banks = omap1610_irq_banks;
205 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
206 }
207#endif
208 printk("Total of %i interrupts in %i interrupt banks\n",
209 irq_bank_count * 32, irq_bank_count);
210
211 /* Mask and clear all interrupts */
212 for (i = 0; i < irq_bank_count; i++) {
213 irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
214 irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
215 }
216
217 /* Clear any pending interrupts */
218 irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
219 irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
220
221 /* Enable interrupts in global mask */
Zebediah C. McClure59185ee2009-03-23 18:07:45 -0700222 if (cpu_is_omap7xx())
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223 irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224
225 /* Install the interrupt handlers for each bank */
226 for (i = 0; i < irq_bank_count; i++) {
227 for (j = i * 32; j < (i + 1) * 32; j++) {
228 int irq_trigger;
229
230 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
231 omap_irq_set_cfg(j, 0, 0, irq_trigger);
232
233 set_irq_chip(j, &omap_irq_chip);
Russell King10dd5ce2006-11-23 11:41:32 +0000234 set_irq_handler(j, handle_level_irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235 set_irq_flags(j, IRQF_VALID);
236 }
237 }
238
239 /* Unmask level 2 handler */
Tony Lindgren3179a012005-11-10 14:26:48 +0000240
Alistair Buxton559663b2009-09-22 06:33:04 +0100241 if (cpu_is_omap7xx())
Alistair Buxton372b1c32009-09-18 04:09:39 +0100242 omap_unmask_irq(INT_7XX_IH2_IRQ);
Andrzej Zaborowskief557d72006-12-06 17:13:48 -0800243 else if (cpu_is_omap15xx())
Tony Lindgren3179a012005-11-10 14:26:48 +0000244 omap_unmask_irq(INT_1510_IH2_IRQ);
245 else if (cpu_is_omap16xx())
246 omap_unmask_irq(INT_1610_IH2_IRQ);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247}