Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/include/asm-arm/cacheflush.h |
| 3 | * |
| 4 | * Copyright (C) 1999-2002 Russell King |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | #ifndef _ASMARM_CACHEFLUSH_H |
| 11 | #define _ASMARM_CACHEFLUSH_H |
| 12 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <linux/sched.h> |
| 14 | #include <linux/mm.h> |
| 15 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | #include <asm/glue.h> |
Russell King | b8a9b66 | 2005-06-20 11:31:09 +0100 | [diff] [blame] | 17 | #include <asm/shmparam.h> |
| 18 | |
| 19 | #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | |
| 21 | /* |
| 22 | * Cache Model |
| 23 | * =========== |
| 24 | */ |
| 25 | #undef _CACHE |
| 26 | #undef MULTI_CACHE |
| 27 | |
Russell King | 6cc7cbe | 2006-09-27 18:00:35 +0100 | [diff] [blame] | 28 | #if defined(CONFIG_CPU_CACHE_V3) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | # ifdef _CACHE |
| 30 | # define MULTI_CACHE 1 |
| 31 | # else |
| 32 | # define _CACHE v3 |
| 33 | # endif |
| 34 | #endif |
| 35 | |
Russell King | 6cc7cbe | 2006-09-27 18:00:35 +0100 | [diff] [blame] | 36 | #if defined(CONFIG_CPU_CACHE_V4) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | # ifdef _CACHE |
| 38 | # define MULTI_CACHE 1 |
| 39 | # else |
| 40 | # define _CACHE v4 |
| 41 | # endif |
| 42 | #endif |
| 43 | |
| 44 | #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \ |
| 45 | defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) |
| 46 | # define MULTI_CACHE 1 |
| 47 | #endif |
| 48 | |
| 49 | #if defined(CONFIG_CPU_ARM926T) |
| 50 | # ifdef _CACHE |
| 51 | # define MULTI_CACHE 1 |
| 52 | # else |
| 53 | # define _CACHE arm926 |
| 54 | # endif |
| 55 | #endif |
| 56 | |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 57 | #if defined(CONFIG_CPU_ARM940T) |
| 58 | # ifdef _CACHE |
| 59 | # define MULTI_CACHE 1 |
| 60 | # else |
| 61 | # define _CACHE arm940 |
| 62 | # endif |
| 63 | #endif |
| 64 | |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 65 | #if defined(CONFIG_CPU_ARM946E) |
| 66 | # ifdef _CACHE |
| 67 | # define MULTI_CACHE 1 |
| 68 | # else |
| 69 | # define _CACHE arm946 |
| 70 | # endif |
| 71 | #endif |
| 72 | |
Russell King | 6cc7cbe | 2006-09-27 18:00:35 +0100 | [diff] [blame] | 73 | #if defined(CONFIG_CPU_CACHE_V4WB) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | # ifdef _CACHE |
| 75 | # define MULTI_CACHE 1 |
| 76 | # else |
| 77 | # define _CACHE v4wb |
| 78 | # endif |
| 79 | #endif |
| 80 | |
| 81 | #if defined(CONFIG_CPU_XSCALE) |
| 82 | # ifdef _CACHE |
| 83 | # define MULTI_CACHE 1 |
| 84 | # else |
| 85 | # define _CACHE xscale |
| 86 | # endif |
| 87 | #endif |
| 88 | |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 89 | #if defined(CONFIG_CPU_XSC3) |
| 90 | # ifdef _CACHE |
| 91 | # define MULTI_CACHE 1 |
| 92 | # else |
| 93 | # define _CACHE xsc3 |
| 94 | # endif |
| 95 | #endif |
| 96 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | #if defined(CONFIG_CPU_V6) |
| 98 | //# ifdef _CACHE |
| 99 | # define MULTI_CACHE 1 |
| 100 | //# else |
| 101 | //# define _CACHE v6 |
| 102 | //# endif |
| 103 | #endif |
| 104 | |
| 105 | #if !defined(_CACHE) && !defined(MULTI_CACHE) |
| 106 | #error Unknown cache maintainence model |
| 107 | #endif |
| 108 | |
| 109 | /* |
| 110 | * This flag is used to indicate that the page pointed to by a pte |
| 111 | * is dirty and requires cleaning before returning it to the user. |
| 112 | */ |
| 113 | #define PG_dcache_dirty PG_arch_1 |
| 114 | |
| 115 | /* |
| 116 | * MM Cache Management |
| 117 | * =================== |
| 118 | * |
| 119 | * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files |
| 120 | * implement these methods. |
| 121 | * |
| 122 | * Start addresses are inclusive and end addresses are exclusive; |
| 123 | * start addresses should be rounded down, end addresses up. |
| 124 | * |
| 125 | * See Documentation/cachetlb.txt for more information. |
| 126 | * Please note that the implementation of these, and the required |
| 127 | * effects are cache-type (VIVT/VIPT/PIPT) specific. |
| 128 | * |
| 129 | * flush_cache_kern_all() |
| 130 | * |
| 131 | * Unconditionally clean and invalidate the entire cache. |
| 132 | * |
| 133 | * flush_cache_user_mm(mm) |
| 134 | * |
| 135 | * Clean and invalidate all user space cache entries |
| 136 | * before a change of page tables. |
| 137 | * |
| 138 | * flush_cache_user_range(start, end, flags) |
| 139 | * |
| 140 | * Clean and invalidate a range of cache entries in the |
| 141 | * specified address space before a change of page tables. |
| 142 | * - start - user start address (inclusive, page aligned) |
| 143 | * - end - user end address (exclusive, page aligned) |
| 144 | * - flags - vma->vm_flags field |
| 145 | * |
| 146 | * coherent_kern_range(start, end) |
| 147 | * |
| 148 | * Ensure coherency between the Icache and the Dcache in the |
| 149 | * region described by start, end. If you have non-snooping |
| 150 | * Harvard caches, you need to implement this function. |
| 151 | * - start - virtual start address |
| 152 | * - end - virtual end address |
| 153 | * |
| 154 | * DMA Cache Coherency |
| 155 | * =================== |
| 156 | * |
| 157 | * dma_inv_range(start, end) |
| 158 | * |
| 159 | * Invalidate (discard) the specified virtual address range. |
| 160 | * May not write back any entries. If 'start' or 'end' |
| 161 | * are not cache line aligned, those lines must be written |
| 162 | * back. |
| 163 | * - start - virtual start address |
| 164 | * - end - virtual end address |
| 165 | * |
| 166 | * dma_clean_range(start, end) |
| 167 | * |
| 168 | * Clean (write back) the specified virtual address range. |
| 169 | * - start - virtual start address |
| 170 | * - end - virtual end address |
| 171 | * |
| 172 | * dma_flush_range(start, end) |
| 173 | * |
| 174 | * Clean and invalidate the specified virtual address range. |
| 175 | * - start - virtual start address |
| 176 | * - end - virtual end address |
| 177 | */ |
| 178 | |
| 179 | struct cpu_cache_fns { |
| 180 | void (*flush_kern_all)(void); |
| 181 | void (*flush_user_all)(void); |
| 182 | void (*flush_user_range)(unsigned long, unsigned long, unsigned int); |
| 183 | |
| 184 | void (*coherent_kern_range)(unsigned long, unsigned long); |
| 185 | void (*coherent_user_range)(unsigned long, unsigned long); |
| 186 | void (*flush_kern_dcache_page)(void *); |
| 187 | |
Russell King | 7ae5a76 | 2007-02-06 17:39:31 +0000 | [diff] [blame] | 188 | void (*dma_inv_range)(const void *, const void *); |
| 189 | void (*dma_clean_range)(const void *, const void *); |
| 190 | void (*dma_flush_range)(const void *, const void *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 191 | }; |
| 192 | |
Catalin Marinas | 953233d | 2007-02-05 14:48:08 +0100 | [diff] [blame] | 193 | struct outer_cache_fns { |
| 194 | void (*inv_range)(unsigned long, unsigned long); |
| 195 | void (*clean_range)(unsigned long, unsigned long); |
| 196 | void (*flush_range)(unsigned long, unsigned long); |
| 197 | }; |
| 198 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | /* |
| 200 | * Select the calling method |
| 201 | */ |
| 202 | #ifdef MULTI_CACHE |
| 203 | |
| 204 | extern struct cpu_cache_fns cpu_cache; |
| 205 | |
| 206 | #define __cpuc_flush_kern_all cpu_cache.flush_kern_all |
| 207 | #define __cpuc_flush_user_all cpu_cache.flush_user_all |
| 208 | #define __cpuc_flush_user_range cpu_cache.flush_user_range |
| 209 | #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range |
| 210 | #define __cpuc_coherent_user_range cpu_cache.coherent_user_range |
| 211 | #define __cpuc_flush_dcache_page cpu_cache.flush_kern_dcache_page |
| 212 | |
| 213 | /* |
| 214 | * These are private to the dma-mapping API. Do not use directly. |
| 215 | * Their sole purpose is to ensure that data held in the cache |
| 216 | * is visible to DMA, or data written by DMA to system memory is |
| 217 | * visible to the CPU. |
| 218 | */ |
| 219 | #define dmac_inv_range cpu_cache.dma_inv_range |
| 220 | #define dmac_clean_range cpu_cache.dma_clean_range |
| 221 | #define dmac_flush_range cpu_cache.dma_flush_range |
| 222 | |
| 223 | #else |
| 224 | |
| 225 | #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) |
| 226 | #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all) |
| 227 | #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) |
| 228 | #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) |
| 229 | #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) |
| 230 | #define __cpuc_flush_dcache_page __glue(_CACHE,_flush_kern_dcache_page) |
| 231 | |
| 232 | extern void __cpuc_flush_kern_all(void); |
| 233 | extern void __cpuc_flush_user_all(void); |
| 234 | extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); |
| 235 | extern void __cpuc_coherent_kern_range(unsigned long, unsigned long); |
| 236 | extern void __cpuc_coherent_user_range(unsigned long, unsigned long); |
| 237 | extern void __cpuc_flush_dcache_page(void *); |
| 238 | |
| 239 | /* |
| 240 | * These are private to the dma-mapping API. Do not use directly. |
| 241 | * Their sole purpose is to ensure that data held in the cache |
| 242 | * is visible to DMA, or data written by DMA to system memory is |
| 243 | * visible to the CPU. |
| 244 | */ |
| 245 | #define dmac_inv_range __glue(_CACHE,_dma_inv_range) |
| 246 | #define dmac_clean_range __glue(_CACHE,_dma_clean_range) |
| 247 | #define dmac_flush_range __glue(_CACHE,_dma_flush_range) |
| 248 | |
Russell King | 7ae5a76 | 2007-02-06 17:39:31 +0000 | [diff] [blame] | 249 | extern void dmac_inv_range(const void *, const void *); |
| 250 | extern void dmac_clean_range(const void *, const void *); |
| 251 | extern void dmac_flush_range(const void *, const void *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 252 | |
| 253 | #endif |
| 254 | |
Catalin Marinas | 953233d | 2007-02-05 14:48:08 +0100 | [diff] [blame] | 255 | #ifdef CONFIG_OUTER_CACHE |
| 256 | |
| 257 | extern struct outer_cache_fns outer_cache; |
| 258 | |
| 259 | static inline void outer_inv_range(unsigned long start, unsigned long end) |
| 260 | { |
| 261 | if (outer_cache.inv_range) |
| 262 | outer_cache.inv_range(start, end); |
| 263 | } |
| 264 | static inline void outer_clean_range(unsigned long start, unsigned long end) |
| 265 | { |
| 266 | if (outer_cache.clean_range) |
| 267 | outer_cache.clean_range(start, end); |
| 268 | } |
| 269 | static inline void outer_flush_range(unsigned long start, unsigned long end) |
| 270 | { |
| 271 | if (outer_cache.flush_range) |
| 272 | outer_cache.flush_range(start, end); |
| 273 | } |
| 274 | |
| 275 | #else |
| 276 | |
| 277 | static inline void outer_inv_range(unsigned long start, unsigned long end) |
| 278 | { } |
| 279 | static inline void outer_clean_range(unsigned long start, unsigned long end) |
| 280 | { } |
| 281 | static inline void outer_flush_range(unsigned long start, unsigned long end) |
| 282 | { } |
| 283 | |
| 284 | #endif |
| 285 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 286 | /* |
| 287 | * flush_cache_vmap() is used when creating mappings (eg, via vmap, |
| 288 | * vmalloc, ioremap etc) in kernel space for pages. Since the |
| 289 | * direct-mappings of these pages may contain cached data, we need |
| 290 | * to do a full cache flush to ensure that writebacks don't corrupt |
| 291 | * data placed into these pages via the new mappings. |
| 292 | */ |
| 293 | #define flush_cache_vmap(start, end) flush_cache_all() |
| 294 | #define flush_cache_vunmap(start, end) flush_cache_all() |
| 295 | |
| 296 | /* |
| 297 | * Copy user data from/to a page which is mapped into a different |
| 298 | * processes address space. Really, we want to allow our "user |
| 299 | * space" model to handle this. |
| 300 | */ |
| 301 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ |
| 302 | do { \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 303 | memcpy(dst, src, len); \ |
George G. Davis | a188ad2 | 2006-09-02 18:43:20 +0100 | [diff] [blame] | 304 | flush_ptrace_access(vma, page, vaddr, dst, len, 1);\ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 305 | } while (0) |
| 306 | |
| 307 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ |
| 308 | do { \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 309 | memcpy(dst, src, len); \ |
| 310 | } while (0) |
| 311 | |
| 312 | /* |
| 313 | * Convert calls to our calling convention. |
| 314 | */ |
| 315 | #define flush_cache_all() __cpuc_flush_kern_all() |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 316 | #ifndef CONFIG_CPU_CACHE_VIPT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 317 | static inline void flush_cache_mm(struct mm_struct *mm) |
| 318 | { |
| 319 | if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) |
| 320 | __cpuc_flush_user_all(); |
| 321 | } |
| 322 | |
| 323 | static inline void |
| 324 | flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) |
| 325 | { |
| 326 | if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) |
| 327 | __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), |
| 328 | vma->vm_flags); |
| 329 | } |
| 330 | |
| 331 | static inline void |
| 332 | flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) |
| 333 | { |
| 334 | if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { |
| 335 | unsigned long addr = user_addr & PAGE_MASK; |
| 336 | __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); |
| 337 | } |
| 338 | } |
George G. Davis | a188ad2 | 2006-09-02 18:43:20 +0100 | [diff] [blame] | 339 | |
| 340 | static inline void |
| 341 | flush_ptrace_access(struct vm_area_struct *vma, struct page *page, |
| 342 | unsigned long uaddr, void *kaddr, |
| 343 | unsigned long len, int write) |
| 344 | { |
| 345 | if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { |
| 346 | unsigned long addr = (unsigned long)kaddr; |
| 347 | __cpuc_coherent_kern_range(addr, addr + len); |
| 348 | } |
| 349 | } |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 350 | #else |
| 351 | extern void flush_cache_mm(struct mm_struct *mm); |
| 352 | extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); |
| 353 | extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn); |
George G. Davis | a188ad2 | 2006-09-02 18:43:20 +0100 | [diff] [blame] | 354 | extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, |
| 355 | unsigned long uaddr, void *kaddr, |
| 356 | unsigned long len, int write); |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 357 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 358 | |
Ralf Baechle | ec8c044 | 2006-12-12 17:14:57 +0000 | [diff] [blame] | 359 | #define flush_cache_dup_mm(mm) flush_cache_mm(mm) |
| 360 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 361 | /* |
| 362 | * flush_cache_user_range is used when we want to ensure that the |
| 363 | * Harvard caches are synchronised for the user space address range. |
| 364 | * This is used for the ARM private sys_cacheflush system call. |
| 365 | */ |
| 366 | #define flush_cache_user_range(vma,start,end) \ |
| 367 | __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) |
| 368 | |
| 369 | /* |
| 370 | * Perform necessary cache operations to ensure that data previously |
| 371 | * stored within this range of addresses can be executed by the CPU. |
| 372 | */ |
| 373 | #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e) |
| 374 | |
| 375 | /* |
| 376 | * Perform necessary cache operations to ensure that the TLB will |
| 377 | * see data written in the specified area. |
| 378 | */ |
| 379 | #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size) |
| 380 | |
| 381 | /* |
| 382 | * flush_dcache_page is used when the kernel has written to the page |
| 383 | * cache page at virtual address page->virtual. |
| 384 | * |
| 385 | * If this page isn't mapped (ie, page_mapping == NULL), or it might |
| 386 | * have userspace mappings, then we _must_ always clean + invalidate |
| 387 | * the dcache entries associated with the kernel mapping. |
| 388 | * |
| 389 | * Otherwise we can defer the operation, and clean the cache when we are |
| 390 | * about to change to user space. This is the same method as used on SPARC64. |
| 391 | * See update_mmu_cache for the user space part. |
| 392 | */ |
| 393 | extern void flush_dcache_page(struct page *); |
| 394 | |
Richard Purdie | 1c9d3df | 2006-12-30 16:08:50 +0100 | [diff] [blame] | 395 | extern void __flush_dcache_page(struct address_space *mapping, struct page *page); |
| 396 | |
Russell King | 6020dff | 2006-12-30 23:17:40 +0000 | [diff] [blame] | 397 | #define ARCH_HAS_FLUSH_ANON_PAGE |
| 398 | static inline void flush_anon_page(struct vm_area_struct *vma, |
| 399 | struct page *page, unsigned long vmaddr) |
| 400 | { |
| 401 | extern void __flush_anon_page(struct vm_area_struct *vma, |
| 402 | struct page *, unsigned long); |
| 403 | if (PageAnon(page)) |
| 404 | __flush_anon_page(vma, page, vmaddr); |
| 405 | } |
| 406 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 407 | #define flush_dcache_mmap_lock(mapping) \ |
| 408 | write_lock_irq(&(mapping)->tree_lock) |
| 409 | #define flush_dcache_mmap_unlock(mapping) \ |
| 410 | write_unlock_irq(&(mapping)->tree_lock) |
| 411 | |
| 412 | #define flush_icache_user_range(vma,page,addr,len) \ |
| 413 | flush_dcache_page(page) |
| 414 | |
| 415 | /* |
| 416 | * We don't appear to need to do anything here. In fact, if we did, we'd |
| 417 | * duplicate cache flushing elsewhere performed by flush_dcache_page(). |
| 418 | */ |
| 419 | #define flush_icache_page(vma,page) do { } while (0) |
| 420 | |
| 421 | #define __cacheid_present(val) (val != read_cpuid(CPUID_ID)) |
| 422 | #define __cacheid_vivt(val) ((val & (15 << 25)) != (14 << 25)) |
| 423 | #define __cacheid_vipt(val) ((val & (15 << 25)) == (14 << 25)) |
| 424 | #define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25)) |
| 425 | #define __cacheid_vipt_aliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23)) |
| 426 | |
| 427 | #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT) |
| 428 | |
| 429 | #define cache_is_vivt() 1 |
| 430 | #define cache_is_vipt() 0 |
| 431 | #define cache_is_vipt_nonaliasing() 0 |
| 432 | #define cache_is_vipt_aliasing() 0 |
| 433 | |
| 434 | #elif defined(CONFIG_CPU_CACHE_VIPT) |
| 435 | |
| 436 | #define cache_is_vivt() 0 |
| 437 | #define cache_is_vipt() 1 |
| 438 | #define cache_is_vipt_nonaliasing() \ |
| 439 | ({ \ |
| 440 | unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ |
| 441 | __cacheid_vipt_nonaliasing(__val); \ |
| 442 | }) |
| 443 | |
| 444 | #define cache_is_vipt_aliasing() \ |
| 445 | ({ \ |
| 446 | unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ |
| 447 | __cacheid_vipt_aliasing(__val); \ |
| 448 | }) |
| 449 | |
| 450 | #else |
| 451 | |
| 452 | #define cache_is_vivt() \ |
| 453 | ({ \ |
| 454 | unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ |
| 455 | (!__cacheid_present(__val)) || __cacheid_vivt(__val); \ |
| 456 | }) |
| 457 | |
| 458 | #define cache_is_vipt() \ |
| 459 | ({ \ |
| 460 | unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ |
| 461 | __cacheid_present(__val) && __cacheid_vipt(__val); \ |
| 462 | }) |
| 463 | |
| 464 | #define cache_is_vipt_nonaliasing() \ |
| 465 | ({ \ |
| 466 | unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ |
| 467 | __cacheid_present(__val) && \ |
| 468 | __cacheid_vipt_nonaliasing(__val); \ |
| 469 | }) |
| 470 | |
| 471 | #define cache_is_vipt_aliasing() \ |
| 472 | ({ \ |
| 473 | unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ |
| 474 | __cacheid_present(__val) && \ |
| 475 | __cacheid_vipt_aliasing(__val); \ |
| 476 | }) |
| 477 | |
| 478 | #endif |
| 479 | |
| 480 | #endif |