Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 1 | /* |
| 2 | * OMAP WakeupGen Source file |
| 3 | * |
| 4 | * OMAP WakeupGen is the interrupt controller extension used along |
| 5 | * with ARM GIC to wake the CPU out from low power states on |
| 6 | * external interrupts. It is responsible for generating wakeup |
| 7 | * event from the incoming interrupts and enable bits. It is |
| 8 | * implemented in MPU always ON power domain. During normal operation, |
| 9 | * WakeupGen delivers external interrupts directly to the GIC. |
| 10 | * |
| 11 | * Copyright (C) 2011 Texas Instruments, Inc. |
| 12 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License version 2 as |
| 16 | * published by the Free Software Foundation. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/io.h> |
| 22 | #include <linux/irq.h> |
| 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/cpu.h> |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 25 | #include <linux/notifier.h> |
| 26 | #include <linux/cpu_pm.h> |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 27 | |
| 28 | #include <asm/hardware/gic.h> |
| 29 | |
Tony Lindgren | 732231a | 2012-09-20 11:41:16 -0700 | [diff] [blame^] | 30 | #include "omap-wakeupgen.h" |
Tony Lindgren | c1db9d7 | 2012-09-20 11:41:14 -0700 | [diff] [blame] | 31 | #include "omap-secure.h" |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 32 | |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 33 | #include "soc.h" |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 34 | #include "omap4-sar-layout.h" |
| 35 | #include "common.h" |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 36 | |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 37 | #define MAX_NR_REG_BANKS 5 |
| 38 | #define MAX_IRQS 160 |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 39 | #define WKG_MASK_ALL 0x00000000 |
| 40 | #define WKG_UNMASK_ALL 0xffffffff |
| 41 | #define CPU_ENA_OFFSET 0x400 |
| 42 | #define CPU0_ID 0x0 |
| 43 | #define CPU1_ID 0x1 |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 44 | #define OMAP4_NR_BANKS 4 |
| 45 | #define OMAP4_NR_IRQS 128 |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 46 | |
| 47 | static void __iomem *wakeupgen_base; |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 48 | static void __iomem *sar_base; |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 49 | static DEFINE_SPINLOCK(wakeupgen_lock); |
| 50 | static unsigned int irq_target_cpu[NR_IRQS]; |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 51 | static unsigned int irq_banks = MAX_NR_REG_BANKS; |
| 52 | static unsigned int max_irqs = MAX_IRQS; |
| 53 | static unsigned int omap_secure_apis; |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 54 | |
| 55 | /* |
| 56 | * Static helper functions. |
| 57 | */ |
| 58 | static inline u32 wakeupgen_readl(u8 idx, u32 cpu) |
| 59 | { |
| 60 | return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 + |
| 61 | (cpu * CPU_ENA_OFFSET) + (idx * 4)); |
| 62 | } |
| 63 | |
| 64 | static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu) |
| 65 | { |
| 66 | __raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 + |
| 67 | (cpu * CPU_ENA_OFFSET) + (idx * 4)); |
| 68 | } |
| 69 | |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 70 | static inline void sar_writel(u32 val, u32 offset, u8 idx) |
| 71 | { |
| 72 | __raw_writel(val, sar_base + offset + (idx * 4)); |
| 73 | } |
| 74 | |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 75 | static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index) |
| 76 | { |
| 77 | unsigned int spi_irq; |
| 78 | |
| 79 | /* |
| 80 | * PPIs and SGIs are not supported. |
| 81 | */ |
| 82 | if (irq < OMAP44XX_IRQ_GIC_START) |
| 83 | return -EINVAL; |
| 84 | |
| 85 | /* |
| 86 | * Subtract the GIC offset. |
| 87 | */ |
| 88 | spi_irq = irq - OMAP44XX_IRQ_GIC_START; |
| 89 | if (spi_irq > MAX_IRQS) { |
| 90 | pr_err("omap wakeupGen: Invalid IRQ%d\n", irq); |
| 91 | return -EINVAL; |
| 92 | } |
| 93 | |
| 94 | /* |
| 95 | * Each WakeupGen register controls 32 interrupt. |
| 96 | * i.e. 1 bit per SPI IRQ |
| 97 | */ |
| 98 | *reg_index = spi_irq >> 5; |
| 99 | *bit_posn = spi_irq %= 32; |
| 100 | |
| 101 | return 0; |
| 102 | } |
| 103 | |
| 104 | static void _wakeupgen_clear(unsigned int irq, unsigned int cpu) |
| 105 | { |
| 106 | u32 val, bit_number; |
| 107 | u8 i; |
| 108 | |
| 109 | if (_wakeupgen_get_irq_info(irq, &bit_number, &i)) |
| 110 | return; |
| 111 | |
| 112 | val = wakeupgen_readl(i, cpu); |
| 113 | val &= ~BIT(bit_number); |
| 114 | wakeupgen_writel(val, i, cpu); |
| 115 | } |
| 116 | |
| 117 | static void _wakeupgen_set(unsigned int irq, unsigned int cpu) |
| 118 | { |
| 119 | u32 val, bit_number; |
| 120 | u8 i; |
| 121 | |
| 122 | if (_wakeupgen_get_irq_info(irq, &bit_number, &i)) |
| 123 | return; |
| 124 | |
| 125 | val = wakeupgen_readl(i, cpu); |
| 126 | val |= BIT(bit_number); |
| 127 | wakeupgen_writel(val, i, cpu); |
| 128 | } |
| 129 | |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 130 | /* |
| 131 | * Architecture specific Mask extension |
| 132 | */ |
| 133 | static void wakeupgen_mask(struct irq_data *d) |
| 134 | { |
| 135 | unsigned long flags; |
| 136 | |
| 137 | spin_lock_irqsave(&wakeupgen_lock, flags); |
| 138 | _wakeupgen_clear(d->irq, irq_target_cpu[d->irq]); |
| 139 | spin_unlock_irqrestore(&wakeupgen_lock, flags); |
| 140 | } |
| 141 | |
| 142 | /* |
| 143 | * Architecture specific Unmask extension |
| 144 | */ |
| 145 | static void wakeupgen_unmask(struct irq_data *d) |
| 146 | { |
| 147 | unsigned long flags; |
| 148 | |
| 149 | spin_lock_irqsave(&wakeupgen_lock, flags); |
| 150 | _wakeupgen_set(d->irq, irq_target_cpu[d->irq]); |
| 151 | spin_unlock_irqrestore(&wakeupgen_lock, flags); |
| 152 | } |
| 153 | |
Kevin Hilman | bb1dbe7 | 2012-03-06 12:00:25 -0800 | [diff] [blame] | 154 | #ifdef CONFIG_HOTPLUG_CPU |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 155 | static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks); |
Kevin Hilman | bb1dbe7 | 2012-03-06 12:00:25 -0800 | [diff] [blame] | 156 | |
| 157 | static void _wakeupgen_save_masks(unsigned int cpu) |
| 158 | { |
| 159 | u8 i; |
| 160 | |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 161 | for (i = 0; i < irq_banks; i++) |
Kevin Hilman | bb1dbe7 | 2012-03-06 12:00:25 -0800 | [diff] [blame] | 162 | per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu); |
| 163 | } |
| 164 | |
| 165 | static void _wakeupgen_restore_masks(unsigned int cpu) |
| 166 | { |
| 167 | u8 i; |
| 168 | |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 169 | for (i = 0; i < irq_banks; i++) |
Kevin Hilman | bb1dbe7 | 2012-03-06 12:00:25 -0800 | [diff] [blame] | 170 | wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu); |
| 171 | } |
| 172 | |
| 173 | static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg) |
| 174 | { |
| 175 | u8 i; |
| 176 | |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 177 | for (i = 0; i < irq_banks; i++) |
Kevin Hilman | bb1dbe7 | 2012-03-06 12:00:25 -0800 | [diff] [blame] | 178 | wakeupgen_writel(reg, i, cpu); |
| 179 | } |
| 180 | |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 181 | /* |
| 182 | * Mask or unmask all interrupts on given CPU. |
| 183 | * 0 = Mask all interrupts on the 'cpu' |
| 184 | * 1 = Unmask all interrupts on the 'cpu' |
| 185 | * Ensure that the initial mask is maintained. This is faster than |
| 186 | * iterating through GIC registers to arrive at the correct masks. |
| 187 | */ |
| 188 | static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set) |
| 189 | { |
| 190 | unsigned long flags; |
| 191 | |
| 192 | spin_lock_irqsave(&wakeupgen_lock, flags); |
| 193 | if (set) { |
| 194 | _wakeupgen_save_masks(cpu); |
| 195 | _wakeupgen_set_all(cpu, WKG_MASK_ALL); |
| 196 | } else { |
| 197 | _wakeupgen_set_all(cpu, WKG_UNMASK_ALL); |
| 198 | _wakeupgen_restore_masks(cpu); |
| 199 | } |
| 200 | spin_unlock_irqrestore(&wakeupgen_lock, flags); |
| 201 | } |
Kevin Hilman | bb1dbe7 | 2012-03-06 12:00:25 -0800 | [diff] [blame] | 202 | #endif |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 203 | |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 204 | #ifdef CONFIG_CPU_PM |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 205 | static inline void omap4_irq_save_context(void) |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 206 | { |
| 207 | u32 i, val; |
| 208 | |
| 209 | if (omap_rev() == OMAP4430_REV_ES1_0) |
| 210 | return; |
| 211 | |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 212 | for (i = 0; i < irq_banks; i++) { |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 213 | /* Save the CPUx interrupt mask for IRQ 0 to 127 */ |
| 214 | val = wakeupgen_readl(i, 0); |
| 215 | sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i); |
| 216 | val = wakeupgen_readl(i, 1); |
| 217 | sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i); |
| 218 | |
| 219 | /* |
| 220 | * Disable the secure interrupts for CPUx. The restore |
| 221 | * code blindly restores secure and non-secure interrupt |
| 222 | * masks from SAR RAM. Secure interrupts are not suppose |
| 223 | * to be enabled from HLOS. So overwrite the SAR location |
| 224 | * so that the secure interrupt remains disabled. |
| 225 | */ |
| 226 | sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i); |
| 227 | sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i); |
| 228 | } |
| 229 | |
| 230 | /* Save AuxBoot* registers */ |
| 231 | val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); |
| 232 | __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET); |
| 233 | val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); |
| 234 | __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET); |
| 235 | |
| 236 | /* Save SyncReq generation logic */ |
| 237 | val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); |
| 238 | __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET); |
| 239 | val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); |
| 240 | __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET); |
| 241 | |
| 242 | /* Save SyncReq generation logic */ |
| 243 | val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK); |
| 244 | __raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET); |
| 245 | val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN); |
| 246 | __raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET); |
| 247 | |
| 248 | /* Set the Backup Bit Mask status */ |
| 249 | val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET); |
| 250 | val |= SAR_BACKUP_STATUS_WAKEUPGEN; |
| 251 | __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET); |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 252 | |
| 253 | } |
| 254 | |
| 255 | static inline void omap5_irq_save_context(void) |
| 256 | { |
| 257 | u32 i, val; |
| 258 | |
| 259 | for (i = 0; i < irq_banks; i++) { |
| 260 | /* Save the CPUx interrupt mask for IRQ 0 to 159 */ |
| 261 | val = wakeupgen_readl(i, 0); |
| 262 | sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i); |
| 263 | val = wakeupgen_readl(i, 1); |
| 264 | sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i); |
| 265 | sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i); |
| 266 | sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i); |
| 267 | } |
| 268 | |
| 269 | /* Save AuxBoot* registers */ |
| 270 | val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); |
| 271 | __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET); |
| 272 | val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); |
| 273 | __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET); |
| 274 | |
| 275 | /* Set the Backup Bit Mask status */ |
| 276 | val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); |
| 277 | val |= SAR_BACKUP_STATUS_WAKEUPGEN; |
| 278 | __raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); |
| 279 | |
| 280 | } |
| 281 | |
| 282 | /* |
| 283 | * Save WakeupGen interrupt context in SAR BANK3. Restore is done by |
| 284 | * ROM code. WakeupGen IP is integrated along with GIC to manage the |
| 285 | * interrupt wakeups from CPU low power states. It manages |
| 286 | * masking/unmasking of Shared peripheral interrupts(SPI). So the |
| 287 | * interrupt enable/disable control should be in sync and consistent |
| 288 | * at WakeupGen and GIC so that interrupts are not lost. |
| 289 | */ |
| 290 | static void irq_save_context(void) |
| 291 | { |
| 292 | if (!sar_base) |
| 293 | sar_base = omap4_get_sar_ram_base(); |
| 294 | |
| 295 | if (soc_is_omap54xx()) |
| 296 | omap5_irq_save_context(); |
| 297 | else |
| 298 | omap4_irq_save_context(); |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 299 | } |
| 300 | |
| 301 | /* |
| 302 | * Clear WakeupGen SAR backup status. |
| 303 | */ |
Paul Walmsley | 8c3d453 | 2012-04-13 06:34:26 -0600 | [diff] [blame] | 304 | static void irq_sar_clear(void) |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 305 | { |
| 306 | u32 val; |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 307 | u32 offset = SAR_BACKUP_STATUS_OFFSET; |
| 308 | |
| 309 | if (soc_is_omap54xx()) |
| 310 | offset = OMAP5_SAR_BACKUP_STATUS_OFFSET; |
| 311 | |
| 312 | val = __raw_readl(sar_base + offset); |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 313 | val &= ~SAR_BACKUP_STATUS_WAKEUPGEN; |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 314 | __raw_writel(val, sar_base + offset); |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 315 | } |
| 316 | |
| 317 | /* |
| 318 | * Save GIC and Wakeupgen interrupt context using secure API |
| 319 | * for HS/EMU devices. |
| 320 | */ |
| 321 | static void irq_save_secure_context(void) |
| 322 | { |
| 323 | u32 ret; |
| 324 | ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX, |
| 325 | FLAG_START_CRITICAL, |
| 326 | 0, 0, 0, 0, 0); |
| 327 | if (ret != API_HAL_RET_VALUE_OK) |
| 328 | pr_err("GIC and Wakeupgen context save failed\n"); |
| 329 | } |
| 330 | #endif |
| 331 | |
Santosh Shilimkar | b5b4f28 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 332 | #ifdef CONFIG_HOTPLUG_CPU |
| 333 | static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self, |
| 334 | unsigned long action, void *hcpu) |
| 335 | { |
| 336 | unsigned int cpu = (unsigned int)hcpu; |
| 337 | |
| 338 | switch (action) { |
| 339 | case CPU_ONLINE: |
| 340 | wakeupgen_irqmask_all(cpu, 0); |
| 341 | break; |
| 342 | case CPU_DEAD: |
| 343 | wakeupgen_irqmask_all(cpu, 1); |
| 344 | break; |
| 345 | } |
| 346 | return NOTIFY_OK; |
| 347 | } |
| 348 | |
| 349 | static struct notifier_block __refdata irq_hotplug_notifier = { |
| 350 | .notifier_call = irq_cpu_hotplug_notify, |
| 351 | }; |
| 352 | |
| 353 | static void __init irq_hotplug_init(void) |
| 354 | { |
| 355 | register_hotcpu_notifier(&irq_hotplug_notifier); |
| 356 | } |
| 357 | #else |
| 358 | static void __init irq_hotplug_init(void) |
| 359 | {} |
| 360 | #endif |
| 361 | |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 362 | #ifdef CONFIG_CPU_PM |
| 363 | static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v) |
| 364 | { |
| 365 | switch (cmd) { |
| 366 | case CPU_CLUSTER_PM_ENTER: |
| 367 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) |
| 368 | irq_save_context(); |
| 369 | else |
| 370 | irq_save_secure_context(); |
| 371 | break; |
| 372 | case CPU_CLUSTER_PM_EXIT: |
| 373 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) |
| 374 | irq_sar_clear(); |
| 375 | break; |
| 376 | } |
| 377 | return NOTIFY_OK; |
| 378 | } |
| 379 | |
| 380 | static struct notifier_block irq_notifier_block = { |
| 381 | .notifier_call = irq_notifier, |
| 382 | }; |
| 383 | |
| 384 | static void __init irq_pm_init(void) |
| 385 | { |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 386 | /* FIXME: Remove this when MPU OSWR support is added */ |
| 387 | if (!soc_is_omap54xx()) |
| 388 | cpu_pm_register_notifier(&irq_notifier_block); |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 389 | } |
| 390 | #else |
| 391 | static void __init irq_pm_init(void) |
| 392 | {} |
| 393 | #endif |
| 394 | |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 395 | void __iomem *omap_get_wakeupgen_base(void) |
| 396 | { |
| 397 | return wakeupgen_base; |
| 398 | } |
| 399 | |
| 400 | int omap_secure_apis_support(void) |
| 401 | { |
| 402 | return omap_secure_apis; |
| 403 | } |
| 404 | |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 405 | /* |
| 406 | * Initialise the wakeupgen module. |
| 407 | */ |
| 408 | int __init omap_wakeupgen_init(void) |
| 409 | { |
| 410 | int i; |
| 411 | unsigned int boot_cpu = smp_processor_id(); |
| 412 | |
| 413 | /* Not supported on OMAP4 ES1.0 silicon */ |
| 414 | if (omap_rev() == OMAP4430_REV_ES1_0) { |
| 415 | WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n"); |
| 416 | return -EPERM; |
| 417 | } |
| 418 | |
| 419 | /* Static mapping, never released */ |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 420 | wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K); |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 421 | if (WARN_ON(!wakeupgen_base)) |
| 422 | return -ENOMEM; |
| 423 | |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 424 | if (cpu_is_omap44xx()) { |
| 425 | irq_banks = OMAP4_NR_BANKS; |
| 426 | max_irqs = OMAP4_NR_IRQS; |
| 427 | omap_secure_apis = 1; |
| 428 | } |
| 429 | |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 430 | /* Clear all IRQ bitmasks at wakeupGen level */ |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 431 | for (i = 0; i < irq_banks; i++) { |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 432 | wakeupgen_writel(0, i, CPU0_ID); |
| 433 | wakeupgen_writel(0, i, CPU1_ID); |
| 434 | } |
| 435 | |
| 436 | /* |
| 437 | * Override GIC architecture specific functions to add |
| 438 | * OMAP WakeupGen interrupt controller along with GIC |
| 439 | */ |
| 440 | gic_arch_extn.irq_mask = wakeupgen_mask; |
| 441 | gic_arch_extn.irq_unmask = wakeupgen_unmask; |
| 442 | gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE; |
| 443 | |
| 444 | /* |
| 445 | * FIXME: Add support to set_smp_affinity() once the core |
| 446 | * GIC code has necessary hooks in place. |
| 447 | */ |
| 448 | |
| 449 | /* Associate all the IRQs to boot CPU like GIC init does. */ |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 450 | for (i = 0; i < max_irqs; i++) |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 451 | irq_target_cpu[i] = boot_cpu; |
| 452 | |
Santosh Shilimkar | b5b4f28 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 453 | irq_hotplug_init(); |
Santosh Shilimkar | 0f3cf2e | 2010-06-16 23:29:31 +0530 | [diff] [blame] | 454 | irq_pm_init(); |
Santosh Shilimkar | b5b4f28 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 455 | |
Santosh Shilimkar | fcf6efa | 2010-06-16 22:19:47 +0530 | [diff] [blame] | 456 | return 0; |
| 457 | } |