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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mm/proc-sa1100.S
3 *
4 * Copyright (C) 1997-2002 Russell King
Hyok S. Choid090ddd2006-06-28 14:10:01 +01005 * hacked for non-paged-MM by Hyok S. Choi, 2003.
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * MMU functions for SA110
12 *
13 * These are the low level assembler for performing cache and TLB
14 * functions on the StrongARM-1100 and StrongARM-1110.
15 *
16 * Note that SA1100 and SA1110 share everything but their name and CPU ID.
17 *
18 * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
19 * Flush the read buffer at context switches
20 */
21#include <linux/linkage.h>
22#include <linux/init.h>
23#include <asm/assembler.h>
Sam Ravnborge6ae7442005-09-09 21:08:59 +020024#include <asm/asm-offsets.h>
Russell King5ec94072008-09-07 19:15:31 +010025#include <asm/hwcap.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010026#include <mach/hardware.h>
Russell King74945c82006-03-16 14:44:36 +000027#include <asm/pgtable-hwdef.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <asm/pgtable.h>
29
Thomas Gleixnerbb8d5a52006-07-03 02:21:18 +020030#include "proc-macros.S"
31
Linus Torvalds1da177e2005-04-16 15:20:36 -070032/*
33 * the cache line size of the I and D cache
34 */
35#define DCACHELINESIZE 32
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
Russell Kingb69874e2011-06-21 18:57:31 +010037 .section .text
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
39/*
40 * cpu_sa1100_proc_init()
41 */
42ENTRY(cpu_sa1100_proc_init)
43 mov r0, #0
44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
46 mov pc, lr
47
Linus Torvalds1da177e2005-04-16 15:20:36 -070048/*
49 * cpu_sa1100_proc_fin()
50 *
51 * Prepare the CPU for reset:
52 * - Disable interrupts
53 * - Clean and turn off caches.
54 */
55ENTRY(cpu_sa1100_proc_fin)
Russell King95f3df62006-04-07 13:17:15 +010056 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
Linus Torvalds1da177e2005-04-16 15:20:36 -070057 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
58 bic r0, r0, #0x1000 @ ...i............
59 bic r0, r0, #0x000e @ ............wca.
60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
Russell King9ca03a22010-07-26 12:22:12 +010061 mov pc, lr
Linus Torvalds1da177e2005-04-16 15:20:36 -070062
63/*
64 * cpu_sa1100_reset(loc)
65 *
66 * Perform a soft reset of the system. Put the CPU into the
67 * same state as it would be if it had been reset, and branch
68 * to what would be the reset vector.
69 *
70 * loc: location to jump to for soft reset
71 */
72 .align 5
Will Deacon1a4baaf2011-11-15 13:25:04 +000073 .pushsection .idmap.text, "ax"
Linus Torvalds1da177e2005-04-16 15:20:36 -070074ENTRY(cpu_sa1100_reset)
75 mov ip, #0
76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
77 mcr p15, 0, ip, c7, c10, 4 @ drain WB
Hyok S. Choid090ddd2006-06-28 14:10:01 +010078#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -070079 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
Hyok S. Choid090ddd2006-06-28 14:10:01 +010080#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070081 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
82 bic ip, ip, #0x000f @ ............wcam
83 bic ip, ip, #0x1100 @ ...i...s........
84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
85 mov pc, r0
Will Deacon1a4baaf2011-11-15 13:25:04 +000086ENDPROC(cpu_sa1100_reset)
87 .popsection
Linus Torvalds1da177e2005-04-16 15:20:36 -070088
89/*
90 * cpu_sa1100_do_idle(type)
91 *
92 * Cause the processor to idle
93 *
94 * type: call type:
95 * 0 = slow idle
96 * 1 = fast idle
97 * 2 = switch to slow processor clock
98 * 3 = switch to fast processor clock
99 */
100 .align 5
101ENTRY(cpu_sa1100_do_idle)
102 mov r0, r0 @ 4 nop padding
103 mov r0, r0
104 mov r0, r0
105 mov r0, r0 @ 4 nop padding
106 mov r0, r0
107 mov r0, r0
108 mov r0, #0
109 ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address
110 @ --- aligned to a cache line
111 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
112 ldr r1, [r1, #0] @ force switch to MCLK
113 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
114 mov r0, r0 @ safety
115 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
116 mov pc, lr
117
118/* ================================= CACHE ================================ */
119
120/*
121 * cpu_sa1100_dcache_clean_area(addr,sz)
122 *
123 * Clean the specified entry of any caches such that the MMU
124 * translation fetches will obtain correct data.
125 *
126 * addr: cache-unaligned virtual address
127 */
128 .align 5
129ENTRY(cpu_sa1100_dcache_clean_area)
1301: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
131 add r0, r0, #DCACHELINESIZE
132 subs r1, r1, #DCACHELINESIZE
133 bhi 1b
134 mov pc, lr
135
136/* =============================== PageTable ============================== */
137
138/*
139 * cpu_sa1100_switch_mm(pgd)
140 *
141 * Set the translation base pointer to be as described by pgd.
142 *
143 * pgd: new page tables
144 */
145 .align 5
146ENTRY(cpu_sa1100_switch_mm)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100147#ifdef CONFIG_MMU
Russell King95f3df62006-04-07 13:17:15 +0100148 str lr, [sp, #-4]!
149 bl v4wb_flush_kern_cache_all @ clears IP
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
152 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
Russell King95f3df62006-04-07 13:17:15 +0100153 ldr pc, [sp], #4
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100154#else
155 mov pc, lr
156#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157
158/*
Russell Kingad1ae2f2006-12-13 14:34:43 +0000159 * cpu_sa1100_set_pte_ext(ptep, pte, ext)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160 *
161 * Set a PTE and flush it out
162 */
163 .align 5
Russell Kingad1ae2f2006-12-13 14:34:43 +0000164ENTRY(cpu_sa1100_set_pte_ext)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100165#ifdef CONFIG_MMU
Russell Kingda091652008-09-06 17:19:08 +0100166 armv3_set_pte_ext wc_disable=0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167 mov r0, r0
168 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
169 mcr p15, 0, r0, c7, c10, 4 @ drain WB
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100170#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171 mov pc, lr
172
Russell Kingf6b0fa02011-02-06 15:48:39 +0000173.globl cpu_sa1100_suspend_size
Russell Kingde8e71c2011-08-27 22:39:09 +0100174.equ cpu_sa1100_suspend_size, 4 * 3
Russell King29ea23f2011-04-02 10:08:55 +0100175#ifdef CONFIG_PM_SLEEP
Russell Kingf6b0fa02011-02-06 15:48:39 +0000176ENTRY(cpu_sa1100_do_suspend)
Russell Kingde8e71c2011-08-27 22:39:09 +0100177 stmfd sp!, {r4 - r6, lr}
Russell Kingf6b0fa02011-02-06 15:48:39 +0000178 mrc p15, 0, r4, c3, c0, 0 @ domain ID
Russell Kingde8e71c2011-08-27 22:39:09 +0100179 mrc p15, 0, r5, c13, c0, 0 @ PID
180 mrc p15, 0, r6, c1, c0, 0 @ control reg
181 stmia r0, {r4 - r6} @ store cp regs
182 ldmfd sp!, {r4 - r6, pc}
Russell Kingf6b0fa02011-02-06 15:48:39 +0000183ENDPROC(cpu_sa1100_do_suspend)
184
185ENTRY(cpu_sa1100_do_resume)
Russell Kingde8e71c2011-08-27 22:39:09 +0100186 ldmia r0, {r4 - r6} @ load cp regs
Russell King6f354e52011-08-27 11:37:58 +0100187 mov ip, #0
188 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
189 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
190 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
191 mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB
Russell Kingf6b0fa02011-02-06 15:48:39 +0000192
193 mcr p15, 0, r4, c3, c0, 0 @ domain ID
Russell Kingde8e71c2011-08-27 22:39:09 +0100194 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
195 mcr p15, 0, r5, c13, c0, 0 @ PID
196 mov r0, r6 @ control register
Russell Kingf6b0fa02011-02-06 15:48:39 +0000197 b cpu_resume_mmu
198ENDPROC(cpu_sa1100_do_resume)
Russell Kingf6b0fa02011-02-06 15:48:39 +0000199#endif
200
Russell King5085f3f2010-10-01 15:37:05 +0100201 __CPUINIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202
203 .type __sa1100_setup, #function
204__sa1100_setup:
205 mov r0, #0
206 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
207 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100208#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100210#endif
Russell King22b190862006-06-29 15:09:57 +0100211 adr r5, sa1100_crval
212 ldmia r5, {r5, r6}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213 mrc p15, 0, r0, c1, c0 @ get control register v4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214 bic r0, r0, r5
Russell King22b190862006-06-29 15:09:57 +0100215 orr r0, r0, r6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216 mov pc, lr
217 .size __sa1100_setup, . - __sa1100_setup
218
219 /*
220 * R
221 * .RVI ZFRS BLDP WCAM
222 * ..11 0001 ..11 1101
223 *
224 */
Russell King22b190862006-06-29 15:09:57 +0100225 .type sa1100_crval, #object
226sa1100_crval:
227 crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228
229 __INITDATA
230
231/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232 * SA1100 and SA1110 share the same function calls
233 */
Dave Martinf58d59f2011-06-23 17:25:30 +0100234
235 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
236 define_processor_functions sa1100, dabort=v4_early_abort, pabort=legacy_pabort, suspend=1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237
238 .section ".rodata"
239
Dave Martinf58d59f2011-06-23 17:25:30 +0100240 string cpu_arch_name, "armv4"
241 string cpu_elf_name, "v4"
242 string cpu_sa1100_name, "StrongARM-1100"
243 string cpu_sa1110_name, "StrongARM-1110"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244
245 .align
246
Ben Dooks02b7dd12005-09-20 16:35:03 +0100247 .section ".proc.info.init", #alloc, #execinstr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248
Dave Martinf58d59f2011-06-23 17:25:30 +0100249.macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
250 .type __\name\()_proc_info,#object
251__\name\()_proc_info:
252 .long \cpu_val
253 .long \cpu_mask
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254 .long PMD_TYPE_SECT | \
255 PMD_SECT_BUFFERABLE | \
256 PMD_SECT_CACHEABLE | \
257 PMD_SECT_AP_WRITE | \
258 PMD_SECT_AP_READ
Russell King8799ee92006-06-29 18:24:21 +0100259 .long PMD_TYPE_SECT | \
260 PMD_SECT_AP_WRITE | \
261 PMD_SECT_AP_READ
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262 b __sa1100_setup
263 .long cpu_arch_name
264 .long cpu_elf_name
265 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
Dave Martinf58d59f2011-06-23 17:25:30 +0100266 .long \cpu_name
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267 .long sa1100_processor_functions
268 .long v4wb_tlb_fns
269 .long v4_mc_user_fns
270 .long v4wb_cache_fns
Dave Martinf58d59f2011-06-23 17:25:30 +0100271 .size __\name\()_proc_info, . - __\name\()_proc_info
272.endm
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273
Dave Martinf58d59f2011-06-23 17:25:30 +0100274 sa1100_proc_info sa1100, 0x4401a110, 0xfffffff0, cpu_sa1100_name
275 sa1100_proc_info sa1110, 0x6901b110, 0xfffffff0, cpu_sa1110_name