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Thierry Redinga1702852009-03-27 00:12:24 -07001/*
2 * linux/drivers/net/ethoc.c
3 *
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
12 */
13
14#include <linux/etherdevice.h>
15#include <linux/crc32.h>
16#include <linux/io.h>
17#include <linux/mii.h>
18#include <linux/phy.h>
19#include <linux/platform_device.h>
Alexey Dobriyand43c36d2009-10-07 17:09:06 +040020#include <linux/sched.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Thierry Redinga1702852009-03-27 00:12:24 -070022#include <net/ethoc.h>
23
Thomas Chou0baa0802009-10-04 23:33:20 +000024static int buffer_size = 0x8000; /* 32 KBytes */
25module_param(buffer_size, int, 0);
26MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
27
Thierry Redinga1702852009-03-27 00:12:24 -070028/* register offsets */
29#define MODER 0x00
30#define INT_SOURCE 0x04
31#define INT_MASK 0x08
32#define IPGT 0x0c
33#define IPGR1 0x10
34#define IPGR2 0x14
35#define PACKETLEN 0x18
36#define COLLCONF 0x1c
37#define TX_BD_NUM 0x20
38#define CTRLMODER 0x24
39#define MIIMODER 0x28
40#define MIICOMMAND 0x2c
41#define MIIADDRESS 0x30
42#define MIITX_DATA 0x34
43#define MIIRX_DATA 0x38
44#define MIISTATUS 0x3c
45#define MAC_ADDR0 0x40
46#define MAC_ADDR1 0x44
47#define ETH_HASH0 0x48
48#define ETH_HASH1 0x4c
49#define ETH_TXCTRL 0x50
50
51/* mode register */
52#define MODER_RXEN (1 << 0) /* receive enable */
53#define MODER_TXEN (1 << 1) /* transmit enable */
54#define MODER_NOPRE (1 << 2) /* no preamble */
55#define MODER_BRO (1 << 3) /* broadcast address */
56#define MODER_IAM (1 << 4) /* individual address mode */
57#define MODER_PRO (1 << 5) /* promiscuous mode */
58#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
59#define MODER_LOOP (1 << 7) /* loopback */
60#define MODER_NBO (1 << 8) /* no back-off */
61#define MODER_EDE (1 << 9) /* excess defer enable */
62#define MODER_FULLD (1 << 10) /* full duplex */
63#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
64#define MODER_DCRC (1 << 12) /* delayed CRC enable */
65#define MODER_CRC (1 << 13) /* CRC enable */
66#define MODER_HUGE (1 << 14) /* huge packets enable */
67#define MODER_PAD (1 << 15) /* padding enabled */
68#define MODER_RSM (1 << 16) /* receive small packets */
69
70/* interrupt source and mask registers */
71#define INT_MASK_TXF (1 << 0) /* transmit frame */
72#define INT_MASK_TXE (1 << 1) /* transmit error */
73#define INT_MASK_RXF (1 << 2) /* receive frame */
74#define INT_MASK_RXE (1 << 3) /* receive error */
75#define INT_MASK_BUSY (1 << 4)
76#define INT_MASK_TXC (1 << 5) /* transmit control frame */
77#define INT_MASK_RXC (1 << 6) /* receive control frame */
78
79#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
80#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
81
82#define INT_MASK_ALL ( \
83 INT_MASK_TXF | INT_MASK_TXE | \
84 INT_MASK_RXF | INT_MASK_RXE | \
85 INT_MASK_TXC | INT_MASK_RXC | \
86 INT_MASK_BUSY \
87 )
88
89/* packet length register */
90#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
91#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
92#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
93 PACKETLEN_MAX(max))
94
95/* transmit buffer number register */
96#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
97
98/* control module mode register */
99#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
100#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
101#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
102
103/* MII mode register */
104#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
105#define MIIMODER_NOPRE (1 << 8) /* no preamble */
106
107/* MII command register */
108#define MIICOMMAND_SCAN (1 << 0) /* scan status */
109#define MIICOMMAND_READ (1 << 1) /* read status */
110#define MIICOMMAND_WRITE (1 << 2) /* write control data */
111
112/* MII address register */
113#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
114#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
115#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
116 MIIADDRESS_RGAD(reg))
117
118/* MII transmit data register */
119#define MIITX_DATA_VAL(x) ((x) & 0xffff)
120
121/* MII receive data register */
122#define MIIRX_DATA_VAL(x) ((x) & 0xffff)
123
124/* MII status register */
125#define MIISTATUS_LINKFAIL (1 << 0)
126#define MIISTATUS_BUSY (1 << 1)
127#define MIISTATUS_INVALID (1 << 2)
128
129/* TX buffer descriptor */
130#define TX_BD_CS (1 << 0) /* carrier sense lost */
131#define TX_BD_DF (1 << 1) /* defer indication */
132#define TX_BD_LC (1 << 2) /* late collision */
133#define TX_BD_RL (1 << 3) /* retransmission limit */
134#define TX_BD_RETRY_MASK (0x00f0)
135#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
136#define TX_BD_UR (1 << 8) /* transmitter underrun */
137#define TX_BD_CRC (1 << 11) /* TX CRC enable */
138#define TX_BD_PAD (1 << 12) /* pad enable for short packets */
139#define TX_BD_WRAP (1 << 13)
140#define TX_BD_IRQ (1 << 14) /* interrupt request enable */
141#define TX_BD_READY (1 << 15) /* TX buffer ready */
142#define TX_BD_LEN(x) (((x) & 0xffff) << 16)
143#define TX_BD_LEN_MASK (0xffff << 16)
144
145#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
146 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
147
148/* RX buffer descriptor */
149#define RX_BD_LC (1 << 0) /* late collision */
150#define RX_BD_CRC (1 << 1) /* RX CRC error */
151#define RX_BD_SF (1 << 2) /* short frame */
152#define RX_BD_TL (1 << 3) /* too long */
153#define RX_BD_DN (1 << 4) /* dribble nibble */
154#define RX_BD_IS (1 << 5) /* invalid symbol */
155#define RX_BD_OR (1 << 6) /* receiver overrun */
156#define RX_BD_MISS (1 << 7)
157#define RX_BD_CF (1 << 8) /* control frame */
158#define RX_BD_WRAP (1 << 13)
159#define RX_BD_IRQ (1 << 14) /* interrupt request enable */
160#define RX_BD_EMPTY (1 << 15)
161#define RX_BD_LEN(x) (((x) & 0xffff) << 16)
162
163#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
164 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
165
166#define ETHOC_BUFSIZ 1536
167#define ETHOC_ZLEN 64
168#define ETHOC_BD_BASE 0x400
169#define ETHOC_TIMEOUT (HZ / 2)
170#define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
171
172/**
173 * struct ethoc - driver-private device structure
174 * @iobase: pointer to I/O memory region
175 * @membase: pointer to buffer memory region
Thomas Chou0baa0802009-10-04 23:33:20 +0000176 * @dma_alloc: dma allocated buffer size
Thomas Chouee02a4e2010-05-23 16:44:02 +0000177 * @io_region_size: I/O memory region size
Thierry Redinga1702852009-03-27 00:12:24 -0700178 * @num_tx: number of send buffers
179 * @cur_tx: last send buffer written
180 * @dty_tx: last buffer actually sent
181 * @num_rx: number of receive buffers
182 * @cur_rx: current receive buffer
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000183 * @vma: pointer to array of virtual memory addresses for buffers
Thierry Redinga1702852009-03-27 00:12:24 -0700184 * @netdev: pointer to network device structure
185 * @napi: NAPI structure
Thierry Redinga1702852009-03-27 00:12:24 -0700186 * @msg_enable: device state flags
187 * @rx_lock: receive lock
188 * @lock: device lock
189 * @phy: attached PHY
190 * @mdio: MDIO bus for PHY access
191 * @phy_id: address of attached PHY
192 */
193struct ethoc {
194 void __iomem *iobase;
195 void __iomem *membase;
Thomas Chou0baa0802009-10-04 23:33:20 +0000196 int dma_alloc;
Thomas Chouee02a4e2010-05-23 16:44:02 +0000197 resource_size_t io_region_size;
Thierry Redinga1702852009-03-27 00:12:24 -0700198
199 unsigned int num_tx;
200 unsigned int cur_tx;
201 unsigned int dty_tx;
202
203 unsigned int num_rx;
204 unsigned int cur_rx;
205
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000206 void** vma;
207
Thierry Redinga1702852009-03-27 00:12:24 -0700208 struct net_device *netdev;
209 struct napi_struct napi;
Thierry Redinga1702852009-03-27 00:12:24 -0700210 u32 msg_enable;
211
212 spinlock_t rx_lock;
213 spinlock_t lock;
214
215 struct phy_device *phy;
216 struct mii_bus *mdio;
217 s8 phy_id;
218};
219
220/**
221 * struct ethoc_bd - buffer descriptor
222 * @stat: buffer statistics
223 * @addr: physical memory address
224 */
225struct ethoc_bd {
226 u32 stat;
227 u32 addr;
228};
229
Thomas Chou16dd18b2009-10-07 14:16:42 +0000230static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
Thierry Redinga1702852009-03-27 00:12:24 -0700231{
232 return ioread32(dev->iobase + offset);
233}
234
Thomas Chou16dd18b2009-10-07 14:16:42 +0000235static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
Thierry Redinga1702852009-03-27 00:12:24 -0700236{
237 iowrite32(data, dev->iobase + offset);
238}
239
Thomas Chou16dd18b2009-10-07 14:16:42 +0000240static inline void ethoc_read_bd(struct ethoc *dev, int index,
241 struct ethoc_bd *bd)
Thierry Redinga1702852009-03-27 00:12:24 -0700242{
243 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
244 bd->stat = ethoc_read(dev, offset + 0);
245 bd->addr = ethoc_read(dev, offset + 4);
246}
247
Thomas Chou16dd18b2009-10-07 14:16:42 +0000248static inline void ethoc_write_bd(struct ethoc *dev, int index,
Thierry Redinga1702852009-03-27 00:12:24 -0700249 const struct ethoc_bd *bd)
250{
251 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
252 ethoc_write(dev, offset + 0, bd->stat);
253 ethoc_write(dev, offset + 4, bd->addr);
254}
255
Thomas Chou16dd18b2009-10-07 14:16:42 +0000256static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
Thierry Redinga1702852009-03-27 00:12:24 -0700257{
258 u32 imask = ethoc_read(dev, INT_MASK);
259 imask |= mask;
260 ethoc_write(dev, INT_MASK, imask);
261}
262
Thomas Chou16dd18b2009-10-07 14:16:42 +0000263static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
Thierry Redinga1702852009-03-27 00:12:24 -0700264{
265 u32 imask = ethoc_read(dev, INT_MASK);
266 imask &= ~mask;
267 ethoc_write(dev, INT_MASK, imask);
268}
269
Thomas Chou16dd18b2009-10-07 14:16:42 +0000270static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
Thierry Redinga1702852009-03-27 00:12:24 -0700271{
272 ethoc_write(dev, INT_SOURCE, mask);
273}
274
Thomas Chou16dd18b2009-10-07 14:16:42 +0000275static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700276{
277 u32 mode = ethoc_read(dev, MODER);
278 mode |= MODER_RXEN | MODER_TXEN;
279 ethoc_write(dev, MODER, mode);
280}
281
Thomas Chou16dd18b2009-10-07 14:16:42 +0000282static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700283{
284 u32 mode = ethoc_read(dev, MODER);
285 mode &= ~(MODER_RXEN | MODER_TXEN);
286 ethoc_write(dev, MODER, mode);
287}
288
David S. Miller5cf3e032010-07-07 18:23:19 -0700289static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start)
Thierry Redinga1702852009-03-27 00:12:24 -0700290{
291 struct ethoc_bd bd;
292 int i;
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000293 void* vma;
Thierry Redinga1702852009-03-27 00:12:24 -0700294
295 dev->cur_tx = 0;
296 dev->dty_tx = 0;
297 dev->cur_rx = 0;
298
Jonas Bonnee4f56b2010-06-11 02:47:36 +0000299 ethoc_write(dev, TX_BD_NUM, dev->num_tx);
300
Thierry Redinga1702852009-03-27 00:12:24 -0700301 /* setup transmission buffers */
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000302 bd.addr = mem_start;
Thierry Redinga1702852009-03-27 00:12:24 -0700303 bd.stat = TX_BD_IRQ | TX_BD_CRC;
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000304 vma = dev->membase;
Thierry Redinga1702852009-03-27 00:12:24 -0700305
306 for (i = 0; i < dev->num_tx; i++) {
307 if (i == dev->num_tx - 1)
308 bd.stat |= TX_BD_WRAP;
309
310 ethoc_write_bd(dev, i, &bd);
311 bd.addr += ETHOC_BUFSIZ;
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000312
313 dev->vma[i] = vma;
314 vma += ETHOC_BUFSIZ;
Thierry Redinga1702852009-03-27 00:12:24 -0700315 }
316
Thierry Redinga1702852009-03-27 00:12:24 -0700317 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
318
319 for (i = 0; i < dev->num_rx; i++) {
320 if (i == dev->num_rx - 1)
321 bd.stat |= RX_BD_WRAP;
322
323 ethoc_write_bd(dev, dev->num_tx + i, &bd);
324 bd.addr += ETHOC_BUFSIZ;
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000325
326 dev->vma[dev->num_tx + i] = vma;
327 vma += ETHOC_BUFSIZ;
Thierry Redinga1702852009-03-27 00:12:24 -0700328 }
329
330 return 0;
331}
332
333static int ethoc_reset(struct ethoc *dev)
334{
335 u32 mode;
336
337 /* TODO: reset controller? */
338
339 ethoc_disable_rx_and_tx(dev);
340
341 /* TODO: setup registers */
342
343 /* enable FCS generation and automatic padding */
344 mode = ethoc_read(dev, MODER);
345 mode |= MODER_CRC | MODER_PAD;
346 ethoc_write(dev, MODER, mode);
347
348 /* set full-duplex mode */
349 mode = ethoc_read(dev, MODER);
350 mode |= MODER_FULLD;
351 ethoc_write(dev, MODER, mode);
352 ethoc_write(dev, IPGT, 0x15);
353
354 ethoc_ack_irq(dev, INT_MASK_ALL);
355 ethoc_enable_irq(dev, INT_MASK_ALL);
356 ethoc_enable_rx_and_tx(dev);
357 return 0;
358}
359
360static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
361 struct ethoc_bd *bd)
362{
363 struct net_device *netdev = dev->netdev;
364 unsigned int ret = 0;
365
366 if (bd->stat & RX_BD_TL) {
367 dev_err(&netdev->dev, "RX: frame too long\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000368 netdev->stats.rx_length_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700369 ret++;
370 }
371
372 if (bd->stat & RX_BD_SF) {
373 dev_err(&netdev->dev, "RX: frame too short\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000374 netdev->stats.rx_length_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700375 ret++;
376 }
377
378 if (bd->stat & RX_BD_DN) {
379 dev_err(&netdev->dev, "RX: dribble nibble\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000380 netdev->stats.rx_frame_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700381 }
382
383 if (bd->stat & RX_BD_CRC) {
384 dev_err(&netdev->dev, "RX: wrong CRC\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000385 netdev->stats.rx_crc_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700386 ret++;
387 }
388
389 if (bd->stat & RX_BD_OR) {
390 dev_err(&netdev->dev, "RX: overrun\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000391 netdev->stats.rx_over_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700392 ret++;
393 }
394
395 if (bd->stat & RX_BD_MISS)
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000396 netdev->stats.rx_missed_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700397
398 if (bd->stat & RX_BD_LC) {
399 dev_err(&netdev->dev, "RX: late collision\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000400 netdev->stats.collisions++;
Thierry Redinga1702852009-03-27 00:12:24 -0700401 ret++;
402 }
403
404 return ret;
405}
406
407static int ethoc_rx(struct net_device *dev, int limit)
408{
409 struct ethoc *priv = netdev_priv(dev);
410 int count;
411
412 for (count = 0; count < limit; ++count) {
413 unsigned int entry;
414 struct ethoc_bd bd;
415
416 entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
417 ethoc_read_bd(priv, entry, &bd);
418 if (bd.stat & RX_BD_EMPTY)
419 break;
420
421 if (ethoc_update_rx_stats(priv, &bd) == 0) {
422 int size = bd.stat >> 16;
Eric Dumazet89d71a62009-10-13 05:34:20 +0000423 struct sk_buff *skb;
Thomas Chou050f91d2009-10-04 23:33:19 +0000424
425 size -= 4; /* strip the CRC */
Eric Dumazet89d71a62009-10-13 05:34:20 +0000426 skb = netdev_alloc_skb_ip_align(dev, size);
Thomas Chou050f91d2009-10-04 23:33:19 +0000427
Thierry Redinga1702852009-03-27 00:12:24 -0700428 if (likely(skb)) {
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000429 void *src = priv->vma[entry];
Thierry Redinga1702852009-03-27 00:12:24 -0700430 memcpy_fromio(skb_put(skb, size), src, size);
431 skb->protocol = eth_type_trans(skb, dev);
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000432 dev->stats.rx_packets++;
433 dev->stats.rx_bytes += size;
Thierry Redinga1702852009-03-27 00:12:24 -0700434 netif_receive_skb(skb);
435 } else {
436 if (net_ratelimit())
437 dev_warn(&dev->dev, "low on memory - "
438 "packet dropped\n");
439
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000440 dev->stats.rx_dropped++;
Thierry Redinga1702852009-03-27 00:12:24 -0700441 break;
442 }
443 }
444
445 /* clear the buffer descriptor so it can be reused */
446 bd.stat &= ~RX_BD_STATS;
447 bd.stat |= RX_BD_EMPTY;
448 ethoc_write_bd(priv, entry, &bd);
449 priv->cur_rx++;
450 }
451
452 return count;
453}
454
455static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
456{
457 struct net_device *netdev = dev->netdev;
458
459 if (bd->stat & TX_BD_LC) {
460 dev_err(&netdev->dev, "TX: late collision\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000461 netdev->stats.tx_window_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700462 }
463
464 if (bd->stat & TX_BD_RL) {
465 dev_err(&netdev->dev, "TX: retransmit limit\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000466 netdev->stats.tx_aborted_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700467 }
468
469 if (bd->stat & TX_BD_UR) {
470 dev_err(&netdev->dev, "TX: underrun\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000471 netdev->stats.tx_fifo_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700472 }
473
474 if (bd->stat & TX_BD_CS) {
475 dev_err(&netdev->dev, "TX: carrier sense lost\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000476 netdev->stats.tx_carrier_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700477 }
478
479 if (bd->stat & TX_BD_STATS)
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000480 netdev->stats.tx_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700481
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000482 netdev->stats.collisions += (bd->stat >> 4) & 0xf;
483 netdev->stats.tx_bytes += bd->stat >> 16;
484 netdev->stats.tx_packets++;
Thierry Redinga1702852009-03-27 00:12:24 -0700485 return 0;
486}
487
488static void ethoc_tx(struct net_device *dev)
489{
490 struct ethoc *priv = netdev_priv(dev);
491
492 spin_lock(&priv->lock);
493
494 while (priv->dty_tx != priv->cur_tx) {
495 unsigned int entry = priv->dty_tx % priv->num_tx;
496 struct ethoc_bd bd;
497
498 ethoc_read_bd(priv, entry, &bd);
499 if (bd.stat & TX_BD_READY)
500 break;
501
502 entry = (++priv->dty_tx) % priv->num_tx;
503 (void)ethoc_update_tx_stats(priv, &bd);
504 }
505
506 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
507 netif_wake_queue(dev);
508
509 ethoc_ack_irq(priv, INT_MASK_TX);
510 spin_unlock(&priv->lock);
511}
512
513static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
514{
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000515 struct net_device *dev = dev_id;
Thierry Redinga1702852009-03-27 00:12:24 -0700516 struct ethoc *priv = netdev_priv(dev);
517 u32 pending;
518
519 ethoc_disable_irq(priv, INT_MASK_ALL);
520 pending = ethoc_read(priv, INT_SOURCE);
521 if (unlikely(pending == 0)) {
522 ethoc_enable_irq(priv, INT_MASK_ALL);
523 return IRQ_NONE;
524 }
525
Thomas Chou50c54a52009-10-07 14:16:43 +0000526 ethoc_ack_irq(priv, pending);
Thierry Redinga1702852009-03-27 00:12:24 -0700527
528 if (pending & INT_MASK_BUSY) {
529 dev_err(&dev->dev, "packet dropped\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000530 dev->stats.rx_dropped++;
Thierry Redinga1702852009-03-27 00:12:24 -0700531 }
532
533 if (pending & INT_MASK_RX) {
534 if (napi_schedule_prep(&priv->napi))
535 __napi_schedule(&priv->napi);
536 } else {
537 ethoc_enable_irq(priv, INT_MASK_RX);
538 }
539
540 if (pending & INT_MASK_TX)
541 ethoc_tx(dev);
542
543 ethoc_enable_irq(priv, INT_MASK_ALL & ~INT_MASK_RX);
544 return IRQ_HANDLED;
545}
546
547static int ethoc_get_mac_address(struct net_device *dev, void *addr)
548{
549 struct ethoc *priv = netdev_priv(dev);
550 u8 *mac = (u8 *)addr;
551 u32 reg;
552
553 reg = ethoc_read(priv, MAC_ADDR0);
554 mac[2] = (reg >> 24) & 0xff;
555 mac[3] = (reg >> 16) & 0xff;
556 mac[4] = (reg >> 8) & 0xff;
557 mac[5] = (reg >> 0) & 0xff;
558
559 reg = ethoc_read(priv, MAC_ADDR1);
560 mac[0] = (reg >> 8) & 0xff;
561 mac[1] = (reg >> 0) & 0xff;
562
563 return 0;
564}
565
566static int ethoc_poll(struct napi_struct *napi, int budget)
567{
568 struct ethoc *priv = container_of(napi, struct ethoc, napi);
569 int work_done = 0;
570
571 work_done = ethoc_rx(priv->netdev, budget);
572 if (work_done < budget) {
573 ethoc_enable_irq(priv, INT_MASK_RX);
574 napi_complete(napi);
575 }
576
577 return work_done;
578}
579
580static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
581{
582 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
583 struct ethoc *priv = bus->priv;
584
585 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
586 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
587
588 while (time_before(jiffies, timeout)) {
589 u32 status = ethoc_read(priv, MIISTATUS);
590 if (!(status & MIISTATUS_BUSY)) {
591 u32 data = ethoc_read(priv, MIIRX_DATA);
592 /* reset MII command register */
593 ethoc_write(priv, MIICOMMAND, 0);
594 return data;
595 }
596
597 schedule();
598 }
599
600 return -EBUSY;
601}
602
603static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
604{
605 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
606 struct ethoc *priv = bus->priv;
607
608 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
609 ethoc_write(priv, MIITX_DATA, val);
610 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
611
612 while (time_before(jiffies, timeout)) {
613 u32 stat = ethoc_read(priv, MIISTATUS);
Jonas Bonnb46773d2010-06-11 02:47:39 +0000614 if (!(stat & MIISTATUS_BUSY)) {
615 /* reset MII command register */
616 ethoc_write(priv, MIICOMMAND, 0);
Thierry Redinga1702852009-03-27 00:12:24 -0700617 return 0;
Jonas Bonnb46773d2010-06-11 02:47:39 +0000618 }
Thierry Redinga1702852009-03-27 00:12:24 -0700619
620 schedule();
621 }
622
623 return -EBUSY;
624}
625
626static int ethoc_mdio_reset(struct mii_bus *bus)
627{
628 return 0;
629}
630
631static void ethoc_mdio_poll(struct net_device *dev)
632{
633}
634
Jonas Bonnf78f09f2010-07-26 18:45:05 -0700635static int __devinit ethoc_mdio_probe(struct net_device *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700636{
637 struct ethoc *priv = netdev_priv(dev);
638 struct phy_device *phy;
Jonas Bonn637f33b82010-06-11 02:47:37 +0000639 int err;
Thierry Redinga1702852009-03-27 00:12:24 -0700640
Jonas Bonn637f33b82010-06-11 02:47:37 +0000641 if (priv->phy_id != -1) {
642 phy = priv->mdio->phy_map[priv->phy_id];
643 } else {
644 phy = phy_find_first(priv->mdio);
Thierry Redinga1702852009-03-27 00:12:24 -0700645 }
646
647 if (!phy) {
648 dev_err(&dev->dev, "no PHY found\n");
649 return -ENXIO;
650 }
651
Jonas Bonn637f33b82010-06-11 02:47:37 +0000652 err = phy_connect_direct(dev, phy, ethoc_mdio_poll, 0,
Thierry Redinga1702852009-03-27 00:12:24 -0700653 PHY_INTERFACE_MODE_GMII);
Jonas Bonn637f33b82010-06-11 02:47:37 +0000654 if (err) {
Thierry Redinga1702852009-03-27 00:12:24 -0700655 dev_err(&dev->dev, "could not attach to PHY\n");
Jonas Bonn637f33b82010-06-11 02:47:37 +0000656 return err;
Thierry Redinga1702852009-03-27 00:12:24 -0700657 }
658
659 priv->phy = phy;
660 return 0;
661}
662
663static int ethoc_open(struct net_device *dev)
664{
665 struct ethoc *priv = netdev_priv(dev);
Thierry Redinga1702852009-03-27 00:12:24 -0700666 int ret;
667
668 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
669 dev->name, dev);
670 if (ret)
671 return ret;
672
David S. Miller5cf3e032010-07-07 18:23:19 -0700673 ethoc_init_ring(priv, dev->mem_start);
Thierry Redinga1702852009-03-27 00:12:24 -0700674 ethoc_reset(priv);
675
676 if (netif_queue_stopped(dev)) {
677 dev_dbg(&dev->dev, " resuming queue\n");
678 netif_wake_queue(dev);
679 } else {
680 dev_dbg(&dev->dev, " starting queue\n");
681 netif_start_queue(dev);
682 }
683
684 phy_start(priv->phy);
685 napi_enable(&priv->napi);
686
687 if (netif_msg_ifup(priv)) {
688 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
689 dev->base_addr, dev->mem_start, dev->mem_end);
690 }
691
692 return 0;
693}
694
695static int ethoc_stop(struct net_device *dev)
696{
697 struct ethoc *priv = netdev_priv(dev);
698
699 napi_disable(&priv->napi);
700
701 if (priv->phy)
702 phy_stop(priv->phy);
703
704 ethoc_disable_rx_and_tx(priv);
705 free_irq(dev->irq, dev);
706
707 if (!netif_queue_stopped(dev))
708 netif_stop_queue(dev);
709
710 return 0;
711}
712
713static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
714{
715 struct ethoc *priv = netdev_priv(dev);
716 struct mii_ioctl_data *mdio = if_mii(ifr);
717 struct phy_device *phy = NULL;
718
719 if (!netif_running(dev))
720 return -EINVAL;
721
722 if (cmd != SIOCGMIIPHY) {
723 if (mdio->phy_id >= PHY_MAX_ADDR)
724 return -ERANGE;
725
726 phy = priv->mdio->phy_map[mdio->phy_id];
727 if (!phy)
728 return -ENODEV;
729 } else {
730 phy = priv->phy;
731 }
732
Richard Cochran28b04112010-07-17 08:48:55 +0000733 return phy_mii_ioctl(phy, ifr, cmd);
Thierry Redinga1702852009-03-27 00:12:24 -0700734}
735
736static int ethoc_config(struct net_device *dev, struct ifmap *map)
737{
738 return -ENOSYS;
739}
740
741static int ethoc_set_mac_address(struct net_device *dev, void *addr)
742{
743 struct ethoc *priv = netdev_priv(dev);
744 u8 *mac = (u8 *)addr;
745
746 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
747 (mac[4] << 8) | (mac[5] << 0));
748 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
749
750 return 0;
751}
752
753static void ethoc_set_multicast_list(struct net_device *dev)
754{
755 struct ethoc *priv = netdev_priv(dev);
756 u32 mode = ethoc_read(priv, MODER);
Jiri Pirko22bedad32010-04-01 21:22:57 +0000757 struct netdev_hw_addr *ha;
Thierry Redinga1702852009-03-27 00:12:24 -0700758 u32 hash[2] = { 0, 0 };
759
760 /* set loopback mode if requested */
761 if (dev->flags & IFF_LOOPBACK)
762 mode |= MODER_LOOP;
763 else
764 mode &= ~MODER_LOOP;
765
766 /* receive broadcast frames if requested */
767 if (dev->flags & IFF_BROADCAST)
768 mode &= ~MODER_BRO;
769 else
770 mode |= MODER_BRO;
771
772 /* enable promiscuous mode if requested */
773 if (dev->flags & IFF_PROMISC)
774 mode |= MODER_PRO;
775 else
776 mode &= ~MODER_PRO;
777
778 ethoc_write(priv, MODER, mode);
779
780 /* receive multicast frames */
781 if (dev->flags & IFF_ALLMULTI) {
782 hash[0] = 0xffffffff;
783 hash[1] = 0xffffffff;
784 } else {
Jiri Pirko22bedad32010-04-01 21:22:57 +0000785 netdev_for_each_mc_addr(ha, dev) {
786 u32 crc = ether_crc(ETH_ALEN, ha->addr);
Thierry Redinga1702852009-03-27 00:12:24 -0700787 int bit = (crc >> 26) & 0x3f;
788 hash[bit >> 5] |= 1 << (bit & 0x1f);
789 }
790 }
791
792 ethoc_write(priv, ETH_HASH0, hash[0]);
793 ethoc_write(priv, ETH_HASH1, hash[1]);
794}
795
796static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
797{
798 return -ENOSYS;
799}
800
801static void ethoc_tx_timeout(struct net_device *dev)
802{
803 struct ethoc *priv = netdev_priv(dev);
804 u32 pending = ethoc_read(priv, INT_SOURCE);
805 if (likely(pending))
806 ethoc_interrupt(dev->irq, dev);
807}
808
809static struct net_device_stats *ethoc_stats(struct net_device *dev)
810{
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000811 return &dev->stats;
Thierry Redinga1702852009-03-27 00:12:24 -0700812}
813
Stephen Hemminger613573252009-08-31 19:50:58 +0000814static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700815{
816 struct ethoc *priv = netdev_priv(dev);
817 struct ethoc_bd bd;
818 unsigned int entry;
819 void *dest;
820
821 if (unlikely(skb->len > ETHOC_BUFSIZ)) {
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000822 dev->stats.tx_errors++;
Patrick McHardy3790c8c2009-06-12 03:00:35 +0000823 goto out;
Thierry Redinga1702852009-03-27 00:12:24 -0700824 }
825
826 entry = priv->cur_tx % priv->num_tx;
827 spin_lock_irq(&priv->lock);
828 priv->cur_tx++;
829
830 ethoc_read_bd(priv, entry, &bd);
831 if (unlikely(skb->len < ETHOC_ZLEN))
832 bd.stat |= TX_BD_PAD;
833 else
834 bd.stat &= ~TX_BD_PAD;
835
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000836 dest = priv->vma[entry];
Thierry Redinga1702852009-03-27 00:12:24 -0700837 memcpy_toio(dest, skb->data, skb->len);
838
839 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
840 bd.stat |= TX_BD_LEN(skb->len);
841 ethoc_write_bd(priv, entry, &bd);
842
843 bd.stat |= TX_BD_READY;
844 ethoc_write_bd(priv, entry, &bd);
845
846 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
847 dev_dbg(&dev->dev, "stopping queue\n");
848 netif_stop_queue(dev);
849 }
850
Thierry Redinga1702852009-03-27 00:12:24 -0700851 spin_unlock_irq(&priv->lock);
Patrick McHardy3790c8c2009-06-12 03:00:35 +0000852out:
853 dev_kfree_skb(skb);
Thierry Redinga1702852009-03-27 00:12:24 -0700854 return NETDEV_TX_OK;
855}
856
857static const struct net_device_ops ethoc_netdev_ops = {
858 .ndo_open = ethoc_open,
859 .ndo_stop = ethoc_stop,
860 .ndo_do_ioctl = ethoc_ioctl,
861 .ndo_set_config = ethoc_config,
862 .ndo_set_mac_address = ethoc_set_mac_address,
863 .ndo_set_multicast_list = ethoc_set_multicast_list,
864 .ndo_change_mtu = ethoc_change_mtu,
865 .ndo_tx_timeout = ethoc_tx_timeout,
866 .ndo_get_stats = ethoc_stats,
867 .ndo_start_xmit = ethoc_start_xmit,
868};
869
870/**
871 * ethoc_probe() - initialize OpenCores ethernet MAC
872 * pdev: platform device
873 */
Jonas Bonnf78f09f2010-07-26 18:45:05 -0700874static int __devinit ethoc_probe(struct platform_device *pdev)
Thierry Redinga1702852009-03-27 00:12:24 -0700875{
876 struct net_device *netdev = NULL;
877 struct resource *res = NULL;
878 struct resource *mmio = NULL;
879 struct resource *mem = NULL;
880 struct ethoc *priv = NULL;
881 unsigned int phy;
Jonas Bonnc527f812010-06-11 02:47:34 +0000882 int num_bd;
Thierry Redinga1702852009-03-27 00:12:24 -0700883 int ret = 0;
884
885 /* allocate networking device */
886 netdev = alloc_etherdev(sizeof(struct ethoc));
887 if (!netdev) {
888 dev_err(&pdev->dev, "cannot allocate network device\n");
889 ret = -ENOMEM;
890 goto out;
891 }
892
893 SET_NETDEV_DEV(netdev, &pdev->dev);
894 platform_set_drvdata(pdev, netdev);
895
896 /* obtain I/O memory space */
897 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
898 if (!res) {
899 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
900 ret = -ENXIO;
901 goto free;
902 }
903
904 mmio = devm_request_mem_region(&pdev->dev, res->start,
Tobias Klauserd8645842010-01-15 01:48:22 -0800905 resource_size(res), res->name);
Julia Lawall463889e2009-07-27 06:13:30 +0000906 if (!mmio) {
Thierry Redinga1702852009-03-27 00:12:24 -0700907 dev_err(&pdev->dev, "cannot request I/O memory space\n");
908 ret = -ENXIO;
909 goto free;
910 }
911
912 netdev->base_addr = mmio->start;
913
914 /* obtain buffer memory space */
915 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
Thomas Chou0baa0802009-10-04 23:33:20 +0000916 if (res) {
917 mem = devm_request_mem_region(&pdev->dev, res->start,
Tobias Klauserd8645842010-01-15 01:48:22 -0800918 resource_size(res), res->name);
Thomas Chou0baa0802009-10-04 23:33:20 +0000919 if (!mem) {
920 dev_err(&pdev->dev, "cannot request memory space\n");
921 ret = -ENXIO;
922 goto free;
923 }
924
925 netdev->mem_start = mem->start;
926 netdev->mem_end = mem->end;
Thierry Redinga1702852009-03-27 00:12:24 -0700927 }
928
Thierry Redinga1702852009-03-27 00:12:24 -0700929
930 /* obtain device IRQ number */
931 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
932 if (!res) {
933 dev_err(&pdev->dev, "cannot obtain IRQ\n");
934 ret = -ENXIO;
935 goto free;
936 }
937
938 netdev->irq = res->start;
939
940 /* setup driver-private data */
941 priv = netdev_priv(netdev);
942 priv->netdev = netdev;
Thomas Chou0baa0802009-10-04 23:33:20 +0000943 priv->dma_alloc = 0;
Thomas Chouee02a4e2010-05-23 16:44:02 +0000944 priv->io_region_size = mmio->end - mmio->start + 1;
Thierry Redinga1702852009-03-27 00:12:24 -0700945
946 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
Tobias Klauserd8645842010-01-15 01:48:22 -0800947 resource_size(mmio));
Thierry Redinga1702852009-03-27 00:12:24 -0700948 if (!priv->iobase) {
949 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
950 ret = -ENXIO;
951 goto error;
952 }
953
Thomas Chou0baa0802009-10-04 23:33:20 +0000954 if (netdev->mem_end) {
955 priv->membase = devm_ioremap_nocache(&pdev->dev,
Tobias Klauserd8645842010-01-15 01:48:22 -0800956 netdev->mem_start, resource_size(mem));
Thomas Chou0baa0802009-10-04 23:33:20 +0000957 if (!priv->membase) {
958 dev_err(&pdev->dev, "cannot remap memory space\n");
959 ret = -ENXIO;
960 goto error;
961 }
962 } else {
963 /* Allocate buffer memory */
Jonas Bonna71fba92010-06-11 02:47:40 +0000964 priv->membase = dmam_alloc_coherent(&pdev->dev,
Thomas Chou0baa0802009-10-04 23:33:20 +0000965 buffer_size, (void *)&netdev->mem_start,
966 GFP_KERNEL);
967 if (!priv->membase) {
968 dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
969 buffer_size);
970 ret = -ENOMEM;
971 goto error;
972 }
973 netdev->mem_end = netdev->mem_start + buffer_size;
974 priv->dma_alloc = buffer_size;
Thierry Redinga1702852009-03-27 00:12:24 -0700975 }
976
Jonas Bonnc527f812010-06-11 02:47:34 +0000977 /* calculate the number of TX/RX buffers, maximum 128 supported */
978 num_bd = min_t(unsigned int,
979 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
980 priv->num_tx = max(2, num_bd / 4);
981 priv->num_rx = num_bd - priv->num_tx;
982
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000983 priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void*), GFP_KERNEL);
984 if (!priv->vma) {
985 ret = -ENOMEM;
986 goto error;
987 }
988
Thierry Redinga1702852009-03-27 00:12:24 -0700989 /* Allow the platform setup code to pass in a MAC address. */
990 if (pdev->dev.platform_data) {
991 struct ethoc_platform_data *pdata =
992 (struct ethoc_platform_data *)pdev->dev.platform_data;
993 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
994 priv->phy_id = pdata->phy_id;
995 }
996
997 /* Check that the given MAC address is valid. If it isn't, read the
998 * current MAC from the controller. */
999 if (!is_valid_ether_addr(netdev->dev_addr))
1000 ethoc_get_mac_address(netdev, netdev->dev_addr);
1001
1002 /* Check the MAC again for validity, if it still isn't choose and
1003 * program a random one. */
1004 if (!is_valid_ether_addr(netdev->dev_addr))
1005 random_ether_addr(netdev->dev_addr);
1006
1007 ethoc_set_mac_address(netdev, netdev->dev_addr);
1008
1009 /* register MII bus */
1010 priv->mdio = mdiobus_alloc();
1011 if (!priv->mdio) {
1012 ret = -ENOMEM;
1013 goto free;
1014 }
1015
1016 priv->mdio->name = "ethoc-mdio";
1017 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1018 priv->mdio->name, pdev->id);
1019 priv->mdio->read = ethoc_mdio_read;
1020 priv->mdio->write = ethoc_mdio_write;
1021 priv->mdio->reset = ethoc_mdio_reset;
1022 priv->mdio->priv = priv;
1023
1024 priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1025 if (!priv->mdio->irq) {
1026 ret = -ENOMEM;
1027 goto free_mdio;
1028 }
1029
1030 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
1031 priv->mdio->irq[phy] = PHY_POLL;
1032
1033 ret = mdiobus_register(priv->mdio);
1034 if (ret) {
1035 dev_err(&netdev->dev, "failed to register MDIO bus\n");
1036 goto free_mdio;
1037 }
1038
1039 ret = ethoc_mdio_probe(netdev);
1040 if (ret) {
1041 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1042 goto error;
1043 }
1044
1045 ether_setup(netdev);
1046
1047 /* setup the net_device structure */
1048 netdev->netdev_ops = &ethoc_netdev_ops;
1049 netdev->watchdog_timeo = ETHOC_TIMEOUT;
1050 netdev->features |= 0;
1051
1052 /* setup NAPI */
Thierry Redinga1702852009-03-27 00:12:24 -07001053 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1054
1055 spin_lock_init(&priv->rx_lock);
1056 spin_lock_init(&priv->lock);
1057
1058 ret = register_netdev(netdev);
1059 if (ret < 0) {
1060 dev_err(&netdev->dev, "failed to register interface\n");
Thomas Chouee02a4e2010-05-23 16:44:02 +00001061 goto error2;
Thierry Redinga1702852009-03-27 00:12:24 -07001062 }
1063
1064 goto out;
1065
Thomas Chouee02a4e2010-05-23 16:44:02 +00001066error2:
1067 netif_napi_del(&priv->napi);
Thierry Redinga1702852009-03-27 00:12:24 -07001068error:
1069 mdiobus_unregister(priv->mdio);
1070free_mdio:
1071 kfree(priv->mdio->irq);
1072 mdiobus_free(priv->mdio);
1073free:
1074 free_netdev(netdev);
1075out:
1076 return ret;
1077}
1078
1079/**
1080 * ethoc_remove() - shutdown OpenCores ethernet MAC
1081 * @pdev: platform device
1082 */
Jonas Bonnf78f09f2010-07-26 18:45:05 -07001083static int __devexit ethoc_remove(struct platform_device *pdev)
Thierry Redinga1702852009-03-27 00:12:24 -07001084{
1085 struct net_device *netdev = platform_get_drvdata(pdev);
1086 struct ethoc *priv = netdev_priv(netdev);
1087
1088 platform_set_drvdata(pdev, NULL);
1089
1090 if (netdev) {
Thomas Chouee02a4e2010-05-23 16:44:02 +00001091 netif_napi_del(&priv->napi);
Thierry Redinga1702852009-03-27 00:12:24 -07001092 phy_disconnect(priv->phy);
1093 priv->phy = NULL;
1094
1095 if (priv->mdio) {
1096 mdiobus_unregister(priv->mdio);
1097 kfree(priv->mdio->irq);
1098 mdiobus_free(priv->mdio);
1099 }
Thierry Redinga1702852009-03-27 00:12:24 -07001100 unregister_netdev(netdev);
1101 free_netdev(netdev);
1102 }
1103
1104 return 0;
1105}
1106
1107#ifdef CONFIG_PM
1108static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1109{
1110 return -ENOSYS;
1111}
1112
1113static int ethoc_resume(struct platform_device *pdev)
1114{
1115 return -ENOSYS;
1116}
1117#else
1118# define ethoc_suspend NULL
1119# define ethoc_resume NULL
1120#endif
1121
1122static struct platform_driver ethoc_driver = {
1123 .probe = ethoc_probe,
Jonas Bonnf78f09f2010-07-26 18:45:05 -07001124 .remove = __devexit_p(ethoc_remove),
Thierry Redinga1702852009-03-27 00:12:24 -07001125 .suspend = ethoc_suspend,
1126 .resume = ethoc_resume,
1127 .driver = {
1128 .name = "ethoc",
1129 },
1130};
1131
1132static int __init ethoc_init(void)
1133{
1134 return platform_driver_register(&ethoc_driver);
1135}
1136
1137static void __exit ethoc_exit(void)
1138{
1139 platform_driver_unregister(&ethoc_driver);
1140}
1141
1142module_init(ethoc_init);
1143module_exit(ethoc_exit);
1144
1145MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1146MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1147MODULE_LICENSE("GPL v2");
1148