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David Ertmane78b80b2014-02-04 01:56:06 +00001/* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
Auke Kokbc7f75f2007-09-17 12:30:59 -070021
22/* Linux PRO/1000 Ethernet Driver main header file */
23
24#ifndef _E1000_H_
25#define _E1000_H_
26
Jeff Kirsher86d70e52011-03-25 16:01:01 +000027#include <linux/bitops.h>
Auke Kokbc7f75f2007-09-17 12:30:59 -070028#include <linux/types.h>
29#include <linux/timer.h>
30#include <linux/workqueue.h>
31#include <linux/io.h>
32#include <linux/netdevice.h>
Bruce Alland8014db2009-11-20 23:24:48 +000033#include <linux/pci.h>
Bruce Allan6f461f62010-04-27 03:33:04 +000034#include <linux/pci-aspm.h>
Bruce Allanfe46f582011-01-06 14:29:51 +000035#include <linux/crc32.h>
Jeff Kirsher86d70e52011-03-25 16:01:01 +000036#include <linux/if_vlan.h>
Richard Cochran74d23cc2014-12-21 19:46:56 +010037#include <linux/timecounter.h>
Bruce Allanb67e1912012-12-27 08:32:33 +000038#include <linux/net_tstamp.h>
Bruce Alland89777b2013-01-19 01:09:58 +000039#include <linux/ptp_clock_kernel.h>
40#include <linux/ptp_classify.h>
Bruce Allanc2ade1a2013-01-16 08:54:35 +000041#include <linux/mii.h>
Bruce Alland495bcb2013-03-20 07:23:11 +000042#include <linux/mdio.h>
Auke Kokbc7f75f2007-09-17 12:30:59 -070043#include "hw.h"
44
45struct e1000_info;
46
Jeff Kirsher44defeb2008-08-04 17:20:41 -070047#define e_dbg(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +000048 netdev_dbg(hw->adapter->netdev, format, ## arg)
Jeff Kirsher44defeb2008-08-04 17:20:41 -070049#define e_err(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +000050 netdev_err(adapter->netdev, format, ## arg)
Jeff Kirsher44defeb2008-08-04 17:20:41 -070051#define e_info(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +000052 netdev_info(adapter->netdev, format, ## arg)
Jeff Kirsher44defeb2008-08-04 17:20:41 -070053#define e_warn(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +000054 netdev_warn(adapter->netdev, format, ## arg)
Jeff Kirsher44defeb2008-08-04 17:20:41 -070055#define e_notice(format, arg...) \
Bruce Allan8544b9f2010-03-24 12:55:30 +000056 netdev_notice(adapter->netdev, format, ## arg)
Auke Kokbc7f75f2007-09-17 12:30:59 -070057
Martin Olsson98a17082009-04-22 18:21:29 +020058/* Interrupt modes, as used by the IntMode parameter */
Bruce Allan4662e822008-08-26 18:37:06 -070059#define E1000E_INT_MODE_LEGACY 0
60#define E1000E_INT_MODE_MSI 1
61#define E1000E_INT_MODE_MSIX 2
62
Bruce Allanad680762008-03-28 09:15:03 -070063/* Tx/Rx descriptor defines */
Auke Kokbc7f75f2007-09-17 12:30:59 -070064#define E1000_DEFAULT_TXD 256
65#define E1000_MAX_TXD 4096
Auke Kok7b1be192008-04-23 11:09:19 -070066#define E1000_MIN_TXD 64
Auke Kokbc7f75f2007-09-17 12:30:59 -070067
68#define E1000_DEFAULT_RXD 256
69#define E1000_MAX_RXD 4096
Auke Kok7b1be192008-04-23 11:09:19 -070070#define E1000_MIN_RXD 64
Auke Kokbc7f75f2007-09-17 12:30:59 -070071
Auke Kokde5b3072008-04-23 11:09:08 -070072#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
73#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
74
Auke Kokbc7f75f2007-09-17 12:30:59 -070075#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
76
77/* How many Tx Descriptors do we need to call netif_wake_queue ? */
78/* How many Rx Buffers do we bundle into one write to the hardware ? */
79#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
80
81#define AUTO_ALL_MODES 0
82#define E1000_EEPROM_APME 0x0400
83
84#define E1000_MNG_VLAN_NONE (-1)
85
Bruce Allan2adc55c2009-06-02 11:28:58 +000086#define DEFAULT_JUMBO 9234
87
Rafael J. Wysocki23606cf2010-03-14 14:35:17 +000088/* Time to wait before putting the device into D3 if there's no link (in ms). */
89#define LINK_TIMEOUT 100
90
Bruce Allane921eb12012-11-28 09:28:37 +000091/* Count for polling __E1000_RESET condition every 10-20msec.
Bruce Allanbb9e44d2012-03-21 00:39:12 +000092 * Experimentation has shown the reset can take approximately 210msec.
93 */
94#define E1000_CHECK_RESET_COUNT 25
95
Jesse Brandeburg3a3b7582010-09-29 21:38:49 +000096#define DEFAULT_RDTR 0
97#define DEFAULT_RADV 8
98#define BURST_RDTR 0x20
99#define BURST_RADV 0x20
100
Bruce Allane921eb12012-11-28 09:28:37 +0000101/* in the case of WTHRESH, it appears at least the 82571/2 hardware
Jesse Brandeburg3a3b7582010-09-29 21:38:49 +0000102 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
Hiroaki SHIMODA8edc0e62012-10-10 15:34:20 +0000103 * WTHRESH=4, so a setting of 5 gives the most efficient bus
104 * utilization but to avoid possible Tx stalls, set it to 1
Jesse Brandeburg3a3b7582010-09-29 21:38:49 +0000105 */
106#define E1000_TXDCTL_DMA_BURST_ENABLE \
107 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
108 E1000_TXDCTL_COUNT_DESC | \
Hiroaki SHIMODA8edc0e62012-10-10 15:34:20 +0000109 (1 << 16) | /* wthresh must be +1 more than desired */\
Jesse Brandeburg3a3b7582010-09-29 21:38:49 +0000110 (1 << 8) | /* hthresh */ \
111 0x1f) /* pthresh */
112
113#define E1000_RXDCTL_DMA_BURST_ENABLE \
114 (0x01000000 | /* set descriptor granularity */ \
115 (4 << 16) | /* set writeback threshold */ \
116 (4 << 8) | /* set prefetch threshold */ \
117 0x20) /* set hthresh */
118
119#define E1000_TIDV_FPD (1 << 31)
120#define E1000_RDTR_FPD (1 << 31)
121
Auke Kokbc7f75f2007-09-17 12:30:59 -0700122enum e1000_boards {
123 board_82571,
124 board_82572,
125 board_82573,
Bruce Allan4662e822008-08-26 18:37:06 -0700126 board_82574,
Alexander Duyck8c81c9c2009-03-19 01:12:27 +0000127 board_82583,
Auke Kokbc7f75f2007-09-17 12:30:59 -0700128 board_80003es2lan,
129 board_ich8lan,
130 board_ich9lan,
Bruce Allanf4187b52008-08-26 18:36:50 -0700131 board_ich10lan,
Bruce Allana4f58f52009-06-02 11:29:18 +0000132 board_pchlan,
Bruce Alland3738bb2010-06-16 13:27:28 +0000133 board_pch2lan,
Bruce Allan2fbe4522012-04-19 03:21:47 +0000134 board_pch_lpt,
Auke Kokbc7f75f2007-09-17 12:30:59 -0700135};
136
Auke Kokbc7f75f2007-09-17 12:30:59 -0700137struct e1000_ps_page {
138 struct page *page;
139 u64 dma; /* must be u64 - written to hw */
140};
141
Bruce Allane921eb12012-11-28 09:28:37 +0000142/* wrappers around a pointer to a socket buffer,
Auke Kokbc7f75f2007-09-17 12:30:59 -0700143 * so a DMA handle can be stored along with the buffer
144 */
145struct e1000_buffer {
146 dma_addr_t dma;
147 struct sk_buff *skb;
148 union {
Bruce Allanad680762008-03-28 09:15:03 -0700149 /* Tx */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700150 struct {
151 unsigned long time_stamp;
152 u16 length;
153 u16 next_to_watch;
Tom Herbert9ed318d2010-05-05 14:02:27 +0000154 unsigned int segs;
155 unsigned int bytecount;
Alexander Duyck03b13202009-12-02 16:45:31 +0000156 u16 mapped_as_page;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700157 };
Bruce Allanad680762008-03-28 09:15:03 -0700158 /* Rx */
Alexander Duyck03b13202009-12-02 16:45:31 +0000159 struct {
160 /* arrays of page information for packet split */
161 struct e1000_ps_page *ps_pages;
162 struct page *page;
163 };
Auke Kokbc7f75f2007-09-17 12:30:59 -0700164 };
Auke Kokbc7f75f2007-09-17 12:30:59 -0700165};
166
167struct e1000_ring {
Bruce Allan55aa6982011-12-16 00:45:45 +0000168 struct e1000_adapter *adapter; /* back pointer to adapter */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700169 void *desc; /* pointer to ring memory */
170 dma_addr_t dma; /* phys address of ring */
171 unsigned int size; /* length of ring in bytes */
172 unsigned int count; /* number of desc. in ring */
173
174 u16 next_to_use;
175 u16 next_to_clean;
176
Bruce Allanc5083cf2011-12-16 00:45:40 +0000177 void __iomem *head;
178 void __iomem *tail;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700179
180 /* array of buffer information structs */
181 struct e1000_buffer *buffer_info;
182
Bruce Allan4662e822008-08-26 18:37:06 -0700183 char name[IFNAMSIZ + 5];
184 u32 ims_val;
185 u32 itr_val;
Bruce Allanc5083cf2011-12-16 00:45:40 +0000186 void __iomem *itr_register;
Bruce Allan4662e822008-08-26 18:37:06 -0700187 int set_itr;
188
Auke Kokbc7f75f2007-09-17 12:30:59 -0700189 struct sk_buff *rx_skb_top;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700190};
191
Bruce Allan7c257692008-04-23 11:09:00 -0700192/* PHY register snapshot values */
193struct e1000_phy_regs {
194 u16 bmcr; /* basic mode control register */
195 u16 bmsr; /* basic mode status register */
196 u16 advertise; /* auto-negotiation advertisement */
197 u16 lpa; /* link partner ability register */
198 u16 expansion; /* auto-negotiation expansion reg */
199 u16 ctrl1000; /* 1000BASE-T control register */
200 u16 stat1000; /* 1000BASE-T status register */
201 u16 estatus; /* extended status register */
202};
203
Auke Kokbc7f75f2007-09-17 12:30:59 -0700204/* board specific private data structure */
205struct e1000_adapter {
206 struct timer_list watchdog_timer;
207 struct timer_list phy_info_timer;
208 struct timer_list blink_timer;
209
210 struct work_struct reset_task;
211 struct work_struct watchdog_task;
212
213 const struct e1000_info *ei;
214
Jeff Kirsher86d70e52011-03-25 16:01:01 +0000215 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
Auke Kokbc7f75f2007-09-17 12:30:59 -0700216 u32 bd_number;
217 u32 rx_buffer_len;
218 u16 mng_vlan_id;
219 u16 link_speed;
220 u16 link_duplex;
Bruce Allan84527592008-11-21 17:00:22 -0800221 u16 eeprom_vers;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700222
Auke Kokbc7f75f2007-09-17 12:30:59 -0700223 /* track device up/down/testing state */
224 unsigned long state;
225
226 /* Interrupt Throttle Rate */
227 u32 itr;
228 u32 itr_setting;
229 u16 tx_itr;
230 u16 rx_itr;
231
Bruce Allan33550ce2013-02-20 04:06:16 +0000232 /* Tx - one ring per active queue */
233 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
Bruce Alland821a4c2012-08-24 20:38:11 +0000234 u32 tx_fifo_limit;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700235
236 struct napi_struct napi;
237
Bruce Allan94fb8482013-01-23 09:00:03 +0000238 unsigned int uncorr_errors; /* uncorrectable ECC errors */
239 unsigned int corr_errors; /* correctable ECC errors */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700240 unsigned int restart_queue;
241 u32 txd_cmd;
242
243 bool detect_tx_hung;
Jeff Kirsher09357b02011-11-18 14:25:00 +0000244 bool tx_hang_recheck;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700245 u8 tx_timeout_factor;
246
247 u32 tx_int_delay;
248 u32 tx_abs_int_delay;
249
250 unsigned int total_tx_bytes;
251 unsigned int total_tx_packets;
252 unsigned int total_rx_bytes;
253 unsigned int total_rx_packets;
254
Bruce Allanad680762008-03-28 09:15:03 -0700255 /* Tx stats */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700256 u64 tpt_old;
257 u64 colc_old;
Bruce Allan7c257692008-04-23 11:09:00 -0700258 u32 gotc;
259 u64 gotc_old;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700260 u32 tx_timeout_count;
261 u32 tx_fifo_head;
262 u32 tx_head_addr;
263 u32 tx_fifo_size;
264 u32 tx_dma_failed;
Jakub Kicinski59c871c2014-03-15 14:55:00 +0000265 u32 tx_hwtstamp_timeouts;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700266
Bruce Allane921eb12012-11-28 09:28:37 +0000267 /* Rx */
David Ertmanb56083e2014-04-07 23:11:09 +0000268 bool (*clean_rx)(struct e1000_ring *ring, int *work_done,
269 int work_to_do) ____cacheline_aligned_in_smp;
270 void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count,
271 gfp_t gfp);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700272 struct e1000_ring *rx_ring;
273
274 u32 rx_int_delay;
275 u32 rx_abs_int_delay;
276
Bruce Allanad680762008-03-28 09:15:03 -0700277 /* Rx stats */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700278 u64 hw_csum_err;
279 u64 hw_csum_good;
280 u64 rx_hdr_split;
Bruce Allan7c257692008-04-23 11:09:00 -0700281 u32 gorc;
282 u64 gorc_old;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700283 u32 alloc_rx_buff_failed;
284 u32 rx_dma_failed;
Bruce Allanb67e1912012-12-27 08:32:33 +0000285 u32 rx_hwtstamp_cleared;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700286
287 unsigned int rx_ps_pages;
288 u16 rx_ps_bsize0;
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700289 u32 max_frame_size;
290 u32 min_frame_size;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700291
292 /* OS defined structs */
293 struct net_device *netdev;
294 struct pci_dev *pdev;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700295
296 /* structs defined in e1000_hw.h */
297 struct e1000_hw hw;
298
Bruce Allan9d570882013-01-04 10:06:03 +0000299 spinlock_t stats64_lock; /* protects statistics counters */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700300 struct e1000_hw_stats stats;
301 struct e1000_phy_info phy_info;
302 struct e1000_phy_stats phy_stats;
303
Bruce Allan7c257692008-04-23 11:09:00 -0700304 /* Snapshot of PHY registers */
305 struct e1000_phy_regs phy_regs;
306
Auke Kokbc7f75f2007-09-17 12:30:59 -0700307 struct e1000_ring test_tx_ring;
308 struct e1000_ring test_rx_ring;
309 u32 test_icr;
310
311 u32 msg_enable;
Jeff Kirsher8e86acd2010-08-02 14:27:23 +0000312 unsigned int num_vectors;
Bruce Allan4662e822008-08-26 18:37:06 -0700313 struct msix_entry *msix_entries;
314 int int_mode;
315 u32 eiac_mask;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700316
317 u32 eeprom_wol;
318 u32 wol;
319 u32 pba;
Bruce Allan2adc55c2009-06-02 11:28:58 +0000320 u32 max_hw_frame_size;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700321
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700322 bool fc_autoneg;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700323
Auke Kokbc7f75f2007-09-17 12:30:59 -0700324 unsigned int flags;
Jeff Kirshereb7c3ad2008-11-14 06:45:23 +0000325 unsigned int flags2;
Jesse Brandeburga8f88ff2008-10-02 16:33:25 -0700326 struct work_struct downshift_task;
327 struct work_struct update_phy_task;
Bruce Allan41cec6f2009-11-20 23:28:56 +0000328 struct work_struct print_hang_task;
Rafael J. Wysocki23606cf2010-03-14 14:35:17 +0000329
Carolyn Wybornyff10e132010-10-28 00:59:53 +0000330 int phy_hang_count;
Bruce Allan55aa6982011-12-16 00:45:45 +0000331
332 u16 tx_ring_count;
333 u16 rx_ring_count;
Bruce Allanb67e1912012-12-27 08:32:33 +0000334
335 struct hwtstamp_config hwtstamp_config;
336 struct delayed_work systim_overflow_work;
337 struct sk_buff *tx_hwtstamp_skb;
Jakub Kicinski59c871c2014-03-15 14:55:00 +0000338 unsigned long tx_hwtstamp_start;
Bruce Allanb67e1912012-12-27 08:32:33 +0000339 struct work_struct tx_hwtstamp_work;
340 spinlock_t systim_lock; /* protects SYSTIML/H regsters */
341 struct cyclecounter cc;
342 struct timecounter tc;
Bruce Alland89777b2013-01-19 01:09:58 +0000343 struct ptp_clock *ptp_clock;
344 struct ptp_clock_info ptp_clock_info;
Bruce Alland495bcb2013-03-20 07:23:11 +0000345
346 u16 eee_advert;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700347};
348
349struct e1000_info {
350 enum e1000_mac_type mac;
351 unsigned int flags;
Bruce Allan6f461f62010-04-27 03:33:04 +0000352 unsigned int flags2;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700353 u32 pba;
Bruce Allan2adc55c2009-06-02 11:28:58 +0000354 u32 max_hw_frame_size;
Jeff Kirsher69e3fd82008-04-02 13:48:18 -0700355 s32 (*get_variants)(struct e1000_adapter *);
Jeff Kirsher8ce9d6c2011-09-24 13:23:52 +0000356 const struct e1000_mac_operations *mac_ops;
357 const struct e1000_phy_operations *phy_ops;
358 const struct e1000_nvm_operations *nvm_ops;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700359};
360
Bruce Alland89777b2013-01-19 01:09:58 +0000361s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
362
Bruce Allanb67e1912012-12-27 08:32:33 +0000363/* The system time is maintained by a 64-bit counter comprised of the 32-bit
364 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore
365 * its resolution) is based on the contents of the TIMINCA register - it
366 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
367 * For the best accuracy, the incperiod should be as small as possible. The
368 * incvalue is scaled by a factor as large as possible (while still fitting
369 * in bits 23:0) so that relatively small clock corrections can be made.
370 *
371 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
372 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
373 * bits to count nanoseconds leaving the rest for fractional nonseconds.
374 */
375#define INCVALUE_96MHz 125
376#define INCVALUE_SHIFT_96MHz 17
377#define INCPERIOD_SHIFT_96MHz 2
378#define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz)
379
380#define INCVALUE_25MHz 40
381#define INCVALUE_SHIFT_25MHz 18
382#define INCPERIOD_25MHz 1
383
384/* Another drawback of scaling the incvalue by a large factor is the
385 * 64-bit SYSTIM register overflows more quickly. This is dealt with
386 * by simply reading the clock before it overflows.
387 *
388 * Clock ns bits Overflows after
389 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~
390 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
391 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours
392 */
393#define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4)
Todd Fujinaka5e7ff972014-05-03 06:41:37 +0000394#define E1000_MAX_82574_SYSTIM_REREADS 50
395#define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL)
Bruce Allanb67e1912012-12-27 08:32:33 +0000396
Auke Kokbc7f75f2007-09-17 12:30:59 -0700397/* hardware capability, feature, and workaround flags */
398#define FLAG_HAS_AMT (1 << 0)
399#define FLAG_HAS_FLASH (1 << 1)
400#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
401#define FLAG_HAS_WOL (1 << 3)
Bruce Allan79d4e902011-12-16 00:46:27 +0000402/* reserved bit4 */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700403#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
404#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
405#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
Bruce Allan4a770352008-10-01 17:18:35 -0700406#define FLAG_READ_ONLY_NVM (1 << 8)
Bruce Allan97ac8ca2008-04-29 09:16:05 -0700407#define FLAG_IS_ICH (1 << 9)
Bruce Allan4662e822008-08-26 18:37:06 -0700408#define FLAG_HAS_MSIX (1 << 10)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700409#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
410#define FLAG_IS_QUAD_PORT_A (1 << 12)
411#define FLAG_IS_QUAD_PORT (1 << 13)
Bruce Allanb67e1912012-12-27 08:32:33 +0000412#define FLAG_HAS_HW_TIMESTAMP (1 << 14)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700413#define FLAG_APME_IN_WUC (1 << 15)
414#define FLAG_APME_IN_CTRL3 (1 << 16)
415#define FLAG_APME_CHECK_PORT_B (1 << 17)
416#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
417#define FLAG_NO_WAKE_UCAST (1 << 19)
418#define FLAG_MNG_PT_ENABLED (1 << 20)
419#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
420#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
421#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
422#define FLAG_RX_NEEDS_RESTART (1 << 24)
423#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
424#define FLAG_SMART_POWER_DOWN (1 << 26)
425#define FLAG_MSI_ENABLED (1 << 27)
Bruce Allandc221292011-08-19 03:23:48 +0000426/* reserved (1 << 28) */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700427#define FLAG_TSO_FORCE (1 << 29)
Bruce Allan12d43f72012-12-05 06:26:14 +0000428#define FLAG_RESTART_NOW (1 << 30)
Bruce Allanf8d59f72008-08-08 18:36:11 -0700429#define FLAG_MSI_TEST_FAILED (1 << 31)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700430
Jeff Kirshereb7c3ad2008-11-14 06:45:23 +0000431#define FLAG2_CRC_STRIPPING (1 << 0)
Bruce Allana4f58f52009-06-02 11:29:18 +0000432#define FLAG2_HAS_PHY_WAKEUP (1 << 1)
Jesse Brandeburgb94b5022010-01-19 14:15:59 +0000433#define FLAG2_IS_DISCARDING (1 << 2)
Bruce Allan6f461f62010-04-27 03:33:04 +0000434#define FLAG2_DISABLE_ASPM_L1 (1 << 3)
Bruce Allan8c7bbb92010-06-16 13:26:41 +0000435#define FLAG2_HAS_PHY_STATS (1 << 4)
Bruce Allane52997f2010-06-16 13:27:49 +0000436#define FLAG2_HAS_EEE (1 << 5)
Jesse Brandeburg3a3b7582010-09-29 21:38:49 +0000437#define FLAG2_DMA_BURST (1 << 6)
Bruce Allan78cd29d2011-03-24 03:09:03 +0000438#define FLAG2_DISABLE_ASPM_L0S (1 << 7)
Bruce Allan828bac82010-09-29 21:39:37 +0000439#define FLAG2_DISABLE_AIM (1 << 8)
Carolyn Wybornyff10e132010-10-28 00:59:53 +0000440#define FLAG2_CHECK_PHY_HANG (1 << 9)
Bruce Allan7f99ae62011-07-22 06:21:35 +0000441#define FLAG2_NO_DISABLE_RX (1 << 10)
Bruce Allanc6e7f512011-07-29 05:53:02 +0000442#define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11)
Ben Greear01840392012-02-11 15:39:25 +0000443#define FLAG2_DFLT_CRC_STRIPPING (1 << 12)
Bruce Allanb67e1912012-12-27 08:32:33 +0000444#define FLAG2_CHECK_RX_HWTSTAMP (1 << 13)
Jeff Kirshereb7c3ad2008-11-14 06:45:23 +0000445
Auke Kokbc7f75f2007-09-17 12:30:59 -0700446#define E1000_RX_DESC_PS(R, i) \
447 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
Bruce Allan5f450212011-07-22 06:21:46 +0000448#define E1000_RX_DESC_EXT(R, i) \
449 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
Auke Kokbc7f75f2007-09-17 12:30:59 -0700450#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
Auke Kokbc7f75f2007-09-17 12:30:59 -0700451#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
452#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
453
454enum e1000_state_t {
455 __E1000_TESTING,
456 __E1000_RESETTING,
Bruce Allana90b4122011-10-07 03:50:38 +0000457 __E1000_ACCESS_SHARED_RESOURCE,
Auke Kokbc7f75f2007-09-17 12:30:59 -0700458 __E1000_DOWN
459};
460
461enum latency_range {
462 lowest_latency = 0,
463 low_latency = 1,
464 bulk_latency = 2,
465 latency_invalid = 255
466};
467
468extern char e1000e_driver_name[];
469extern const char e1000e_driver_version[];
470
Joe Perches5ccc9212013-09-23 11:37:59 -0700471void e1000e_check_options(struct e1000_adapter *adapter);
472void e1000e_set_ethtool_ops(struct net_device *netdev);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700473
Joe Perches5ccc9212013-09-23 11:37:59 -0700474int e1000e_up(struct e1000_adapter *adapter);
David Ertman28002092014-02-14 07:16:41 +0000475void e1000e_down(struct e1000_adapter *adapter, bool reset);
Joe Perches5ccc9212013-09-23 11:37:59 -0700476void e1000e_reinit_locked(struct e1000_adapter *adapter);
477void e1000e_reset(struct e1000_adapter *adapter);
478void e1000e_power_up_phy(struct e1000_adapter *adapter);
479int e1000e_setup_rx_resources(struct e1000_ring *ring);
480int e1000e_setup_tx_resources(struct e1000_ring *ring);
481void e1000e_free_rx_resources(struct e1000_ring *ring);
482void e1000e_free_tx_resources(struct e1000_ring *ring);
483struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
484 struct rtnl_link_stats64 *stats);
485void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
486void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
487void e1000e_get_hw_control(struct e1000_adapter *adapter);
488void e1000e_release_hw_control(struct e1000_adapter *adapter);
489void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700490
491extern unsigned int copybreak;
492
Jeff Kirsher8ce9d6c2011-09-24 13:23:52 +0000493extern const struct e1000_info e1000_82571_info;
494extern const struct e1000_info e1000_82572_info;
495extern const struct e1000_info e1000_82573_info;
496extern const struct e1000_info e1000_82574_info;
497extern const struct e1000_info e1000_82583_info;
498extern const struct e1000_info e1000_ich8_info;
499extern const struct e1000_info e1000_ich9_info;
500extern const struct e1000_info e1000_ich10_info;
501extern const struct e1000_info e1000_pch_info;
502extern const struct e1000_info e1000_pch2_info;
Bruce Allan2fbe4522012-04-19 03:21:47 +0000503extern const struct e1000_info e1000_pch_lpt_info;
Jeff Kirsher8ce9d6c2011-09-24 13:23:52 +0000504extern const struct e1000_info e1000_es2_info;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700505
Joe Perches5ccc9212013-09-23 11:37:59 -0700506void e1000e_ptp_init(struct e1000_adapter *adapter);
507void e1000e_ptp_remove(struct e1000_adapter *adapter);
Bruce Allan0be84012009-12-02 17:03:18 +0000508
Auke Kokbc7f75f2007-09-17 12:30:59 -0700509static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
510{
Bruce Allan94d81862009-11-20 23:25:26 +0000511 return hw->phy.ops.reset(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700512}
513
Auke Kokbc7f75f2007-09-17 12:30:59 -0700514static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
515{
Bruce Allan94d81862009-11-20 23:25:26 +0000516 return hw->phy.ops.read_reg(hw, offset, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700517}
518
Bruce Allanf1430d62012-04-14 04:21:52 +0000519static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
520{
521 return hw->phy.ops.read_reg_locked(hw, offset, data);
522}
523
Auke Kokbc7f75f2007-09-17 12:30:59 -0700524static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
525{
Bruce Allan94d81862009-11-20 23:25:26 +0000526 return hw->phy.ops.write_reg(hw, offset, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700527}
528
Bruce Allanf1430d62012-04-14 04:21:52 +0000529static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
530{
531 return hw->phy.ops.write_reg_locked(hw, offset, data);
532}
533
Joe Perches5ccc9212013-09-23 11:37:59 -0700534void e1000e_reload_nvm_generic(struct e1000_hw *hw);
Bruce Allan608f8a02010-01-13 02:04:58 +0000535
536static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
537{
538 if (hw->mac.ops.read_mac_addr)
539 return hw->mac.ops.read_mac_addr(hw);
540
541 return e1000_read_mac_addr_generic(hw);
542}
Auke Kokbc7f75f2007-09-17 12:30:59 -0700543
544static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
545{
Bruce Allan94d81862009-11-20 23:25:26 +0000546 return hw->nvm.ops.validate(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700547}
548
549static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
550{
Bruce Allan94d81862009-11-20 23:25:26 +0000551 return hw->nvm.ops.update(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700552}
553
Bruce Allanc29c3ba2013-02-20 04:05:50 +0000554static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
555 u16 *data)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700556{
Bruce Allan94d81862009-11-20 23:25:26 +0000557 return hw->nvm.ops.read(hw, offset, words, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700558}
559
Bruce Allanc29c3ba2013-02-20 04:05:50 +0000560static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
561 u16 *data)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700562{
Bruce Allan94d81862009-11-20 23:25:26 +0000563 return hw->nvm.ops.write(hw, offset, words, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700564}
565
566static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
567{
Bruce Allan94d81862009-11-20 23:25:26 +0000568 return hw->phy.ops.get_info(hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700569}
570
Auke Kokbc7f75f2007-09-17 12:30:59 -0700571static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
572{
573 return readl(hw->hw_addr + reg);
574}
575
Bruce Allanbdc125f2012-03-20 03:47:52 +0000576#define er32(reg) __er32(hw, E1000_##reg)
577
Andi Kleenc6f31482014-05-20 08:22:45 +0000578s32 __ew32_prepare(struct e1000_hw *hw);
579void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700580
Bruce Allanbdc125f2012-03-20 03:47:52 +0000581#define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
582
583#define e1e_flush() er32(STATUS)
584
585#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
586 (__ew32((a), (reg + ((offset) << 2)), (value)))
587
588#define E1000_READ_REG_ARRAY(a, reg, offset) \
589 (readl((a)->hw_addr + reg + ((offset) << 2)))
590
Auke Kokbc7f75f2007-09-17 12:30:59 -0700591#endif /* _E1000_H_ */