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Linus Torvalds1da177e2005-04-16 15:20:36 -07001comment "Processor Type"
2
3config CPU_32
4 bool
5 default y
6
7# Select CPU types depending on the architecture selected. This selects
8# which CPUs we support in the kernel image, and the compiler instruction
9# optimiser behaviour.
10
11# ARM610
12config CPU_ARM610
13 bool "Support ARM610 processor"
14 depends on ARCH_RPC
15 select CPU_32v3
16 select CPU_CACHE_V3
17 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +090018 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +010019 select CPU_COPY_V3 if MMU
20 select CPU_TLB_V3 if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 help
22 The ARM610 is the successor to the ARM3 processor
23 and was produced by VLSI Technology Inc.
24
25 Say Y if you want support for the ARM610 processor.
26 Otherwise, say N.
27
Hyok S. Choi07e0da72006-09-26 17:37:36 +090028# ARM7TDMI
29config CPU_ARM7TDMI
30 bool "Support ARM7TDMI processor"
Russell King6b237a32006-09-27 17:44:39 +010031 depends on !MMU
Hyok S. Choi07e0da72006-09-26 17:37:36 +090032 select CPU_32v4T
33 select CPU_ABRT_LV4T
34 select CPU_CACHE_V4
35 help
36 A 32-bit RISC microprocessor based on the ARM7 processor core
37 which has no memory control unit and cache.
38
39 Say Y if you want support for the ARM7TDMI processor.
40 Otherwise, say N.
41
Linus Torvalds1da177e2005-04-16 15:20:36 -070042# ARM710
43config CPU_ARM710
44 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
45 default y if ARCH_CLPS7500
46 select CPU_32v3
47 select CPU_CACHE_V3
48 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +090049 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +010050 select CPU_COPY_V3 if MMU
51 select CPU_TLB_V3 if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -070052 help
53 A 32-bit RISC microprocessor based on the ARM7 processor core
54 designed by Advanced RISC Machines Ltd. The ARM710 is the
55 successor to the ARM610 processor. It was released in
56 July 1994 by VLSI Technology Inc.
57
58 Say Y if you want support for the ARM710 processor.
59 Otherwise, say N.
60
61# ARM720T
62config CPU_ARM720T
63 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
64 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
Lennert Buytenhek260e98e2006-08-28 12:51:20 +010065 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -070066 select CPU_ABRT_LV4T
67 select CPU_CACHE_V4
68 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +090069 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +010070 select CPU_COPY_V4WT if MMU
71 select CPU_TLB_V4WT if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 help
73 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
74 MMU built around an ARM7TDMI core.
75
76 Say Y if you want support for the ARM720T processor.
77 Otherwise, say N.
78
Hyok S. Choib731c312006-09-26 17:37:50 +090079# ARM740T
80config CPU_ARM740T
81 bool "Support ARM740T processor" if ARCH_INTEGRATOR
Russell King6b237a32006-09-27 17:44:39 +010082 depends on !MMU
Hyok S. Choib731c312006-09-26 17:37:50 +090083 select CPU_32v4T
84 select CPU_ABRT_LV4T
85 select CPU_CACHE_V3 # although the core is v4t
86 select CPU_CP15_MPU
87 help
88 A 32-bit RISC processor with 8KB cache or 4KB variants,
89 write buffer and MPU(Protection Unit) built around
90 an ARM7TDMI core.
91
92 Say Y if you want support for the ARM740T processor.
93 Otherwise, say N.
94
Hyok S. Choi43f5f012006-09-26 17:38:05 +090095# ARM9TDMI
96config CPU_ARM9TDMI
97 bool "Support ARM9TDMI processor"
Russell King6b237a32006-09-27 17:44:39 +010098 depends on !MMU
Hyok S. Choi43f5f012006-09-26 17:38:05 +090099 select CPU_32v4T
Hyok S. Choi0f45d7f2006-09-28 21:46:16 +0900100 select CPU_ABRT_NOMMU
Hyok S. Choi43f5f012006-09-26 17:38:05 +0900101 select CPU_CACHE_V4
102 help
103 A 32-bit RISC microprocessor based on the ARM9 processor core
104 which has no memory control unit and cache.
105
106 Say Y if you want support for the ARM9TDMI processor.
107 Otherwise, say N.
108
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109# ARM920T
110config CPU_ARM920T
Ben Dooks3434d9d2006-06-24 21:21:28 +0100111 bool "Support ARM920T processor"
112 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
113 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
Lennert Buytenhek260e98e2006-08-28 12:51:20 +0100114 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115 select CPU_ABRT_EV4T
116 select CPU_CACHE_V4WT
117 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900118 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100119 select CPU_COPY_V4WB if MMU
120 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121 help
122 The ARM920T is licensed to be produced by numerous vendors,
123 and is used in the Maverick EP9312 and the Samsung S3C2410.
124
125 More information on the Maverick EP9312 at
126 <http://linuxdevices.com/products/PD2382866068.html>.
127
128 Say Y if you want support for the ARM920T processor.
129 Otherwise, say N.
130
131# ARM922T
132config CPU_ARM922T
133 bool "Support ARM922T processor" if ARCH_INTEGRATOR
Russell King0fec53a2006-01-08 22:37:46 +0000134 depends on ARCH_LH7A40X || ARCH_INTEGRATOR
135 default y if ARCH_LH7A40X
Lennert Buytenhek260e98e2006-08-28 12:51:20 +0100136 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137 select CPU_ABRT_EV4T
138 select CPU_CACHE_V4WT
139 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900140 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100141 select CPU_COPY_V4WB if MMU
142 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 help
144 The ARM922T is a version of the ARM920T, but with smaller
145 instruction and data caches. It is used in Altera's
146 Excalibur XA device family.
147
148 Say Y if you want support for the ARM922T processor.
149 Otherwise, say N.
150
151# ARM925T
152config CPU_ARM925T
Tony Lindgrenb288f752005-07-10 19:58:08 +0100153 bool "Support ARM925T processor" if ARCH_OMAP1
Tony Lindgren3179a012005-11-10 14:26:48 +0000154 depends on ARCH_OMAP15XX
155 default y if ARCH_OMAP15XX
Lennert Buytenhek260e98e2006-08-28 12:51:20 +0100156 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157 select CPU_ABRT_EV4T
158 select CPU_CACHE_V4WT
159 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900160 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100161 select CPU_COPY_V4WB if MMU
162 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163 help
164 The ARM925T is a mix between the ARM920T and ARM926T, but with
165 different instruction and data caches. It is used in TI's OMAP
166 device family.
167
168 Say Y if you want support for the ARM925T processor.
169 Otherwise, say N.
170
171# ARM926T
172config CPU_ARM926T
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000173 bool "Support ARM926T processor"
Andrew Victor8fc5ffa2006-06-29 16:06:33 +0100174 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
175 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176 select CPU_32v5
177 select CPU_ABRT_EV5TJ
178 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900179 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100180 select CPU_COPY_V4WB if MMU
181 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182 help
183 This is a variant of the ARM920. It has slightly different
184 instruction sequences for cache and TLB operations. Curiously,
185 there is no documentation on it at the ARM corporate website.
186
187 Say Y if you want support for the ARM926T processor.
188 Otherwise, say N.
189
Hyok S. Choid60674e2006-09-26 17:38:18 +0900190# ARM940T
191config CPU_ARM940T
192 bool "Support ARM940T processor" if ARCH_INTEGRATOR
Russell King6b237a32006-09-27 17:44:39 +0100193 depends on !MMU
Hyok S. Choid60674e2006-09-26 17:38:18 +0900194 select CPU_32v4T
Hyok S. Choi0f45d7f2006-09-28 21:46:16 +0900195 select CPU_ABRT_NOMMU
Hyok S. Choid60674e2006-09-26 17:38:18 +0900196 select CPU_CACHE_VIVT
197 select CPU_CP15_MPU
198 help
199 ARM940T is a member of the ARM9TDMI family of general-
200 purpose microprocessors with MPU and seperate 4KB
201 instruction and 4KB data cases, each with a 4-word line
202 length.
203
204 Say Y if you want support for the ARM940T processor.
205 Otherwise, say N.
206
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900207# ARM946E-S
208config CPU_ARM946E
209 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
Russell King6b237a32006-09-27 17:44:39 +0100210 depends on !MMU
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900211 select CPU_32v5
Hyok S. Choi0f45d7f2006-09-28 21:46:16 +0900212 select CPU_ABRT_NOMMU
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900213 select CPU_CACHE_VIVT
214 select CPU_CP15_MPU
215 help
216 ARM946E-S is a member of the ARM9E-S family of high-
217 performance, 32-bit system-on-chip processor solutions.
218 The TCM and ARMv5TE 32-bit instruction set is supported.
219
220 Say Y if you want support for the ARM946E-S processor.
221 Otherwise, say N.
222
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223# ARM1020 - needs validating
224config CPU_ARM1020
225 bool "Support ARM1020T (rev 0) processor"
226 depends on ARCH_INTEGRATOR
227 select CPU_32v5
228 select CPU_ABRT_EV4T
229 select CPU_CACHE_V4WT
230 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900231 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100232 select CPU_COPY_V4WB if MMU
233 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234 help
235 The ARM1020 is the 32K cached version of the ARM10 processor,
236 with an addition of a floating-point unit.
237
238 Say Y if you want support for the ARM1020 processor.
239 Otherwise, say N.
240
241# ARM1020E - needs validating
242config CPU_ARM1020E
243 bool "Support ARM1020E processor"
244 depends on ARCH_INTEGRATOR
245 select CPU_32v5
246 select CPU_ABRT_EV4T
247 select CPU_CACHE_V4WT
248 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900249 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100250 select CPU_COPY_V4WB if MMU
251 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252 depends on n
253
254# ARM1022E
255config CPU_ARM1022
256 bool "Support ARM1022E processor"
257 depends on ARCH_INTEGRATOR
258 select CPU_32v5
259 select CPU_ABRT_EV4T
260 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900261 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100262 select CPU_COPY_V4WB if MMU # can probably do better
263 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264 help
265 The ARM1022E is an implementation of the ARMv5TE architecture
266 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
267 embedded trace macrocell, and a floating-point unit.
268
269 Say Y if you want support for the ARM1022E processor.
270 Otherwise, say N.
271
272# ARM1026EJ-S
273config CPU_ARM1026
274 bool "Support ARM1026EJ-S processor"
275 depends on ARCH_INTEGRATOR
276 select CPU_32v5
277 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
278 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900279 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100280 select CPU_COPY_V4WB if MMU # can probably do better
281 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282 help
283 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
284 based upon the ARM10 integer core.
285
286 Say Y if you want support for the ARM1026EJ-S processor.
287 Otherwise, say N.
288
289# SA110
290config CPU_SA110
291 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
292 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
293 select CPU_32v3 if ARCH_RPC
294 select CPU_32v4 if !ARCH_RPC
295 select CPU_ABRT_EV4
296 select CPU_CACHE_V4WB
297 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900298 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100299 select CPU_COPY_V4WB if MMU
300 select CPU_TLB_V4WB if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301 help
302 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
303 is available at five speeds ranging from 100 MHz to 233 MHz.
304 More information is available at
305 <http://developer.intel.com/design/strong/sa110.htm>.
306
307 Say Y if you want support for the SA-110 processor.
308 Otherwise, say N.
309
310# SA1100
311config CPU_SA1100
312 bool
313 depends on ARCH_SA1100
314 default y
315 select CPU_32v4
316 select CPU_ABRT_EV4
317 select CPU_CACHE_V4WB
318 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900319 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100320 select CPU_TLB_V4WB if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321
322# XScale
323config CPU_XSCALE
324 bool
Lennert Buytenhek3f7e5812006-09-18 23:10:26 +0100325 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326 default y
327 select CPU_32v5
328 select CPU_ABRT_EV5T
329 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900330 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100331 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100333# XScale Core Version 3
334config CPU_XSC3
335 bool
336 depends on ARCH_IXP23XX
337 default y
338 select CPU_32v5
339 select CPU_ABRT_EV5T
340 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900341 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100342 select CPU_TLB_V4WBI if MMU
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100343 select IO_36
344
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345# ARMv6
346config CPU_V6
347 bool "Support ARM V6 processor"
Tony Lindgren1dbae812005-11-10 14:26:51 +0000348 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349 select CPU_32v6
350 select CPU_ABRT_EV6
351 select CPU_CACHE_V6
352 select CPU_CACHE_VIPT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900353 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100354 select CPU_COPY_V6 if MMU
355 select CPU_TLB_V6 if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356
Russell King4a5f79e2005-11-03 15:48:21 +0000357# ARMv6k
358config CPU_32v6K
359 bool "Support ARM V6K processor extensions" if !SMP
360 depends on CPU_V6
361 default y if SMP
362 help
363 Say Y here if your ARMv6 processor supports the 'K' extension.
364 This enables the kernel to use some instructions not present
365 on previous processors, and as such a kernel build with this
366 enabled will not boot on processors with do not support these
367 instructions.
368
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369# Figure out what processor architecture version we should be using.
370# This defines the compiler instruction set which depends on the machine type.
371config CPU_32v3
372 bool
Russell King60b6cf62006-06-19 17:36:43 +0100373 select TLS_REG_EMUL if SMP || !MMU
Russell King48fa14f2006-03-16 14:52:33 +0000374 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375
376config CPU_32v4
377 bool
Russell King60b6cf62006-06-19 17:36:43 +0100378 select TLS_REG_EMUL if SMP || !MMU
Russell King48fa14f2006-03-16 14:52:33 +0000379 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380
Lennert Buytenhek260e98e2006-08-28 12:51:20 +0100381config CPU_32v4T
382 bool
383 select TLS_REG_EMUL if SMP || !MMU
384 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
385
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386config CPU_32v5
387 bool
Russell King60b6cf62006-06-19 17:36:43 +0100388 select TLS_REG_EMUL if SMP || !MMU
Russell King48fa14f2006-03-16 14:52:33 +0000389 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390
391config CPU_32v6
392 bool
393
394# The abort model
Hyok S. Choi0f45d7f2006-09-28 21:46:16 +0900395config CPU_ABRT_NOMMU
396 bool
397
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398config CPU_ABRT_EV4
399 bool
400
401config CPU_ABRT_EV4T
402 bool
403
404config CPU_ABRT_LV4T
405 bool
406
407config CPU_ABRT_EV5T
408 bool
409
410config CPU_ABRT_EV5TJ
411 bool
412
413config CPU_ABRT_EV6
414 bool
415
416# The cache model
417config CPU_CACHE_V3
418 bool
419
420config CPU_CACHE_V4
421 bool
422
423config CPU_CACHE_V4WT
424 bool
425
426config CPU_CACHE_V4WB
427 bool
428
429config CPU_CACHE_V6
430 bool
431
432config CPU_CACHE_VIVT
433 bool
434
435config CPU_CACHE_VIPT
436 bool
437
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100438if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439# The copy-page model
440config CPU_COPY_V3
441 bool
442
443config CPU_COPY_V4WT
444 bool
445
446config CPU_COPY_V4WB
447 bool
448
449config CPU_COPY_V6
450 bool
451
452# This selects the TLB model
453config CPU_TLB_V3
454 bool
455 help
456 ARM Architecture Version 3 TLB.
457
458config CPU_TLB_V4WT
459 bool
460 help
461 ARM Architecture Version 4 TLB with writethrough cache.
462
463config CPU_TLB_V4WB
464 bool
465 help
466 ARM Architecture Version 4 TLB with writeback cache.
467
468config CPU_TLB_V4WBI
469 bool
470 help
471 ARM Architecture Version 4 TLB with writeback cache and invalidate
472 instruction cache entry.
473
474config CPU_TLB_V6
475 bool
476
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100477endif
478
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900479config CPU_CP15
480 bool
481 help
482 Processor has the CP15 register.
483
484config CPU_CP15_MMU
485 bool
486 select CPU_CP15
487 help
488 Processor has the CP15 register, which has MMU related registers.
489
490config CPU_CP15_MPU
491 bool
492 select CPU_CP15
493 help
494 Processor has the CP15 register, which has MPU related registers.
495
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100496#
497# CPU supports 36-bit I/O
498#
499config IO_36
500 bool
501
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502comment "Processor Features"
503
504config ARM_THUMB
505 bool "Support Thumb user binaries"
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900506 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507 default y
508 help
509 Say Y if you want to include kernel support for running user space
510 Thumb binaries.
511
512 The Thumb instruction set is a compressed form of the standard ARM
513 instruction set resulting in smaller binaries at the expense of
514 slightly less efficient code.
515
516 If you don't know what this all is, saying Y is a safe choice.
517
518config CPU_BIG_ENDIAN
519 bool "Build big-endian kernel"
520 depends on ARCH_SUPPORTS_BIG_ENDIAN
521 help
522 Say Y if you plan on running a kernel in big-endian mode.
523 Note that your board must be properly built and your board
524 port must properly enable any big-endian related features
525 of your chipset/board/processor.
526
Hyok S. Choi6afd6fa2006-09-28 21:46:34 +0900527config CPU_HIGH_VECTOR
528 depends !MMU && CPU_CP15 && !CPU_ARM740T
529 bool "Select the High exception vector"
530 default n
531 help
532 Say Y here to select high exception vector(0xFFFF0000~).
533 The exception vector can be vary depending on the platform
534 design in nommu mode. If your platform needs to select
535 high exception vector, say Y.
536 Otherwise or if you are unsure, say N, and the low exception
537 vector (0x00000000~) will be used.
538
Linus Torvalds1da177e2005-04-16 15:20:36 -0700539config CPU_ICACHE_DISABLE
Hyok S. Choif12d0d72006-09-26 17:36:37 +0900540 bool "Disable I-Cache (I-bit)"
541 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542 help
543 Say Y here to disable the processor instruction cache. Unless
544 you have a reason not to or are unsure, say N.
545
546config CPU_DCACHE_DISABLE
Hyok S. Choif12d0d72006-09-26 17:36:37 +0900547 bool "Disable D-Cache (C-bit)"
548 depends on CPU_CP15
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549 help
550 Say Y here to disable the processor data cache. Unless
551 you have a reason not to or are unsure, say N.
552
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900553config CPU_DCACHE_SIZE
554 hex
555 depends on CPU_ARM740T || CPU_ARM946E
556 default 0x00001000 if CPU_ARM740T
557 default 0x00002000 # default size for ARM946E-S
558 help
559 Some cores are synthesizable to have various sized cache. For
560 ARM946E-S case, it can vary from 0KB to 1MB.
561 To support such cache operations, it is efficient to know the size
562 before compile time.
563 If your SoC is configured to have a different size, define the value
564 here with proper conditions.
565
Linus Torvalds1da177e2005-04-16 15:20:36 -0700566config CPU_DCACHE_WRITETHROUGH
567 bool "Force write through D-cache"
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900568 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700569 default y if CPU_ARM925T
570 help
571 Say Y here to use the data cache in writethrough mode. Unless you
572 specifically require this or are unsure, say N.
573
574config CPU_CACHE_ROUND_ROBIN
575 bool "Round robin I and D cache replacement algorithm"
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900576 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577 help
578 Say Y here to use the predictable round-robin cache replacement
579 policy. Unless you specifically require this or are unsure, say N.
580
581config CPU_BPREDICT_DISABLE
582 bool "Disable branch prediction"
Catalin Marinase03eb522005-10-05 23:06:36 +0100583 depends on CPU_ARM1020 || CPU_V6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584 help
585 Say Y here to disable branch prediction. If unsure, say N.
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100586
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100587config TLS_REG_EMUL
588 bool
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100589 help
Nicolas Pitre70489c82005-05-12 19:27:12 +0100590 An SMP system using a pre-ARMv6 processor (there are apparently
591 a few prototypes like that in existence) and therefore access to
592 that required register must be emulated.
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100593
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100594config HAS_TLS_REG
595 bool
Nicolas Pitre70489c82005-05-12 19:27:12 +0100596 depends on !TLS_REG_EMUL
597 default y if SMP || CPU_32v7
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100598 help
599 This selects support for the CP15 thread register.
Nicolas Pitre70489c82005-05-12 19:27:12 +0100600 It is defined to be available on some ARMv6 processors (including
601 all SMP capable ARMv6's) or later processors. User space may
602 assume directly accessing that register and always obtain the
603 expected value only on ARMv7 and above.
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100604
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100605config NEEDS_SYSCALL_FOR_CMPXCHG
606 bool
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100607 help
608 SMP on a pre-ARMv6 processor? Well OK then.
609 Forget about fast user space cmpxchg support.
610 It is just not possible.
611