blob: 6e12bf4bc6cf73fd43b8450e891dcb656359bd2e [file] [log] [blame]
Divy Le Ray4d22de32007-01-18 22:04:14 -05001#define A_SG_CONTROL 0x0
2
3#define S_DROPPKT 20
4#define V_DROPPKT(x) ((x) << S_DROPPKT)
5#define F_DROPPKT V_DROPPKT(1U)
6
7#define S_EGRGENCTRL 19
8#define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL)
9#define F_EGRGENCTRL V_EGRGENCTRL(1U)
10
11#define S_USERSPACESIZE 14
12#define M_USERSPACESIZE 0x1f
13#define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE)
14
15#define S_HOSTPAGESIZE 11
16#define M_HOSTPAGESIZE 0x7
17#define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE)
18
19#define S_FLMODE 9
20#define V_FLMODE(x) ((x) << S_FLMODE)
21#define F_FLMODE V_FLMODE(1U)
22
23#define S_PKTSHIFT 6
24#define M_PKTSHIFT 0x7
25#define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
26
27#define S_ONEINTMULTQ 5
28#define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ)
29#define F_ONEINTMULTQ V_ONEINTMULTQ(1U)
30
31#define S_BIGENDIANINGRESS 2
32#define V_BIGENDIANINGRESS(x) ((x) << S_BIGENDIANINGRESS)
33#define F_BIGENDIANINGRESS V_BIGENDIANINGRESS(1U)
34
35#define S_ISCSICOALESCING 1
36#define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING)
37#define F_ISCSICOALESCING V_ISCSICOALESCING(1U)
38
39#define S_GLOBALENABLE 0
40#define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
41#define F_GLOBALENABLE V_GLOBALENABLE(1U)
42
43#define S_AVOIDCQOVFL 24
44#define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL)
45#define F_AVOIDCQOVFL V_AVOIDCQOVFL(1U)
46
47#define S_OPTONEINTMULTQ 23
48#define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ)
49#define F_OPTONEINTMULTQ V_OPTONEINTMULTQ(1U)
50
51#define S_CQCRDTCTRL 22
52#define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL)
53#define F_CQCRDTCTRL V_CQCRDTCTRL(1U)
54
55#define A_SG_KDOORBELL 0x4
56
57#define S_SELEGRCNTX 31
58#define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX)
59#define F_SELEGRCNTX V_SELEGRCNTX(1U)
60
61#define S_EGRCNTX 0
62#define M_EGRCNTX 0xffff
63#define V_EGRCNTX(x) ((x) << S_EGRCNTX)
64
65#define A_SG_GTS 0x8
66
67#define S_RSPQ 29
68#define M_RSPQ 0x7
69#define V_RSPQ(x) ((x) << S_RSPQ)
70#define G_RSPQ(x) (((x) >> S_RSPQ) & M_RSPQ)
71
72#define S_NEWTIMER 16
73#define M_NEWTIMER 0x1fff
74#define V_NEWTIMER(x) ((x) << S_NEWTIMER)
75
76#define S_NEWINDEX 0
77#define M_NEWINDEX 0xffff
78#define V_NEWINDEX(x) ((x) << S_NEWINDEX)
79
80#define A_SG_CONTEXT_CMD 0xc
81
82#define S_CONTEXT_CMD_OPCODE 28
83#define M_CONTEXT_CMD_OPCODE 0xf
84#define V_CONTEXT_CMD_OPCODE(x) ((x) << S_CONTEXT_CMD_OPCODE)
85
86#define S_CONTEXT_CMD_BUSY 27
87#define V_CONTEXT_CMD_BUSY(x) ((x) << S_CONTEXT_CMD_BUSY)
88#define F_CONTEXT_CMD_BUSY V_CONTEXT_CMD_BUSY(1U)
89
90#define S_CQ_CREDIT 20
91
92#define M_CQ_CREDIT 0x7f
93
94#define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT)
95
96#define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT)
97
98#define S_CQ 19
99
100#define V_CQ(x) ((x) << S_CQ)
101#define F_CQ V_CQ(1U)
102
103#define S_RESPONSEQ 18
104#define V_RESPONSEQ(x) ((x) << S_RESPONSEQ)
105#define F_RESPONSEQ V_RESPONSEQ(1U)
106
107#define S_EGRESS 17
108#define V_EGRESS(x) ((x) << S_EGRESS)
109#define F_EGRESS V_EGRESS(1U)
110
111#define S_FREELIST 16
112#define V_FREELIST(x) ((x) << S_FREELIST)
113#define F_FREELIST V_FREELIST(1U)
114
115#define S_CONTEXT 0
116#define M_CONTEXT 0xffff
117#define V_CONTEXT(x) ((x) << S_CONTEXT)
118
119#define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT)
120
121#define A_SG_CONTEXT_DATA0 0x10
122
123#define A_SG_CONTEXT_DATA1 0x14
124
125#define A_SG_CONTEXT_DATA2 0x18
126
127#define A_SG_CONTEXT_DATA3 0x1c
128
129#define A_SG_CONTEXT_MASK0 0x20
130
131#define A_SG_CONTEXT_MASK1 0x24
132
133#define A_SG_CONTEXT_MASK2 0x28
134
135#define A_SG_CONTEXT_MASK3 0x2c
136
137#define A_SG_RSPQ_CREDIT_RETURN 0x30
138
139#define S_CREDITS 0
140#define M_CREDITS 0xffff
141#define V_CREDITS(x) ((x) << S_CREDITS)
142
143#define A_SG_DATA_INTR 0x34
144
145#define S_ERRINTR 31
146#define V_ERRINTR(x) ((x) << S_ERRINTR)
147#define F_ERRINTR V_ERRINTR(1U)
148
149#define A_SG_HI_DRB_HI_THRSH 0x38
150
151#define A_SG_HI_DRB_LO_THRSH 0x3c
152
153#define A_SG_LO_DRB_HI_THRSH 0x40
154
155#define A_SG_LO_DRB_LO_THRSH 0x44
156
157#define A_SG_RSPQ_FL_STATUS 0x4c
158
159#define S_RSPQ0DISABLED 8
160
161#define A_SG_EGR_RCQ_DRB_THRSH 0x54
162
163#define S_HIRCQDRBTHRSH 16
164#define M_HIRCQDRBTHRSH 0x7ff
165#define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH)
166
167#define S_LORCQDRBTHRSH 0
168#define M_LORCQDRBTHRSH 0x7ff
169#define V_LORCQDRBTHRSH(x) ((x) << S_LORCQDRBTHRSH)
170
171#define A_SG_EGR_CNTX_BADDR 0x58
172
173#define A_SG_INT_CAUSE 0x5c
174
Divy Le Ray6e3f03b2007-08-21 20:49:10 -0700175#define S_HIPIODRBDROPERR 11
176#define V_HIPIODRBDROPERR(x) ((x) << S_HIPIODRBDROPERR)
177#define F_HIPIODRBDROPERR V_HIPIODRBDROPERR(1U)
178
179#define S_LOPIODRBDROPERR 10
180#define V_LOPIODRBDROPERR(x) ((x) << S_LOPIODRBDROPERR)
181#define F_LOPIODRBDROPERR V_LOPIODRBDROPERR(1U)
182
Divy Le Ray4d22de32007-01-18 22:04:14 -0500183#define S_RSPQDISABLED 3
184#define V_RSPQDISABLED(x) ((x) << S_RSPQDISABLED)
185#define F_RSPQDISABLED V_RSPQDISABLED(1U)
186
187#define S_RSPQCREDITOVERFOW 2
188#define V_RSPQCREDITOVERFOW(x) ((x) << S_RSPQCREDITOVERFOW)
189#define F_RSPQCREDITOVERFOW V_RSPQCREDITOVERFOW(1U)
190
191#define A_SG_INT_ENABLE 0x60
192
193#define A_SG_CMDQ_CREDIT_TH 0x64
194
195#define S_TIMEOUT 8
196#define M_TIMEOUT 0xffffff
197#define V_TIMEOUT(x) ((x) << S_TIMEOUT)
198
199#define S_THRESHOLD 0
200#define M_THRESHOLD 0xff
201#define V_THRESHOLD(x) ((x) << S_THRESHOLD)
202
203#define A_SG_TIMER_TICK 0x68
204
205#define A_SG_CQ_CONTEXT_BADDR 0x6c
206
207#define A_SG_OCO_BASE 0x70
208
209#define S_BASE1 16
210#define M_BASE1 0xffff
211#define V_BASE1(x) ((x) << S_BASE1)
212
213#define A_SG_DRB_PRI_THRESH 0x74
214
215#define A_PCIX_INT_ENABLE 0x80
216
217#define S_MSIXPARERR 22
218#define M_MSIXPARERR 0x7
219
220#define V_MSIXPARERR(x) ((x) << S_MSIXPARERR)
221
222#define S_CFPARERR 18
223#define M_CFPARERR 0xf
224
225#define V_CFPARERR(x) ((x) << S_CFPARERR)
226
227#define S_RFPARERR 14
228#define M_RFPARERR 0xf
229
230#define V_RFPARERR(x) ((x) << S_RFPARERR)
231
232#define S_WFPARERR 12
233#define M_WFPARERR 0x3
234
235#define V_WFPARERR(x) ((x) << S_WFPARERR)
236
237#define S_PIOPARERR 11
238#define V_PIOPARERR(x) ((x) << S_PIOPARERR)
239#define F_PIOPARERR V_PIOPARERR(1U)
240
241#define S_DETUNCECCERR 10
242#define V_DETUNCECCERR(x) ((x) << S_DETUNCECCERR)
243#define F_DETUNCECCERR V_DETUNCECCERR(1U)
244
245#define S_DETCORECCERR 9
246#define V_DETCORECCERR(x) ((x) << S_DETCORECCERR)
247#define F_DETCORECCERR V_DETCORECCERR(1U)
248
249#define S_RCVSPLCMPERR 8
250#define V_RCVSPLCMPERR(x) ((x) << S_RCVSPLCMPERR)
251#define F_RCVSPLCMPERR V_RCVSPLCMPERR(1U)
252
253#define S_UNXSPLCMP 7
254#define V_UNXSPLCMP(x) ((x) << S_UNXSPLCMP)
255#define F_UNXSPLCMP V_UNXSPLCMP(1U)
256
257#define S_SPLCMPDIS 6
258#define V_SPLCMPDIS(x) ((x) << S_SPLCMPDIS)
259#define F_SPLCMPDIS V_SPLCMPDIS(1U)
260
261#define S_DETPARERR 5
262#define V_DETPARERR(x) ((x) << S_DETPARERR)
263#define F_DETPARERR V_DETPARERR(1U)
264
265#define S_SIGSYSERR 4
266#define V_SIGSYSERR(x) ((x) << S_SIGSYSERR)
267#define F_SIGSYSERR V_SIGSYSERR(1U)
268
269#define S_RCVMSTABT 3
270#define V_RCVMSTABT(x) ((x) << S_RCVMSTABT)
271#define F_RCVMSTABT V_RCVMSTABT(1U)
272
273#define S_RCVTARABT 2
274#define V_RCVTARABT(x) ((x) << S_RCVTARABT)
275#define F_RCVTARABT V_RCVTARABT(1U)
276
277#define S_SIGTARABT 1
278#define V_SIGTARABT(x) ((x) << S_SIGTARABT)
279#define F_SIGTARABT V_SIGTARABT(1U)
280
281#define S_MSTDETPARERR 0
282#define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR)
283#define F_MSTDETPARERR V_MSTDETPARERR(1U)
284
285#define A_PCIX_INT_CAUSE 0x84
286
287#define A_PCIX_CFG 0x88
288
289#define S_CLIDECEN 18
290#define V_CLIDECEN(x) ((x) << S_CLIDECEN)
291#define F_CLIDECEN V_CLIDECEN(1U)
292
293#define A_PCIX_MODE 0x8c
294
295#define S_PCLKRANGE 6
296#define M_PCLKRANGE 0x3
297#define V_PCLKRANGE(x) ((x) << S_PCLKRANGE)
298#define G_PCLKRANGE(x) (((x) >> S_PCLKRANGE) & M_PCLKRANGE)
299
300#define S_PCIXINITPAT 2
301#define M_PCIXINITPAT 0xf
302#define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT)
303#define G_PCIXINITPAT(x) (((x) >> S_PCIXINITPAT) & M_PCIXINITPAT)
304
305#define S_64BIT 0
306#define V_64BIT(x) ((x) << S_64BIT)
307#define F_64BIT V_64BIT(1U)
308
309#define A_PCIE_INT_ENABLE 0x80
310
311#define S_BISTERR 15
312#define M_BISTERR 0xff
313
314#define V_BISTERR(x) ((x) << S_BISTERR)
315
316#define S_PCIE_MSIXPARERR 12
317#define M_PCIE_MSIXPARERR 0x7
318
319#define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR)
320
321#define S_PCIE_CFPARERR 11
322#define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR)
323#define F_PCIE_CFPARERR V_PCIE_CFPARERR(1U)
324
325#define S_PCIE_RFPARERR 10
326#define V_PCIE_RFPARERR(x) ((x) << S_PCIE_RFPARERR)
327#define F_PCIE_RFPARERR V_PCIE_RFPARERR(1U)
328
329#define S_PCIE_WFPARERR 9
330#define V_PCIE_WFPARERR(x) ((x) << S_PCIE_WFPARERR)
331#define F_PCIE_WFPARERR V_PCIE_WFPARERR(1U)
332
333#define S_PCIE_PIOPARERR 8
334#define V_PCIE_PIOPARERR(x) ((x) << S_PCIE_PIOPARERR)
335#define F_PCIE_PIOPARERR V_PCIE_PIOPARERR(1U)
336
337#define S_UNXSPLCPLERRC 7
338#define V_UNXSPLCPLERRC(x) ((x) << S_UNXSPLCPLERRC)
339#define F_UNXSPLCPLERRC V_UNXSPLCPLERRC(1U)
340
341#define S_UNXSPLCPLERRR 6
342#define V_UNXSPLCPLERRR(x) ((x) << S_UNXSPLCPLERRR)
343#define F_UNXSPLCPLERRR V_UNXSPLCPLERRR(1U)
344
345#define S_PEXERR 0
346#define V_PEXERR(x) ((x) << S_PEXERR)
347#define F_PEXERR V_PEXERR(1U)
348
349#define A_PCIE_INT_CAUSE 0x84
350
351#define A_PCIE_CFG 0x88
352
353#define S_PCIE_CLIDECEN 16
354#define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN)
355#define F_PCIE_CLIDECEN V_PCIE_CLIDECEN(1U)
356
357#define S_CRSTWRMMODE 0
358#define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE)
359#define F_CRSTWRMMODE V_CRSTWRMMODE(1U)
360
361#define A_PCIE_MODE 0x8c
362
363#define S_NUMFSTTRNSEQRX 10
364#define M_NUMFSTTRNSEQRX 0xff
365#define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX)
366#define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX)
367
368#define A_PCIE_PEX_CTRL0 0x98
369
370#define S_NUMFSTTRNSEQ 22
371#define M_NUMFSTTRNSEQ 0xff
372#define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ)
373#define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ)
374
375#define S_REPLAYLMT 2
376#define M_REPLAYLMT 0xfffff
377
378#define V_REPLAYLMT(x) ((x) << S_REPLAYLMT)
379
380#define A_PCIE_PEX_CTRL1 0x9c
381
382#define S_T3A_ACKLAT 0
383#define M_T3A_ACKLAT 0x7ff
384
385#define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT)
386
387#define S_ACKLAT 0
388#define M_ACKLAT 0x1fff
389
390#define V_ACKLAT(x) ((x) << S_ACKLAT)
391
392#define A_PCIE_PEX_ERR 0xa4
393
394#define A_T3DBG_GPIO_EN 0xd0
395
396#define S_GPIO11_OEN 27
397#define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
398#define F_GPIO11_OEN V_GPIO11_OEN(1U)
399
400#define S_GPIO10_OEN 26
401#define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
402#define F_GPIO10_OEN V_GPIO10_OEN(1U)
403
404#define S_GPIO7_OEN 23
405#define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
406#define F_GPIO7_OEN V_GPIO7_OEN(1U)
407
408#define S_GPIO6_OEN 22
409#define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
410#define F_GPIO6_OEN V_GPIO6_OEN(1U)
411
412#define S_GPIO5_OEN 21
413#define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
414#define F_GPIO5_OEN V_GPIO5_OEN(1U)
415
416#define S_GPIO4_OEN 20
417#define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
418#define F_GPIO4_OEN V_GPIO4_OEN(1U)
419
420#define S_GPIO2_OEN 18
421#define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
422#define F_GPIO2_OEN V_GPIO2_OEN(1U)
423
424#define S_GPIO1_OEN 17
425#define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
426#define F_GPIO1_OEN V_GPIO1_OEN(1U)
427
428#define S_GPIO0_OEN 16
429#define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
430#define F_GPIO0_OEN V_GPIO0_OEN(1U)
431
432#define S_GPIO10_OUT_VAL 10
433#define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
434#define F_GPIO10_OUT_VAL V_GPIO10_OUT_VAL(1U)
435
436#define S_GPIO7_OUT_VAL 7
437#define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
438#define F_GPIO7_OUT_VAL V_GPIO7_OUT_VAL(1U)
439
440#define S_GPIO6_OUT_VAL 6
441#define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
442#define F_GPIO6_OUT_VAL V_GPIO6_OUT_VAL(1U)
443
444#define S_GPIO5_OUT_VAL 5
445#define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
446#define F_GPIO5_OUT_VAL V_GPIO5_OUT_VAL(1U)
447
448#define S_GPIO4_OUT_VAL 4
449#define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
450#define F_GPIO4_OUT_VAL V_GPIO4_OUT_VAL(1U)
451
452#define S_GPIO2_OUT_VAL 2
453#define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
454#define F_GPIO2_OUT_VAL V_GPIO2_OUT_VAL(1U)
455
456#define S_GPIO1_OUT_VAL 1
457#define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
458#define F_GPIO1_OUT_VAL V_GPIO1_OUT_VAL(1U)
459
460#define S_GPIO0_OUT_VAL 0
461#define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
462#define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U)
463
464#define A_T3DBG_INT_ENABLE 0xd8
465
466#define S_GPIO11 11
467#define V_GPIO11(x) ((x) << S_GPIO11)
468#define F_GPIO11 V_GPIO11(1U)
469
470#define S_GPIO10 10
471#define V_GPIO10(x) ((x) << S_GPIO10)
472#define F_GPIO10 V_GPIO10(1U)
473
474#define S_GPIO7 7
475#define V_GPIO7(x) ((x) << S_GPIO7)
476#define F_GPIO7 V_GPIO7(1U)
477
478#define S_GPIO6 6
479#define V_GPIO6(x) ((x) << S_GPIO6)
480#define F_GPIO6 V_GPIO6(1U)
481
482#define S_GPIO5 5
483#define V_GPIO5(x) ((x) << S_GPIO5)
484#define F_GPIO5 V_GPIO5(1U)
485
486#define S_GPIO4 4
487#define V_GPIO4(x) ((x) << S_GPIO4)
488#define F_GPIO4 V_GPIO4(1U)
489
490#define S_GPIO3 3
491#define V_GPIO3(x) ((x) << S_GPIO3)
492#define F_GPIO3 V_GPIO3(1U)
493
494#define S_GPIO2 2
495#define V_GPIO2(x) ((x) << S_GPIO2)
496#define F_GPIO2 V_GPIO2(1U)
497
498#define S_GPIO1 1
499#define V_GPIO1(x) ((x) << S_GPIO1)
500#define F_GPIO1 V_GPIO1(1U)
501
502#define S_GPIO0 0
503#define V_GPIO0(x) ((x) << S_GPIO0)
504#define F_GPIO0 V_GPIO0(1U)
505
506#define A_T3DBG_INT_CAUSE 0xdc
507
508#define A_T3DBG_GPIO_ACT_LOW 0xf0
509
510#define MC7_PMRX_BASE_ADDR 0x100
511
512#define A_MC7_CFG 0x100
513
514#define S_IFEN 13
515#define V_IFEN(x) ((x) << S_IFEN)
516#define F_IFEN V_IFEN(1U)
517
518#define S_TERM150 11
519#define V_TERM150(x) ((x) << S_TERM150)
520#define F_TERM150 V_TERM150(1U)
521
522#define S_SLOW 10
523#define V_SLOW(x) ((x) << S_SLOW)
524#define F_SLOW V_SLOW(1U)
525
526#define S_WIDTH 8
527#define M_WIDTH 0x3
528#define V_WIDTH(x) ((x) << S_WIDTH)
529#define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
530
531#define S_BKS 6
532#define V_BKS(x) ((x) << S_BKS)
533#define F_BKS V_BKS(1U)
534
535#define S_ORG 5
536#define V_ORG(x) ((x) << S_ORG)
537#define F_ORG V_ORG(1U)
538
539#define S_DEN 2
540#define M_DEN 0x7
541#define V_DEN(x) ((x) << S_DEN)
542#define G_DEN(x) (((x) >> S_DEN) & M_DEN)
543
544#define S_RDY 1
545#define V_RDY(x) ((x) << S_RDY)
546#define F_RDY V_RDY(1U)
547
548#define S_CLKEN 0
549#define V_CLKEN(x) ((x) << S_CLKEN)
550#define F_CLKEN V_CLKEN(1U)
551
552#define A_MC7_MODE 0x104
553
554#define S_BUSY 31
555#define V_BUSY(x) ((x) << S_BUSY)
556#define F_BUSY V_BUSY(1U)
557
558#define S_BUSY 31
559#define V_BUSY(x) ((x) << S_BUSY)
560#define F_BUSY V_BUSY(1U)
561
562#define A_MC7_EXT_MODE1 0x108
563
564#define A_MC7_EXT_MODE2 0x10c
565
566#define A_MC7_EXT_MODE3 0x110
567
568#define A_MC7_PRE 0x114
569
570#define A_MC7_REF 0x118
571
572#define S_PREREFDIV 1
573#define M_PREREFDIV 0x3fff
574#define V_PREREFDIV(x) ((x) << S_PREREFDIV)
575
576#define S_PERREFEN 0
577#define V_PERREFEN(x) ((x) << S_PERREFEN)
578#define F_PERREFEN V_PERREFEN(1U)
579
580#define A_MC7_DLL 0x11c
581
582#define S_DLLENB 1
583#define V_DLLENB(x) ((x) << S_DLLENB)
584#define F_DLLENB V_DLLENB(1U)
585
586#define S_DLLRST 0
587#define V_DLLRST(x) ((x) << S_DLLRST)
588#define F_DLLRST V_DLLRST(1U)
589
590#define A_MC7_PARM 0x120
591
592#define S_ACTTOPREDLY 26
593#define M_ACTTOPREDLY 0xf
594#define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY)
595
596#define S_ACTTORDWRDLY 23
597#define M_ACTTORDWRDLY 0x7
598#define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY)
599
600#define S_PRECYC 20
601#define M_PRECYC 0x7
602#define V_PRECYC(x) ((x) << S_PRECYC)
603
604#define S_REFCYC 13
605#define M_REFCYC 0x7f
606#define V_REFCYC(x) ((x) << S_REFCYC)
607
608#define S_BKCYC 8
609#define M_BKCYC 0x1f
610#define V_BKCYC(x) ((x) << S_BKCYC)
611
612#define S_WRTORDDLY 4
613#define M_WRTORDDLY 0xf
614#define V_WRTORDDLY(x) ((x) << S_WRTORDDLY)
615
616#define S_RDTOWRDLY 0
617#define M_RDTOWRDLY 0xf
618#define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY)
619
620#define A_MC7_CAL 0x128
621
622#define S_BUSY 31
623#define V_BUSY(x) ((x) << S_BUSY)
624#define F_BUSY V_BUSY(1U)
625
626#define S_BUSY 31
627#define V_BUSY(x) ((x) << S_BUSY)
628#define F_BUSY V_BUSY(1U)
629
630#define S_CAL_FAULT 30
631#define V_CAL_FAULT(x) ((x) << S_CAL_FAULT)
632#define F_CAL_FAULT V_CAL_FAULT(1U)
633
634#define S_SGL_CAL_EN 20
635#define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN)
636#define F_SGL_CAL_EN V_SGL_CAL_EN(1U)
637
638#define A_MC7_ERR_ADDR 0x12c
639
640#define A_MC7_ECC 0x130
641
642#define S_ECCCHKEN 1
643#define V_ECCCHKEN(x) ((x) << S_ECCCHKEN)
644#define F_ECCCHKEN V_ECCCHKEN(1U)
645
646#define S_ECCGENEN 0
647#define V_ECCGENEN(x) ((x) << S_ECCGENEN)
648#define F_ECCGENEN V_ECCGENEN(1U)
649
650#define A_MC7_CE_ADDR 0x134
651
652#define A_MC7_CE_DATA0 0x138
653
654#define A_MC7_CE_DATA1 0x13c
655
656#define A_MC7_CE_DATA2 0x140
657
658#define S_DATA 0
659#define M_DATA 0xff
660
661#define G_DATA(x) (((x) >> S_DATA) & M_DATA)
662
663#define A_MC7_UE_ADDR 0x144
664
665#define A_MC7_UE_DATA0 0x148
666
667#define A_MC7_UE_DATA1 0x14c
668
669#define A_MC7_UE_DATA2 0x150
670
671#define A_MC7_BD_ADDR 0x154
672
673#define S_ADDR 3
674
675#define M_ADDR 0x1fffffff
676
677#define A_MC7_BD_DATA0 0x158
678
679#define A_MC7_BD_DATA1 0x15c
680
681#define A_MC7_BD_OP 0x164
682
683#define S_OP 0
684
685#define V_OP(x) ((x) << S_OP)
686#define F_OP V_OP(1U)
687
688#define F_OP V_OP(1U)
689#define A_SF_OP 0x6dc
690
691#define A_MC7_BIST_ADDR_BEG 0x168
692
693#define A_MC7_BIST_ADDR_END 0x16c
694
695#define A_MC7_BIST_DATA 0x170
696
697#define A_MC7_BIST_OP 0x174
698
699#define S_CONT 3
700#define V_CONT(x) ((x) << S_CONT)
701#define F_CONT V_CONT(1U)
702
703#define F_CONT V_CONT(1U)
704
705#define A_MC7_INT_ENABLE 0x178
706
707#define S_AE 17
708#define V_AE(x) ((x) << S_AE)
709#define F_AE V_AE(1U)
710
711#define S_PE 2
712#define M_PE 0x7fff
713
714#define V_PE(x) ((x) << S_PE)
715
716#define G_PE(x) (((x) >> S_PE) & M_PE)
717
718#define S_UE 1
719#define V_UE(x) ((x) << S_UE)
720#define F_UE V_UE(1U)
721
722#define S_CE 0
723#define V_CE(x) ((x) << S_CE)
724#define F_CE V_CE(1U)
725
726#define A_MC7_INT_CAUSE 0x17c
727
728#define MC7_PMTX_BASE_ADDR 0x180
729
730#define MC7_CM_BASE_ADDR 0x200
731
732#define A_CIM_BOOT_CFG 0x280
733
734#define S_BOOTADDR 2
735#define M_BOOTADDR 0x3fffffff
736#define V_BOOTADDR(x) ((x) << S_BOOTADDR)
737
738#define A_CIM_SDRAM_BASE_ADDR 0x28c
739
740#define A_CIM_SDRAM_ADDR_SIZE 0x290
741
742#define A_CIM_HOST_INT_ENABLE 0x298
743
744#define A_CIM_HOST_INT_CAUSE 0x29c
745
746#define S_BLKWRPLINT 12
747#define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
748#define F_BLKWRPLINT V_BLKWRPLINT(1U)
749
750#define S_BLKRDPLINT 11
751#define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
752#define F_BLKRDPLINT V_BLKRDPLINT(1U)
753
754#define S_BLKWRCTLINT 10
755#define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
756#define F_BLKWRCTLINT V_BLKWRCTLINT(1U)
757
758#define S_BLKRDCTLINT 9
759#define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
760#define F_BLKRDCTLINT V_BLKRDCTLINT(1U)
761
762#define S_BLKWRFLASHINT 8
763#define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
764#define F_BLKWRFLASHINT V_BLKWRFLASHINT(1U)
765
766#define S_BLKRDFLASHINT 7
767#define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
768#define F_BLKRDFLASHINT V_BLKRDFLASHINT(1U)
769
770#define S_SGLWRFLASHINT 6
771#define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
772#define F_SGLWRFLASHINT V_SGLWRFLASHINT(1U)
773
774#define S_WRBLKFLASHINT 5
775#define V_WRBLKFLASHINT(x) ((x) << S_WRBLKFLASHINT)
776#define F_WRBLKFLASHINT V_WRBLKFLASHINT(1U)
777
778#define S_BLKWRBOOTINT 4
779#define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
780#define F_BLKWRBOOTINT V_BLKWRBOOTINT(1U)
781
782#define S_FLASHRANGEINT 2
783#define V_FLASHRANGEINT(x) ((x) << S_FLASHRANGEINT)
784#define F_FLASHRANGEINT V_FLASHRANGEINT(1U)
785
786#define S_SDRAMRANGEINT 1
787#define V_SDRAMRANGEINT(x) ((x) << S_SDRAMRANGEINT)
788#define F_SDRAMRANGEINT V_SDRAMRANGEINT(1U)
789
790#define S_RSVDSPACEINT 0
791#define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
792#define F_RSVDSPACEINT V_RSVDSPACEINT(1U)
793
794#define A_CIM_HOST_ACC_CTRL 0x2b0
795
796#define S_HOSTBUSY 17
797#define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
798#define F_HOSTBUSY V_HOSTBUSY(1U)
799
800#define A_CIM_HOST_ACC_DATA 0x2b4
801
802#define A_TP_IN_CONFIG 0x300
803
804#define S_NICMODE 14
805#define V_NICMODE(x) ((x) << S_NICMODE)
806#define F_NICMODE V_NICMODE(1U)
807
808#define F_NICMODE V_NICMODE(1U)
809
810#define S_IPV6ENABLE 15
811#define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
812#define F_IPV6ENABLE V_IPV6ENABLE(1U)
813
814#define A_TP_OUT_CONFIG 0x304
815
816#define S_VLANEXTRACTIONENABLE 12
817
818#define A_TP_GLOBAL_CONFIG 0x308
819
820#define S_TXPACINGENABLE 24
821#define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
822#define F_TXPACINGENABLE V_TXPACINGENABLE(1U)
823
824#define S_PATHMTU 15
825#define V_PATHMTU(x) ((x) << S_PATHMTU)
826#define F_PATHMTU V_PATHMTU(1U)
827
828#define S_IPCHECKSUMOFFLOAD 13
829#define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
830#define F_IPCHECKSUMOFFLOAD V_IPCHECKSUMOFFLOAD(1U)
831
832#define S_UDPCHECKSUMOFFLOAD 12
833#define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
834#define F_UDPCHECKSUMOFFLOAD V_UDPCHECKSUMOFFLOAD(1U)
835
836#define S_TCPCHECKSUMOFFLOAD 11
837#define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
838#define F_TCPCHECKSUMOFFLOAD V_TCPCHECKSUMOFFLOAD(1U)
839
840#define S_IPTTL 0
841#define M_IPTTL 0xff
842#define V_IPTTL(x) ((x) << S_IPTTL)
843
844#define A_TP_CMM_MM_BASE 0x314
845
846#define A_TP_CMM_TIMER_BASE 0x318
847
848#define S_CMTIMERMAXNUM 28
849#define M_CMTIMERMAXNUM 0x3
850#define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
851
852#define A_TP_PMM_SIZE 0x31c
853
854#define A_TP_PMM_TX_BASE 0x320
855
856#define A_TP_PMM_RX_BASE 0x328
857
858#define A_TP_PMM_RX_PAGE_SIZE 0x32c
859
860#define A_TP_PMM_RX_MAX_PAGE 0x330
861
862#define A_TP_PMM_TX_PAGE_SIZE 0x334
863
864#define A_TP_PMM_TX_MAX_PAGE 0x338
865
866#define A_TP_TCP_OPTIONS 0x340
867
868#define S_MTUDEFAULT 16
869#define M_MTUDEFAULT 0xffff
870#define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
871
872#define S_MTUENABLE 10
873#define V_MTUENABLE(x) ((x) << S_MTUENABLE)
874#define F_MTUENABLE V_MTUENABLE(1U)
875
876#define S_SACKRX 8
877#define V_SACKRX(x) ((x) << S_SACKRX)
878#define F_SACKRX V_SACKRX(1U)
879
880#define S_SACKMODE 4
881
882#define M_SACKMODE 0x3
883
884#define V_SACKMODE(x) ((x) << S_SACKMODE)
885
886#define S_WINDOWSCALEMODE 2
887#define M_WINDOWSCALEMODE 0x3
888#define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
889
890#define S_TIMESTAMPSMODE 0
891
892#define M_TIMESTAMPSMODE 0x3
893
894#define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
895
896#define A_TP_DACK_CONFIG 0x344
897
898#define S_AUTOSTATE3 30
899#define M_AUTOSTATE3 0x3
900#define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
901
902#define S_AUTOSTATE2 28
903#define M_AUTOSTATE2 0x3
904#define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
905
906#define S_AUTOSTATE1 26
907#define M_AUTOSTATE1 0x3
908#define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
909
910#define S_BYTETHRESHOLD 5
911#define M_BYTETHRESHOLD 0xfffff
912#define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
913
914#define S_MSSTHRESHOLD 3
915#define M_MSSTHRESHOLD 0x3
916#define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
917
918#define S_AUTOCAREFUL 2
919#define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
920#define F_AUTOCAREFUL V_AUTOCAREFUL(1U)
921
922#define S_AUTOENABLE 1
923#define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
924#define F_AUTOENABLE V_AUTOENABLE(1U)
925
926#define S_DACK_MODE 0
927#define V_DACK_MODE(x) ((x) << S_DACK_MODE)
928#define F_DACK_MODE V_DACK_MODE(1U)
929
930#define A_TP_PC_CONFIG 0x348
931
932#define S_TXTOSQUEUEMAPMODE 26
933#define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE)
934#define F_TXTOSQUEUEMAPMODE V_TXTOSQUEUEMAPMODE(1U)
935
936#define S_ENABLEEPCMDAFULL 23
937#define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
938#define F_ENABLEEPCMDAFULL V_ENABLEEPCMDAFULL(1U)
939
940#define S_MODULATEUNIONMODE 22
941#define V_MODULATEUNIONMODE(x) ((x) << S_MODULATEUNIONMODE)
942#define F_MODULATEUNIONMODE V_MODULATEUNIONMODE(1U)
943
944#define S_TXDEFERENABLE 20
945#define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
946#define F_TXDEFERENABLE V_TXDEFERENABLE(1U)
947
948#define S_RXCONGESTIONMODE 19
949#define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
950#define F_RXCONGESTIONMODE V_RXCONGESTIONMODE(1U)
951
952#define S_HEARBEATDACK 16
953#define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
954#define F_HEARBEATDACK V_HEARBEATDACK(1U)
955
956#define S_TXCONGESTIONMODE 15
957#define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
958#define F_TXCONGESTIONMODE V_TXCONGESTIONMODE(1U)
959
960#define S_ENABLEOCSPIFULL 30
961#define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
962#define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U)
963
964#define S_LOCKTID 28
965#define V_LOCKTID(x) ((x) << S_LOCKTID)
966#define F_LOCKTID V_LOCKTID(1U)
967
968#define A_TP_PC_CONFIG2 0x34c
969
970#define S_CHDRAFULL 4
971#define V_CHDRAFULL(x) ((x) << S_CHDRAFULL)
972#define F_CHDRAFULL V_CHDRAFULL(1U)
973
974#define A_TP_TCP_BACKOFF_REG0 0x350
975
976#define A_TP_TCP_BACKOFF_REG1 0x354
977
978#define A_TP_TCP_BACKOFF_REG2 0x358
979
980#define A_TP_TCP_BACKOFF_REG3 0x35c
981
982#define A_TP_PARA_REG2 0x368
983
984#define S_MAXRXDATA 16
985#define M_MAXRXDATA 0xffff
986#define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
987
988#define S_RXCOALESCESIZE 0
989#define M_RXCOALESCESIZE 0xffff
990#define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
991
992#define A_TP_PARA_REG3 0x36c
993
994#define S_TXDATAACKIDX 16
995#define M_TXDATAACKIDX 0xf
996
997#define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
998
999#define S_TXPACEAUTOSTRICT 10
1000#define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
1001#define F_TXPACEAUTOSTRICT V_TXPACEAUTOSTRICT(1U)
1002
1003#define S_TXPACEFIXED 9
1004#define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
1005#define F_TXPACEFIXED V_TXPACEFIXED(1U)
1006
1007#define S_TXPACEAUTO 8
1008#define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
1009#define F_TXPACEAUTO V_TXPACEAUTO(1U)
1010
1011#define S_RXCOALESCEENABLE 1
1012#define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
1013#define F_RXCOALESCEENABLE V_RXCOALESCEENABLE(1U)
1014
1015#define S_RXCOALESCEPSHEN 0
1016#define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
1017#define F_RXCOALESCEPSHEN V_RXCOALESCEPSHEN(1U)
1018
1019#define A_TP_PARA_REG4 0x370
1020
1021#define A_TP_PARA_REG6 0x378
1022
1023#define S_T3A_ENABLEESND 13
1024#define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND)
1025#define F_T3A_ENABLEESND V_T3A_ENABLEESND(1U)
1026
1027#define S_ENABLEESND 11
1028#define V_ENABLEESND(x) ((x) << S_ENABLEESND)
1029#define F_ENABLEESND V_ENABLEESND(1U)
1030
1031#define A_TP_PARA_REG7 0x37c
1032
1033#define S_PMMAXXFERLEN1 16
1034#define M_PMMAXXFERLEN1 0xffff
1035#define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
1036
1037#define S_PMMAXXFERLEN0 0
1038#define M_PMMAXXFERLEN0 0xffff
1039#define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
1040
1041#define A_TP_TIMER_RESOLUTION 0x390
1042
1043#define S_TIMERRESOLUTION 16
1044#define M_TIMERRESOLUTION 0xff
1045#define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
1046
1047#define S_TIMESTAMPRESOLUTION 8
1048#define M_TIMESTAMPRESOLUTION 0xff
1049#define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
1050
1051#define S_DELAYEDACKRESOLUTION 0
1052#define M_DELAYEDACKRESOLUTION 0xff
1053#define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
1054
1055#define A_TP_MSL 0x394
1056
1057#define A_TP_RXT_MIN 0x398
1058
1059#define A_TP_RXT_MAX 0x39c
1060
1061#define A_TP_PERS_MIN 0x3a0
1062
1063#define A_TP_PERS_MAX 0x3a4
1064
1065#define A_TP_KEEP_IDLE 0x3a8
1066
1067#define A_TP_KEEP_INTVL 0x3ac
1068
1069#define A_TP_INIT_SRTT 0x3b0
1070
1071#define A_TP_DACK_TIMER 0x3b4
1072
1073#define A_TP_FINWAIT2_TIMER 0x3b8
1074
1075#define A_TP_SHIFT_CNT 0x3c0
1076
1077#define S_SYNSHIFTMAX 24
1078
1079#define M_SYNSHIFTMAX 0xff
1080
1081#define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
1082
1083#define S_RXTSHIFTMAXR1 20
1084
1085#define M_RXTSHIFTMAXR1 0xf
1086
1087#define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
1088
1089#define S_RXTSHIFTMAXR2 16
1090
1091#define M_RXTSHIFTMAXR2 0xf
1092
1093#define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
1094
1095#define S_PERSHIFTBACKOFFMAX 12
1096#define M_PERSHIFTBACKOFFMAX 0xf
1097#define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
1098
1099#define S_PERSHIFTMAX 8
1100#define M_PERSHIFTMAX 0xf
1101#define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
1102
1103#define S_KEEPALIVEMAX 0
1104
1105#define M_KEEPALIVEMAX 0xff
1106
1107#define V_KEEPALIVEMAX(x) ((x) << S_KEEPALIVEMAX)
1108
1109#define A_TP_MTU_PORT_TABLE 0x3d0
1110
1111#define A_TP_CCTRL_TABLE 0x3dc
1112
1113#define A_TP_MTU_TABLE 0x3e4
1114
1115#define A_TP_RSS_MAP_TABLE 0x3e8
1116
1117#define A_TP_RSS_LKP_TABLE 0x3ec
1118
1119#define A_TP_RSS_CONFIG 0x3f0
1120
1121#define S_TNL4TUPEN 29
1122#define V_TNL4TUPEN(x) ((x) << S_TNL4TUPEN)
1123#define F_TNL4TUPEN V_TNL4TUPEN(1U)
1124
1125#define S_TNL2TUPEN 28
1126#define V_TNL2TUPEN(x) ((x) << S_TNL2TUPEN)
1127#define F_TNL2TUPEN V_TNL2TUPEN(1U)
1128
1129#define S_TNLPRTEN 26
1130#define V_TNLPRTEN(x) ((x) << S_TNLPRTEN)
1131#define F_TNLPRTEN V_TNLPRTEN(1U)
1132
1133#define S_TNLMAPEN 25
1134#define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
1135#define F_TNLMAPEN V_TNLMAPEN(1U)
1136
1137#define S_TNLLKPEN 24
1138#define V_TNLLKPEN(x) ((x) << S_TNLLKPEN)
1139#define F_TNLLKPEN V_TNLLKPEN(1U)
1140
1141#define S_RRCPLCPUSIZE 4
1142#define M_RRCPLCPUSIZE 0x7
1143#define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE)
1144
1145#define S_RQFEEDBACKENABLE 3
1146#define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE)
1147#define F_RQFEEDBACKENABLE V_RQFEEDBACKENABLE(1U)
1148
1149#define S_DISABLE 0
1150
1151#define A_TP_TM_PIO_ADDR 0x418
1152
1153#define A_TP_TM_PIO_DATA 0x41c
1154
1155#define A_TP_TX_MOD_QUE_TABLE 0x420
1156
1157#define A_TP_TX_RESOURCE_LIMIT 0x424
1158
1159#define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428
1160
1161#define S_TX_MOD_QUEUE_REQ_MAP 0
1162#define M_TX_MOD_QUEUE_REQ_MAP 0xff
1163#define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
1164
1165#define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c
1166
1167#define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430
1168
1169#define A_TP_MOD_CHANNEL_WEIGHT 0x434
1170
Divy Le Ray8a9fab22007-05-30 21:10:52 -07001171#define A_TP_MOD_RATE_LIMIT 0x438
1172
Divy Le Ray4d22de32007-01-18 22:04:14 -05001173#define A_TP_PIO_ADDR 0x440
1174
1175#define A_TP_PIO_DATA 0x444
1176
1177#define A_TP_RESET 0x44c
1178
1179#define S_FLSTINITENABLE 1
1180#define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
1181#define F_FLSTINITENABLE V_FLSTINITENABLE(1U)
1182
1183#define S_TPRESET 0
1184#define V_TPRESET(x) ((x) << S_TPRESET)
1185#define F_TPRESET V_TPRESET(1U)
1186
1187#define A_TP_CMM_MM_RX_FLST_BASE 0x460
1188
1189#define A_TP_CMM_MM_TX_FLST_BASE 0x464
1190
1191#define A_TP_CMM_MM_PS_FLST_BASE 0x468
1192
1193#define A_TP_MIB_INDEX 0x450
1194
1195#define A_TP_MIB_RDATA 0x454
1196
1197#define A_TP_CMM_MM_MAX_PSTRUCT 0x46c
1198
1199#define A_TP_INT_ENABLE 0x470
1200
1201#define A_TP_INT_CAUSE 0x474
1202
1203#define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
1204
1205#define A_TP_TX_DROP_CFG_CH0 0x12b
1206
1207#define A_TP_TX_DROP_MODE 0x12f
1208
1209#define A_TP_EGRESS_CONFIG 0x145
1210
1211#define S_REWRITEFORCETOSIZE 0
1212#define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
1213#define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U)
1214
1215#define A_TP_TX_TRC_KEY0 0x20
1216
1217#define A_TP_RX_TRC_KEY0 0x120
1218
Divy Le Rayfc906642007-03-18 13:10:12 -07001219#define A_TP_TX_DROP_CNT_CH0 0x12d
1220
1221#define S_TXDROPCNTCH0RCVD 0
1222#define M_TXDROPCNTCH0RCVD 0xffff
1223#define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
1224#define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & \
1225 M_TXDROPCNTCH0RCVD)
1226
Divy Le Ray8a9fab22007-05-30 21:10:52 -07001227#define A_TP_PROXY_FLOW_CNTL 0x4b0
1228
Divy Le Ray480fe1a2007-05-30 21:10:58 -07001229#define A_TP_EMBED_OP_FIELD0 0x4e8
1230#define A_TP_EMBED_OP_FIELD1 0x4ec
1231#define A_TP_EMBED_OP_FIELD2 0x4f0
1232#define A_TP_EMBED_OP_FIELD3 0x4f4
1233#define A_TP_EMBED_OP_FIELD4 0x4f8
1234#define A_TP_EMBED_OP_FIELD5 0x4fc
1235
Divy Le Ray4d22de32007-01-18 22:04:14 -05001236#define A_ULPRX_CTL 0x500
1237
1238#define S_ROUND_ROBIN 4
1239#define V_ROUND_ROBIN(x) ((x) << S_ROUND_ROBIN)
1240#define F_ROUND_ROBIN V_ROUND_ROBIN(1U)
1241
1242#define A_ULPRX_INT_ENABLE 0x504
1243
1244#define S_PARERR 0
1245#define V_PARERR(x) ((x) << S_PARERR)
1246#define F_PARERR V_PARERR(1U)
1247
1248#define A_ULPRX_INT_CAUSE 0x508
1249
1250#define A_ULPRX_ISCSI_LLIMIT 0x50c
1251
1252#define A_ULPRX_ISCSI_ULIMIT 0x510
1253
1254#define A_ULPRX_ISCSI_TAGMASK 0x514
1255
Divy Le Ray6cdbd772007-04-09 20:10:33 -07001256#define S_HPZ0 0
1257#define M_HPZ0 0xf
1258#define V_HPZ0(x) ((x) << S_HPZ0)
1259#define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
1260
Divy Le Ray4d22de32007-01-18 22:04:14 -05001261#define A_ULPRX_TDDP_LLIMIT 0x51c
1262
1263#define A_ULPRX_TDDP_ULIMIT 0x520
Divy Le Ray6cdbd772007-04-09 20:10:33 -07001264#define A_ULPRX_TDDP_PSZ 0x528
Divy Le Ray4d22de32007-01-18 22:04:14 -05001265
1266#define A_ULPRX_STAG_LLIMIT 0x52c
1267
1268#define A_ULPRX_STAG_ULIMIT 0x530
1269
1270#define A_ULPRX_RQ_LLIMIT 0x534
1271#define A_ULPRX_RQ_LLIMIT 0x534
1272
1273#define A_ULPRX_RQ_ULIMIT 0x538
1274#define A_ULPRX_RQ_ULIMIT 0x538
1275
1276#define A_ULPRX_PBL_LLIMIT 0x53c
1277
1278#define A_ULPRX_PBL_ULIMIT 0x540
1279#define A_ULPRX_PBL_ULIMIT 0x540
1280
1281#define A_ULPRX_TDDP_TAGMASK 0x524
1282
1283#define A_ULPRX_RQ_LLIMIT 0x534
1284#define A_ULPRX_RQ_LLIMIT 0x534
1285
1286#define A_ULPRX_RQ_ULIMIT 0x538
1287#define A_ULPRX_RQ_ULIMIT 0x538
1288
1289#define A_ULPRX_PBL_ULIMIT 0x540
1290#define A_ULPRX_PBL_ULIMIT 0x540
1291
1292#define A_ULPTX_CONFIG 0x580
1293
1294#define S_CFG_RR_ARB 0
1295#define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB)
1296#define F_CFG_RR_ARB V_CFG_RR_ARB(1U)
1297
1298#define A_ULPTX_INT_ENABLE 0x584
1299
1300#define S_PBL_BOUND_ERR_CH1 1
1301#define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
1302#define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U)
1303
1304#define S_PBL_BOUND_ERR_CH0 0
1305#define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
1306#define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U)
1307
1308#define A_ULPTX_INT_CAUSE 0x588
1309
1310#define A_ULPTX_TPT_LLIMIT 0x58c
1311
1312#define A_ULPTX_TPT_ULIMIT 0x590
1313
1314#define A_ULPTX_PBL_LLIMIT 0x594
1315
1316#define A_ULPTX_PBL_ULIMIT 0x598
1317
1318#define A_ULPTX_DMA_WEIGHT 0x5ac
1319
1320#define S_D1_WEIGHT 16
1321#define M_D1_WEIGHT 0xffff
1322#define V_D1_WEIGHT(x) ((x) << S_D1_WEIGHT)
1323
1324#define S_D0_WEIGHT 0
1325#define M_D0_WEIGHT 0xffff
1326#define V_D0_WEIGHT(x) ((x) << S_D0_WEIGHT)
1327
1328#define A_PM1_RX_CFG 0x5c0
Divy Le Ray3f61e422007-08-21 20:49:41 -07001329#define A_PM1_RX_MODE 0x5c4
Divy Le Ray4d22de32007-01-18 22:04:14 -05001330
1331#define A_PM1_RX_INT_ENABLE 0x5d8
1332
1333#define S_ZERO_E_CMD_ERROR 18
1334#define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
1335#define F_ZERO_E_CMD_ERROR V_ZERO_E_CMD_ERROR(1U)
1336
1337#define S_IESPI0_FIFO2X_RX_FRAMING_ERROR 17
1338#define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
1339#define F_IESPI0_FIFO2X_RX_FRAMING_ERROR V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
1340
1341#define S_IESPI1_FIFO2X_RX_FRAMING_ERROR 16
1342#define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
1343#define F_IESPI1_FIFO2X_RX_FRAMING_ERROR V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
1344
1345#define S_IESPI0_RX_FRAMING_ERROR 15
1346#define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
1347#define F_IESPI0_RX_FRAMING_ERROR V_IESPI0_RX_FRAMING_ERROR(1U)
1348
1349#define S_IESPI1_RX_FRAMING_ERROR 14
1350#define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
1351#define F_IESPI1_RX_FRAMING_ERROR V_IESPI1_RX_FRAMING_ERROR(1U)
1352
1353#define S_IESPI0_TX_FRAMING_ERROR 13
1354#define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
1355#define F_IESPI0_TX_FRAMING_ERROR V_IESPI0_TX_FRAMING_ERROR(1U)
1356
1357#define S_IESPI1_TX_FRAMING_ERROR 12
1358#define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
1359#define F_IESPI1_TX_FRAMING_ERROR V_IESPI1_TX_FRAMING_ERROR(1U)
1360
1361#define S_OCSPI0_RX_FRAMING_ERROR 11
1362#define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
1363#define F_OCSPI0_RX_FRAMING_ERROR V_OCSPI0_RX_FRAMING_ERROR(1U)
1364
1365#define S_OCSPI1_RX_FRAMING_ERROR 10
1366#define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
1367#define F_OCSPI1_RX_FRAMING_ERROR V_OCSPI1_RX_FRAMING_ERROR(1U)
1368
1369#define S_OCSPI0_TX_FRAMING_ERROR 9
1370#define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
1371#define F_OCSPI0_TX_FRAMING_ERROR V_OCSPI0_TX_FRAMING_ERROR(1U)
1372
1373#define S_OCSPI1_TX_FRAMING_ERROR 8
1374#define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
1375#define F_OCSPI1_TX_FRAMING_ERROR V_OCSPI1_TX_FRAMING_ERROR(1U)
1376
1377#define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR 7
1378#define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
1379#define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
1380
1381#define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR 6
1382#define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
1383#define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
1384
1385#define S_IESPI_PAR_ERROR 3
1386#define M_IESPI_PAR_ERROR 0x7
1387
1388#define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
1389
1390#define S_OCSPI_PAR_ERROR 0
1391#define M_OCSPI_PAR_ERROR 0x7
1392
1393#define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
1394
1395#define A_PM1_RX_INT_CAUSE 0x5dc
1396
1397#define A_PM1_TX_CFG 0x5e0
Divy Le Ray3f61e422007-08-21 20:49:41 -07001398#define A_PM1_TX_MODE 0x5e4
Divy Le Ray4d22de32007-01-18 22:04:14 -05001399
1400#define A_PM1_TX_INT_ENABLE 0x5f8
1401
1402#define S_ZERO_C_CMD_ERROR 18
1403#define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
1404#define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U)
1405
1406#define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR 17
1407#define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
1408#define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
1409
1410#define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR 16
1411#define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
1412#define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
1413
1414#define S_ICSPI0_RX_FRAMING_ERROR 15
1415#define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
1416#define F_ICSPI0_RX_FRAMING_ERROR V_ICSPI0_RX_FRAMING_ERROR(1U)
1417
1418#define S_ICSPI1_RX_FRAMING_ERROR 14
1419#define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
1420#define F_ICSPI1_RX_FRAMING_ERROR V_ICSPI1_RX_FRAMING_ERROR(1U)
1421
1422#define S_ICSPI0_TX_FRAMING_ERROR 13
1423#define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
1424#define F_ICSPI0_TX_FRAMING_ERROR V_ICSPI0_TX_FRAMING_ERROR(1U)
1425
1426#define S_ICSPI1_TX_FRAMING_ERROR 12
1427#define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
1428#define F_ICSPI1_TX_FRAMING_ERROR V_ICSPI1_TX_FRAMING_ERROR(1U)
1429
1430#define S_OESPI0_RX_FRAMING_ERROR 11
1431#define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
1432#define F_OESPI0_RX_FRAMING_ERROR V_OESPI0_RX_FRAMING_ERROR(1U)
1433
1434#define S_OESPI1_RX_FRAMING_ERROR 10
1435#define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
1436#define F_OESPI1_RX_FRAMING_ERROR V_OESPI1_RX_FRAMING_ERROR(1U)
1437
1438#define S_OESPI0_TX_FRAMING_ERROR 9
1439#define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
1440#define F_OESPI0_TX_FRAMING_ERROR V_OESPI0_TX_FRAMING_ERROR(1U)
1441
1442#define S_OESPI1_TX_FRAMING_ERROR 8
1443#define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
1444#define F_OESPI1_TX_FRAMING_ERROR V_OESPI1_TX_FRAMING_ERROR(1U)
1445
1446#define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR 7
1447#define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
1448#define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
1449
1450#define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR 6
1451#define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
1452#define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
1453
1454#define S_ICSPI_PAR_ERROR 3
1455#define M_ICSPI_PAR_ERROR 0x7
1456
1457#define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
1458
1459#define S_OESPI_PAR_ERROR 0
1460#define M_OESPI_PAR_ERROR 0x7
1461
1462#define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
1463
1464#define A_PM1_TX_INT_CAUSE 0x5fc
1465
1466#define A_MPS_CFG 0x600
1467
1468#define S_TPRXPORTEN 4
1469#define V_TPRXPORTEN(x) ((x) << S_TPRXPORTEN)
1470#define F_TPRXPORTEN V_TPRXPORTEN(1U)
1471
1472#define S_TPTXPORT1EN 3
1473#define V_TPTXPORT1EN(x) ((x) << S_TPTXPORT1EN)
1474#define F_TPTXPORT1EN V_TPTXPORT1EN(1U)
1475
1476#define S_TPTXPORT0EN 2
1477#define V_TPTXPORT0EN(x) ((x) << S_TPTXPORT0EN)
1478#define F_TPTXPORT0EN V_TPTXPORT0EN(1U)
1479
1480#define S_PORT1ACTIVE 1
1481#define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE)
1482#define F_PORT1ACTIVE V_PORT1ACTIVE(1U)
1483
1484#define S_PORT0ACTIVE 0
1485#define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE)
1486#define F_PORT0ACTIVE V_PORT0ACTIVE(1U)
1487
1488#define S_ENFORCEPKT 11
1489#define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT)
1490#define F_ENFORCEPKT V_ENFORCEPKT(1U)
1491
1492#define A_MPS_INT_ENABLE 0x61c
1493
1494#define S_MCAPARERRENB 6
1495#define M_MCAPARERRENB 0x7
1496
1497#define V_MCAPARERRENB(x) ((x) << S_MCAPARERRENB)
1498
1499#define S_RXTPPARERRENB 4
1500#define M_RXTPPARERRENB 0x3
1501
1502#define V_RXTPPARERRENB(x) ((x) << S_RXTPPARERRENB)
1503
1504#define S_TX1TPPARERRENB 2
1505#define M_TX1TPPARERRENB 0x3
1506
1507#define V_TX1TPPARERRENB(x) ((x) << S_TX1TPPARERRENB)
1508
1509#define S_TX0TPPARERRENB 0
1510#define M_TX0TPPARERRENB 0x3
1511
1512#define V_TX0TPPARERRENB(x) ((x) << S_TX0TPPARERRENB)
1513
1514#define A_MPS_INT_CAUSE 0x620
1515
1516#define S_MCAPARERR 6
1517#define M_MCAPARERR 0x7
1518
1519#define V_MCAPARERR(x) ((x) << S_MCAPARERR)
1520
1521#define S_RXTPPARERR 4
1522#define M_RXTPPARERR 0x3
1523
1524#define V_RXTPPARERR(x) ((x) << S_RXTPPARERR)
1525
1526#define S_TX1TPPARERR 2
1527#define M_TX1TPPARERR 0x3
1528
1529#define V_TX1TPPARERR(x) ((x) << S_TX1TPPARERR)
1530
1531#define S_TX0TPPARERR 0
1532#define M_TX0TPPARERR 0x3
1533
1534#define V_TX0TPPARERR(x) ((x) << S_TX0TPPARERR)
1535
1536#define A_CPL_SWITCH_CNTRL 0x640
1537
1538#define A_CPL_INTR_ENABLE 0x650
1539
1540#define S_CIM_OVFL_ERROR 4
1541#define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
1542#define F_CIM_OVFL_ERROR V_CIM_OVFL_ERROR(1U)
1543
1544#define S_TP_FRAMING_ERROR 3
1545#define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
1546#define F_TP_FRAMING_ERROR V_TP_FRAMING_ERROR(1U)
1547
1548#define S_SGE_FRAMING_ERROR 2
1549#define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
1550#define F_SGE_FRAMING_ERROR V_SGE_FRAMING_ERROR(1U)
1551
1552#define S_CIM_FRAMING_ERROR 1
1553#define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
1554#define F_CIM_FRAMING_ERROR V_CIM_FRAMING_ERROR(1U)
1555
1556#define S_ZERO_SWITCH_ERROR 0
1557#define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
1558#define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U)
1559
1560#define A_CPL_INTR_CAUSE 0x654
1561
1562#define A_CPL_MAP_TBL_DATA 0x65c
1563
1564#define A_SMB_GLOBAL_TIME_CFG 0x660
1565
1566#define A_I2C_CFG 0x6a0
1567
1568#define S_I2C_CLKDIV 0
1569#define M_I2C_CLKDIV 0xfff
1570#define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
1571
1572#define A_MI1_CFG 0x6b0
1573
1574#define S_CLKDIV 5
1575#define M_CLKDIV 0xff
1576#define V_CLKDIV(x) ((x) << S_CLKDIV)
1577
1578#define S_ST 3
1579
1580#define M_ST 0x3
1581
1582#define V_ST(x) ((x) << S_ST)
1583
1584#define G_ST(x) (((x) >> S_ST) & M_ST)
1585
1586#define S_PREEN 2
1587#define V_PREEN(x) ((x) << S_PREEN)
1588#define F_PREEN V_PREEN(1U)
1589
1590#define S_MDIINV 1
1591#define V_MDIINV(x) ((x) << S_MDIINV)
1592#define F_MDIINV V_MDIINV(1U)
1593
1594#define S_MDIEN 0
1595#define V_MDIEN(x) ((x) << S_MDIEN)
1596#define F_MDIEN V_MDIEN(1U)
1597
1598#define A_MI1_ADDR 0x6b4
1599
1600#define S_PHYADDR 5
1601#define M_PHYADDR 0x1f
1602#define V_PHYADDR(x) ((x) << S_PHYADDR)
1603
1604#define S_REGADDR 0
1605#define M_REGADDR 0x1f
1606#define V_REGADDR(x) ((x) << S_REGADDR)
1607
1608#define A_MI1_DATA 0x6b8
1609
1610#define A_MI1_OP 0x6bc
1611
1612#define S_MDI_OP 0
1613#define M_MDI_OP 0x3
1614#define V_MDI_OP(x) ((x) << S_MDI_OP)
1615
1616#define A_SF_DATA 0x6d8
1617
1618#define A_SF_OP 0x6dc
1619
1620#define S_BYTECNT 1
1621#define M_BYTECNT 0x3
1622#define V_BYTECNT(x) ((x) << S_BYTECNT)
1623
1624#define A_PL_INT_ENABLE0 0x6e0
1625
1626#define S_T3DBG 23
1627#define V_T3DBG(x) ((x) << S_T3DBG)
1628#define F_T3DBG V_T3DBG(1U)
1629
1630#define S_XGMAC0_1 20
1631#define V_XGMAC0_1(x) ((x) << S_XGMAC0_1)
1632#define F_XGMAC0_1 V_XGMAC0_1(1U)
1633
1634#define S_XGMAC0_0 19
1635#define V_XGMAC0_0(x) ((x) << S_XGMAC0_0)
1636#define F_XGMAC0_0 V_XGMAC0_0(1U)
1637
1638#define S_MC5A 18
1639#define V_MC5A(x) ((x) << S_MC5A)
1640#define F_MC5A V_MC5A(1U)
1641
1642#define S_CPL_SWITCH 12
1643#define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
1644#define F_CPL_SWITCH V_CPL_SWITCH(1U)
1645
1646#define S_MPS0 11
1647#define V_MPS0(x) ((x) << S_MPS0)
1648#define F_MPS0 V_MPS0(1U)
1649
1650#define S_PM1_TX 10
1651#define V_PM1_TX(x) ((x) << S_PM1_TX)
1652#define F_PM1_TX V_PM1_TX(1U)
1653
1654#define S_PM1_RX 9
1655#define V_PM1_RX(x) ((x) << S_PM1_RX)
1656#define F_PM1_RX V_PM1_RX(1U)
1657
1658#define S_ULP2_TX 8
1659#define V_ULP2_TX(x) ((x) << S_ULP2_TX)
1660#define F_ULP2_TX V_ULP2_TX(1U)
1661
1662#define S_ULP2_RX 7
1663#define V_ULP2_RX(x) ((x) << S_ULP2_RX)
1664#define F_ULP2_RX V_ULP2_RX(1U)
1665
1666#define S_TP1 6
1667#define V_TP1(x) ((x) << S_TP1)
1668#define F_TP1 V_TP1(1U)
1669
1670#define S_CIM 5
1671#define V_CIM(x) ((x) << S_CIM)
1672#define F_CIM V_CIM(1U)
1673
1674#define S_MC7_CM 4
1675#define V_MC7_CM(x) ((x) << S_MC7_CM)
1676#define F_MC7_CM V_MC7_CM(1U)
1677
1678#define S_MC7_PMTX 3
1679#define V_MC7_PMTX(x) ((x) << S_MC7_PMTX)
1680#define F_MC7_PMTX V_MC7_PMTX(1U)
1681
1682#define S_MC7_PMRX 2
1683#define V_MC7_PMRX(x) ((x) << S_MC7_PMRX)
1684#define F_MC7_PMRX V_MC7_PMRX(1U)
1685
1686#define S_PCIM0 1
1687#define V_PCIM0(x) ((x) << S_PCIM0)
1688#define F_PCIM0 V_PCIM0(1U)
1689
1690#define S_SGE3 0
1691#define V_SGE3(x) ((x) << S_SGE3)
1692#define F_SGE3 V_SGE3(1U)
1693
1694#define A_PL_INT_CAUSE0 0x6e4
1695
1696#define A_PL_RST 0x6f0
1697
1698#define S_CRSTWRM 1
1699#define V_CRSTWRM(x) ((x) << S_CRSTWRM)
1700#define F_CRSTWRM V_CRSTWRM(1U)
1701
1702#define A_PL_REV 0x6f4
1703
1704#define A_PL_CLI 0x6f8
1705
1706#define A_MC5_DB_CONFIG 0x704
1707
1708#define S_TMTYPEHI 30
1709#define V_TMTYPEHI(x) ((x) << S_TMTYPEHI)
1710#define F_TMTYPEHI V_TMTYPEHI(1U)
1711
1712#define S_TMPARTSIZE 28
1713#define M_TMPARTSIZE 0x3
1714#define V_TMPARTSIZE(x) ((x) << S_TMPARTSIZE)
1715#define G_TMPARTSIZE(x) (((x) >> S_TMPARTSIZE) & M_TMPARTSIZE)
1716
1717#define S_TMTYPE 26
1718#define M_TMTYPE 0x3
1719#define V_TMTYPE(x) ((x) << S_TMTYPE)
1720#define G_TMTYPE(x) (((x) >> S_TMTYPE) & M_TMTYPE)
1721
1722#define S_COMPEN 17
1723#define V_COMPEN(x) ((x) << S_COMPEN)
1724#define F_COMPEN V_COMPEN(1U)
1725
1726#define S_PRTYEN 6
1727#define V_PRTYEN(x) ((x) << S_PRTYEN)
1728#define F_PRTYEN V_PRTYEN(1U)
1729
1730#define S_MBUSEN 5
1731#define V_MBUSEN(x) ((x) << S_MBUSEN)
1732#define F_MBUSEN V_MBUSEN(1U)
1733
1734#define S_DBGIEN 4
1735#define V_DBGIEN(x) ((x) << S_DBGIEN)
1736#define F_DBGIEN V_DBGIEN(1U)
1737
1738#define S_TMRDY 2
1739#define V_TMRDY(x) ((x) << S_TMRDY)
1740#define F_TMRDY V_TMRDY(1U)
1741
1742#define S_TMRST 1
1743#define V_TMRST(x) ((x) << S_TMRST)
1744#define F_TMRST V_TMRST(1U)
1745
1746#define S_TMMODE 0
1747#define V_TMMODE(x) ((x) << S_TMMODE)
1748#define F_TMMODE V_TMMODE(1U)
1749
1750#define F_TMMODE V_TMMODE(1U)
1751
1752#define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c
1753
1754#define A_MC5_DB_FILTER_TABLE 0x710
1755
1756#define A_MC5_DB_SERVER_INDEX 0x714
1757
1758#define A_MC5_DB_RSP_LATENCY 0x720
1759
1760#define S_RDLAT 16
1761#define M_RDLAT 0x1f
1762#define V_RDLAT(x) ((x) << S_RDLAT)
1763
1764#define S_LRNLAT 8
1765#define M_LRNLAT 0x1f
1766#define V_LRNLAT(x) ((x) << S_LRNLAT)
1767
1768#define S_SRCHLAT 0
1769#define M_SRCHLAT 0x1f
1770#define V_SRCHLAT(x) ((x) << S_SRCHLAT)
1771
1772#define A_MC5_DB_PART_ID_INDEX 0x72c
1773
1774#define A_MC5_DB_INT_ENABLE 0x740
1775
1776#define S_DELACTEMPTY 18
1777#define V_DELACTEMPTY(x) ((x) << S_DELACTEMPTY)
1778#define F_DELACTEMPTY V_DELACTEMPTY(1U)
1779
1780#define S_DISPQPARERR 17
1781#define V_DISPQPARERR(x) ((x) << S_DISPQPARERR)
1782#define F_DISPQPARERR V_DISPQPARERR(1U)
1783
1784#define S_REQQPARERR 16
1785#define V_REQQPARERR(x) ((x) << S_REQQPARERR)
1786#define F_REQQPARERR V_REQQPARERR(1U)
1787
1788#define S_UNKNOWNCMD 15
1789#define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
1790#define F_UNKNOWNCMD V_UNKNOWNCMD(1U)
1791
1792#define S_NFASRCHFAIL 8
1793#define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
1794#define F_NFASRCHFAIL V_NFASRCHFAIL(1U)
1795
1796#define S_ACTRGNFULL 7
1797#define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
1798#define F_ACTRGNFULL V_ACTRGNFULL(1U)
1799
1800#define S_PARITYERR 6
1801#define V_PARITYERR(x) ((x) << S_PARITYERR)
1802#define F_PARITYERR V_PARITYERR(1U)
1803
1804#define A_MC5_DB_INT_CAUSE 0x744
1805
1806#define A_MC5_DB_DBGI_CONFIG 0x774
1807
1808#define A_MC5_DB_DBGI_REQ_CMD 0x778
1809
1810#define A_MC5_DB_DBGI_REQ_ADDR0 0x77c
1811
1812#define A_MC5_DB_DBGI_REQ_ADDR1 0x780
1813
1814#define A_MC5_DB_DBGI_REQ_ADDR2 0x784
1815
1816#define A_MC5_DB_DBGI_REQ_DATA0 0x788
1817
1818#define A_MC5_DB_DBGI_REQ_DATA1 0x78c
1819
1820#define A_MC5_DB_DBGI_REQ_DATA2 0x790
1821
1822#define A_MC5_DB_DBGI_RSP_STATUS 0x7b0
1823
1824#define S_DBGIRSPVALID 0
1825#define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
1826#define F_DBGIRSPVALID V_DBGIRSPVALID(1U)
1827
1828#define A_MC5_DB_DBGI_RSP_DATA0 0x7b4
1829
1830#define A_MC5_DB_DBGI_RSP_DATA1 0x7b8
1831
1832#define A_MC5_DB_DBGI_RSP_DATA2 0x7bc
1833
1834#define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc
1835
1836#define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0
1837
1838#define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4
1839
1840#define A_MC5_DB_AOPEN_LRN_CMD 0x7d8
1841
1842#define A_MC5_DB_SYN_SRCH_CMD 0x7dc
1843
1844#define A_MC5_DB_SYN_LRN_CMD 0x7e0
1845
1846#define A_MC5_DB_ACK_SRCH_CMD 0x7e4
1847
1848#define A_MC5_DB_ACK_LRN_CMD 0x7e8
1849
1850#define A_MC5_DB_ILOOKUP_CMD 0x7ec
1851
1852#define A_MC5_DB_ELOOKUP_CMD 0x7f0
1853
1854#define A_MC5_DB_DATA_WRITE_CMD 0x7f4
1855
1856#define A_MC5_DB_DATA_READ_CMD 0x7f8
1857
1858#define XGMAC0_0_BASE_ADDR 0x800
1859
1860#define A_XGM_TX_CTRL 0x800
1861
1862#define S_TXEN 0
1863#define V_TXEN(x) ((x) << S_TXEN)
1864#define F_TXEN V_TXEN(1U)
1865
1866#define A_XGM_TX_CFG 0x804
1867
1868#define S_TXPAUSEEN 0
1869#define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
1870#define F_TXPAUSEEN V_TXPAUSEEN(1U)
1871
Divy Le Rayfc906642007-03-18 13:10:12 -07001872#define A_XGM_TX_PAUSE_QUANTA 0x808
1873
Divy Le Ray4d22de32007-01-18 22:04:14 -05001874#define A_XGM_RX_CTRL 0x80c
1875
1876#define S_RXEN 0
1877#define V_RXEN(x) ((x) << S_RXEN)
1878#define F_RXEN V_RXEN(1U)
1879
1880#define A_XGM_RX_CFG 0x810
1881
1882#define S_DISPAUSEFRAMES 9
1883#define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
1884#define F_DISPAUSEFRAMES V_DISPAUSEFRAMES(1U)
1885
1886#define S_EN1536BFRAMES 8
1887#define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
1888#define F_EN1536BFRAMES V_EN1536BFRAMES(1U)
1889
1890#define S_ENJUMBO 7
1891#define V_ENJUMBO(x) ((x) << S_ENJUMBO)
1892#define F_ENJUMBO V_ENJUMBO(1U)
1893
1894#define S_RMFCS 6
1895#define V_RMFCS(x) ((x) << S_RMFCS)
1896#define F_RMFCS V_RMFCS(1U)
1897
1898#define S_ENHASHMCAST 2
1899#define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
1900#define F_ENHASHMCAST V_ENHASHMCAST(1U)
1901
1902#define S_COPYALLFRAMES 0
1903#define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
1904#define F_COPYALLFRAMES V_COPYALLFRAMES(1U)
1905
Divy Le Ray7b581a02007-05-30 10:01:44 -07001906#define S_DISBCAST 1
1907#define V_DISBCAST(x) ((x) << S_DISBCAST)
1908#define F_DISBCAST V_DISBCAST(1U)
1909
Divy Le Ray4d22de32007-01-18 22:04:14 -05001910#define A_XGM_RX_HASH_LOW 0x814
1911
1912#define A_XGM_RX_HASH_HIGH 0x818
1913
1914#define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c
1915
1916#define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820
1917
1918#define A_XGM_RX_EXACT_MATCH_LOW_2 0x824
1919
1920#define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c
1921
1922#define A_XGM_RX_EXACT_MATCH_LOW_4 0x834
1923
1924#define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c
1925
1926#define A_XGM_RX_EXACT_MATCH_LOW_6 0x844
1927
1928#define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c
1929
1930#define A_XGM_RX_EXACT_MATCH_LOW_8 0x854
1931
1932#define A_XGM_STAT_CTRL 0x880
1933
1934#define S_CLRSTATS 2
1935#define V_CLRSTATS(x) ((x) << S_CLRSTATS)
1936#define F_CLRSTATS V_CLRSTATS(1U)
1937
1938#define A_XGM_RXFIFO_CFG 0x884
1939
Divy Le Ray75758e82007-12-05 10:15:01 -08001940#define S_RXFIFO_EMPTY 31
1941#define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY)
1942#define F_RXFIFO_EMPTY V_RXFIFO_EMPTY(1U)
1943
Divy Le Ray4d22de32007-01-18 22:04:14 -05001944#define S_RXFIFOPAUSEHWM 17
1945#define M_RXFIFOPAUSEHWM 0xfff
1946
1947#define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM)
1948
1949#define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM)
1950
1951#define S_RXFIFOPAUSELWM 5
1952#define M_RXFIFOPAUSELWM 0xfff
1953
1954#define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM)
1955
1956#define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM)
1957
1958#define S_RXSTRFRWRD 1
1959#define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD)
1960#define F_RXSTRFRWRD V_RXSTRFRWRD(1U)
1961
1962#define S_DISERRFRAMES 0
1963#define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES)
1964#define F_DISERRFRAMES V_DISERRFRAMES(1U)
1965
1966#define A_XGM_TXFIFO_CFG 0x888
1967
Divy Le Ray75758e82007-12-05 10:15:01 -08001968#define S_UNDERUNFIX 22
1969#define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX)
1970#define F_UNDERUNFIX V_UNDERUNFIX(1U)
1971
Divy Le Rayfc906642007-03-18 13:10:12 -07001972#define S_TXIPG 13
1973#define M_TXIPG 0xff
1974#define V_TXIPG(x) ((x) << S_TXIPG)
1975#define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG)
1976
Divy Le Ray4d22de32007-01-18 22:04:14 -05001977#define S_TXFIFOTHRESH 4
1978#define M_TXFIFOTHRESH 0x1ff
1979
1980#define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH)
1981
Divy Le Ray6d6daba2007-03-31 00:23:24 -07001982#define S_ENDROPPKT 21
1983#define V_ENDROPPKT(x) ((x) << S_ENDROPPKT)
1984#define F_ENDROPPKT V_ENDROPPKT(1U)
1985
Divy Le Ray4d22de32007-01-18 22:04:14 -05001986#define A_XGM_SERDES_CTRL 0x890
1987#define A_XGM_SERDES_CTRL0 0x8e0
1988
1989#define S_SERDESRESET_ 24
1990#define V_SERDESRESET_(x) ((x) << S_SERDESRESET_)
1991#define F_SERDESRESET_ V_SERDESRESET_(1U)
1992
1993#define S_RXENABLE 4
1994#define V_RXENABLE(x) ((x) << S_RXENABLE)
1995#define F_RXENABLE V_RXENABLE(1U)
1996
1997#define S_TXENABLE 3
1998#define V_TXENABLE(x) ((x) << S_TXENABLE)
1999#define F_TXENABLE V_TXENABLE(1U)
2000
2001#define A_XGM_PAUSE_TIMER 0x890
2002
2003#define A_XGM_RGMII_IMP 0x89c
2004
2005#define S_XGM_IMPSETUPDATE 6
2006#define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE)
2007#define F_XGM_IMPSETUPDATE V_XGM_IMPSETUPDATE(1U)
2008
2009#define S_RGMIIIMPPD 3
2010#define M_RGMIIIMPPD 0x7
2011#define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD)
2012
2013#define S_RGMIIIMPPU 0
2014#define M_RGMIIIMPPU 0x7
2015#define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU)
2016
2017#define S_CALRESET 8
2018#define V_CALRESET(x) ((x) << S_CALRESET)
2019#define F_CALRESET V_CALRESET(1U)
2020
2021#define S_CALUPDATE 7
2022#define V_CALUPDATE(x) ((x) << S_CALUPDATE)
2023#define F_CALUPDATE V_CALUPDATE(1U)
2024
2025#define A_XGM_XAUI_IMP 0x8a0
2026
2027#define S_CALBUSY 31
2028#define V_CALBUSY(x) ((x) << S_CALBUSY)
2029#define F_CALBUSY V_CALBUSY(1U)
2030
2031#define S_XGM_CALFAULT 29
2032#define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT)
2033#define F_XGM_CALFAULT V_XGM_CALFAULT(1U)
2034
2035#define S_CALIMP 24
2036#define M_CALIMP 0x1f
2037#define V_CALIMP(x) ((x) << S_CALIMP)
2038#define G_CALIMP(x) (((x) >> S_CALIMP) & M_CALIMP)
2039
2040#define S_XAUIIMP 0
2041#define M_XAUIIMP 0x7
2042#define V_XAUIIMP(x) ((x) << S_XAUIIMP)
2043
2044#define A_XGM_RX_MAX_PKT_SIZE 0x8a8
Divy Le Ray75758e82007-12-05 10:15:01 -08002045
2046#define S_RXMAXFRAMERSIZE 17
2047#define M_RXMAXFRAMERSIZE 0x3fff
2048#define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE)
2049#define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE)
2050
2051#define S_RXENFRAMER 14
2052#define V_RXENFRAMER(x) ((x) << S_RXENFRAMER)
2053#define F_RXENFRAMER V_RXENFRAMER(1U)
2054
2055#define S_RXMAXPKTSIZE 0
2056#define M_RXMAXPKTSIZE 0x3fff
2057#define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE)
2058#define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE)
Divy Le Ray4d22de32007-01-18 22:04:14 -05002059
2060#define A_XGM_RESET_CTRL 0x8ac
2061
Divy Le Ray75758e82007-12-05 10:15:01 -08002062#define S_XGMAC_STOP_EN 4
2063#define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN)
2064#define F_XGMAC_STOP_EN V_XGMAC_STOP_EN(1U)
2065
Divy Le Ray4d22de32007-01-18 22:04:14 -05002066#define S_XG2G_RESET_ 3
2067#define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_)
2068#define F_XG2G_RESET_ V_XG2G_RESET_(1U)
2069
2070#define S_RGMII_RESET_ 2
2071#define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_)
2072#define F_RGMII_RESET_ V_RGMII_RESET_(1U)
2073
2074#define S_PCS_RESET_ 1
2075#define V_PCS_RESET_(x) ((x) << S_PCS_RESET_)
2076#define F_PCS_RESET_ V_PCS_RESET_(1U)
2077
2078#define S_MAC_RESET_ 0
2079#define V_MAC_RESET_(x) ((x) << S_MAC_RESET_)
2080#define F_MAC_RESET_ V_MAC_RESET_(1U)
2081
2082#define A_XGM_PORT_CFG 0x8b8
2083
2084#define S_CLKDIVRESET_ 3
2085#define V_CLKDIVRESET_(x) ((x) << S_CLKDIVRESET_)
2086#define F_CLKDIVRESET_ V_CLKDIVRESET_(1U)
2087
2088#define S_PORTSPEED 1
2089#define M_PORTSPEED 0x3
2090
2091#define V_PORTSPEED(x) ((x) << S_PORTSPEED)
2092
2093#define S_ENRGMII 0
2094#define V_ENRGMII(x) ((x) << S_ENRGMII)
2095#define F_ENRGMII V_ENRGMII(1U)
2096
2097#define A_XGM_INT_ENABLE 0x8d4
2098
2099#define S_TXFIFO_PRTY_ERR 17
2100#define M_TXFIFO_PRTY_ERR 0x7
2101
2102#define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
2103
2104#define S_RXFIFO_PRTY_ERR 14
2105#define M_RXFIFO_PRTY_ERR 0x7
2106
2107#define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
2108
2109#define S_TXFIFO_UNDERRUN 13
2110#define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN)
2111#define F_TXFIFO_UNDERRUN V_TXFIFO_UNDERRUN(1U)
2112
2113#define S_RXFIFO_OVERFLOW 12
2114#define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW)
2115#define F_RXFIFO_OVERFLOW V_RXFIFO_OVERFLOW(1U)
2116
2117#define S_SERDES_LOS 4
2118#define M_SERDES_LOS 0xf
2119
2120#define V_SERDES_LOS(x) ((x) << S_SERDES_LOS)
2121
2122#define S_XAUIPCSCTCERR 3
2123#define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR)
2124#define F_XAUIPCSCTCERR V_XAUIPCSCTCERR(1U)
2125
2126#define S_XAUIPCSALIGNCHANGE 2
2127#define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE)
2128#define F_XAUIPCSALIGNCHANGE V_XAUIPCSALIGNCHANGE(1U)
2129
2130#define A_XGM_INT_CAUSE 0x8d8
2131
2132#define A_XGM_XAUI_ACT_CTRL 0x8dc
2133
2134#define S_TXACTENABLE 1
2135#define V_TXACTENABLE(x) ((x) << S_TXACTENABLE)
2136#define F_TXACTENABLE V_TXACTENABLE(1U)
2137
2138#define A_XGM_SERDES_CTRL0 0x8e0
2139
2140#define S_RESET3 23
2141#define V_RESET3(x) ((x) << S_RESET3)
2142#define F_RESET3 V_RESET3(1U)
2143
2144#define S_RESET2 22
2145#define V_RESET2(x) ((x) << S_RESET2)
2146#define F_RESET2 V_RESET2(1U)
2147
2148#define S_RESET1 21
2149#define V_RESET1(x) ((x) << S_RESET1)
2150#define F_RESET1 V_RESET1(1U)
2151
2152#define S_RESET0 20
2153#define V_RESET0(x) ((x) << S_RESET0)
2154#define F_RESET0 V_RESET0(1U)
2155
2156#define S_PWRDN3 19
2157#define V_PWRDN3(x) ((x) << S_PWRDN3)
2158#define F_PWRDN3 V_PWRDN3(1U)
2159
2160#define S_PWRDN2 18
2161#define V_PWRDN2(x) ((x) << S_PWRDN2)
2162#define F_PWRDN2 V_PWRDN2(1U)
2163
2164#define S_PWRDN1 17
2165#define V_PWRDN1(x) ((x) << S_PWRDN1)
2166#define F_PWRDN1 V_PWRDN1(1U)
2167
2168#define S_PWRDN0 16
2169#define V_PWRDN0(x) ((x) << S_PWRDN0)
2170#define F_PWRDN0 V_PWRDN0(1U)
2171
2172#define S_RESETPLL23 15
2173#define V_RESETPLL23(x) ((x) << S_RESETPLL23)
2174#define F_RESETPLL23 V_RESETPLL23(1U)
2175
2176#define S_RESETPLL01 14
2177#define V_RESETPLL01(x) ((x) << S_RESETPLL01)
2178#define F_RESETPLL01 V_RESETPLL01(1U)
2179
2180#define A_XGM_SERDES_STAT0 0x8f0
Divy Le Rayc706bfb2007-05-30 10:01:39 -07002181#define A_XGM_SERDES_STAT1 0x8f4
2182#define A_XGM_SERDES_STAT2 0x8f8
Divy Le Ray4d22de32007-01-18 22:04:14 -05002183
2184#define S_LOWSIG0 0
2185#define V_LOWSIG0(x) ((x) << S_LOWSIG0)
2186#define F_LOWSIG0 V_LOWSIG0(1U)
2187
2188#define A_XGM_SERDES_STAT3 0x8fc
2189
2190#define A_XGM_STAT_TX_BYTE_LOW 0x900
2191
2192#define A_XGM_STAT_TX_BYTE_HIGH 0x904
2193
2194#define A_XGM_STAT_TX_FRAME_LOW 0x908
2195
2196#define A_XGM_STAT_TX_FRAME_HIGH 0x90c
2197
2198#define A_XGM_STAT_TX_BCAST 0x910
2199
2200#define A_XGM_STAT_TX_MCAST 0x914
2201
2202#define A_XGM_STAT_TX_PAUSE 0x918
2203
2204#define A_XGM_STAT_TX_64B_FRAMES 0x91c
2205
2206#define A_XGM_STAT_TX_65_127B_FRAMES 0x920
2207
2208#define A_XGM_STAT_TX_128_255B_FRAMES 0x924
2209
2210#define A_XGM_STAT_TX_256_511B_FRAMES 0x928
2211
2212#define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c
2213
2214#define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930
2215
2216#define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934
2217
2218#define A_XGM_STAT_TX_ERR_FRAMES 0x938
2219
2220#define A_XGM_STAT_RX_BYTES_LOW 0x93c
2221
2222#define A_XGM_STAT_RX_BYTES_HIGH 0x940
2223
2224#define A_XGM_STAT_RX_FRAMES_LOW 0x944
2225
2226#define A_XGM_STAT_RX_FRAMES_HIGH 0x948
2227
2228#define A_XGM_STAT_RX_BCAST_FRAMES 0x94c
2229
2230#define A_XGM_STAT_RX_MCAST_FRAMES 0x950
2231
2232#define A_XGM_STAT_RX_PAUSE_FRAMES 0x954
2233
2234#define A_XGM_STAT_RX_64B_FRAMES 0x958
2235
2236#define A_XGM_STAT_RX_65_127B_FRAMES 0x95c
2237
2238#define A_XGM_STAT_RX_128_255B_FRAMES 0x960
2239
2240#define A_XGM_STAT_RX_256_511B_FRAMES 0x964
2241
2242#define A_XGM_STAT_RX_512_1023B_FRAMES 0x968
2243
2244#define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c
2245
2246#define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970
2247
2248#define A_XGM_STAT_RX_SHORT_FRAMES 0x974
2249
2250#define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978
2251
2252#define A_XGM_STAT_RX_JABBER_FRAMES 0x97c
2253
2254#define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980
2255
2256#define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984
2257
2258#define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988
2259
2260#define A_XGM_SERDES_STATUS0 0x98c
2261
2262#define A_XGM_SERDES_STATUS1 0x990
2263
2264#define S_CMULOCK 31
2265#define V_CMULOCK(x) ((x) << S_CMULOCK)
2266#define F_CMULOCK V_CMULOCK(1U)
2267
2268#define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
2269
Divy Le Rayfc906642007-03-18 13:10:12 -07002270#define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8
2271
2272#define S_TXSPI4SOPCNT 16
2273#define M_TXSPI4SOPCNT 0xffff
2274#define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT)
2275#define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT)
2276
Divy Le Ray4d22de32007-01-18 22:04:14 -05002277#define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac
2278
2279#define XGMAC0_1_BASE_ADDR 0xa00