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Feng Tange24c7452009-12-14 14:20:22 -08001/*
Grant Likelyca632f52011-06-06 01:16:30 -06002 * Designware SPI core controller driver (refer pxa2xx_spi.c)
Feng Tange24c7452009-12-14 14:20:22 -08003 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
Feng Tange24c7452009-12-14 14:20:22 -080014 */
15
16#include <linux/dma-mapping.h>
17#include <linux/interrupt.h>
Paul Gortmakerd7614de2011-07-03 15:44:29 -040018#include <linux/module.h>
Feng Tange24c7452009-12-14 14:20:22 -080019#include <linux/highmem.h>
20#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Feng Tange24c7452009-12-14 14:20:22 -080022#include <linux/spi/spi.h>
Baruch Siachd9c73bb2014-01-31 12:07:47 +020023#include <linux/gpio.h>
Feng Tange24c7452009-12-14 14:20:22 -080024
Grant Likelyca632f52011-06-06 01:16:30 -060025#include "spi-dw.h"
Grant Likely568a60e2011-02-28 12:47:12 -070026
Feng Tange24c7452009-12-14 14:20:22 -080027#ifdef CONFIG_DEBUG_FS
28#include <linux/debugfs.h>
29#endif
30
31#define START_STATE ((void *)0)
32#define RUNNING_STATE ((void *)1)
33#define DONE_STATE ((void *)2)
34#define ERROR_STATE ((void *)-1)
35
Feng Tange24c7452009-12-14 14:20:22 -080036/* Slave spi_dev related */
37struct chip_data {
38 u16 cr0;
39 u8 cs; /* chip select pin */
40 u8 n_bytes; /* current is a 1/2/4 byte op */
41 u8 tmode; /* TR/TO/RO/EEPROM */
42 u8 type; /* SPI/SSP/MicroWire */
43
44 u8 poll_mode; /* 1 means use poll mode */
45
46 u32 dma_width;
47 u32 rx_threshold;
48 u32 tx_threshold;
49 u8 enable_dma;
50 u8 bits_per_word;
51 u16 clk_div; /* baud rate divider */
52 u32 speed_hz; /* baud rate */
Feng Tange24c7452009-12-14 14:20:22 -080053 void (*cs_control)(u32 command);
54};
55
56#ifdef CONFIG_DEBUG_FS
Feng Tange24c7452009-12-14 14:20:22 -080057#define SPI_REGS_BUFSIZE 1024
Andy Shevchenko53288fe2014-09-12 15:11:56 +030058static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
59 size_t count, loff_t *ppos)
Feng Tange24c7452009-12-14 14:20:22 -080060{
Andy Shevchenko53288fe2014-09-12 15:11:56 +030061 struct dw_spi *dws = file->private_data;
Feng Tange24c7452009-12-14 14:20:22 -080062 char *buf;
63 u32 len = 0;
64 ssize_t ret;
65
Feng Tange24c7452009-12-14 14:20:22 -080066 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
67 if (!buf)
68 return 0;
69
70 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
Andy Shevchenko53288fe2014-09-12 15:11:56 +030071 "%s registers:\n", dev_name(&dws->master->dev));
Feng Tange24c7452009-12-14 14:20:22 -080072 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
73 "=================================\n");
74 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070075 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
Feng Tange24c7452009-12-14 14:20:22 -080076 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070077 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
Feng Tange24c7452009-12-14 14:20:22 -080078 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070079 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
Feng Tange24c7452009-12-14 14:20:22 -080080 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070081 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
Feng Tange24c7452009-12-14 14:20:22 -080082 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070083 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
Feng Tange24c7452009-12-14 14:20:22 -080084 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070085 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
Feng Tange24c7452009-12-14 14:20:22 -080086 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070087 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
Feng Tange24c7452009-12-14 14:20:22 -080088 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070089 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
Feng Tange24c7452009-12-14 14:20:22 -080090 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070091 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
Feng Tange24c7452009-12-14 14:20:22 -080092 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070093 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
Feng Tange24c7452009-12-14 14:20:22 -080094 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070095 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
Feng Tange24c7452009-12-14 14:20:22 -080096 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070097 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
Feng Tange24c7452009-12-14 14:20:22 -080098 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070099 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
Feng Tange24c7452009-12-14 14:20:22 -0800100 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700101 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
Feng Tange24c7452009-12-14 14:20:22 -0800102 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700103 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
Feng Tange24c7452009-12-14 14:20:22 -0800104 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
105 "=================================\n");
106
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300107 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
Feng Tange24c7452009-12-14 14:20:22 -0800108 kfree(buf);
109 return ret;
110}
111
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300112static const struct file_operations dw_spi_regs_ops = {
Feng Tange24c7452009-12-14 14:20:22 -0800113 .owner = THIS_MODULE,
Stephen Boyd234e3402012-04-05 14:25:11 -0700114 .open = simple_open,
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300115 .read = dw_spi_show_regs,
Arnd Bergmann6038f372010-08-15 18:52:59 +0200116 .llseek = default_llseek,
Feng Tange24c7452009-12-14 14:20:22 -0800117};
118
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300119static int dw_spi_debugfs_init(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800120{
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300121 dws->debugfs = debugfs_create_dir("dw_spi", NULL);
Feng Tange24c7452009-12-14 14:20:22 -0800122 if (!dws->debugfs)
123 return -ENOMEM;
124
125 debugfs_create_file("registers", S_IFREG | S_IRUGO,
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300126 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
Feng Tange24c7452009-12-14 14:20:22 -0800127 return 0;
128}
129
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300130static void dw_spi_debugfs_remove(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800131{
Jingoo Hanfadcace2014-09-02 11:49:24 +0900132 debugfs_remove_recursive(dws->debugfs);
Feng Tange24c7452009-12-14 14:20:22 -0800133}
134
135#else
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300136static inline int dw_spi_debugfs_init(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800137{
George Shore20a588f2010-01-21 11:40:49 +0000138 return 0;
Feng Tange24c7452009-12-14 14:20:22 -0800139}
140
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300141static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800142{
143}
144#endif /* CONFIG_DEBUG_FS */
145
Alek Du2ff271b2011-03-30 23:09:54 +0800146/* Return the max entries we can fill into tx fifo */
147static inline u32 tx_max(struct dw_spi *dws)
148{
149 u32 tx_left, tx_room, rxtx_gap;
150
151 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700152 tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);
Alek Du2ff271b2011-03-30 23:09:54 +0800153
154 /*
155 * Another concern is about the tx/rx mismatch, we
156 * though to use (dws->fifo_len - rxflr - txflr) as
157 * one maximum value for tx, but it doesn't cover the
158 * data which is out of tx/rx fifo and inside the
159 * shift registers. So a control from sw point of
160 * view is taken.
161 */
162 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
163 / dws->n_bytes;
164
165 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
166}
167
168/* Return the max entries we should read out of rx fifo */
169static inline u32 rx_max(struct dw_spi *dws)
170{
171 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
172
Jingoo Hanfadcace2014-09-02 11:49:24 +0900173 return min_t(u32, rx_left, dw_readw(dws, DW_SPI_RXFLR));
Alek Du2ff271b2011-03-30 23:09:54 +0800174}
175
Alek Du3b8a4dd2011-03-30 23:09:55 +0800176static void dw_writer(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800177{
Alek Du2ff271b2011-03-30 23:09:54 +0800178 u32 max = tx_max(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800179 u16 txw = 0;
Feng Tange24c7452009-12-14 14:20:22 -0800180
Alek Du2ff271b2011-03-30 23:09:54 +0800181 while (max--) {
182 /* Set the tx word if the transfer's original "tx" is not null */
183 if (dws->tx_end - dws->len) {
184 if (dws->n_bytes == 1)
185 txw = *(u8 *)(dws->tx);
186 else
187 txw = *(u16 *)(dws->tx);
188 }
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700189 dw_writew(dws, DW_SPI_DR, txw);
Alek Du2ff271b2011-03-30 23:09:54 +0800190 dws->tx += dws->n_bytes;
Feng Tange24c7452009-12-14 14:20:22 -0800191 }
Feng Tange24c7452009-12-14 14:20:22 -0800192}
193
Alek Du3b8a4dd2011-03-30 23:09:55 +0800194static void dw_reader(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800195{
Alek Du2ff271b2011-03-30 23:09:54 +0800196 u32 max = rx_max(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800197 u16 rxw;
Feng Tange24c7452009-12-14 14:20:22 -0800198
Alek Du2ff271b2011-03-30 23:09:54 +0800199 while (max--) {
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700200 rxw = dw_readw(dws, DW_SPI_DR);
Feng Tangde6efe02011-03-30 23:09:52 +0800201 /* Care rx only if the transfer's original "rx" is not null */
202 if (dws->rx_end - dws->len) {
203 if (dws->n_bytes == 1)
204 *(u8 *)(dws->rx) = rxw;
205 else
206 *(u16 *)(dws->rx) = rxw;
207 }
208 dws->rx += dws->n_bytes;
Feng Tange24c7452009-12-14 14:20:22 -0800209 }
Feng Tange24c7452009-12-14 14:20:22 -0800210}
211
212static void *next_transfer(struct dw_spi *dws)
213{
214 struct spi_message *msg = dws->cur_msg;
215 struct spi_transfer *trans = dws->cur_transfer;
216
217 /* Move to next transfer */
218 if (trans->transfer_list.next != &msg->transfers) {
219 dws->cur_transfer =
220 list_entry(trans->transfer_list.next,
221 struct spi_transfer,
222 transfer_list);
223 return RUNNING_STATE;
Jingoo Hanfadcace2014-09-02 11:49:24 +0900224 }
225
226 return DONE_STATE;
Feng Tange24c7452009-12-14 14:20:22 -0800227}
228
229/*
230 * Note: first step is the protocol driver prepares
231 * a dma-capable memory, and this func just need translate
232 * the virt addr to physical
233 */
234static int map_dma_buffers(struct dw_spi *dws)
235{
Feng Tang7063c0d2010-12-24 13:59:11 +0800236 if (!dws->cur_msg->is_dma_mapped
237 || !dws->dma_inited
238 || !dws->cur_chip->enable_dma
239 || !dws->dma_ops)
Feng Tange24c7452009-12-14 14:20:22 -0800240 return 0;
241
242 if (dws->cur_transfer->tx_dma)
243 dws->tx_dma = dws->cur_transfer->tx_dma;
244
245 if (dws->cur_transfer->rx_dma)
246 dws->rx_dma = dws->cur_transfer->rx_dma;
247
248 return 1;
249}
250
251/* Caller already set message->status; dma and pio irqs are blocked */
252static void giveback(struct dw_spi *dws)
253{
254 struct spi_transfer *last_transfer;
Feng Tange24c7452009-12-14 14:20:22 -0800255 struct spi_message *msg;
256
Feng Tange24c7452009-12-14 14:20:22 -0800257 msg = dws->cur_msg;
258 dws->cur_msg = NULL;
259 dws->cur_transfer = NULL;
260 dws->prev_chip = dws->cur_chip;
261 dws->cur_chip = NULL;
262 dws->dma_mapped = 0;
Feng Tange24c7452009-12-14 14:20:22 -0800263
Axel Lin23e2c2a2014-02-12 22:13:27 +0800264 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
Feng Tange24c7452009-12-14 14:20:22 -0800265 transfer_list);
266
Baruch Siachd9c73bb2014-01-31 12:07:47 +0200267 if (!last_transfer->cs_change)
Andy Shevchenko08a707b2014-08-27 19:26:08 +0300268 spi_chip_sel(dws, msg->spi, 0);
Feng Tange24c7452009-12-14 14:20:22 -0800269
Baruch Siachec37e8e2014-01-31 12:07:44 +0200270 spi_finalize_current_message(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800271}
272
273static void int_error_stop(struct dw_spi *dws, const char *msg)
274{
Alek Du8a33a372011-03-30 23:09:53 +0800275 /* Stop the hw */
Feng Tange24c7452009-12-14 14:20:22 -0800276 spi_enable_chip(dws, 0);
277
278 dev_err(&dws->master->dev, "%s\n", msg);
279 dws->cur_msg->state = ERROR_STATE;
280 tasklet_schedule(&dws->pump_transfers);
281}
282
Feng Tang7063c0d2010-12-24 13:59:11 +0800283void dw_spi_xfer_done(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800284{
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300285 /* Update total byte transferred return count actual bytes read */
Feng Tange24c7452009-12-14 14:20:22 -0800286 dws->cur_msg->actual_length += dws->len;
287
288 /* Move to next transfer */
289 dws->cur_msg->state = next_transfer(dws);
290
291 /* Handle end of message */
292 if (dws->cur_msg->state == DONE_STATE) {
293 dws->cur_msg->status = 0;
294 giveback(dws);
295 } else
296 tasklet_schedule(&dws->pump_transfers);
297}
Feng Tang7063c0d2010-12-24 13:59:11 +0800298EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
Feng Tange24c7452009-12-14 14:20:22 -0800299
300static irqreturn_t interrupt_transfer(struct dw_spi *dws)
301{
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700302 u16 irq_status = dw_readw(dws, DW_SPI_ISR);
Feng Tange24c7452009-12-14 14:20:22 -0800303
Feng Tange24c7452009-12-14 14:20:22 -0800304 /* Error handling */
305 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700306 dw_readw(dws, DW_SPI_TXOICR);
307 dw_readw(dws, DW_SPI_RXOICR);
308 dw_readw(dws, DW_SPI_RXUICR);
Alek Du3b8a4dd2011-03-30 23:09:55 +0800309 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
Feng Tange24c7452009-12-14 14:20:22 -0800310 return IRQ_HANDLED;
311 }
312
Alek Du3b8a4dd2011-03-30 23:09:55 +0800313 dw_reader(dws);
314 if (dws->rx_end == dws->rx) {
315 spi_mask_intr(dws, SPI_INT_TXEI);
316 dw_spi_xfer_done(dws);
317 return IRQ_HANDLED;
318 }
Feng Tang552e4502010-01-20 13:49:45 -0700319 if (irq_status & SPI_INT_TXEI) {
320 spi_mask_intr(dws, SPI_INT_TXEI);
Alek Du3b8a4dd2011-03-30 23:09:55 +0800321 dw_writer(dws);
322 /* Enable TX irq always, it will be disabled when RX finished */
323 spi_umask_intr(dws, SPI_INT_TXEI);
Feng Tange24c7452009-12-14 14:20:22 -0800324 }
Feng Tang552e4502010-01-20 13:49:45 -0700325
Feng Tange24c7452009-12-14 14:20:22 -0800326 return IRQ_HANDLED;
327}
328
329static irqreturn_t dw_spi_irq(int irq, void *dev_id)
330{
331 struct dw_spi *dws = dev_id;
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700332 u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
Yong Wangcbcc0622010-09-07 15:27:27 +0800333
Yong Wangcbcc0622010-09-07 15:27:27 +0800334 if (!irq_status)
335 return IRQ_NONE;
Feng Tange24c7452009-12-14 14:20:22 -0800336
337 if (!dws->cur_msg) {
338 spi_mask_intr(dws, SPI_INT_TXEI);
Feng Tange24c7452009-12-14 14:20:22 -0800339 return IRQ_HANDLED;
340 }
341
342 return dws->transfer_handler(dws);
343}
344
345/* Must be called inside pump_transfers() */
346static void poll_transfer(struct dw_spi *dws)
347{
Alek Du2ff271b2011-03-30 23:09:54 +0800348 do {
349 dw_writer(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800350 dw_reader(dws);
Alek Du2ff271b2011-03-30 23:09:54 +0800351 cpu_relax();
352 } while (dws->rx_end > dws->rx);
Feng Tange24c7452009-12-14 14:20:22 -0800353
Feng Tang7063c0d2010-12-24 13:59:11 +0800354 dw_spi_xfer_done(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800355}
356
357static void pump_transfers(unsigned long data)
358{
359 struct dw_spi *dws = (struct dw_spi *)data;
360 struct spi_message *message = NULL;
361 struct spi_transfer *transfer = NULL;
362 struct spi_transfer *previous = NULL;
363 struct spi_device *spi = NULL;
364 struct chip_data *chip = NULL;
365 u8 bits = 0;
366 u8 imask = 0;
367 u8 cs_change = 0;
Feng Tang552e4502010-01-20 13:49:45 -0700368 u16 txint_level = 0;
Feng Tange24c7452009-12-14 14:20:22 -0800369 u16 clk_div = 0;
370 u32 speed = 0;
371 u32 cr0 = 0;
372
373 /* Get current state information */
374 message = dws->cur_msg;
375 transfer = dws->cur_transfer;
376 chip = dws->cur_chip;
377 spi = message->spi;
378
379 if (message->state == ERROR_STATE) {
380 message->status = -EIO;
381 goto early_exit;
382 }
383
384 /* Handle end of message */
385 if (message->state == DONE_STATE) {
386 message->status = 0;
387 goto early_exit;
388 }
389
Andy Shevchenkoc3c6e232014-09-18 20:08:57 +0300390 /* Delay if requested at end of transfer */
Feng Tange24c7452009-12-14 14:20:22 -0800391 if (message->state == RUNNING_STATE) {
392 previous = list_entry(transfer->transfer_list.prev,
393 struct spi_transfer,
394 transfer_list);
395 if (previous->delay_usecs)
396 udelay(previous->delay_usecs);
397 }
398
399 dws->n_bytes = chip->n_bytes;
400 dws->dma_width = chip->dma_width;
401 dws->cs_control = chip->cs_control;
402
403 dws->rx_dma = transfer->rx_dma;
404 dws->tx_dma = transfer->tx_dma;
405 dws->tx = (void *)transfer->tx_buf;
406 dws->tx_end = dws->tx + transfer->len;
407 dws->rx = transfer->rx_buf;
408 dws->rx_end = dws->rx + transfer->len;
Feng Tange24c7452009-12-14 14:20:22 -0800409 dws->len = dws->cur_transfer->len;
410 if (chip != dws->prev_chip)
411 cs_change = 1;
412
413 cr0 = chip->cr0;
414
415 /* Handle per transfer options for bpw and speed */
416 if (transfer->speed_hz) {
417 speed = chip->speed_hz;
418
Thor Thayer0a8727e2014-11-06 13:54:27 -0600419 if ((transfer->speed_hz != speed) || (!chip->clk_div)) {
Feng Tange24c7452009-12-14 14:20:22 -0800420 speed = transfer->speed_hz;
Feng Tange24c7452009-12-14 14:20:22 -0800421
422 /* clk_div doesn't support odd number */
423 clk_div = dws->max_freq / speed;
Feng Tang552e4502010-01-20 13:49:45 -0700424 clk_div = (clk_div + 1) & 0xfffe;
Feng Tange24c7452009-12-14 14:20:22 -0800425
426 chip->speed_hz = speed;
427 chip->clk_div = clk_div;
428 }
429 }
430 if (transfer->bits_per_word) {
431 bits = transfer->bits_per_word;
Stephen Warren24778be2013-05-21 20:36:35 -0600432 dws->n_bytes = dws->dma_width = bits >> 3;
Feng Tange24c7452009-12-14 14:20:22 -0800433 cr0 = (bits - 1)
434 | (chip->type << SPI_FRF_OFFSET)
435 | (spi->mode << SPI_MODE_OFFSET)
436 | (chip->tmode << SPI_TMOD_OFFSET);
437 }
438 message->state = RUNNING_STATE;
439
George Shore052dc7c2010-01-21 11:40:52 +0000440 /*
441 * Adjust transfer mode if necessary. Requires platform dependent
442 * chipselect mechanism.
443 */
444 if (dws->cs_control) {
445 if (dws->rx && dws->tx)
Feng Tange3e55ff2010-09-07 15:52:06 +0800446 chip->tmode = SPI_TMOD_TR;
George Shore052dc7c2010-01-21 11:40:52 +0000447 else if (dws->rx)
Feng Tange3e55ff2010-09-07 15:52:06 +0800448 chip->tmode = SPI_TMOD_RO;
George Shore052dc7c2010-01-21 11:40:52 +0000449 else
Feng Tange3e55ff2010-09-07 15:52:06 +0800450 chip->tmode = SPI_TMOD_TO;
George Shore052dc7c2010-01-21 11:40:52 +0000451
Feng Tange3e55ff2010-09-07 15:52:06 +0800452 cr0 &= ~SPI_TMOD_MASK;
George Shore052dc7c2010-01-21 11:40:52 +0000453 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
454 }
455
Feng Tange24c7452009-12-14 14:20:22 -0800456 /* Check if current transfer is a DMA transaction */
457 dws->dma_mapped = map_dma_buffers(dws);
458
Feng Tang552e4502010-01-20 13:49:45 -0700459 /*
460 * Interrupt mode
461 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
462 */
Feng Tange24c7452009-12-14 14:20:22 -0800463 if (!dws->dma_mapped && !chip->poll_mode) {
Feng Tang552e4502010-01-20 13:49:45 -0700464 int templen = dws->len / dws->n_bytes;
Jingoo Hanfadcace2014-09-02 11:49:24 +0900465
Feng Tang552e4502010-01-20 13:49:45 -0700466 txint_level = dws->fifo_len / 2;
467 txint_level = (templen > txint_level) ? txint_level : templen;
468
Jingoo Hanfadcace2014-09-02 11:49:24 +0900469 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
470 SPI_INT_RXUI | SPI_INT_RXOI;
Feng Tange24c7452009-12-14 14:20:22 -0800471 dws->transfer_handler = interrupt_transfer;
472 }
473
474 /*
475 * Reprogram registers only if
476 * 1. chip select changes
477 * 2. clk_div is changed
478 * 3. control value changes
479 */
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700480 if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) {
Feng Tange24c7452009-12-14 14:20:22 -0800481 spi_enable_chip(dws, 0);
482
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700483 if (dw_readw(dws, DW_SPI_CTRL0) != cr0)
484 dw_writew(dws, DW_SPI_CTRL0, cr0);
Feng Tange24c7452009-12-14 14:20:22 -0800485
Feng Tange24c7452009-12-14 14:20:22 -0800486 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
Baruch Siachd9c73bb2014-01-31 12:07:47 +0200487 spi_chip_sel(dws, spi, 1);
Feng Tange24c7452009-12-14 14:20:22 -0800488
Justin P. Mattock2f263d92010-12-30 15:07:51 -0800489 /* Set the interrupt mask, for poll mode just disable all int */
Feng Tang552e4502010-01-20 13:49:45 -0700490 spi_mask_intr(dws, 0xff);
491 if (imask)
492 spi_umask_intr(dws, imask);
493 if (txint_level)
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700494 dw_writew(dws, DW_SPI_TXFLTR, txint_level);
Feng Tang552e4502010-01-20 13:49:45 -0700495
496 spi_enable_chip(dws, 1);
Feng Tange24c7452009-12-14 14:20:22 -0800497 if (cs_change)
498 dws->prev_chip = chip;
499 }
500
501 if (dws->dma_mapped)
Feng Tang7063c0d2010-12-24 13:59:11 +0800502 dws->dma_ops->dma_transfer(dws, cs_change);
Feng Tange24c7452009-12-14 14:20:22 -0800503
504 if (chip->poll_mode)
505 poll_transfer(dws);
506
507 return;
508
509early_exit:
510 giveback(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800511}
512
Baruch Siachec37e8e2014-01-31 12:07:44 +0200513static int dw_spi_transfer_one_message(struct spi_master *master,
514 struct spi_message *msg)
Feng Tange24c7452009-12-14 14:20:22 -0800515{
Baruch Siachec37e8e2014-01-31 12:07:44 +0200516 struct dw_spi *dws = spi_master_get_devdata(master);
Feng Tange24c7452009-12-14 14:20:22 -0800517
Baruch Siachec37e8e2014-01-31 12:07:44 +0200518 dws->cur_msg = msg;
Andy Shevchenkoc3c6e232014-09-18 20:08:57 +0300519 /* Initial message state */
Feng Tange24c7452009-12-14 14:20:22 -0800520 dws->cur_msg->state = START_STATE;
521 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
522 struct spi_transfer,
523 transfer_list);
524 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
525
Baruch Siachec37e8e2014-01-31 12:07:44 +0200526 /* Launch transfers */
Feng Tange24c7452009-12-14 14:20:22 -0800527 tasklet_schedule(&dws->pump_transfers);
528
Feng Tange24c7452009-12-14 14:20:22 -0800529 return 0;
530}
531
532/* This may be called twice for each spi dev */
533static int dw_spi_setup(struct spi_device *spi)
534{
535 struct dw_spi_chip *chip_info = NULL;
536 struct chip_data *chip;
Baruch Siachd9c73bb2014-01-31 12:07:47 +0200537 int ret;
Feng Tange24c7452009-12-14 14:20:22 -0800538
Feng Tange24c7452009-12-14 14:20:22 -0800539 /* Only alloc on first setup */
540 chip = spi_get_ctldata(spi);
541 if (!chip) {
Axel Lina97c8832014-08-31 12:47:06 +0800542 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
Feng Tange24c7452009-12-14 14:20:22 -0800543 if (!chip)
544 return -ENOMEM;
Baruch Siach43f627a2013-12-30 20:30:46 +0200545 spi_set_ctldata(spi, chip);
Feng Tange24c7452009-12-14 14:20:22 -0800546 }
547
548 /*
549 * Protocol drivers may change the chip settings, so...
550 * if chip_info exists, use it
551 */
552 chip_info = spi->controller_data;
553
554 /* chip_info doesn't always exist */
555 if (chip_info) {
556 if (chip_info->cs_control)
557 chip->cs_control = chip_info->cs_control;
558
559 chip->poll_mode = chip_info->poll_mode;
560 chip->type = chip_info->type;
561
562 chip->rx_threshold = 0;
563 chip->tx_threshold = 0;
564
565 chip->enable_dma = chip_info->enable_dma;
566 }
567
Stephen Warren24778be2013-05-21 20:36:35 -0600568 if (spi->bits_per_word == 8) {
Feng Tange24c7452009-12-14 14:20:22 -0800569 chip->n_bytes = 1;
570 chip->dma_width = 1;
Stephen Warren24778be2013-05-21 20:36:35 -0600571 } else if (spi->bits_per_word == 16) {
Feng Tange24c7452009-12-14 14:20:22 -0800572 chip->n_bytes = 2;
573 chip->dma_width = 2;
Feng Tange24c7452009-12-14 14:20:22 -0800574 }
575 chip->bits_per_word = spi->bits_per_word;
576
Feng Tang552e4502010-01-20 13:49:45 -0700577 if (!spi->max_speed_hz) {
578 dev_err(&spi->dev, "No max speed HZ parameter\n");
579 return -EINVAL;
580 }
Feng Tange24c7452009-12-14 14:20:22 -0800581
582 chip->tmode = 0; /* Tx & Rx */
583 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
584 chip->cr0 = (chip->bits_per_word - 1)
585 | (chip->type << SPI_FRF_OFFSET)
586 | (spi->mode << SPI_MODE_OFFSET)
587 | (chip->tmode << SPI_TMOD_OFFSET);
588
Andy Shevchenkoc3ce15b2014-09-18 20:08:56 +0300589 if (spi->mode & SPI_LOOP)
590 chip->cr0 |= 1 << SPI_SRL_OFFSET;
591
Baruch Siachd9c73bb2014-01-31 12:07:47 +0200592 if (gpio_is_valid(spi->cs_gpio)) {
593 ret = gpio_direction_output(spi->cs_gpio,
594 !(spi->mode & SPI_CS_HIGH));
595 if (ret)
596 return ret;
597 }
598
Feng Tange24c7452009-12-14 14:20:22 -0800599 return 0;
600}
601
Axel Lina97c8832014-08-31 12:47:06 +0800602static void dw_spi_cleanup(struct spi_device *spi)
603{
604 struct chip_data *chip = spi_get_ctldata(spi);
605
606 kfree(chip);
607 spi_set_ctldata(spi, NULL);
608}
609
Feng Tange24c7452009-12-14 14:20:22 -0800610/* Restart the controller, disable all interrupts, clean rx fifo */
611static void spi_hw_init(struct dw_spi *dws)
612{
613 spi_enable_chip(dws, 0);
614 spi_mask_intr(dws, 0xff);
615 spi_enable_chip(dws, 1);
Feng Tangc587b6f2010-01-21 10:41:10 +0800616
617 /*
618 * Try to detect the FIFO depth if not set by interface driver,
619 * the depth could be from 2 to 256 from HW spec
620 */
621 if (!dws->fifo_len) {
622 u32 fifo;
Jingoo Hanfadcace2014-09-02 11:49:24 +0900623
Feng Tangc587b6f2010-01-21 10:41:10 +0800624 for (fifo = 2; fifo <= 257; fifo++) {
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700625 dw_writew(dws, DW_SPI_TXFLTR, fifo);
626 if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
Feng Tangc587b6f2010-01-21 10:41:10 +0800627 break;
628 }
629
630 dws->fifo_len = (fifo == 257) ? 0 : fifo;
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700631 dw_writew(dws, DW_SPI_TXFLTR, 0);
Feng Tangc587b6f2010-01-21 10:41:10 +0800632 }
Feng Tange24c7452009-12-14 14:20:22 -0800633}
634
Baruch Siach04f421e2013-12-30 20:30:44 +0200635int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800636{
637 struct spi_master *master;
638 int ret;
639
640 BUG_ON(dws == NULL);
641
Baruch Siach04f421e2013-12-30 20:30:44 +0200642 master = spi_alloc_master(dev, 0);
643 if (!master)
644 return -ENOMEM;
Feng Tange24c7452009-12-14 14:20:22 -0800645
646 dws->master = master;
647 dws->type = SSI_MOTO_SPI;
648 dws->prev_chip = NULL;
649 dws->dma_inited = 0;
650 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
Andy Shevchenkoc3c6e232014-09-18 20:08:57 +0300651 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
Feng Tange24c7452009-12-14 14:20:22 -0800652
Baruch Siach04f421e2013-12-30 20:30:44 +0200653 ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
Liu, ShuoX40bfff82011-07-08 14:24:31 +0800654 dws->name, dws);
Feng Tange24c7452009-12-14 14:20:22 -0800655 if (ret < 0) {
656 dev_err(&master->dev, "can not get IRQ\n");
657 goto err_free_master;
658 }
659
Andy Shevchenkoc3ce15b2014-09-18 20:08:56 +0300660 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
Stephen Warren24778be2013-05-21 20:36:35 -0600661 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
Feng Tange24c7452009-12-14 14:20:22 -0800662 master->bus_num = dws->bus_num;
663 master->num_chipselect = dws->num_cs;
Feng Tange24c7452009-12-14 14:20:22 -0800664 master->setup = dw_spi_setup;
Axel Lina97c8832014-08-31 12:47:06 +0800665 master->cleanup = dw_spi_cleanup;
Baruch Siachec37e8e2014-01-31 12:07:44 +0200666 master->transfer_one_message = dw_spi_transfer_one_message;
Axel Lin765ee702014-02-20 21:37:56 +0800667 master->max_speed_hz = dws->max_freq;
Thor Thayer9c6de472014-10-08 13:51:34 -0500668 master->dev.of_node = dev->of_node;
Feng Tange24c7452009-12-14 14:20:22 -0800669
Feng Tange24c7452009-12-14 14:20:22 -0800670 /* Basic HW init */
671 spi_hw_init(dws);
672
Feng Tang7063c0d2010-12-24 13:59:11 +0800673 if (dws->dma_ops && dws->dma_ops->dma_init) {
674 ret = dws->dma_ops->dma_init(dws);
675 if (ret) {
676 dev_warn(&master->dev, "DMA init failed\n");
677 dws->dma_inited = 0;
678 }
679 }
680
Baruch Siachec37e8e2014-01-31 12:07:44 +0200681 tasklet_init(&dws->pump_transfers, pump_transfers, (unsigned long)dws);
Feng Tange24c7452009-12-14 14:20:22 -0800682
683 spi_master_set_devdata(master, dws);
Baruch Siach04f421e2013-12-30 20:30:44 +0200684 ret = devm_spi_register_master(dev, master);
Feng Tange24c7452009-12-14 14:20:22 -0800685 if (ret) {
686 dev_err(&master->dev, "problem registering spi master\n");
Baruch Siachec37e8e2014-01-31 12:07:44 +0200687 goto err_dma_exit;
Feng Tange24c7452009-12-14 14:20:22 -0800688 }
689
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300690 dw_spi_debugfs_init(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800691 return 0;
692
Baruch Siachec37e8e2014-01-31 12:07:44 +0200693err_dma_exit:
Feng Tang7063c0d2010-12-24 13:59:11 +0800694 if (dws->dma_ops && dws->dma_ops->dma_exit)
695 dws->dma_ops->dma_exit(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800696 spi_enable_chip(dws, 0);
Feng Tange24c7452009-12-14 14:20:22 -0800697err_free_master:
698 spi_master_put(master);
Feng Tange24c7452009-12-14 14:20:22 -0800699 return ret;
700}
Feng Tang79290a22010-12-24 13:59:10 +0800701EXPORT_SYMBOL_GPL(dw_spi_add_host);
Feng Tange24c7452009-12-14 14:20:22 -0800702
Grant Likelyfd4a3192012-12-07 16:57:14 +0000703void dw_spi_remove_host(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800704{
Feng Tange24c7452009-12-14 14:20:22 -0800705 if (!dws)
706 return;
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300707 dw_spi_debugfs_remove(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800708
Feng Tang7063c0d2010-12-24 13:59:11 +0800709 if (dws->dma_ops && dws->dma_ops->dma_exit)
710 dws->dma_ops->dma_exit(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800711 spi_enable_chip(dws, 0);
712 /* Disable clk */
713 spi_set_clk(dws, 0);
Feng Tange24c7452009-12-14 14:20:22 -0800714}
Feng Tang79290a22010-12-24 13:59:10 +0800715EXPORT_SYMBOL_GPL(dw_spi_remove_host);
Feng Tange24c7452009-12-14 14:20:22 -0800716
717int dw_spi_suspend_host(struct dw_spi *dws)
718{
719 int ret = 0;
720
Baruch Siachec37e8e2014-01-31 12:07:44 +0200721 ret = spi_master_suspend(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800722 if (ret)
723 return ret;
724 spi_enable_chip(dws, 0);
725 spi_set_clk(dws, 0);
726 return ret;
727}
Feng Tang79290a22010-12-24 13:59:10 +0800728EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
Feng Tange24c7452009-12-14 14:20:22 -0800729
730int dw_spi_resume_host(struct dw_spi *dws)
731{
732 int ret;
733
734 spi_hw_init(dws);
Baruch Siachec37e8e2014-01-31 12:07:44 +0200735 ret = spi_master_resume(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800736 if (ret)
737 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
738 return ret;
739}
Feng Tang79290a22010-12-24 13:59:10 +0800740EXPORT_SYMBOL_GPL(dw_spi_resume_host);
Feng Tange24c7452009-12-14 14:20:22 -0800741
742MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
743MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
744MODULE_LICENSE("GPL v2");