Alex Deucher | 30388c6 | 2012-01-20 14:50:18 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Alex Deucher |
| 23 | * |
| 24 | */ |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame^] | 25 | #include <drm/drmP.h> |
| 26 | #include <drm/radeon_drm.h> |
Alex Deucher | 30388c6 | 2012-01-20 14:50:18 -0500 | [diff] [blame] | 27 | #include "radeon.h" |
| 28 | #include "atom.h" |
| 29 | |
| 30 | #define TARGET_HW_I2C_CLOCK 50 |
| 31 | |
| 32 | /* these are a limitation of ProcessI2cChannelTransaction not the hw */ |
| 33 | #define ATOM_MAX_HW_I2C_WRITE 2 |
| 34 | #define ATOM_MAX_HW_I2C_READ 255 |
| 35 | |
| 36 | static int radeon_process_i2c_ch(struct radeon_i2c_chan *chan, |
| 37 | u8 slave_addr, u8 flags, |
| 38 | u8 *buf, u8 num) |
| 39 | { |
| 40 | struct drm_device *dev = chan->dev; |
| 41 | struct radeon_device *rdev = dev->dev_private; |
| 42 | PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args; |
| 43 | int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction); |
| 44 | unsigned char *base; |
| 45 | u16 out; |
| 46 | |
| 47 | memset(&args, 0, sizeof(args)); |
| 48 | |
| 49 | base = (unsigned char *)rdev->mode_info.atom_context->scratch; |
| 50 | |
| 51 | if (flags & HW_I2C_WRITE) { |
| 52 | if (num > ATOM_MAX_HW_I2C_WRITE) { |
| 53 | DRM_ERROR("hw i2c: tried to write too many bytes (%d vs 2)\n", num); |
| 54 | return -EINVAL; |
| 55 | } |
| 56 | memcpy(&out, buf, num); |
| 57 | args.lpI2CDataOut = cpu_to_le16(out); |
| 58 | } else { |
| 59 | if (num > ATOM_MAX_HW_I2C_READ) { |
| 60 | DRM_ERROR("hw i2c: tried to read too many bytes (%d vs 255)\n", num); |
| 61 | return -EINVAL; |
| 62 | } |
| 63 | } |
| 64 | |
| 65 | args.ucI2CSpeed = TARGET_HW_I2C_CLOCK; |
| 66 | args.ucRegIndex = 0; |
| 67 | args.ucTransBytes = num; |
| 68 | args.ucSlaveAddr = slave_addr << 1; |
| 69 | args.ucLineNumber = chan->rec.i2c_id; |
| 70 | |
| 71 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 72 | |
| 73 | /* error */ |
| 74 | if (args.ucStatus != HW_ASSISTED_I2C_STATUS_SUCCESS) { |
| 75 | DRM_DEBUG_KMS("hw_i2c error\n"); |
| 76 | return -EIO; |
| 77 | } |
| 78 | |
| 79 | if (!(flags & HW_I2C_WRITE)) |
| 80 | memcpy(buf, base, num); |
| 81 | |
| 82 | return 0; |
| 83 | } |
| 84 | |
| 85 | int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap, |
| 86 | struct i2c_msg *msgs, int num) |
| 87 | { |
| 88 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); |
| 89 | struct i2c_msg *p; |
| 90 | int i, remaining, current_count, buffer_offset, max_bytes, ret; |
| 91 | u8 buf = 0, flags; |
| 92 | |
| 93 | /* check for bus probe */ |
| 94 | p = &msgs[0]; |
| 95 | if ((num == 1) && (p->len == 0)) { |
| 96 | ret = radeon_process_i2c_ch(i2c, |
| 97 | p->addr, HW_I2C_WRITE, |
| 98 | &buf, 1); |
| 99 | if (ret) |
| 100 | return ret; |
| 101 | else |
| 102 | return num; |
| 103 | } |
| 104 | |
| 105 | for (i = 0; i < num; i++) { |
| 106 | p = &msgs[i]; |
| 107 | remaining = p->len; |
| 108 | buffer_offset = 0; |
| 109 | /* max_bytes are a limitation of ProcessI2cChannelTransaction not the hw */ |
| 110 | if (p->flags & I2C_M_RD) { |
| 111 | max_bytes = ATOM_MAX_HW_I2C_READ; |
| 112 | flags = HW_I2C_READ; |
| 113 | } else { |
| 114 | max_bytes = ATOM_MAX_HW_I2C_WRITE; |
| 115 | flags = HW_I2C_WRITE; |
| 116 | } |
| 117 | while (remaining) { |
| 118 | if (remaining > max_bytes) |
| 119 | current_count = max_bytes; |
| 120 | else |
| 121 | current_count = remaining; |
| 122 | ret = radeon_process_i2c_ch(i2c, |
| 123 | p->addr, flags, |
| 124 | &p->buf[buffer_offset], current_count); |
| 125 | if (ret) |
| 126 | return ret; |
| 127 | remaining -= current_count; |
| 128 | buffer_offset += current_count; |
| 129 | } |
| 130 | } |
| 131 | |
| 132 | return num; |
| 133 | } |
| 134 | |
| 135 | u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap) |
| 136 | { |
| 137 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
| 138 | } |
| 139 | |