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David Brownellff4569c2009-03-04 12:01:37 -08001/*
2 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
3 *
4 * Copyright © 2006 Texas Instruments.
5 *
6 * Port to 2.6.23 Copyright © 2008 by:
7 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
8 * Troy Kisky <troy.kisky@boundarydevices.com>
9 * Dirk Behme <Dirk.Behme@gmail.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/kernel.h>
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
30#include <linux/err.h>
31#include <linux/clk.h>
32#include <linux/io.h>
33#include <linux/mtd/nand.h>
34#include <linux/mtd/partitions.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090035#include <linux/slab.h>
Heiko Schochercdeadd72012-07-30 09:22:24 +020036#include <linux/of_device.h>
Sachin Kamatc4f8cde2013-03-14 15:37:01 +053037#include <linux/of.h>
David Brownellff4569c2009-03-04 12:01:37 -080038
Arnd Bergmannec2a0832012-08-24 15:11:34 +020039#include <linux/platform_data/mtd-davinci.h>
40#include <linux/platform_data/mtd-davinci-aemif.h>
David Brownellff4569c2009-03-04 12:01:37 -080041
David Brownellff4569c2009-03-04 12:01:37 -080042/*
43 * This is a device driver for the NAND flash controller found on the
44 * various DaVinci family chips. It handles up to four SoC chipselects,
45 * and some flavors of secondary chipselect (e.g. based on A12) as used
46 * with multichip packages.
47 *
David Brownell6a4123e2009-04-21 19:58:13 -070048 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
David Brownellff4569c2009-03-04 12:01:37 -080049 * available on chips like the DM355 and OMAP-L137 and needed with the
50 * more error-prone MLC NAND chips.
51 *
52 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
53 * outputs in a "wire-AND" configuration, with no per-chip signals.
54 */
55struct davinci_nand_info {
56 struct mtd_info mtd;
57 struct nand_chip chip;
David Brownell6a4123e2009-04-21 19:58:13 -070058 struct nand_ecclayout ecclayout;
David Brownellff4569c2009-03-04 12:01:37 -080059
60 struct device *dev;
61 struct clk *clk;
David Brownellff4569c2009-03-04 12:01:37 -080062
David Brownell6a4123e2009-04-21 19:58:13 -070063 bool is_readmode;
64
David Brownellff4569c2009-03-04 12:01:37 -080065 void __iomem *base;
66 void __iomem *vaddr;
67
68 uint32_t ioaddr;
69 uint32_t current_cs;
70
71 uint32_t mask_chipsel;
72 uint32_t mask_ale;
73 uint32_t mask_cle;
74
75 uint32_t core_chipsel;
Sekhar Noria88dbc52010-08-09 15:46:36 +053076
77 struct davinci_aemif_timing *timing;
David Brownellff4569c2009-03-04 12:01:37 -080078};
79
80static DEFINE_SPINLOCK(davinci_nand_lock);
David Brownell6a4123e2009-04-21 19:58:13 -070081static bool ecc4_busy;
David Brownellff4569c2009-03-04 12:01:37 -080082
83#define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)
84
85
86static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
87 int offset)
88{
89 return __raw_readl(info->base + offset);
90}
91
92static inline void davinci_nand_writel(struct davinci_nand_info *info,
93 int offset, unsigned long value)
94{
95 __raw_writel(value, info->base + offset);
96}
97
98/*----------------------------------------------------------------------*/
99
100/*
101 * Access to hardware control lines: ALE, CLE, secondary chipselect.
102 */
103
104static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
105 unsigned int ctrl)
106{
107 struct davinci_nand_info *info = to_davinci_nand(mtd);
108 uint32_t addr = info->current_cs;
109 struct nand_chip *nand = mtd->priv;
110
111 /* Did the control lines change? */
112 if (ctrl & NAND_CTRL_CHANGE) {
113 if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
114 addr |= info->mask_cle;
115 else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
116 addr |= info->mask_ale;
117
118 nand->IO_ADDR_W = (void __iomem __force *)addr;
119 }
120
121 if (cmd != NAND_CMD_NONE)
122 iowrite8(cmd, nand->IO_ADDR_W);
123}
124
125static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
126{
127 struct davinci_nand_info *info = to_davinci_nand(mtd);
128 uint32_t addr = info->ioaddr;
129
130 /* maybe kick in a second chipselect */
131 if (chip > 0)
132 addr |= info->mask_chipsel;
133 info->current_cs = addr;
134
135 info->chip.IO_ADDR_W = (void __iomem __force *)addr;
136 info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
137}
138
139/*----------------------------------------------------------------------*/
140
141/*
142 * 1-bit hardware ECC ... context maintained for each core chipselect
143 */
144
145static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
146{
147 struct davinci_nand_info *info = to_davinci_nand(mtd);
148
149 return davinci_nand_readl(info, NANDF1ECC_OFFSET
150 + 4 * info->core_chipsel);
151}
152
153static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
154{
155 struct davinci_nand_info *info;
156 uint32_t nandcfr;
157 unsigned long flags;
158
159 info = to_davinci_nand(mtd);
160
161 /* Reset ECC hardware */
162 nand_davinci_readecc_1bit(mtd);
163
164 spin_lock_irqsave(&davinci_nand_lock, flags);
165
166 /* Restart ECC hardware */
167 nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
168 nandcfr |= BIT(8 + info->core_chipsel);
169 davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
170
171 spin_unlock_irqrestore(&davinci_nand_lock, flags);
172}
173
174/*
175 * Read hardware ECC value and pack into three bytes
176 */
177static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
178 const u_char *dat, u_char *ecc_code)
179{
180 unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
181 unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
182
183 /* invert so that erased block ecc is correct */
184 ecc24 = ~ecc24;
185 ecc_code[0] = (u_char)(ecc24);
186 ecc_code[1] = (u_char)(ecc24 >> 8);
187 ecc_code[2] = (u_char)(ecc24 >> 16);
188
189 return 0;
190}
191
192static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
193 u_char *read_ecc, u_char *calc_ecc)
194{
195 struct nand_chip *chip = mtd->priv;
196 uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
197 (read_ecc[2] << 16);
198 uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
199 (calc_ecc[2] << 16);
200 uint32_t diff = eccCalc ^ eccNand;
201
202 if (diff) {
203 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
204 /* Correctable error */
205 if ((diff >> (12 + 3)) < chip->ecc.size) {
206 dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
207 return 1;
208 } else {
209 return -1;
210 }
211 } else if (!(diff & (diff - 1))) {
212 /* Single bit ECC error in the ECC itself,
213 * nothing to fix */
214 return 1;
215 } else {
216 /* Uncorrectable error */
217 return -1;
218 }
219
220 }
221 return 0;
222}
223
224/*----------------------------------------------------------------------*/
225
226/*
David Brownell6a4123e2009-04-21 19:58:13 -0700227 * 4-bit hardware ECC ... context maintained over entire AEMIF
228 *
229 * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
230 * since that forces use of a problematic "infix OOB" layout.
231 * Among other things, it trashes manufacturer bad block markers.
232 * Also, and specific to this hardware, it ECC-protects the "prepad"
233 * in the OOB ... while having ECC protection for parts of OOB would
234 * seem useful, the current MTD stack sometimes wants to update the
235 * OOB without recomputing ECC.
236 */
237
238static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
239{
240 struct davinci_nand_info *info = to_davinci_nand(mtd);
241 unsigned long flags;
242 u32 val;
243
244 spin_lock_irqsave(&davinci_nand_lock, flags);
245
246 /* Start 4-bit ECC calculation for read/write */
247 val = davinci_nand_readl(info, NANDFCR_OFFSET);
248 val &= ~(0x03 << 4);
249 val |= (info->core_chipsel << 4) | BIT(12);
250 davinci_nand_writel(info, NANDFCR_OFFSET, val);
251
252 info->is_readmode = (mode == NAND_ECC_READ);
253
254 spin_unlock_irqrestore(&davinci_nand_lock, flags);
255}
256
257/* Read raw ECC code after writing to NAND. */
258static void
259nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
260{
261 const u32 mask = 0x03ff03ff;
262
263 code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
264 code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
265 code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
266 code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
267}
268
269/* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
270static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
271 const u_char *dat, u_char *ecc_code)
272{
273 struct davinci_nand_info *info = to_davinci_nand(mtd);
274 u32 raw_ecc[4], *p;
275 unsigned i;
276
277 /* After a read, terminate ECC calculation by a dummy read
278 * of some 4-bit ECC register. ECC covers everything that
279 * was read; correct() just uses the hardware state, so
280 * ecc_code is not needed.
281 */
282 if (info->is_readmode) {
283 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
284 return 0;
285 }
286
287 /* Pack eight raw 10-bit ecc values into ten bytes, making
288 * two passes which each convert four values (in upper and
289 * lower halves of two 32-bit words) into five bytes. The
290 * ROM boot loader uses this same packing scheme.
291 */
292 nand_davinci_readecc_4bit(info, raw_ecc);
293 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
294 *ecc_code++ = p[0] & 0xff;
295 *ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
296 *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
297 *ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
298 *ecc_code++ = (p[1] >> 18) & 0xff;
299 }
300
301 return 0;
302}
303
304/* Correct up to 4 bits in data we just read, using state left in the
305 * hardware plus the ecc_code computed when it was first written.
306 */
307static int nand_davinci_correct_4bit(struct mtd_info *mtd,
308 u_char *data, u_char *ecc_code, u_char *null)
309{
310 int i;
311 struct davinci_nand_info *info = to_davinci_nand(mtd);
312 unsigned short ecc10[8];
313 unsigned short *ecc16;
314 u32 syndrome[4];
Sudhakar Rajashekhara1c3275b2010-07-20 15:24:01 -0700315 u32 ecc_state;
David Brownell6a4123e2009-04-21 19:58:13 -0700316 unsigned num_errors, corrected;
Wolfram Sang2bdb0532010-09-03 12:35:37 +0200317 unsigned long timeo;
David Brownell6a4123e2009-04-21 19:58:13 -0700318
319 /* All bytes 0xff? It's an erased page; ignore its ECC. */
320 for (i = 0; i < 10; i++) {
321 if (ecc_code[i] != 0xff)
322 goto compare;
323 }
324 return 0;
325
326compare:
327 /* Unpack ten bytes into eight 10 bit values. We know we're
328 * little-endian, and use type punning for less shifting/masking.
329 */
330 if (WARN_ON(0x01 & (unsigned) ecc_code))
331 return -EINVAL;
332 ecc16 = (unsigned short *)ecc_code;
333
334 ecc10[0] = (ecc16[0] >> 0) & 0x3ff;
335 ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
336 ecc10[2] = (ecc16[1] >> 4) & 0x3ff;
337 ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc);
338 ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300);
339 ecc10[5] = (ecc16[3] >> 2) & 0x3ff;
340 ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0);
341 ecc10[7] = (ecc16[4] >> 6) & 0x3ff;
342
343 /* Tell ECC controller about the expected ECC codes. */
344 for (i = 7; i >= 0; i--)
345 davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
346
347 /* Allow time for syndrome calculation ... then read it.
348 * A syndrome of all zeroes 0 means no detected errors.
349 */
350 davinci_nand_readl(info, NANDFSR_OFFSET);
351 nand_davinci_readecc_4bit(info, syndrome);
352 if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
353 return 0;
354
Sneha Narnakajef12a9472009-09-18 12:51:48 -0700355 /*
356 * Clear any previous address calculation by doing a dummy read of an
357 * error address register.
358 */
359 davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
360
David Brownell6a4123e2009-04-21 19:58:13 -0700361 /* Start address calculation, and wait for it to complete.
362 * We _could_ start reading more data while this is working,
363 * to speed up the overall page read.
364 */
365 davinci_nand_writel(info, NANDFCR_OFFSET,
366 davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
Sudhakar Rajashekhara1c3275b2010-07-20 15:24:01 -0700367
368 /*
369 * ECC_STATE field reads 0x3 (Error correction complete) immediately
370 * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
371 * begin trying to poll for the state, you may fall right out of your
372 * loop without any of the correction calculations having taken place.
Wolfram Sangeea116e2010-08-25 14:18:20 +0200373 * The recommendation from the hardware team is to initially delay as
374 * long as ECC_STATE reads less than 4. After that, ECC HW has entered
375 * correction state.
Sudhakar Rajashekhara1c3275b2010-07-20 15:24:01 -0700376 */
Wolfram Sang2bdb0532010-09-03 12:35:37 +0200377 timeo = jiffies + usecs_to_jiffies(100);
Sudhakar Rajashekhara1c3275b2010-07-20 15:24:01 -0700378 do {
379 ecc_state = (davinci_nand_readl(info,
380 NANDFSR_OFFSET) >> 8) & 0x0f;
381 cpu_relax();
382 } while ((ecc_state < 4) && time_before(jiffies, timeo));
383
David Brownell6a4123e2009-04-21 19:58:13 -0700384 for (;;) {
385 u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
386
387 switch ((fsr >> 8) & 0x0f) {
388 case 0: /* no error, should not happen */
Sneha Narnakajef12a9472009-09-18 12:51:48 -0700389 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
David Brownell6a4123e2009-04-21 19:58:13 -0700390 return 0;
391 case 1: /* five or more errors detected */
Sneha Narnakajef12a9472009-09-18 12:51:48 -0700392 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
David Brownell6a4123e2009-04-21 19:58:13 -0700393 return -EIO;
394 case 2: /* error addresses computed */
395 case 3:
396 num_errors = 1 + ((fsr >> 16) & 0x03);
397 goto correct;
398 default: /* still working on it */
399 cpu_relax();
400 continue;
401 }
402 }
403
404correct:
405 /* correct each error */
406 for (i = 0, corrected = 0; i < num_errors; i++) {
407 int error_address, error_value;
408
409 if (i > 1) {
410 error_address = davinci_nand_readl(info,
411 NAND_ERR_ADD2_OFFSET);
412 error_value = davinci_nand_readl(info,
413 NAND_ERR_ERRVAL2_OFFSET);
414 } else {
415 error_address = davinci_nand_readl(info,
416 NAND_ERR_ADD1_OFFSET);
417 error_value = davinci_nand_readl(info,
418 NAND_ERR_ERRVAL1_OFFSET);
419 }
420
421 if (i & 1) {
422 error_address >>= 16;
423 error_value >>= 16;
424 }
425 error_address &= 0x3ff;
426 error_address = (512 + 7) - error_address;
427
428 if (error_address < 512) {
429 data[error_address] ^= error_value;
430 corrected++;
431 }
432 }
433
434 return corrected;
435}
436
437/*----------------------------------------------------------------------*/
438
439/*
David Brownellff4569c2009-03-04 12:01:37 -0800440 * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
441 * how these chips are normally wired. This translates to both 8 and 16
442 * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
443 *
444 * For now we assume that configuration, or any other one which ignores
445 * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
446 * and have that transparently morphed into multiple NAND operations.
447 */
448static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
449{
450 struct nand_chip *chip = mtd->priv;
451
452 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
453 ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
454 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
455 ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
456 else
457 ioread8_rep(chip->IO_ADDR_R, buf, len);
458}
459
460static void nand_davinci_write_buf(struct mtd_info *mtd,
461 const uint8_t *buf, int len)
462{
463 struct nand_chip *chip = mtd->priv;
464
465 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
466 iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
467 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
468 iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
469 else
470 iowrite8_rep(chip->IO_ADDR_R, buf, len);
471}
472
473/*
474 * Check hardware register for wait status. Returns 1 if device is ready,
475 * 0 if it is still busy.
476 */
477static int nand_davinci_dev_ready(struct mtd_info *mtd)
478{
479 struct davinci_nand_info *info = to_davinci_nand(mtd);
480
481 return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
482}
483
David Brownellff4569c2009-03-04 12:01:37 -0800484/*----------------------------------------------------------------------*/
485
David Brownell6a4123e2009-04-21 19:58:13 -0700486/* An ECC layout for using 4-bit ECC with small-page flash, storing
487 * ten ECC bytes plus the manufacturer's bad block marker byte, and
488 * and not overlapping the default BBT markers.
489 */
490static struct nand_ecclayout hwecc4_small __initconst = {
491 .eccbytes = 10,
492 .eccpos = { 0, 1, 2, 3, 4,
493 /* offset 5 holds the badblock marker */
494 6, 7,
495 13, 14, 15, },
496 .oobfree = {
497 {.offset = 8, .length = 5, },
498 {.offset = 16, },
499 },
500};
501
Sneha Narnakajef12a9472009-09-18 12:51:48 -0700502/* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash,
503 * storing ten ECC bytes plus the manufacturer's bad block marker byte,
504 * and not overlapping the default BBT markers.
505 */
506static struct nand_ecclayout hwecc4_2048 __initconst = {
507 .eccbytes = 40,
508 .eccpos = {
509 /* at the end of spare sector */
510 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
511 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
512 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
513 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
514 },
515 .oobfree = {
516 /* 2 bytes at offset 0 hold manufacturer badblock markers */
517 {.offset = 2, .length = 22, },
518 /* 5 bytes at offset 8 hold BBT markers */
519 /* 8 bytes at offset 16 hold JFFS2 clean markers */
520 },
521};
David Brownell6a4123e2009-04-21 19:58:13 -0700522
Heiko Schochercdeadd72012-07-30 09:22:24 +0200523#if defined(CONFIG_OF)
524static const struct of_device_id davinci_nand_of_match[] = {
525 {.compatible = "ti,davinci-nand", },
526 {},
Sergei Shtylyov13daa222013-01-03 21:27:34 +0300527};
Heiko Schochercdeadd72012-07-30 09:22:24 +0200528MODULE_DEVICE_TABLE(of, davinci_nand_of_match);
529
530static struct davinci_nand_pdata
531 *nand_davinci_get_pdata(struct platform_device *pdev)
532{
533 if (!pdev->dev.platform_data && pdev->dev.of_node) {
534 struct davinci_nand_pdata *pdata;
535 const char *mode;
536 u32 prop;
537 int len;
538
539 pdata = devm_kzalloc(&pdev->dev,
540 sizeof(struct davinci_nand_pdata),
541 GFP_KERNEL);
542 pdev->dev.platform_data = pdata;
543 if (!pdata)
544 return NULL;
545 if (!of_property_read_u32(pdev->dev.of_node,
546 "ti,davinci-chipselect", &prop))
547 pdev->id = prop;
548 if (!of_property_read_u32(pdev->dev.of_node,
549 "ti,davinci-mask-ale", &prop))
550 pdata->mask_ale = prop;
551 if (!of_property_read_u32(pdev->dev.of_node,
552 "ti,davinci-mask-cle", &prop))
553 pdata->mask_cle = prop;
554 if (!of_property_read_u32(pdev->dev.of_node,
555 "ti,davinci-mask-chipsel", &prop))
556 pdata->mask_chipsel = prop;
557 if (!of_property_read_string(pdev->dev.of_node,
558 "ti,davinci-ecc-mode", &mode)) {
559 if (!strncmp("none", mode, 4))
560 pdata->ecc_mode = NAND_ECC_NONE;
561 if (!strncmp("soft", mode, 4))
562 pdata->ecc_mode = NAND_ECC_SOFT;
563 if (!strncmp("hw", mode, 2))
564 pdata->ecc_mode = NAND_ECC_HW;
565 }
566 if (!of_property_read_u32(pdev->dev.of_node,
567 "ti,davinci-ecc-bits", &prop))
568 pdata->ecc_bits = prop;
569 if (!of_property_read_u32(pdev->dev.of_node,
570 "ti,davinci-nand-buswidth", &prop))
571 if (prop == 16)
572 pdata->options |= NAND_BUSWIDTH_16;
573 if (of_find_property(pdev->dev.of_node,
574 "ti,davinci-nand-use-bbt", &len))
575 pdata->bbt_options = NAND_BBT_USE_FLASH;
576 }
577
578 return pdev->dev.platform_data;
579}
580#else
Heiko Schochercdeadd72012-07-30 09:22:24 +0200581static struct davinci_nand_pdata
582 *nand_davinci_get_pdata(struct platform_device *pdev)
583{
584 return pdev->dev.platform_data;
585}
586#endif
587
David Brownellff4569c2009-03-04 12:01:37 -0800588static int __init nand_davinci_probe(struct platform_device *pdev)
589{
Heiko Schochercdeadd72012-07-30 09:22:24 +0200590 struct davinci_nand_pdata *pdata;
David Brownellff4569c2009-03-04 12:01:37 -0800591 struct davinci_nand_info *info;
592 struct resource *res1;
593 struct resource *res2;
594 void __iomem *vaddr;
595 void __iomem *base;
596 int ret;
597 uint32_t val;
598 nand_ecc_modes_t ecc_mode;
599
Heiko Schochercdeadd72012-07-30 09:22:24 +0200600 pdata = nand_davinci_get_pdata(pdev);
David Brownell533a0142009-04-21 19:51:31 -0700601 /* insist on board-specific configuration */
602 if (!pdata)
603 return -ENODEV;
604
David Brownellff4569c2009-03-04 12:01:37 -0800605 /* which external chipselect will we be managing? */
606 if (pdev->id < 0 || pdev->id > 3)
607 return -ENODEV;
608
Mrugesh Katepallewaref4e0c22013-02-07 16:03:15 +0530609 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
David Brownellff4569c2009-03-04 12:01:37 -0800610 if (!info) {
611 dev_err(&pdev->dev, "unable to allocate memory\n");
612 ret = -ENOMEM;
613 goto err_nomem;
614 }
615
616 platform_set_drvdata(pdev, info);
617
618 res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
619 res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
620 if (!res1 || !res2) {
621 dev_err(&pdev->dev, "resource missing\n");
622 ret = -EINVAL;
623 goto err_nomem;
624 }
625
Mrugesh Katepallewaref4e0c22013-02-07 16:03:15 +0530626 vaddr = devm_request_and_ioremap(&pdev->dev, res1);
627 base = devm_request_and_ioremap(&pdev->dev, res2);
David Brownellff4569c2009-03-04 12:01:37 -0800628 if (!vaddr || !base) {
629 dev_err(&pdev->dev, "ioremap failed\n");
Mrugesh Katepallewaref4e0c22013-02-07 16:03:15 +0530630 ret = -EADDRNOTAVAIL;
David Brownellff4569c2009-03-04 12:01:37 -0800631 goto err_ioremap;
632 }
633
634 info->dev = &pdev->dev;
635 info->base = base;
636 info->vaddr = vaddr;
637
638 info->mtd.priv = &info->chip;
639 info->mtd.name = dev_name(&pdev->dev);
640 info->mtd.owner = THIS_MODULE;
641
David Brownell87f39f02009-03-26 00:42:50 -0700642 info->mtd.dev.parent = &pdev->dev;
643
David Brownellff4569c2009-03-04 12:01:37 -0800644 info->chip.IO_ADDR_R = vaddr;
645 info->chip.IO_ADDR_W = vaddr;
646 info->chip.chip_delay = 0;
647 info->chip.select_chip = nand_davinci_select_chip;
648
Brian Norrisbb9ebd42011-05-31 16:31:23 -0700649 /* options such as NAND_BBT_USE_FLASH */
Brian Norrisa40f7342011-05-31 16:31:22 -0700650 info->chip.bbt_options = pdata->bbt_options;
651 /* options such as 16-bit widths */
David Brownell533a0142009-04-21 19:51:31 -0700652 info->chip.options = pdata->options;
Mark A. Greerf611a792009-10-12 16:16:37 -0700653 info->chip.bbt_td = pdata->bbt_td;
654 info->chip.bbt_md = pdata->bbt_md;
Sekhar Noria88dbc52010-08-09 15:46:36 +0530655 info->timing = pdata->timing;
David Brownellff4569c2009-03-04 12:01:37 -0800656
657 info->ioaddr = (uint32_t __force) vaddr;
658
659 info->current_cs = info->ioaddr;
660 info->core_chipsel = pdev->id;
661 info->mask_chipsel = pdata->mask_chipsel;
662
663 /* use nandboot-capable ALE/CLE masks by default */
Hemant Pedanekar5cd0be82009-10-01 19:55:06 +0530664 info->mask_ale = pdata->mask_ale ? : MASK_ALE;
David Brownell533a0142009-04-21 19:51:31 -0700665 info->mask_cle = pdata->mask_cle ? : MASK_CLE;
David Brownellff4569c2009-03-04 12:01:37 -0800666
667 /* Set address of hardware control function */
668 info->chip.cmd_ctrl = nand_davinci_hwcontrol;
669 info->chip.dev_ready = nand_davinci_dev_ready;
670
671 /* Speed up buffer I/O */
672 info->chip.read_buf = nand_davinci_read_buf;
673 info->chip.write_buf = nand_davinci_write_buf;
674
David Brownell533a0142009-04-21 19:51:31 -0700675 /* Use board-specific ECC config */
676 ecc_mode = pdata->ecc_mode;
David Brownellff4569c2009-03-04 12:01:37 -0800677
David Brownell6a4123e2009-04-21 19:58:13 -0700678 ret = -EINVAL;
David Brownellff4569c2009-03-04 12:01:37 -0800679 switch (ecc_mode) {
680 case NAND_ECC_NONE:
681 case NAND_ECC_SOFT:
David Brownell6a4123e2009-04-21 19:58:13 -0700682 pdata->ecc_bits = 0;
David Brownellff4569c2009-03-04 12:01:37 -0800683 break;
684 case NAND_ECC_HW:
David Brownell6a4123e2009-04-21 19:58:13 -0700685 if (pdata->ecc_bits == 4) {
686 /* No sanity checks: CPUs must support this,
687 * and the chips may not use NAND_BUSWIDTH_16.
688 */
David Brownellff4569c2009-03-04 12:01:37 -0800689
David Brownell6a4123e2009-04-21 19:58:13 -0700690 /* No sharing 4-bit hardware between chipselects yet */
691 spin_lock_irq(&davinci_nand_lock);
692 if (ecc4_busy)
693 ret = -EBUSY;
694 else
695 ecc4_busy = true;
696 spin_unlock_irq(&davinci_nand_lock);
697
698 if (ret == -EBUSY)
699 goto err_ecc;
700
701 info->chip.ecc.calculate = nand_davinci_calculate_4bit;
702 info->chip.ecc.correct = nand_davinci_correct_4bit;
703 info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
704 info->chip.ecc.bytes = 10;
705 } else {
706 info->chip.ecc.calculate = nand_davinci_calculate_1bit;
707 info->chip.ecc.correct = nand_davinci_correct_1bit;
708 info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
709 info->chip.ecc.bytes = 3;
710 }
711 info->chip.ecc.size = 512;
Mike Dunn6a918ba2012-03-11 14:21:11 -0700712 info->chip.ecc.strength = pdata->ecc_bits;
David Brownell6a4123e2009-04-21 19:58:13 -0700713 break;
David Brownellff4569c2009-03-04 12:01:37 -0800714 default:
715 ret = -EINVAL;
716 goto err_ecc;
717 }
718 info->chip.ecc.mode = ecc_mode;
719
Mrugesh Katepallewaref4e0c22013-02-07 16:03:15 +0530720 info->clk = devm_clk_get(&pdev->dev, "aemif");
David Brownellff4569c2009-03-04 12:01:37 -0800721 if (IS_ERR(info->clk)) {
722 ret = PTR_ERR(info->clk);
Kevin Hilmancd24f8c2009-06-05 18:48:08 +0100723 dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
David Brownellff4569c2009-03-04 12:01:37 -0800724 goto err_clk;
725 }
726
m-karicheri2@ti.comea73fe72012-09-12 21:06:19 +0000727 ret = clk_prepare_enable(info->clk);
David Brownellff4569c2009-03-04 12:01:37 -0800728 if (ret < 0) {
Kevin Hilmancd24f8c2009-06-05 18:48:08 +0100729 dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
730 ret);
David Brownellff4569c2009-03-04 12:01:37 -0800731 goto err_clk_enable;
732 }
733
Sekhar Noria88dbc52010-08-09 15:46:36 +0530734 /*
735 * Setup Async configuration register in case we did not boot from
736 * NAND and so bootloader did not bother to set it up.
David Brownellff4569c2009-03-04 12:01:37 -0800737 */
Sekhar Noria88dbc52010-08-09 15:46:36 +0530738 val = davinci_nand_readl(info, A1CR_OFFSET + info->core_chipsel * 4);
739
740 /* Extended Wait is not valid and Select Strobe mode is not used */
741 val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK);
742 if (info->chip.options & NAND_BUSWIDTH_16)
743 val |= 0x1;
744
745 davinci_nand_writel(info, A1CR_OFFSET + info->core_chipsel * 4, val);
746
Heiko Schocher47882d72011-12-04 10:37:36 +0100747 ret = 0;
748 if (info->timing)
749 ret = davinci_aemif_setup_timing(info->timing, info->base,
Sekhar Noria88dbc52010-08-09 15:46:36 +0530750 info->core_chipsel);
751 if (ret < 0) {
752 dev_dbg(&pdev->dev, "NAND timing values setup fail\n");
753 goto err_timing;
754 }
David Brownellff4569c2009-03-04 12:01:37 -0800755
756 spin_lock_irq(&davinci_nand_lock);
757
758 /* put CSxNAND into NAND mode */
759 val = davinci_nand_readl(info, NANDFCR_OFFSET);
760 val |= BIT(info->core_chipsel);
761 davinci_nand_writel(info, NANDFCR_OFFSET, val);
762
763 spin_unlock_irq(&davinci_nand_lock);
764
765 /* Scan to find existence of the device(s) */
David Woodhouse5e81e882010-02-26 18:32:56 +0000766 ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1, NULL);
David Brownellff4569c2009-03-04 12:01:37 -0800767 if (ret < 0) {
768 dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
769 goto err_scan;
770 }
771
David Brownell6a4123e2009-04-21 19:58:13 -0700772 /* Update ECC layout if needed ... for 1-bit HW ECC, the default
773 * is OK, but it allocates 6 bytes when only 3 are needed (for
774 * each 512 bytes). For the 4-bit HW ECC, that default is not
775 * usable: 10 bytes are needed, not 6.
776 */
777 if (pdata->ecc_bits == 4) {
778 int chunks = info->mtd.writesize / 512;
779
780 if (!chunks || info->mtd.oobsize < 16) {
781 dev_dbg(&pdev->dev, "too small\n");
782 ret = -EINVAL;
783 goto err_scan;
784 }
785
786 /* For small page chips, preserve the manufacturer's
787 * badblock marking data ... and make sure a flash BBT
788 * table marker fits in the free bytes.
789 */
790 if (chunks == 1) {
791 info->ecclayout = hwecc4_small;
792 info->ecclayout.oobfree[1].length =
793 info->mtd.oobsize - 16;
794 goto syndrome_done;
795 }
Sneha Narnakajef12a9472009-09-18 12:51:48 -0700796 if (chunks == 4) {
797 info->ecclayout = hwecc4_2048;
798 info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
799 goto syndrome_done;
800 }
David Brownell6a4123e2009-04-21 19:58:13 -0700801
Sneha Narnakajef12a9472009-09-18 12:51:48 -0700802 /* 4KiB page chips are not yet supported. The eccpos from
803 * nand_ecclayout cannot hold 80 bytes and change to eccpos[]
804 * breaks userspace ioctl interface with mtd-utils. Once we
805 * resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used
806 * for the 4KiB page chips.
Brian Norriscc26c3c2010-08-24 18:12:00 -0700807 *
808 * TODO: Note that nand_ecclayout has now been expanded and can
809 * hold plenty of OOB entries.
David Brownell6a4123e2009-04-21 19:58:13 -0700810 */
811 dev_warn(&pdev->dev, "no 4-bit ECC support yet "
Sneha Narnakajef12a9472009-09-18 12:51:48 -0700812 "for 4KiB-page NAND\n");
David Brownell6a4123e2009-04-21 19:58:13 -0700813 ret = -EIO;
814 goto err_scan;
815
816syndrome_done:
817 info->chip.ecc.layout = &info->ecclayout;
818 }
819
820 ret = nand_scan_tail(&info->mtd);
821 if (ret < 0)
822 goto err_scan;
823
Murali Karicheri192afdb2012-11-02 10:22:41 -0400824 if (pdata->parts)
825 ret = mtd_device_parse_register(&info->mtd, NULL, NULL,
826 pdata->parts, pdata->nr_parts);
827 else {
828 struct mtd_part_parser_data ppdata;
David Brownellff4569c2009-03-04 12:01:37 -0800829
Murali Karicheri192afdb2012-11-02 10:22:41 -0400830 ppdata.of_node = pdev->dev.of_node;
831 ret = mtd_device_parse_register(&info->mtd, NULL, &ppdata,
832 NULL, 0);
833 }
David Brownellff4569c2009-03-04 12:01:37 -0800834 if (ret < 0)
835 goto err_scan;
836
837 val = davinci_nand_readl(info, NRCSR_OFFSET);
838 dev_info(&pdev->dev, "controller rev. %d.%d\n",
839 (val >> 8) & 0xff, val & 0xff);
840
841 return 0;
842
843err_scan:
Sekhar Noria88dbc52010-08-09 15:46:36 +0530844err_timing:
m-karicheri2@ti.comea73fe72012-09-12 21:06:19 +0000845 clk_disable_unprepare(info->clk);
David Brownellff4569c2009-03-04 12:01:37 -0800846
847err_clk_enable:
David Brownell6a4123e2009-04-21 19:58:13 -0700848 spin_lock_irq(&davinci_nand_lock);
849 if (ecc_mode == NAND_ECC_HW_SYNDROME)
850 ecc4_busy = false;
851 spin_unlock_irq(&davinci_nand_lock);
852
David Brownellff4569c2009-03-04 12:01:37 -0800853err_ecc:
854err_clk:
855err_ioremap:
David Brownellff4569c2009-03-04 12:01:37 -0800856err_nomem:
David Brownellff4569c2009-03-04 12:01:37 -0800857 return ret;
858}
859
860static int __exit nand_davinci_remove(struct platform_device *pdev)
861{
862 struct davinci_nand_info *info = platform_get_drvdata(pdev);
David Brownellff4569c2009-03-04 12:01:37 -0800863
David Brownell6a4123e2009-04-21 19:58:13 -0700864 spin_lock_irq(&davinci_nand_lock);
865 if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
866 ecc4_busy = false;
867 spin_unlock_irq(&davinci_nand_lock);
868
David Brownellff4569c2009-03-04 12:01:37 -0800869 nand_release(&info->mtd);
870
m-karicheri2@ti.comea73fe72012-09-12 21:06:19 +0000871 clk_disable_unprepare(info->clk);
David Brownellff4569c2009-03-04 12:01:37 -0800872
873 return 0;
874}
875
876static struct platform_driver nand_davinci_driver = {
877 .remove = __exit_p(nand_davinci_remove),
878 .driver = {
879 .name = "davinci_nand",
Heiko Schochercdeadd72012-07-30 09:22:24 +0200880 .owner = THIS_MODULE,
Sachin Kamatc4f8cde2013-03-14 15:37:01 +0530881 .of_match_table = of_match_ptr(davinci_nand_of_match),
David Brownellff4569c2009-03-04 12:01:37 -0800882 },
883};
884MODULE_ALIAS("platform:davinci_nand");
885
Jingoo Han97135112013-03-05 13:31:47 +0900886module_platform_driver_probe(nand_davinci_driver, nand_davinci_probe);
David Brownellff4569c2009-03-04 12:01:37 -0800887
888MODULE_LICENSE("GPL");
889MODULE_AUTHOR("Texas Instruments");
890MODULE_DESCRIPTION("Davinci NAND flash driver");
891