blob: 17b308592c4fc3bacc41b2f92c0671da940596f2 [file] [log] [blame]
Dave Airlie0d6aa602006-01-02 20:14:23 +11001/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10006 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110027 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Jesse Barnes63eeaf32009-06-18 16:56:52 -070029#include <linux/sysrq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080034#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#define MAX_NOPID ((u32)~0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Keith Packard7c463582008-11-04 02:03:27 -080038/**
39 * Interrupts that are always left unmasked.
40 *
41 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
42 * we leave them always unmasked in IMR and then control enabling them through
43 * PIPESTAT alone.
44 */
Jesse Barnes63eeaf32009-06-18 16:56:52 -070045#define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
46 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
47 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
48 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Keith Packard7c463582008-11-04 02:03:27 -080049
50/** Interrupts that we mask and unmask at runtime. */
51#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
52
Jesse Barnes79e53942008-11-07 14:24:08 -080053#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
54 PIPE_VBLANK_INTERRUPT_STATUS)
55
56#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
57 PIPE_VBLANK_INTERRUPT_ENABLE)
58
59#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
60 DRM_I915_VBLANK_PIPE_B)
61
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +010062void
Zhenyu Wang036a4a72009-06-08 14:40:19 +080063igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
64{
65 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
66 dev_priv->gt_irq_mask_reg &= ~mask;
67 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
68 (void) I915_READ(GTIMR);
69 }
70}
71
72static inline void
73igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
74{
75 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
76 dev_priv->gt_irq_mask_reg |= mask;
77 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
78 (void) I915_READ(GTIMR);
79 }
80}
81
82/* For display hotplug interrupt */
83void
84igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
85{
86 if ((dev_priv->irq_mask_reg & mask) != 0) {
87 dev_priv->irq_mask_reg &= ~mask;
88 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
89 (void) I915_READ(DEIMR);
90 }
91}
92
93static inline void
94igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
95{
96 if ((dev_priv->irq_mask_reg & mask) != mask) {
97 dev_priv->irq_mask_reg |= mask;
98 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
99 (void) I915_READ(DEIMR);
100 }
101}
102
103void
Eric Anholted4cb412008-07-29 12:10:39 -0700104i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
105{
106 if ((dev_priv->irq_mask_reg & mask) != 0) {
107 dev_priv->irq_mask_reg &= ~mask;
108 I915_WRITE(IMR, dev_priv->irq_mask_reg);
109 (void) I915_READ(IMR);
110 }
111}
112
113static inline void
114i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
115{
116 if ((dev_priv->irq_mask_reg & mask) != mask) {
117 dev_priv->irq_mask_reg |= mask;
118 I915_WRITE(IMR, dev_priv->irq_mask_reg);
119 (void) I915_READ(IMR);
120 }
121}
122
Keith Packard7c463582008-11-04 02:03:27 -0800123static inline u32
124i915_pipestat(int pipe)
125{
126 if (pipe == 0)
127 return PIPEASTAT;
128 if (pipe == 1)
129 return PIPEBSTAT;
Andrew Morton9c84ba42008-12-01 13:14:08 -0800130 BUG();
Keith Packard7c463582008-11-04 02:03:27 -0800131}
132
133void
134i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
135{
136 if ((dev_priv->pipestat[pipe] & mask) != mask) {
137 u32 reg = i915_pipestat(pipe);
138
139 dev_priv->pipestat[pipe] |= mask;
140 /* Enable the interrupt, clear any pending status */
141 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
142 (void) I915_READ(reg);
143 }
144}
145
146void
147i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
148{
149 if ((dev_priv->pipestat[pipe] & mask) != 0) {
150 u32 reg = i915_pipestat(pipe);
151
152 dev_priv->pipestat[pipe] &= ~mask;
153 I915_WRITE(reg, dev_priv->pipestat[pipe]);
154 (void) I915_READ(reg);
155 }
156}
157
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000158/**
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700159 * i915_pipe_enabled - check if a pipe is enabled
160 * @dev: DRM device
161 * @pipe: pipe to check
162 *
163 * Reading certain registers when the pipe is disabled can hang the chip.
164 * Use this routine to make sure the PLL is running and the pipe is active
165 * before reading such registers if unsure.
166 */
167static int
168i915_pipe_enabled(struct drm_device *dev, int pipe)
169{
170 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
171 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
172
173 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
174 return 1;
175
176 return 0;
177}
178
Keith Packard42f52ef2008-10-18 19:39:29 -0700179/* Called from drm generic code, passed a 'crtc', which
180 * we use as a pipe index
181 */
182u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700183{
184 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
185 unsigned long high_frame;
186 unsigned long low_frame;
187 u32 high1, high2, low, count;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700188
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700189 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
190 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
191
192 if (!i915_pipe_enabled(dev, pipe)) {
193 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
194 return 0;
195 }
196
197 /*
198 * High & low register fields aren't synchronized, so make sure
199 * we get a low value that's stable across two reads of the high
200 * register.
201 */
202 do {
203 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
204 PIPE_FRAME_HIGH_SHIFT);
205 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
206 PIPE_FRAME_LOW_SHIFT);
207 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
208 PIPE_FRAME_HIGH_SHIFT);
209 } while (high1 != high2);
210
211 count = (high1 << 8) | low;
212
213 return count;
214}
215
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800216u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
217{
218 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
219 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
220
221 if (!i915_pipe_enabled(dev, pipe)) {
222 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
223 return 0;
224 }
225
226 return I915_READ(reg);
227}
228
Jesse Barnes5ca58282009-03-31 14:11:15 -0700229/*
230 * Handle hotplug events outside the interrupt handler proper.
231 */
232static void i915_hotplug_work_func(struct work_struct *work)
233{
234 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
235 hotplug_work);
236 struct drm_device *dev = dev_priv->dev;
Keith Packardc31c4ba2009-05-06 11:48:58 -0700237 struct drm_mode_config *mode_config = &dev->mode_config;
238 struct drm_connector *connector;
Jesse Barnes5ca58282009-03-31 14:11:15 -0700239
Keith Packardc31c4ba2009-05-06 11:48:58 -0700240 if (mode_config->num_connector) {
241 list_for_each_entry(connector, &mode_config->connector_list, head) {
242 struct intel_output *intel_output = to_intel_output(connector);
243
244 if (intel_output->hot_plug)
245 (*intel_output->hot_plug) (intel_output);
246 }
247 }
Jesse Barnes5ca58282009-03-31 14:11:15 -0700248 /* Just fire off a uevent and let userspace tell us what to do */
249 drm_sysfs_hotplug_event(dev);
250}
251
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800252irqreturn_t igdng_irq_handler(struct drm_device *dev)
253{
254 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
255 int ret = IRQ_NONE;
256 u32 de_iir, gt_iir;
257 u32 new_de_iir, new_gt_iir;
258 struct drm_i915_master_private *master_priv;
259
260 de_iir = I915_READ(DEIIR);
261 gt_iir = I915_READ(GTIIR);
262
263 for (;;) {
264 if (de_iir == 0 && gt_iir == 0)
265 break;
266
267 ret = IRQ_HANDLED;
268
269 I915_WRITE(DEIIR, de_iir);
270 new_de_iir = I915_READ(DEIIR);
271 I915_WRITE(GTIIR, gt_iir);
272 new_gt_iir = I915_READ(GTIIR);
273
274 if (dev->primary->master) {
275 master_priv = dev->primary->master->driver_priv;
276 if (master_priv->sarea_priv)
277 master_priv->sarea_priv->last_dispatch =
278 READ_BREADCRUMB(dev_priv);
279 }
280
281 if (gt_iir & GT_USER_INTERRUPT) {
282 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
283 DRM_WAKEUP(&dev_priv->irq_queue);
284 }
285
286 de_iir = new_de_iir;
287 gt_iir = new_gt_iir;
288 }
289
290 return ret;
291}
292
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700293static void i915_capture_error_state(struct drm_device *dev)
294{
295 struct drm_i915_private *dev_priv = dev->dev_private;
296 struct drm_i915_error_state *error;
297 unsigned long flags;
298
299 spin_lock_irqsave(&dev_priv->error_lock, flags);
300 if (dev_priv->first_error)
301 goto out;
302
303 error = kmalloc(sizeof(*error), GFP_ATOMIC);
304 if (!error) {
305 DRM_DEBUG("out ot memory, not capturing error state\n");
306 goto out;
307 }
308
309 error->eir = I915_READ(EIR);
310 error->pgtbl_er = I915_READ(PGTBL_ER);
311 error->pipeastat = I915_READ(PIPEASTAT);
312 error->pipebstat = I915_READ(PIPEBSTAT);
313 error->instpm = I915_READ(INSTPM);
314 if (!IS_I965G(dev)) {
315 error->ipeir = I915_READ(IPEIR);
316 error->ipehr = I915_READ(IPEHR);
317 error->instdone = I915_READ(INSTDONE);
318 error->acthd = I915_READ(ACTHD);
319 } else {
320 error->ipeir = I915_READ(IPEIR_I965);
321 error->ipehr = I915_READ(IPEHR_I965);
322 error->instdone = I915_READ(INSTDONE_I965);
323 error->instps = I915_READ(INSTPS);
324 error->instdone1 = I915_READ(INSTDONE1);
325 error->acthd = I915_READ(ACTHD_I965);
326 }
327
328 dev_priv->first_error = error;
329
330out:
331 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
332}
333
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
335{
Dave Airlie84b1fd12007-07-11 15:53:27 +1000336 struct drm_device *dev = (struct drm_device *) arg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000338 struct drm_i915_master_private *master_priv;
Eric Anholtcdfbc412008-11-04 15:50:30 -0800339 u32 iir, new_iir;
340 u32 pipea_stats, pipeb_stats;
Keith Packard05eff842008-11-19 14:03:05 -0800341 u32 vblank_status;
342 u32 vblank_enable;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700343 int vblank = 0;
Keith Packard7c463582008-11-04 02:03:27 -0800344 unsigned long irqflags;
Keith Packard05eff842008-11-19 14:03:05 -0800345 int irq_received;
346 int ret = IRQ_NONE;
Dave Airlieaf6061a2008-05-07 12:15:39 +1000347
Eric Anholt630681d2008-10-06 15:14:12 -0700348 atomic_inc(&dev_priv->irq_received);
349
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800350 if (IS_IGDNG(dev))
351 return igdng_irq_handler(dev);
352
Eric Anholted4cb412008-07-29 12:10:39 -0700353 iir = I915_READ(IIR);
Dave Airlieaf6061a2008-05-07 12:15:39 +1000354
Keith Packard05eff842008-11-19 14:03:05 -0800355 if (IS_I965G(dev)) {
356 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
357 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
358 } else {
359 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
360 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
361 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362
Keith Packard05eff842008-11-19 14:03:05 -0800363 for (;;) {
364 irq_received = iir != 0;
365
366 /* Can't rely on pipestat interrupt bit in iir as it might
367 * have been cleared after the pipestat interrupt was received.
368 * It doesn't set the bit in iir again, but it still produces
369 * interrupts (for non-MSI).
370 */
371 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
372 pipea_stats = I915_READ(PIPEASTAT);
373 pipeb_stats = I915_READ(PIPEBSTAT);
Jesse Barnes79e53942008-11-07 14:24:08 -0800374
Eric Anholtcdfbc412008-11-04 15:50:30 -0800375 /*
376 * Clear the PIPE(A|B)STAT regs before the IIR
377 */
Keith Packard05eff842008-11-19 14:03:05 -0800378 if (pipea_stats & 0x8000ffff) {
Eric Anholtcdfbc412008-11-04 15:50:30 -0800379 I915_WRITE(PIPEASTAT, pipea_stats);
Keith Packard05eff842008-11-19 14:03:05 -0800380 irq_received = 1;
Eric Anholtcdfbc412008-11-04 15:50:30 -0800381 }
Keith Packard7c463582008-11-04 02:03:27 -0800382
Keith Packard05eff842008-11-19 14:03:05 -0800383 if (pipeb_stats & 0x8000ffff) {
Eric Anholtcdfbc412008-11-04 15:50:30 -0800384 I915_WRITE(PIPEBSTAT, pipeb_stats);
Keith Packard05eff842008-11-19 14:03:05 -0800385 irq_received = 1;
Eric Anholtcdfbc412008-11-04 15:50:30 -0800386 }
Keith Packard05eff842008-11-19 14:03:05 -0800387 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
388
389 if (!irq_received)
390 break;
391
392 ret = IRQ_HANDLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393
Jesse Barnes5ca58282009-03-31 14:11:15 -0700394 /* Consume port. Then clear IIR or we'll miss events */
395 if ((I915_HAS_HOTPLUG(dev)) &&
396 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
397 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
398
399 DRM_DEBUG("hotplug event received, stat 0x%08x\n",
400 hotplug_status);
401 if (hotplug_status & dev_priv->hotplug_supported_mask)
402 schedule_work(&dev_priv->hotplug_work);
403
404 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
405 I915_READ(PORT_HOTPLUG_STAT);
406 }
407
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700408 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) {
409 u32 eir = I915_READ(EIR);
410
411 i915_capture_error_state(dev);
412
413 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
414 eir);
415 if (eir & I915_ERROR_PAGE_TABLE) {
416 u32 pgtbl_err = I915_READ(PGTBL_ER);
417 printk(KERN_ERR "page table error\n");
418 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
419 pgtbl_err);
420 I915_WRITE(PGTBL_ER, pgtbl_err);
421 (void)I915_READ(PGTBL_ER);
422 }
423 if (eir & I915_ERROR_MEMORY_REFRESH) {
424 printk(KERN_ERR "memory refresh error\n");
425 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
426 pipea_stats);
427 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
428 pipeb_stats);
429 /* pipestat has already been acked */
430 }
431 if (eir & I915_ERROR_INSTRUCTION) {
432 printk(KERN_ERR "instruction error\n");
433 printk(KERN_ERR " INSTPM: 0x%08x\n",
434 I915_READ(INSTPM));
435 if (!IS_I965G(dev)) {
436 u32 ipeir = I915_READ(IPEIR);
437
438 printk(KERN_ERR " IPEIR: 0x%08x\n",
439 I915_READ(IPEIR));
440 printk(KERN_ERR " IPEHR: 0x%08x\n",
441 I915_READ(IPEHR));
442 printk(KERN_ERR " INSTDONE: 0x%08x\n",
443 I915_READ(INSTDONE));
444 printk(KERN_ERR " ACTHD: 0x%08x\n",
445 I915_READ(ACTHD));
446 I915_WRITE(IPEIR, ipeir);
447 (void)I915_READ(IPEIR);
448 } else {
449 u32 ipeir = I915_READ(IPEIR_I965);
450
451 printk(KERN_ERR " IPEIR: 0x%08x\n",
452 I915_READ(IPEIR_I965));
453 printk(KERN_ERR " IPEHR: 0x%08x\n",
454 I915_READ(IPEHR_I965));
455 printk(KERN_ERR " INSTDONE: 0x%08x\n",
456 I915_READ(INSTDONE_I965));
457 printk(KERN_ERR " INSTPS: 0x%08x\n",
458 I915_READ(INSTPS));
459 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
460 I915_READ(INSTDONE1));
461 printk(KERN_ERR " ACTHD: 0x%08x\n",
462 I915_READ(ACTHD_I965));
463 I915_WRITE(IPEIR_I965, ipeir);
464 (void)I915_READ(IPEIR_I965);
465 }
466 }
467
468 I915_WRITE(EIR, eir);
469 (void)I915_READ(EIR);
470 eir = I915_READ(EIR);
471 if (eir) {
472 /*
473 * some errors might have become stuck,
474 * mask them.
475 */
476 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
477 I915_WRITE(EMR, I915_READ(EMR) | eir);
478 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
479 }
480 }
481
Eric Anholtcdfbc412008-11-04 15:50:30 -0800482 I915_WRITE(IIR, iir);
483 new_iir = I915_READ(IIR); /* Flush posted writes */
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100484
Dave Airlie7c1c2872008-11-28 14:22:24 +1000485 if (dev->primary->master) {
486 master_priv = dev->primary->master->driver_priv;
487 if (master_priv->sarea_priv)
488 master_priv->sarea_priv->last_dispatch =
489 READ_BREADCRUMB(dev_priv);
490 }
Keith Packard7c463582008-11-04 02:03:27 -0800491
Eric Anholtcdfbc412008-11-04 15:50:30 -0800492 if (iir & I915_USER_INTERRUPT) {
493 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
494 DRM_WAKEUP(&dev_priv->irq_queue);
495 }
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700496
Keith Packard05eff842008-11-19 14:03:05 -0800497 if (pipea_stats & vblank_status) {
Eric Anholtcdfbc412008-11-04 15:50:30 -0800498 vblank++;
499 drm_handle_vblank(dev, 0);
500 }
Eric Anholt673a3942008-07-30 12:06:12 -0700501
Keith Packard05eff842008-11-19 14:03:05 -0800502 if (pipeb_stats & vblank_status) {
Eric Anholtcdfbc412008-11-04 15:50:30 -0800503 vblank++;
504 drm_handle_vblank(dev, 1);
505 }
Keith Packard7c463582008-11-04 02:03:27 -0800506
Eric Anholtcdfbc412008-11-04 15:50:30 -0800507 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
508 (iir & I915_ASLE_INTERRUPT))
509 opregion_asle_intr(dev);
Keith Packard7c463582008-11-04 02:03:27 -0800510
Eric Anholtcdfbc412008-11-04 15:50:30 -0800511 /* With MSI, interrupts are only generated when iir
512 * transitions from zero to nonzero. If another bit got
513 * set while we were handling the existing iir bits, then
514 * we would never get another interrupt.
515 *
516 * This is fine on non-MSI as well, as if we hit this path
517 * we avoid exiting the interrupt handler only to generate
518 * another one.
519 *
520 * Note that for MSI this could cause a stray interrupt report
521 * if an interrupt landed in the time between writing IIR and
522 * the posting read. This should be rare enough to never
523 * trigger the 99% of 100,000 interrupts test for disabling
524 * stray interrupts.
525 */
526 iir = new_iir;
Keith Packard05eff842008-11-19 14:03:05 -0800527 }
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700528
Keith Packard05eff842008-11-19 14:03:05 -0800529 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530}
531
Dave Airlieaf6061a2008-05-07 12:15:39 +1000532static int i915_emit_irq(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533{
534 drm_i915_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000535 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536 RING_LOCALS;
537
538 i915_kernel_lost_context(dev);
539
Márton Németh3e684ea2008-01-24 15:58:57 +1000540 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541
Kristian Høgsbergc99b0582008-08-20 11:20:13 -0400542 dev_priv->counter++;
Alan Hourihanec29b6692006-08-12 16:29:24 +1000543 if (dev_priv->counter > 0x7FFFFFFFUL)
Kristian Høgsbergc99b0582008-08-20 11:20:13 -0400544 dev_priv->counter = 1;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000545 if (master_priv->sarea_priv)
546 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
Alan Hourihanec29b6692006-08-12 16:29:24 +1000547
Keith Packard0baf8232008-11-08 11:44:14 +1000548 BEGIN_LP_RING(4);
Jesse Barnes585fb112008-07-29 11:54:06 -0700549 OUT_RING(MI_STORE_DWORD_INDEX);
Keith Packard0baf8232008-11-08 11:44:14 +1000550 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
Alan Hourihanec29b6692006-08-12 16:29:24 +1000551 OUT_RING(dev_priv->counter);
Jesse Barnes585fb112008-07-29 11:54:06 -0700552 OUT_RING(MI_USER_INTERRUPT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553 ADVANCE_LP_RING();
Dave Airliebc5f4522007-11-05 12:50:58 +1000554
Alan Hourihanec29b6692006-08-12 16:29:24 +1000555 return dev_priv->counter;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556}
557
Eric Anholt673a3942008-07-30 12:06:12 -0700558void i915_user_irq_get(struct drm_device *dev)
Eric Anholted4cb412008-07-29 12:10:39 -0700559{
560 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -0700561 unsigned long irqflags;
Eric Anholted4cb412008-07-29 12:10:39 -0700562
Keith Packarde9d21d72008-10-16 11:31:38 -0700563 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800564 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
565 if (IS_IGDNG(dev))
566 igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
567 else
568 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
569 }
Keith Packarde9d21d72008-10-16 11:31:38 -0700570 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
Eric Anholted4cb412008-07-29 12:10:39 -0700571}
572
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700573void i915_user_irq_put(struct drm_device *dev)
Eric Anholted4cb412008-07-29 12:10:39 -0700574{
575 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -0700576 unsigned long irqflags;
Eric Anholted4cb412008-07-29 12:10:39 -0700577
Keith Packarde9d21d72008-10-16 11:31:38 -0700578 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
Eric Anholted4cb412008-07-29 12:10:39 -0700579 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800580 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
581 if (IS_IGDNG(dev))
582 igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
583 else
584 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
585 }
Keith Packarde9d21d72008-10-16 11:31:38 -0700586 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
Eric Anholted4cb412008-07-29 12:10:39 -0700587}
588
Dave Airlie84b1fd12007-07-11 15:53:27 +1000589static int i915_wait_irq(struct drm_device * dev, int irq_nr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700590{
591 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000592 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593 int ret = 0;
594
Márton Németh3e684ea2008-01-24 15:58:57 +1000595 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596 READ_BREADCRUMB(dev_priv));
597
Eric Anholted4cb412008-07-29 12:10:39 -0700598 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
Dave Airlie7c1c2872008-11-28 14:22:24 +1000599 if (master_priv->sarea_priv)
600 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601 return 0;
Eric Anholted4cb412008-07-29 12:10:39 -0700602 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603
Dave Airlie7c1c2872008-11-28 14:22:24 +1000604 if (master_priv->sarea_priv)
605 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606
Eric Anholted4cb412008-07-29 12:10:39 -0700607 i915_user_irq_get(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
609 READ_BREADCRUMB(dev_priv) >= irq_nr);
Eric Anholted4cb412008-07-29 12:10:39 -0700610 i915_user_irq_put(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611
Eric Anholt20caafa2007-08-25 19:22:43 +1000612 if (ret == -EBUSY) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000613 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
615 }
616
Dave Airlieaf6061a2008-05-07 12:15:39 +1000617 return ret;
618}
619
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620/* Needs the lock as it touches the ring.
621 */
Eric Anholtc153f452007-09-03 12:06:45 +1000622int i915_irq_emit(struct drm_device *dev, void *data,
623 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +1000626 drm_i915_irq_emit_t *emit = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 int result;
628
Eric Anholt07f4f8b2009-04-16 13:46:12 -0700629 if (!dev_priv || !dev_priv->ring.virtual_start) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000630 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000631 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632 }
Eric Anholt299eb932009-02-24 22:14:12 -0800633
634 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
635
Eric Anholt546b0972008-09-01 16:45:29 -0700636 mutex_lock(&dev->struct_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637 result = i915_emit_irq(dev);
Eric Anholt546b0972008-09-01 16:45:29 -0700638 mutex_unlock(&dev->struct_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639
Eric Anholtc153f452007-09-03 12:06:45 +1000640 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641 DRM_ERROR("copy_to_user\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000642 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643 }
644
645 return 0;
646}
647
648/* Doesn't need the hardware lock.
649 */
Eric Anholtc153f452007-09-03 12:06:45 +1000650int i915_irq_wait(struct drm_device *dev, void *data,
651 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +1000654 drm_i915_irq_wait_t *irqwait = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655
656 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000657 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000658 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659 }
660
Eric Anholtc153f452007-09-03 12:06:45 +1000661 return i915_wait_irq(dev, irqwait->irq_seq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662}
663
Keith Packard42f52ef2008-10-18 19:39:29 -0700664/* Called from drm generic code, passed 'crtc' which
665 * we use as a pipe index
666 */
667int i915_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700668{
669 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -0700670 unsigned long irqflags;
Jesse Barnes71e0ffa2009-01-08 10:42:15 -0800671 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
672 u32 pipeconf;
673
674 pipeconf = I915_READ(pipeconf_reg);
675 if (!(pipeconf & PIPEACONF_ENABLE))
676 return -EINVAL;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700677
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800678 if (IS_IGDNG(dev))
679 return 0;
680
Keith Packarde9d21d72008-10-16 11:31:38 -0700681 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
Keith Packarde9d21d72008-10-16 11:31:38 -0700682 if (IS_I965G(dev))
Keith Packard7c463582008-11-04 02:03:27 -0800683 i915_enable_pipestat(dev_priv, pipe,
684 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -0700685 else
Keith Packard7c463582008-11-04 02:03:27 -0800686 i915_enable_pipestat(dev_priv, pipe,
687 PIPE_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -0700688 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700689 return 0;
690}
691
Keith Packard42f52ef2008-10-18 19:39:29 -0700692/* Called from drm generic code, passed 'crtc' which
693 * we use as a pipe index
694 */
695void i915_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700696{
697 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -0700698 unsigned long irqflags;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700699
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800700 if (IS_IGDNG(dev))
701 return;
702
Keith Packarde9d21d72008-10-16 11:31:38 -0700703 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
Keith Packard7c463582008-11-04 02:03:27 -0800704 i915_disable_pipestat(dev_priv, pipe,
705 PIPE_VBLANK_INTERRUPT_ENABLE |
706 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -0700707 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700708}
709
Jesse Barnes79e53942008-11-07 14:24:08 -0800710void i915_enable_interrupt (struct drm_device *dev)
711{
712 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wange170b032009-06-05 15:38:40 +0800713
714 if (!IS_IGDNG(dev))
715 opregion_enable_asle(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -0800716 dev_priv->irq_enabled = 1;
717}
718
719
Dave Airlie702880f2006-06-24 17:07:34 +1000720/* Set the vblank monitor pipe
721 */
Eric Anholtc153f452007-09-03 12:06:45 +1000722int i915_vblank_pipe_set(struct drm_device *dev, void *data,
723 struct drm_file *file_priv)
Dave Airlie702880f2006-06-24 17:07:34 +1000724{
Dave Airlie702880f2006-06-24 17:07:34 +1000725 drm_i915_private_t *dev_priv = dev->dev_private;
Dave Airlie702880f2006-06-24 17:07:34 +1000726
727 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000728 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000729 return -EINVAL;
Dave Airlie702880f2006-06-24 17:07:34 +1000730 }
731
=?utf-8?q?Michel_D=C3=A4nzer?=5b516942006-10-25 00:08:23 +1000732 return 0;
Dave Airlie702880f2006-06-24 17:07:34 +1000733}
734
Eric Anholtc153f452007-09-03 12:06:45 +1000735int i915_vblank_pipe_get(struct drm_device *dev, void *data,
736 struct drm_file *file_priv)
Dave Airlie702880f2006-06-24 17:07:34 +1000737{
Dave Airlie702880f2006-06-24 17:07:34 +1000738 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +1000739 drm_i915_vblank_pipe_t *pipe = data;
Dave Airlie702880f2006-06-24 17:07:34 +1000740
741 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000742 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000743 return -EINVAL;
Dave Airlie702880f2006-06-24 17:07:34 +1000744 }
745
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700746 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
Eric Anholtc153f452007-09-03 12:06:45 +1000747
Dave Airlie702880f2006-06-24 17:07:34 +1000748 return 0;
749}
750
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000751/**
752 * Schedule buffer swap at given vertical blank.
753 */
Eric Anholtc153f452007-09-03 12:06:45 +1000754int i915_vblank_swap(struct drm_device *dev, void *data,
755 struct drm_file *file_priv)
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000756{
Eric Anholtbd95e0a2008-11-04 12:01:24 -0800757 /* The delayed swap mechanism was fundamentally racy, and has been
758 * removed. The model was that the client requested a delayed flip/swap
759 * from the kernel, then waited for vblank before continuing to perform
760 * rendering. The problem was that the kernel might wake the client
761 * up before it dispatched the vblank swap (since the lock has to be
762 * held while touching the ringbuffer), in which case the client would
763 * clear and start the next frame before the swap occurred, and
764 * flicker would occur in addition to likely missing the vblank.
765 *
766 * In the absence of this ioctl, userland falls back to a correct path
767 * of waiting for a vblank, then dispatching the swap on its own.
768 * Context switching to userland and back is plenty fast enough for
769 * meeting the requirements of vblank swapping.
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700770 */
Eric Anholtbd95e0a2008-11-04 12:01:24 -0800771 return -EINVAL;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000772}
773
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774/* drm_dma.h hooks
775*/
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800776static void igdng_irq_preinstall(struct drm_device *dev)
777{
778 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
779
780 I915_WRITE(HWSTAM, 0xeffe);
781
782 /* XXX hotplug from PCH */
783
784 I915_WRITE(DEIMR, 0xffffffff);
785 I915_WRITE(DEIER, 0x0);
786 (void) I915_READ(DEIER);
787
788 /* and GT */
789 I915_WRITE(GTIMR, 0xffffffff);
790 I915_WRITE(GTIER, 0x0);
791 (void) I915_READ(GTIER);
792}
793
794static int igdng_irq_postinstall(struct drm_device *dev)
795{
796 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
797 /* enable kind of interrupts always enabled */
798 u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */;
799 u32 render_mask = GT_USER_INTERRUPT;
800
801 dev_priv->irq_mask_reg = ~display_mask;
802 dev_priv->de_irq_enable_reg = display_mask;
803
804 /* should always can generate irq */
805 I915_WRITE(DEIIR, I915_READ(DEIIR));
806 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
807 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
808 (void) I915_READ(DEIER);
809
810 /* user interrupt should be enabled, but masked initial */
811 dev_priv->gt_irq_mask_reg = 0xffffffff;
812 dev_priv->gt_irq_enable_reg = render_mask;
813
814 I915_WRITE(GTIIR, I915_READ(GTIIR));
815 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
816 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
817 (void) I915_READ(GTIER);
818
819 return 0;
820}
821
Dave Airlie84b1fd12007-07-11 15:53:27 +1000822void i915_driver_irq_preinstall(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823{
824 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
825
Jesse Barnes79e53942008-11-07 14:24:08 -0800826 atomic_set(&dev_priv->irq_received, 0);
827
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800828 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
829
830 if (IS_IGDNG(dev)) {
831 igdng_irq_preinstall(dev);
832 return;
833 }
834
Jesse Barnes5ca58282009-03-31 14:11:15 -0700835 if (I915_HAS_HOTPLUG(dev)) {
836 I915_WRITE(PORT_HOTPLUG_EN, 0);
837 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
838 }
839
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700840 I915_WRITE(HWSTAM, 0xeffe);
Keith Packard7c463582008-11-04 02:03:27 -0800841 I915_WRITE(PIPEASTAT, 0);
842 I915_WRITE(PIPEBSTAT, 0);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700843 I915_WRITE(IMR, 0xffffffff);
Eric Anholted4cb412008-07-29 12:10:39 -0700844 I915_WRITE(IER, 0x0);
Keith Packard7c463582008-11-04 02:03:27 -0800845 (void) I915_READ(IER);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700846}
847
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700848int i915_driver_irq_postinstall(struct drm_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849{
850 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes5ca58282009-03-31 14:11:15 -0700851 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700852 u32 error_mask;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700853
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800854 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
855
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700856 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700857
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800858 if (IS_IGDNG(dev))
859 return igdng_irq_postinstall(dev);
860
Keith Packard7c463582008-11-04 02:03:27 -0800861 /* Unmask the interrupts that we always want on. */
862 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100863
Keith Packard7c463582008-11-04 02:03:27 -0800864 dev_priv->pipestat[0] = 0;
865 dev_priv->pipestat[1] = 0;
866
Jesse Barnes5ca58282009-03-31 14:11:15 -0700867 if (I915_HAS_HOTPLUG(dev)) {
868 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
869
870 /* Leave other bits alone */
871 hotplug_en |= HOTPLUG_EN_MASK;
872 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
873
874 dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
875 TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
876 SDVOB_HOTPLUG_INT_STATUS;
877 if (IS_G4X(dev)) {
878 dev_priv->hotplug_supported_mask |=
879 HDMIB_HOTPLUG_INT_STATUS |
880 HDMIC_HOTPLUG_INT_STATUS |
881 HDMID_HOTPLUG_INT_STATUS;
882 }
883 /* Enable in IER... */
884 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
885 /* and unmask in IMR */
886 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
887 }
888
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700889 /*
890 * Enable some error detection, note the instruction error mask
891 * bit is reserved, so we leave it masked.
892 */
893 if (IS_G4X(dev)) {
894 error_mask = ~(GM45_ERROR_PAGE_TABLE |
895 GM45_ERROR_MEM_PRIV |
896 GM45_ERROR_CP_PRIV |
897 I915_ERROR_MEMORY_REFRESH);
898 } else {
899 error_mask = ~(I915_ERROR_PAGE_TABLE |
900 I915_ERROR_MEMORY_REFRESH);
901 }
902 I915_WRITE(EMR, error_mask);
903
Keith Packard7c463582008-11-04 02:03:27 -0800904 /* Disable pipe interrupt enables, clear pending pipe status */
905 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
906 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
907 /* Clear pending interrupt status */
908 I915_WRITE(IIR, I915_READ(IIR));
909
Jesse Barnes5ca58282009-03-31 14:11:15 -0700910 I915_WRITE(IER, enable_mask);
Keith Packard7c463582008-11-04 02:03:27 -0800911 I915_WRITE(IMR, dev_priv->irq_mask_reg);
Eric Anholted4cb412008-07-29 12:10:39 -0700912 (void) I915_READ(IER);
913
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100914 opregion_enable_asle(dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700915
916 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700917}
918
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800919static void igdng_irq_uninstall(struct drm_device *dev)
920{
921 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
922 I915_WRITE(HWSTAM, 0xffffffff);
923
924 I915_WRITE(DEIMR, 0xffffffff);
925 I915_WRITE(DEIER, 0x0);
926 I915_WRITE(DEIIR, I915_READ(DEIIR));
927
928 I915_WRITE(GTIMR, 0xffffffff);
929 I915_WRITE(GTIER, 0x0);
930 I915_WRITE(GTIIR, I915_READ(GTIIR));
931}
932
Dave Airlie84b1fd12007-07-11 15:53:27 +1000933void i915_driver_irq_uninstall(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934{
935 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Dave Airlie91e37382006-02-18 15:17:04 +1100936
Linus Torvalds1da177e2005-04-16 15:20:36 -0700937 if (!dev_priv)
938 return;
939
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700940 dev_priv->vblank_pipe = 0;
941
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800942 if (IS_IGDNG(dev)) {
943 igdng_irq_uninstall(dev);
944 return;
945 }
946
Jesse Barnes5ca58282009-03-31 14:11:15 -0700947 if (I915_HAS_HOTPLUG(dev)) {
948 I915_WRITE(PORT_HOTPLUG_EN, 0);
949 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
950 }
951
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700952 I915_WRITE(HWSTAM, 0xffffffff);
Keith Packard7c463582008-11-04 02:03:27 -0800953 I915_WRITE(PIPEASTAT, 0);
954 I915_WRITE(PIPEBSTAT, 0);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700955 I915_WRITE(IMR, 0xffffffff);
Eric Anholted4cb412008-07-29 12:10:39 -0700956 I915_WRITE(IER, 0x0);
Dave Airlie91e37382006-02-18 15:17:04 +1100957
Keith Packard7c463582008-11-04 02:03:27 -0800958 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
959 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
960 I915_WRITE(IIR, I915_READ(IIR));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961}