arch/arm64/boot/dts/qcom/sdm845-sde.dtsi

/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&soc {
	mdss_mdp: qcom,mdss_mdp@ae00000 {
		compatible = "qcom,sde-kms";
		reg = <0x0ae00000 0x81d40>,
		      <0x0aeb0000 0x2008>,
		      <0x0aeac000 0xf0>;
		reg-names = "mdp_phys",
			"vbif_phys",
			"regdma_phys";

		clocks =
			<&clock_gcc GCC_DISP_AHB_CLK>,
			<&clock_gcc GCC_DISP_AXI_CLK>,
			<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
			<&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
			<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
			<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
		clock-names = "gcc_iface", "gcc_bus", "iface_clk",
				"bus_clk", "core_clk", "vsync_clk";
		clock-rate = <0 0 0 0 300000000 19200000 0>;
		clock-max-rate = <0 0 0 0 430000000 19200000 0>;

		sde-vdd-supply = <&mdss_core_gdsc>;

		/* interrupt config */
		interrupt-parent = <&pdc>;
		interrupts = <0 83 0>;
		interrupt-controller;
		#interrupt-cells = <1>;
		iommus = <&apps_smmu 0x880 0x8>,
			<&apps_smmu 0xc80 0x8>;

		#address-cells = <1>;
		#size-cells = <0>;

		/* hw blocks */
		qcom,sde-off = <0x1000>;
		qcom,sde-len = <0x45C>;

		qcom,sde-ctl-off = <0x2000 0x2200 0x2400
				     0x2600 0x2800>;
		qcom,sde-ctl-size = <0xE4>;

		qcom,sde-mixer-off = <0x45000 0x46000 0x47000
				      0x48000 0x49000 0x4a000>;
		qcom,sde-mixer-size = <0x320>;

		qcom,sde-dspp-top-off = <0x1300>;
		qcom,sde-dspp-top-size = <0xc>;

		qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
		qcom,sde-dspp-size = <0x17e0>;

		qcom,sde-wb-off = <0x66000>;
		qcom,sde-wb-size = <0x2c8>;

		qcom,sde-wb-xin-id = <6>;
		qcom,sde-wb-id = <2>;
		qcom,sde-intf-off = <0x6b000 0x6b800
					0x6c000 0x6c800>;
		qcom,sde-intf-size = <0x280>;

		qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
		qcom,sde-pp-off = <0x71000 0x71800
					  0x72000 0x72800 0x73000>;
		qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x1>;
		qcom,sde-pp-size = <0xd4>;

		qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0>;
		qcom,sde-cdm-off = <0x7a200>;
		qcom,sde-cdm-size = <0x224>;

		qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>;
		qcom,sde-dsc-size = <0x140>;

		qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0 0x0>;
		qcom,sde-dither-version = <0x00010000>;
		qcom,sde-dither-size = <0x20>;

		qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
					"dma", "dma", "dma", "dma";

		qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
					0x25000 0x27000 0x29000 0x2b000>;
		qcom,sde-sspp-src-size = <0x1c8>;

		qcom,sde-sspp-xin-id = <0 4 8 12
					1 5 9 13>;
		qcom,sde-sspp-excl-rect = <1 1 1 1
						1 1 1 1>;
		qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;
		qcom,sde-smart-dma-rev = "smart_dma_v2";

		qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>;

		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
						0xb0 0xc8 0xe0 0xf8 0x110>;

		/* offsets are relative to "mdp_phys + qcom,sde-off */
		qcom,sde-sspp-clk-ctrl =
				<0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
				 <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
		qcom,sde-sspp-csc-off = <0x1a00>;
		qcom,sde-csc-type = "csc-10bit";
		qcom,sde-qseed-type = "qseedv3";
		qcom,sde-sspp-qseed-off = <0xa00>;
		qcom,sde-mixer-linewidth = <2560>;
		qcom,sde-sspp-linewidth = <2560>;
		qcom,sde-wb-linewidth = <4096>;
		qcom,sde-mixer-blendstages = <0xb>;
		qcom,sde-highest-bank-bit = <0x2>;
		qcom,sde-ubwc-version = <0x200>;
		qcom,sde-panic-per-pipe;
		qcom,sde-has-cdp;
		qcom,sde-has-src-split;
		qcom,sde-has-dim-layer;
		qcom,sde-has-idle-pc;
		qcom,sde-max-bw-low-kbps = <9600000>;
		qcom,sde-max-bw-high-kbps = <9600000>;
		qcom,sde-dram-channels = <2>;
		qcom,sde-num-nrt-paths = <0>;
		qcom,sde-dspp-ad-version = <0x00040000>;
		qcom,sde-dspp-ad-off = <0x28000 0x27000>;

		qcom,sde-vbif-off = <0>;
		qcom,sde-vbif-size = <0x1040>;
		qcom,sde-vbif-id = <0>;
		qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
		qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;

		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
		qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;

		qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000
			0x00000000>;
		qcom,sde-safe-lut = <0xfffc 0xff00 0xffff 0xffff>;
		qcom,sde-qos-lut-linear =
			<4 0x00000000 0x00000357>,
			<5 0x00000000 0x00003357>,
			<6 0x00000000 0x00023357>,
			<7 0x00000000 0x00223357>,
			<8 0x00000000 0x02223357>,
			<9 0x00000000 0x22223357>,
			<10 0x00000002 0x22223357>,
			<11 0x00000022 0x22223357>,
			<12 0x00000222 0x22223357>,
			<13 0x00002222 0x22223357>,
			<14 0x00012222 0x22223357>,
			<0 0x00112222 0x22223357>;
		qcom,sde-qos-lut-macrotile =
			<10 0x00000003 0x44556677>,
			<11 0x00000033 0x44556677>,
			<12 0x00000233 0x44556677>,
			<13 0x00002233 0x44556677>,
			<14 0x00012233 0x44556677>,
			<0 0x00112233 0x44556677>;
		qcom,sde-qos-lut-nrt =
			<0 0x00000000 0x00000000>;
		qcom,sde-qos-lut-cwb =
			<0 0x75300000 0x00000000>;

		qcom,sde-cdp-setting = <1 1>, <1 0>;

		qcom,sde-inline-rotator = <&mdss_rotator 0>;
		qcom,sde-inline-rot-xin = <10 11>;
		qcom,sde-inline-rot-xin-type = "sspp", "wb";

		/* offsets are relative to "mdp_phys + qcom,sde-off */
		qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>;

		qcom,sde-reg-dma-off = <0>;
		qcom,sde-reg-dma-version = <0x1>;
		qcom,sde-reg-dma-trigger-off = <0x119c>;

		qcom,sde-sspp-vig-blocks {
			qcom,sde-vig-csc-off = <0x1a00>;
			qcom,sde-vig-qseed-off = <0xa00>;
			qcom,sde-vig-qseed-size = <0xa0>;
		};

		qcom,sde-dspp-blocks {
			qcom,sde-dspp-igc = <0x0 0x00030001>;
			qcom,sde-dspp-vlut = <0xa00 0x00010008>;
			qcom,sde-dspp-gamut = <0x1000 0x00040000>;
			qcom,sde-dspp-pcc = <0x1700 0x00040000>;
			qcom,sde-dspp-gc = <0x17c0 0x00010008>;
		};

		qcom,platform-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,platform-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "sde-vdd";
				qcom,supply-min-voltage = <0>;
				qcom,supply-max-voltage = <0>;
				qcom,supply-enable-load = <0>;
				qcom,supply-disable-load = <0>;
			};
		};

		smmu_sde_sec: qcom,smmu_sde_sec_cb {
			compatible = "qcom,smmu_sde_sec";
			iommus = <&apps_smmu 0x881 0x8>,
			       <&apps_smmu 0xc81 0x8>;
		};

		/* data and reg bus scale settings */
		qcom,sde-data-bus {
			qcom,msm-bus,name = "mdss_sde_mnoc";
			qcom,msm-bus,num-cases = <3>;
			qcom,msm-bus,num-paths = <2>;
			qcom,msm-bus,vectors-KBps =
			    <22 773 0 0>, <23 773 0 0>,
			    <22 773 0 6400000>, <23 773 0 6400000>,
			    <22 773 0 6400000>, <23 773 0 6400000>;
		};

		qcom,sde-llcc-bus {
			qcom,msm-bus,name = "mdss_sde_llcc";
			qcom,msm-bus,num-cases = <3>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
			    <132 770 0 0>,
			    <132 770 0 6400000>,
			    <132 770 0 6400000>;
		};

		qcom,sde-ebi-bus {
			qcom,msm-bus,name = "mdss_sde_ebi";
			qcom,msm-bus,num-cases = <3>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
			    <129 512 0 0>,
			    <129 512 0 6400000>,
			    <129 512 0 6400000>;
		};

		qcom,sde-reg-bus {
			qcom,msm-bus,name = "mdss_reg";
			qcom,msm-bus,num-cases = <4>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,active-only;
			qcom,msm-bus,vectors-KBps =
				<1 590 0 0>,
				<1 590 0 76800>,
				<1 590 0 150000>,
				<1 590 0 300000>;
		};
	};

	sde_rscc: qcom,sde_rscc@af20000 {
		cell-index = <0>;
		compatible = "qcom,sde-rsc";
		reg = <0xaf20000 0x1c44>,
			<0xaf30000 0x3fd4>;
		reg-names = "drv", "wrapper";
		qcom,sde-rsc-version = <1>;

		vdd-supply = <&mdss_core_gdsc>;
		clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
			<&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
		clock-names = "vsync_clk", "iface_clk";
		clock-rate = <0 0>;

		qcom,sde-dram-channels = <2>;

		mboxes = <&disp_rsc 0>;
		mbox-names = "disp_rsc";

		/* data and reg bus scale settings */
		qcom,sde-data-bus {
			qcom,msm-bus,name = "disp_rsc_mnoc";
			qcom,msm-bus,active-only;
			qcom,msm-bus,num-cases = <3>;
			qcom,msm-bus,num-paths = <2>;
			qcom,msm-bus,vectors-KBps =
			    <20003 20515 0 0>, <20004 20515 0 0>,
			    <20003 20515 0 6400000>, <20004 20515 0 6400000>,
			    <20003 20515 0 6400000>, <20004 20515 0 6400000>;
		};

		qcom,sde-llcc-bus {
			qcom,msm-bus,name = "disp_rsc_llcc";
			qcom,msm-bus,active-only;
			qcom,msm-bus,num-cases = <3>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
			    <20001 20513 0 0>,
			    <20001 20513 0 6400000>,
			    <20001 20513 0 6400000>;
		};

		qcom,sde-ebi-bus {
			qcom,msm-bus,name = "disp_rsc_ebi";
			qcom,msm-bus,active-only;
			qcom,msm-bus,num-cases = <3>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
			    <20000 20512 0 0>,
			    <20000 20512 0 6400000>,
			    <20000 20512 0 6400000>;
		};
	};

	mdss_rotator: qcom,mdss_rotator@ae00000 {
		compatible = "qcom,sde_rotator";
		reg = <0x0ae00000 0xac000>,
		      <0x0aeb8000 0x3000>;
		reg-names = "mdp_phys",
			"rot_vbif_phys";

		#list-cells = <1>;

		qcom,mdss-rot-mode = <1>;
		qcom,mdss-highest-bank-bit = <0x2>;

		/* Bus Scale Settings */
		qcom,msm-bus,name = "mdss_rotator";
		qcom,msm-bus,num-cases = <3>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<25 512 0 0>,
			<25 512 0 6400000>,
			<25 512 0 6400000>;

		rot-vdd-supply = <&mdss_core_gdsc>;
		qcom,supply-names = "rot-vdd";

		clocks =
			<&clock_gcc GCC_DISP_AHB_CLK>,
			<&clock_gcc GCC_DISP_AXI_CLK>,
			<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
			<&clock_dispcc DISP_CC_MDSS_ROT_CLK>,
			<&clock_dispcc DISP_CC_MDSS_AXI_CLK>;
		clock-names = "gcc_iface", "gcc_bus",
			"iface_clk", "rot_clk", "axi_clk";

		interrupt-parent = <&mdss_mdp>;
		interrupts = <2 0>;

		/* Offline rotator QoS setting */
		qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
		qcom,mdss-rot-vbif-memtype = <3 3>;
		qcom,mdss-rot-cdp-setting = <1 1>;
		qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
		qcom,mdss-rot-danger-lut = <0x0 0x0>;
		qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;

		/* Inline rotator QoS Setting */
		/* setting default register values for RD - qos/danger/safe */
		qcom,mdss-inline-rot-qos-lut = <0x44556677 0x00112233
							0x44556677 0x00112233>;
		qcom,mdss-inline-rot-danger-lut = <0x0055aaff 0x0000ffff>;
		qcom,mdss-inline-rot-safe-lut = <0x0000f000 0x0000ff00>;

		qcom,mdss-default-ot-rd-limit = <32>;
		qcom,mdss-default-ot-wr-limit = <32>;

		qcom,mdss-sbuf-headroom = <20>;

		cache-slice-names = "rotator";
		cache-slices = <&llcc 4>;

		/* reg bus scale settings */
		rot_reg: qcom,rot-reg-bus {
			qcom,msm-bus,name = "mdss_rot_reg";
			qcom,msm-bus,num-cases = <2>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,active-only;
			qcom,msm-bus,vectors-KBps =
				<1 590 0 0>,
				<1 590 0 76800>;
		};

		smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
			compatible = "qcom,smmu_sde_rot_unsec";
			iommus = <&apps_smmu 0x1090 0x0>;
		};

		smmu_rot_sec: qcom,smmu_rot_sec_cb {
			compatible = "qcom,smmu_sde_rot_sec";
			iommus = <&apps_smmu 0x1091 0x0>;
		};
	};

	mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
		compatible = "qcom,dsi-ctrl-hw-v2.2";
		label = "dsi-ctrl-0";
		cell-index = <0>;
		reg =   <0xae94000 0x400>,
			<0xaf08000 0x4>;
		reg-names = "dsi_ctrl", "disp_cc_base";
		interrupt-parent = <&mdss_mdp>;
		interrupts = <4 0>;
		vdda-1p2-supply = <&pm8998_l26>;
		clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
		<&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
		<&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
		<&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>,
		<&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
		<&clock_dispcc DISP_CC_MDSS_ESC0_CLK>;
		clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
					"pixel_clk", "pixel_clk_rcg",
					"esc_clk";

		qcom,ctrl-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,ctrl-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdda-1p2";
				qcom,supply-min-voltage = <1200000>;
				qcom,supply-max-voltage = <1200000>;
				qcom,supply-enable-load = <21800>;
				qcom,supply-disable-load = <4>;
			};
		};
	};

	mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
		compatible = "qcom,dsi-ctrl-hw-v2.2";
		label = "dsi-ctrl-1";
		cell-index = <1>;
		reg =   <0xae96000 0x400>,
			<0xaf08000 0x4>;
		reg-names = "dsi_ctrl", "disp_cc_base";
		interrupt-parent = <&mdss_mdp>;
		interrupts = <5 0>;
		vdda-1p2-supply = <&pm8998_l26>;
		clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,
		<&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
		<&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
		<&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>,
		<&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
		<&clock_dispcc DISP_CC_MDSS_ESC1_CLK>;
		clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
				"pixel_clk", "pixel_clk_rcg", "esc_clk";
		qcom,ctrl-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,ctrl-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdda-1p2";
				qcom,supply-min-voltage = <1200000>;
				qcom,supply-max-voltage = <1200000>;
				qcom,supply-enable-load = <21800>;
				qcom,supply-disable-load = <4>;
			};
		};
	};

	mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 {
		compatible = "qcom,dsi-phy-v3.0";
		label = "dsi-phy-0";
		cell-index = <0>;
		reg = <0xae94400 0x7c0>;
		reg-names = "dsi_phy";
		gdsc-supply = <&mdss_core_gdsc>;
		vdda-0p9-supply = <&pm8998_l1>;
		qcom,platform-strength-ctrl = [55 03
						55 03
						55 03
						55 03
						55 00];
		qcom,platform-lane-config = [00 00 00 00
						00 00 00 00
						00 00 00 00
						00 00 00 00
						00 00 00 80];
		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
		qcom,phy-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;
			qcom,phy-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdda-0p9";
				qcom,supply-min-voltage = <880000>;
				qcom,supply-max-voltage = <880000>;
				qcom,supply-enable-load = <36000>;
				qcom,supply-disable-load = <32>;
			};
		};
	};

	mdss_dsi_phy1: qcom,mdss_dsi_phy0@ae96400 {
		compatible = "qcom,dsi-phy-v3.0";
		label = "dsi-phy-1";
		cell-index = <1>;
		reg = <0xae96400 0x7c0>;
		reg-names = "dsi_phy";
		gdsc-supply = <&mdss_core_gdsc>;
		vdda-0p9-supply = <&pm8998_l1>;
		qcom,platform-strength-ctrl = [55 03
						55 03
						55 03
						55 03
						55 00];
		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
		qcom,platform-lane-config = [00 00 00 00
						00 00 00 00
						00 00 00 00
						00 00 00 00
						00 00 00 80];
		qcom,phy-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;
			qcom,phy-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdda-0p9";
				qcom,supply-min-voltage = <880000>;
				qcom,supply-max-voltage = <880000>;
				qcom,supply-enable-load = <36000>;
				qcom,supply-disable-load = <32>;
			};
		};
	};

};