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Rodolfo Giomettib92a78e2008-10-23 10:08:07 +02001/*
2 * Host interface registers
3 */
4
5#define OXU_DEVICEID 0x00
6 #define OXU_REV_MASK 0xffff0000
7 #define OXU_REV_SHIFT 16
8 #define OXU_REV_2100 0x2100
9 #define OXU_BO_SHIFT 8
10 #define OXU_BO_MASK (0x3 << OXU_BO_SHIFT)
11 #define OXU_MAJ_REV_SHIFT 4
12 #define OXU_MAJ_REV_MASK (0xf << OXU_MAJ_REV_SHIFT)
13 #define OXU_MIN_REV_SHIFT 0
14 #define OXU_MIN_REV_MASK (0xf << OXU_MIN_REV_SHIFT)
15#define OXU_HOSTIFCONFIG 0x04
16#define OXU_SOFTRESET 0x08
17 #define OXU_SRESET (1 << 0)
18
19#define OXU_PIOBURSTREADCTRL 0x0C
20
21#define OXU_CHIPIRQSTATUS 0x10
22#define OXU_CHIPIRQEN_SET 0x14
23#define OXU_CHIPIRQEN_CLR 0x18
24 #define OXU_USBSPHLPWUI 0x00000080
25 #define OXU_USBOTGLPWUI 0x00000040
26 #define OXU_USBSPHI 0x00000002
27 #define OXU_USBOTGI 0x00000001
28
29#define OXU_CLKCTRL_SET 0x1C
30 #define OXU_SYSCLKEN 0x00000008
31 #define OXU_USBSPHCLKEN 0x00000002
32 #define OXU_USBOTGCLKEN 0x00000001
33
34#define OXU_ASO 0x68
35 #define OXU_SPHPOEN 0x00000100
36 #define OXU_OVRCCURPUPDEN 0x00000800
37 #define OXU_ASO_OP (1 << 10)
38 #define OXU_COMPARATOR 0x000004000
39
40#define OXU_USBMODE 0x1A8
41 #define OXU_VBPS 0x00000020
42 #define OXU_ES_LITTLE 0x00000000
43 #define OXU_CM_HOST_ONLY 0x00000003
44
45/*
46 * Proper EHCI structs & defines
47 */
48
49/* Magic numbers that can affect system performance */
50#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
51#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
52#define EHCI_TUNE_RL_TT 0
53#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
54#define EHCI_TUNE_MULT_TT 1
55#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
56
57struct oxu_hcd;
58
59/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
60
61/* Section 2.2 Host Controller Capability Registers */
62struct ehci_caps {
63 /* these fields are specified as 8 and 16 bit registers,
64 * but some hosts can't perform 8 or 16 bit PCI accesses.
65 */
66 u32 hc_capbase;
67#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
68#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
69 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
70#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
71#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
72#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
73#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
74#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
75#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
76#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
77
78 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
79#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
80#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
81#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
82#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
83#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
84#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
85 u8 portroute[8]; /* nibbles for routing - offset 0xC */
86} __attribute__ ((packed));
87
88
89/* Section 2.3 Host Controller Operational Registers */
90struct ehci_regs {
91 /* USBCMD: offset 0x00 */
92 u32 command;
93/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
94#define CMD_PARK (1<<11) /* enable "park" on async qh */
95#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
96#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
97#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
98#define CMD_ASE (1<<5) /* async schedule enable */
99#define CMD_PSE (1<<4) /* periodic schedule enable */
100/* 3:2 is periodic frame list size */
101#define CMD_RESET (1<<1) /* reset HC not bus */
102#define CMD_RUN (1<<0) /* start/stop HC */
103
104 /* USBSTS: offset 0x04 */
105 u32 status;
106#define STS_ASS (1<<15) /* Async Schedule Status */
107#define STS_PSS (1<<14) /* Periodic Schedule Status */
108#define STS_RECL (1<<13) /* Reclamation */
109#define STS_HALT (1<<12) /* Not running (any reason) */
110/* some bits reserved */
111 /* these STS_* flags are also intr_enable bits (USBINTR) */
112#define STS_IAA (1<<5) /* Interrupted on async advance */
113#define STS_FATAL (1<<4) /* such as some PCI access errors */
114#define STS_FLR (1<<3) /* frame list rolled over */
115#define STS_PCD (1<<2) /* port change detect */
116#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
117#define STS_INT (1<<0) /* "normal" completion (short, ...) */
118
119#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
120
121 /* USBINTR: offset 0x08 */
122 u32 intr_enable;
123
124 /* FRINDEX: offset 0x0C */
125 u32 frame_index; /* current microframe number */
126 /* CTRLDSSEGMENT: offset 0x10 */
127 u32 segment; /* address bits 63:32 if needed */
128 /* PERIODICLISTBASE: offset 0x14 */
129 u32 frame_list; /* points to periodic list */
130 /* ASYNCLISTADDR: offset 0x18 */
131 u32 async_next; /* address of next async queue head */
132
133 u32 reserved[9];
134
135 /* CONFIGFLAG: offset 0x40 */
136 u32 configured_flag;
137#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
138
139 /* PORTSC: offset 0x44 */
140 u32 port_status[0]; /* up to N_PORTS */
141/* 31:23 reserved */
142#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
143#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
144#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
145/* 19:16 for port testing */
146#define PORT_LED_OFF (0<<14)
147#define PORT_LED_AMBER (1<<14)
148#define PORT_LED_GREEN (2<<14)
149#define PORT_LED_MASK (3<<14)
150#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
151#define PORT_POWER (1<<12) /* true: has power (see PPC) */
152#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
153/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
154/* 9 reserved */
155#define PORT_RESET (1<<8) /* reset port */
156#define PORT_SUSPEND (1<<7) /* suspend port */
157#define PORT_RESUME (1<<6) /* resume it */
158#define PORT_OCC (1<<5) /* over current change */
159#define PORT_OC (1<<4) /* over current active */
160#define PORT_PEC (1<<3) /* port enable change */
161#define PORT_PE (1<<2) /* port enable */
162#define PORT_CSC (1<<1) /* connect status change */
163#define PORT_CONNECT (1<<0) /* device connected */
164#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
165} __attribute__ ((packed));
166
167/* Appendix C, Debug port ... intended for use with special "debug devices"
168 * that can help if there's no serial console. (nonstandard enumeration.)
169 */
170struct ehci_dbg_port {
171 u32 control;
172#define DBGP_OWNER (1<<30)
173#define DBGP_ENABLED (1<<28)
174#define DBGP_DONE (1<<16)
175#define DBGP_INUSE (1<<10)
176#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
177# define DBGP_ERR_BAD 1
178# define DBGP_ERR_SIGNAL 2
179#define DBGP_ERROR (1<<6)
180#define DBGP_GO (1<<5)
181#define DBGP_OUT (1<<4)
182#define DBGP_LEN(x) (((x)>>0)&0x0f)
183 u32 pids;
184#define DBGP_PID_GET(x) (((x)>>16)&0xff)
185#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
186 u32 data03;
187 u32 data47;
188 u32 address;
189#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
190} __attribute__ ((packed));
191
192
193#define QTD_NEXT(dma) cpu_to_le32((u32)dma)
194
195/*
196 * EHCI Specification 0.95 Section 3.5
197 * QTD: describe data transfer components (buffer, direction, ...)
198 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
199 *
200 * These are associated only with "QH" (Queue Head) structures,
201 * used with control, bulk, and interrupt transfers.
202 */
203struct ehci_qtd {
204 /* first part defined by EHCI spec */
205 __le32 hw_next; /* see EHCI 3.5.1 */
206 __le32 hw_alt_next; /* see EHCI 3.5.2 */
207 __le32 hw_token; /* see EHCI 3.5.3 */
208#define QTD_TOGGLE (1 << 31) /* data toggle */
209#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
210#define QTD_IOC (1 << 15) /* interrupt on complete */
211#define QTD_CERR(tok) (((tok)>>10) & 0x3)
212#define QTD_PID(tok) (((tok)>>8) & 0x3)
213#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
214#define QTD_STS_HALT (1 << 6) /* halted on error */
215#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
216#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
217#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
218#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
219#define QTD_STS_STS (1 << 1) /* split transaction state */
220#define QTD_STS_PING (1 << 0) /* issue PING? */
221 __le32 hw_buf[5]; /* see EHCI 3.5.4 */
222 __le32 hw_buf_hi[5]; /* Appendix B */
223
224 /* the rest is HCD-private */
225 dma_addr_t qtd_dma; /* qtd address */
226 struct list_head qtd_list; /* sw qtd list */
227 struct urb *urb; /* qtd's urb */
228 size_t length; /* length of buffer */
229
230 u32 qtd_buffer_len;
231 void *buffer;
232 dma_addr_t buffer_dma;
233 void *transfer_buffer;
234 void *transfer_dma;
235} __attribute__ ((aligned(32)));
236
237/* mask NakCnt+T in qh->hw_alt_next */
Harvey Harrison551509d2009-02-11 14:11:36 -0800238#define QTD_MASK cpu_to_le32 (~0x1f)
Rodolfo Giomettib92a78e2008-10-23 10:08:07 +0200239
240#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
241
242/* Type tag from {qh, itd, sitd, fstn}->hw_next */
Harvey Harrison551509d2009-02-11 14:11:36 -0800243#define Q_NEXT_TYPE(dma) ((dma) & cpu_to_le32 (3 << 1))
Rodolfo Giomettib92a78e2008-10-23 10:08:07 +0200244
245/* values for that type tag */
Harvey Harrison551509d2009-02-11 14:11:36 -0800246#define Q_TYPE_QH cpu_to_le32 (1 << 1)
Rodolfo Giomettib92a78e2008-10-23 10:08:07 +0200247
248/* next async queue entry, or pointer to interrupt/periodic QH */
249#define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
250
251/* for periodic/async schedules and qtd lists, mark end of list */
Harvey Harrison551509d2009-02-11 14:11:36 -0800252#define EHCI_LIST_END cpu_to_le32(1) /* "null pointer" to hw */
Rodolfo Giomettib92a78e2008-10-23 10:08:07 +0200253
254/*
255 * Entries in periodic shadow table are pointers to one of four kinds
256 * of data structure. That's dictated by the hardware; a type tag is
257 * encoded in the low bits of the hardware's periodic schedule. Use
258 * Q_NEXT_TYPE to get the tag.
259 *
260 * For entries in the async schedule, the type tag always says "qh".
261 */
262union ehci_shadow {
263 struct ehci_qh *qh; /* Q_TYPE_QH */
264 __le32 *hw_next; /* (all types) */
265 void *ptr;
266};
267
268/*
269 * EHCI Specification 0.95 Section 3.6
270 * QH: describes control/bulk/interrupt endpoints
271 * See Fig 3-7 "Queue Head Structure Layout".
272 *
273 * These appear in both the async and (for interrupt) periodic schedules.
274 */
275
276struct ehci_qh {
277 /* first part defined by EHCI spec */
278 __le32 hw_next; /* see EHCI 3.6.1 */
279 __le32 hw_info1; /* see EHCI 3.6.2 */
280#define QH_HEAD 0x00008000
281 __le32 hw_info2; /* see EHCI 3.6.2 */
282#define QH_SMASK 0x000000ff
283#define QH_CMASK 0x0000ff00
284#define QH_HUBADDR 0x007f0000
285#define QH_HUBPORT 0x3f800000
286#define QH_MULT 0xc0000000
287 __le32 hw_current; /* qtd list - see EHCI 3.6.4 */
288
289 /* qtd overlay (hardware parts of a struct ehci_qtd) */
290 __le32 hw_qtd_next;
291 __le32 hw_alt_next;
292 __le32 hw_token;
293 __le32 hw_buf[5];
294 __le32 hw_buf_hi[5];
295
296 /* the rest is HCD-private */
297 dma_addr_t qh_dma; /* address of qh */
298 union ehci_shadow qh_next; /* ptr to qh; or periodic */
299 struct list_head qtd_list; /* sw qtd list */
300 struct ehci_qtd *dummy;
301 struct ehci_qh *reclaim; /* next to reclaim */
302
303 struct oxu_hcd *oxu;
304 struct kref kref;
305 unsigned stamp;
306
307 u8 qh_state;
308#define QH_STATE_LINKED 1 /* HC sees this */
309#define QH_STATE_UNLINK 2 /* HC may still see this */
310#define QH_STATE_IDLE 3 /* HC doesn't see this */
311#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
312#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
313
314 /* periodic schedule info */
315 u8 usecs; /* intr bandwidth */
316 u8 gap_uf; /* uframes split/csplit gap */
317 u8 c_usecs; /* ... split completion bw */
318 u16 tt_usecs; /* tt downstream bandwidth */
319 unsigned short period; /* polling interval */
320 unsigned short start; /* where polling starts */
321#define NO_FRAME ((unsigned short)~0) /* pick new start */
322 struct usb_device *dev; /* access to TT */
323} __attribute__ ((aligned(32)));
324
325/*
326 * Proper OXU210HP structs
327 */
328
329#define OXU_OTG_CORE_OFFSET 0x00400
330#define OXU_OTG_CAP_OFFSET (OXU_OTG_CORE_OFFSET + 0x100)
331#define OXU_SPH_CORE_OFFSET 0x00800
332#define OXU_SPH_CAP_OFFSET (OXU_SPH_CORE_OFFSET + 0x100)
333
334#define OXU_OTG_MEM 0xE000
335#define OXU_SPH_MEM 0x16000
336
337/* Only how many elements & element structure are specifies here. */
338/* 2 host controllers are enabled - total size <= 28 kbytes */
339#define DEFAULT_I_TDPS 1024
340#define QHEAD_NUM 16
341#define QTD_NUM 32
342#define SITD_NUM 8
343#define MURB_NUM 8
344
345#define BUFFER_NUM 8
346#define BUFFER_SIZE 512
347
348struct oxu_info {
349 struct usb_hcd *hcd[2];
350};
351
352struct oxu_buf {
353 u8 buffer[BUFFER_SIZE];
354} __attribute__ ((aligned(BUFFER_SIZE)));
355
356struct oxu_onchip_mem {
357 struct oxu_buf db_pool[BUFFER_NUM];
358
359 u32 frame_list[DEFAULT_I_TDPS];
360 struct ehci_qh qh_pool[QHEAD_NUM];
361 struct ehci_qtd qtd_pool[QTD_NUM];
362} __attribute__ ((aligned(4 << 10)));
363
364#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
365
366struct oxu_murb {
367 struct urb urb;
368 struct urb *main;
369 u8 last;
370};
371
372struct oxu_hcd { /* one per controller */
373 unsigned int is_otg:1;
374
375 u8 qh_used[QHEAD_NUM];
376 u8 qtd_used[QTD_NUM];
377 u8 db_used[BUFFER_NUM];
378 u8 murb_used[MURB_NUM];
379
380 struct oxu_onchip_mem __iomem *mem;
381 spinlock_t mem_lock;
382
383 struct timer_list urb_timer;
384
385 struct ehci_caps __iomem *caps;
386 struct ehci_regs __iomem *regs;
387
388 __u32 hcs_params; /* cached register copy */
389 spinlock_t lock;
390
391 /* async schedule support */
392 struct ehci_qh *async;
393 struct ehci_qh *reclaim;
394 unsigned reclaim_ready:1;
395 unsigned scanning:1;
396
397 /* periodic schedule support */
398 unsigned periodic_size;
399 __le32 *periodic; /* hw periodic table */
400 dma_addr_t periodic_dma;
401 unsigned i_thresh; /* uframes HC might cache */
402
403 union ehci_shadow *pshadow; /* mirror hw periodic table */
404 int next_uframe; /* scan periodic, start here */
405 unsigned periodic_sched; /* periodic activity count */
406
407 /* per root hub port */
408 unsigned long reset_done[EHCI_MAX_ROOT_PORTS];
409 /* bit vectors (one bit per port) */
410 unsigned long bus_suspended; /* which ports were
411 * already suspended at the
412 * start of a bus suspend
413 */
414 unsigned long companion_ports;/* which ports are dedicated
415 * to the companion controller
416 */
417
418 struct timer_list watchdog;
419 unsigned long actions;
420 unsigned stamp;
421 unsigned long next_statechange;
422 u32 command;
423
424 /* SILICON QUIRKS */
425 struct list_head urb_list; /* this is the head to urb
426 * queue that didn't get enough
427 * resources
428 */
429 struct oxu_murb *murb_pool; /* murb per split big urb */
430 unsigned urb_len;
431
432 u8 sbrn; /* packed release number */
433};
434
435#define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
436#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
437#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
438#define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
439
440enum ehci_timer_action {
441 TIMER_IO_WATCHDOG,
442 TIMER_IAA_WATCHDOG,
443 TIMER_ASYNC_SHRINK,
444 TIMER_ASYNC_OFF,
445};
446
447#include <linux/oxu210hp.h>