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David Brownella30d46c2008-10-20 23:46:28 +02001/*
2 * twl4030-irq.c - TWL4030/TPS659x0 irq support
3 *
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
5 *
6 * Modifications to defer interrupt handling to a kernel thread:
7 * Copyright (C) 2006 MontaVista Software, Inc.
8 *
9 * Based on tlv320aic23.c:
10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
11 *
12 * Code cleanup and modifications to IRQ handler.
13 * by syed khasim <x0khasim@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 */
29
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/irq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090033#include <linux/slab.h>
David Brownella30d46c2008-10-20 23:46:28 +020034
Santosh Shilimkarb07682b2009-12-13 20:05:51 +010035#include <linux/i2c/twl.h>
David Brownella30d46c2008-10-20 23:46:28 +020036
G, Manjunath Kondaiahb0b4a7c2010-10-19 11:02:48 +020037#include "twl-core.h"
David Brownella30d46c2008-10-20 23:46:28 +020038
39/*
40 * TWL4030 IRQ handling has two stages in hardware, and thus in software.
41 * The Primary Interrupt Handler (PIH) stage exposes status bits saying
42 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
43 * SIH modules are more traditional IRQ components, which support per-IRQ
44 * enable/disable and trigger controls; they do most of the work.
45 *
46 * These chips are designed to support IRQ handling from two different
47 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
48 * and mask registers in the PIH and SIH modules.
49 *
50 * We set up IRQs starting at a platform-specified base, always starting
51 * with PIH and the SIH for PWR_INT and then usually adding GPIO:
52 * base + 0 .. base + 7 PIH
53 * base + 8 .. base + 15 SIH for PWR_INT
54 * base + 16 .. base + 33 SIH for GPIO
55 */
56
57/* PIH register offsets */
58#define REG_PIH_ISR_P1 0x01
59#define REG_PIH_ISR_P2 0x02
60#define REG_PIH_SIR 0x03 /* for testing */
61
62
63/* Linux could (eventually) use either IRQ line */
64static int irq_line;
65
66struct sih {
67 char name[8];
68 u8 module; /* module id */
69 u8 control_offset; /* for SIH_CTRL */
70 bool set_cor;
71
72 u8 bits; /* valid in isr/imr */
73 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
74
75 u8 edr_offset;
76 u8 bytes_edr; /* bytelen of EDR */
77
Ilkka Koskinen1920a612009-11-10 17:26:15 +020078 u8 irq_lines; /* number of supported irq lines */
79
David Brownella30d46c2008-10-20 23:46:28 +020080 /* SIR ignored -- set interrupt, for testing only */
Thomas Gleixner35a27e82010-10-01 16:35:59 +020081 struct sih_irq_data {
David Brownella30d46c2008-10-20 23:46:28 +020082 u8 isr_offset;
83 u8 imr_offset;
84 } mask[2];
85 /* + 2 bytes padding */
86};
87
Ilkka Koskinen1920a612009-11-10 17:26:15 +020088static const struct sih *sih_modules;
89static int nr_sih_modules;
90
David Brownella30d46c2008-10-20 23:46:28 +020091#define SIH_INITIALIZER(modname, nbits) \
92 .module = TWL4030_MODULE_ ## modname, \
93 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
94 .bits = nbits, \
95 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \
96 .edr_offset = TWL4030_ ## modname ## _EDR, \
97 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
Ilkka Koskinen1920a612009-11-10 17:26:15 +020098 .irq_lines = 2, \
David Brownella30d46c2008-10-20 23:46:28 +020099 .mask = { { \
100 .isr_offset = TWL4030_ ## modname ## _ISR1, \
101 .imr_offset = TWL4030_ ## modname ## _IMR1, \
102 }, \
103 { \
104 .isr_offset = TWL4030_ ## modname ## _ISR2, \
105 .imr_offset = TWL4030_ ## modname ## _IMR2, \
106 }, },
107
108/* register naming policies are inconsistent ... */
109#define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
110#define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
111#define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
112
113
114/* Order in this table matches order in PIH_ISR. That is,
115 * BIT(n) in PIH_ISR is sih_modules[n].
116 */
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200117/* sih_modules_twl4030 is used both in twl4030 and twl5030 */
118static const struct sih sih_modules_twl4030[6] = {
David Brownella30d46c2008-10-20 23:46:28 +0200119 [0] = {
120 .name = "gpio",
121 .module = TWL4030_MODULE_GPIO,
122 .control_offset = REG_GPIO_SIH_CTRL,
123 .set_cor = true,
124 .bits = TWL4030_GPIO_MAX,
125 .bytes_ixr = 3,
126 /* Note: *all* of these IRQs default to no-trigger */
127 .edr_offset = REG_GPIO_EDR1,
128 .bytes_edr = 5,
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200129 .irq_lines = 2,
David Brownella30d46c2008-10-20 23:46:28 +0200130 .mask = { {
131 .isr_offset = REG_GPIO_ISR1A,
132 .imr_offset = REG_GPIO_IMR1A,
133 }, {
134 .isr_offset = REG_GPIO_ISR1B,
135 .imr_offset = REG_GPIO_IMR1B,
136 }, },
137 },
138 [1] = {
139 .name = "keypad",
140 .set_cor = true,
141 SIH_INITIALIZER(KEYPAD_KEYP, 4)
142 },
143 [2] = {
144 .name = "bci",
145 .module = TWL4030_MODULE_INTERRUPTS,
146 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
Grazvydas Ignotas8e52e272010-09-28 16:22:19 +0300147 .set_cor = true,
David Brownella30d46c2008-10-20 23:46:28 +0200148 .bits = 12,
149 .bytes_ixr = 2,
150 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
151 /* Note: most of these IRQs default to no-trigger */
152 .bytes_edr = 3,
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200153 .irq_lines = 2,
David Brownella30d46c2008-10-20 23:46:28 +0200154 .mask = { {
155 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
156 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
157 }, {
158 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
159 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
160 }, },
161 },
162 [3] = {
163 .name = "madc",
164 SIH_INITIALIZER(MADC, 4)
165 },
166 [4] = {
167 /* USB doesn't use the same SIH organization */
168 .name = "usb",
169 },
170 [5] = {
171 .name = "power",
172 .set_cor = true,
173 SIH_INITIALIZER(INT_PWR, 8)
174 },
175 /* there are no SIH modules #6 or #7 ... */
176};
177
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200178static const struct sih sih_modules_twl5031[8] = {
179 [0] = {
180 .name = "gpio",
181 .module = TWL4030_MODULE_GPIO,
182 .control_offset = REG_GPIO_SIH_CTRL,
183 .set_cor = true,
184 .bits = TWL4030_GPIO_MAX,
185 .bytes_ixr = 3,
186 /* Note: *all* of these IRQs default to no-trigger */
187 .edr_offset = REG_GPIO_EDR1,
188 .bytes_edr = 5,
189 .irq_lines = 2,
190 .mask = { {
191 .isr_offset = REG_GPIO_ISR1A,
192 .imr_offset = REG_GPIO_IMR1A,
193 }, {
194 .isr_offset = REG_GPIO_ISR1B,
195 .imr_offset = REG_GPIO_IMR1B,
196 }, },
197 },
198 [1] = {
199 .name = "keypad",
200 .set_cor = true,
201 SIH_INITIALIZER(KEYPAD_KEYP, 4)
202 },
203 [2] = {
204 .name = "bci",
205 .module = TWL5031_MODULE_INTERRUPTS,
206 .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL,
207 .bits = 7,
208 .bytes_ixr = 1,
209 .edr_offset = TWL5031_INTERRUPTS_BCIEDR1,
210 /* Note: most of these IRQs default to no-trigger */
211 .bytes_edr = 2,
212 .irq_lines = 2,
213 .mask = { {
214 .isr_offset = TWL5031_INTERRUPTS_BCIISR1,
215 .imr_offset = TWL5031_INTERRUPTS_BCIIMR1,
216 }, {
217 .isr_offset = TWL5031_INTERRUPTS_BCIISR2,
218 .imr_offset = TWL5031_INTERRUPTS_BCIIMR2,
219 }, },
220 },
221 [3] = {
222 .name = "madc",
223 SIH_INITIALIZER(MADC, 4)
224 },
225 [4] = {
226 /* USB doesn't use the same SIH organization */
227 .name = "usb",
228 },
229 [5] = {
230 .name = "power",
231 .set_cor = true,
232 SIH_INITIALIZER(INT_PWR, 8)
233 },
234 [6] = {
235 /*
Ilkka Koskinen191211f2010-05-20 13:04:20 +0300236 * ECI/DBI doesn't use the same SIH organization.
237 * For example, it supports only one interrupt output line.
238 * That is, the interrupts are seen on both INT1 and INT2 lines.
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200239 */
Ilkka Koskinen191211f2010-05-20 13:04:20 +0300240 .name = "eci_dbi",
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200241 .module = TWL5031_MODULE_ACCESSORY,
242 .bits = 9,
243 .bytes_ixr = 2,
244 .irq_lines = 1,
245 .mask = { {
246 .isr_offset = TWL5031_ACIIDR_LSB,
247 .imr_offset = TWL5031_ACIIMR_LSB,
248 }, },
249
250 },
251 [7] = {
Ilkka Koskinen191211f2010-05-20 13:04:20 +0300252 /* Audio accessory */
253 .name = "audio",
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200254 .module = TWL5031_MODULE_ACCESSORY,
255 .control_offset = TWL5031_ACCSIHCTRL,
256 .bits = 2,
257 .bytes_ixr = 1,
258 .edr_offset = TWL5031_ACCEDR1,
259 /* Note: most of these IRQs default to no-trigger */
260 .bytes_edr = 1,
261 .irq_lines = 2,
262 .mask = { {
263 .isr_offset = TWL5031_ACCISR1,
264 .imr_offset = TWL5031_ACCIMR1,
265 }, {
266 .isr_offset = TWL5031_ACCISR2,
267 .imr_offset = TWL5031_ACCIMR2,
268 }, },
269 },
270};
271
David Brownella30d46c2008-10-20 23:46:28 +0200272#undef TWL4030_MODULE_KEYPAD_KEYP
273#undef TWL4030_MODULE_INT_PWR
274#undef TWL4030_INT_PWR_EDR
275
276/*----------------------------------------------------------------------*/
277
278static unsigned twl4030_irq_base;
279
David Brownella30d46c2008-10-20 23:46:28 +0200280/*
281 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
282 * This is a chained interrupt, so there is no desc->action method for it.
283 * Now we need to query the interrupt controller in the twl4030 to determine
284 * which module is generating the interrupt request. However, we can't do i2c
285 * transactions in interrupt context, so we must defer that work to a kernel
286 * thread. All we do here is acknowledge and mask the interrupt and wakeup
287 * the kernel thread.
288 */
Russell King1cef8e42009-07-27 11:30:48 +0530289static irqreturn_t handle_twl4030_pih(int irq, void *devid)
David Brownella30d46c2008-10-20 23:46:28 +0200290{
Felipe Balbi7750c9b2011-06-30 12:51:06 +0300291 int module_irq;
292 irqreturn_t ret;
293 u8 pih_isr;
294
295 ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr,
296 REG_PIH_ISR_P1);
297 if (ret) {
298 pr_warning("twl4030: I2C error %d reading PIH ISR\n", ret);
299 return IRQ_NONE;
300 }
301
302 /* these handlers deal with the relevant SIH irq status */
303 for (module_irq = twl4030_irq_base;
304 pih_isr;
305 pih_isr >>= 1, module_irq++) {
306 if (pih_isr & 0x1)
307 generic_handle_irq(module_irq);
308 }
309
Russell King1cef8e42009-07-27 11:30:48 +0530310 return IRQ_HANDLED;
David Brownella30d46c2008-10-20 23:46:28 +0200311}
David Brownella30d46c2008-10-20 23:46:28 +0200312/*----------------------------------------------------------------------*/
313
314/*
315 * twl4030_init_sih_modules() ... start from a known state where no
316 * IRQs will be coming in, and where we can quickly enable them then
317 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
318 *
319 * NOTE: we don't touch EDR registers here; they stay with hardware
320 * defaults or whatever the last value was. Note that when both EDR
321 * bits for an IRQ are clear, that's as if its IMR bit is set...
322 */
323static int twl4030_init_sih_modules(unsigned line)
324{
325 const struct sih *sih;
326 u8 buf[4];
327 int i;
328 int status;
329
330 /* line 0 == int1_n signal; line 1 == int2_n signal */
331 if (line > 1)
332 return -EINVAL;
333
334 irq_line = line;
335
336 /* disable all interrupts on our line */
337 memset(buf, 0xff, sizeof buf);
338 sih = sih_modules;
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200339 for (i = 0; i < nr_sih_modules; i++, sih++) {
David Brownella30d46c2008-10-20 23:46:28 +0200340
341 /* skip USB -- it's funky */
342 if (!sih->bytes_ixr)
343 continue;
344
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200345 /* Not all the SIH modules support multiple interrupt lines */
346 if (sih->irq_lines <= line)
347 continue;
348
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100349 status = twl_i2c_write(sih->module, buf,
David Brownella30d46c2008-10-20 23:46:28 +0200350 sih->mask[line].imr_offset, sih->bytes_ixr);
351 if (status < 0)
352 pr_err("twl4030: err %d initializing %s %s\n",
353 status, sih->name, "IMR");
354
355 /* Maybe disable "exclusive" mode; buffer second pending irq;
356 * set Clear-On-Read (COR) bit.
357 *
358 * NOTE that sometimes COR polarity is documented as being
Grazvydas Ignotas8e52e272010-09-28 16:22:19 +0300359 * inverted: for MADC, COR=1 means "clear on write".
David Brownella30d46c2008-10-20 23:46:28 +0200360 * And for PWR_INT it's not documented...
361 */
362 if (sih->set_cor) {
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100363 status = twl_i2c_write_u8(sih->module,
David Brownella30d46c2008-10-20 23:46:28 +0200364 TWL4030_SIH_CTRL_COR_MASK,
365 sih->control_offset);
366 if (status < 0)
367 pr_err("twl4030: err %d initializing %s %s\n",
368 status, sih->name, "SIH_CTRL");
369 }
370 }
371
372 sih = sih_modules;
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200373 for (i = 0; i < nr_sih_modules; i++, sih++) {
David Brownella30d46c2008-10-20 23:46:28 +0200374 u8 rxbuf[4];
375 int j;
376
377 /* skip USB */
378 if (!sih->bytes_ixr)
379 continue;
380
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200381 /* Not all the SIH modules support multiple interrupt lines */
382 if (sih->irq_lines <= line)
383 continue;
384
David Brownella30d46c2008-10-20 23:46:28 +0200385 /* Clear pending interrupt status. Either the read was
386 * enough, or we need to write those bits. Repeat, in
387 * case an IRQ is pending (PENDDIS=0) ... that's not
388 * uncommon with PWR_INT.PWRON.
389 */
390 for (j = 0; j < 2; j++) {
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100391 status = twl_i2c_read(sih->module, rxbuf,
David Brownella30d46c2008-10-20 23:46:28 +0200392 sih->mask[line].isr_offset, sih->bytes_ixr);
393 if (status < 0)
394 pr_err("twl4030: err %d initializing %s %s\n",
395 status, sih->name, "ISR");
396
397 if (!sih->set_cor)
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100398 status = twl_i2c_write(sih->module, buf,
David Brownella30d46c2008-10-20 23:46:28 +0200399 sih->mask[line].isr_offset,
400 sih->bytes_ixr);
401 /* else COR=1 means read sufficed.
402 * (for most SIH modules...)
403 */
404 }
405 }
406
407 return 0;
408}
409
410static inline void activate_irq(int irq)
411{
412#ifdef CONFIG_ARM
413 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
414 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
415 */
416 set_irq_flags(irq, IRQF_VALID);
417#else
418 /* same effect on other architectures */
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000419 irq_set_noprobe(irq);
David Brownella30d46c2008-10-20 23:46:28 +0200420#endif
421}
422
423/*----------------------------------------------------------------------*/
424
David Brownella30d46c2008-10-20 23:46:28 +0200425static struct workqueue_struct *wq;
426
427struct sih_agent {
428 int irq_base;
429 const struct sih *sih;
430
431 u32 imr;
432 bool imr_change_pending;
433 struct work_struct mask_work;
434
435 u32 edge_change;
436 struct work_struct edge_work;
Felipe Balbi91e35692011-06-30 12:51:05 +0300437
438 struct mutex irq_lock;
David Brownella30d46c2008-10-20 23:46:28 +0200439};
440
441static void twl4030_sih_do_mask(struct work_struct *work)
442{
443 struct sih_agent *agent;
444 const struct sih *sih;
445 union {
446 u8 bytes[4];
447 u32 word;
448 } imr;
449 int status;
450
451 agent = container_of(work, struct sih_agent, mask_work);
452
453 /* see what work we have */
David Brownella30d46c2008-10-20 23:46:28 +0200454 if (agent->imr_change_pending) {
455 sih = agent->sih;
456 /* byte[0] gets overwritten as we write ... */
457 imr.word = cpu_to_le32(agent->imr << 8);
458 agent->imr_change_pending = false;
459 } else
460 sih = NULL;
David Brownella30d46c2008-10-20 23:46:28 +0200461 if (!sih)
462 return;
463
464 /* write the whole mask ... simpler than subsetting it */
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100465 status = twl_i2c_write(sih->module, imr.bytes,
David Brownella30d46c2008-10-20 23:46:28 +0200466 sih->mask[irq_line].imr_offset, sih->bytes_ixr);
467 if (status)
468 pr_err("twl4030: %s, %s --> %d\n", __func__,
469 "write", status);
470}
471
472static void twl4030_sih_do_edge(struct work_struct *work)
473{
474 struct sih_agent *agent;
475 const struct sih *sih;
476 u8 bytes[6];
477 u32 edge_change;
478 int status;
479
480 agent = container_of(work, struct sih_agent, edge_work);
481
482 /* see what work we have */
David Brownella30d46c2008-10-20 23:46:28 +0200483 edge_change = agent->edge_change;
Joe Perchesdf10d642009-06-28 09:26:30 -0700484 agent->edge_change = 0;
David Brownella30d46c2008-10-20 23:46:28 +0200485 sih = edge_change ? agent->sih : NULL;
David Brownella30d46c2008-10-20 23:46:28 +0200486 if (!sih)
487 return;
488
489 /* Read, reserving first byte for write scratch. Yes, this
490 * could be cached for some speedup ... but be careful about
491 * any processor on the other IRQ line, EDR registers are
492 * shared.
493 */
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100494 status = twl_i2c_read(sih->module, bytes + 1,
David Brownella30d46c2008-10-20 23:46:28 +0200495 sih->edr_offset, sih->bytes_edr);
496 if (status) {
497 pr_err("twl4030: %s, %s --> %d\n", __func__,
498 "read", status);
499 return;
500 }
501
502 /* Modify only the bits we know must change */
503 while (edge_change) {
504 int i = fls(edge_change) - 1;
Thomas Gleixnerd740f452011-03-25 11:12:31 +0000505 struct irq_data *idata = irq_get_irq_data(i + agent->irq_base);
David Brownella30d46c2008-10-20 23:46:28 +0200506 int byte = 1 + (i >> 2);
507 int off = (i & 0x3) * 2;
Thomas Gleixnerd740f452011-03-25 11:12:31 +0000508 unsigned int type;
Samuel Ortiz94964f92008-12-18 11:38:02 +0100509
David Brownella30d46c2008-10-20 23:46:28 +0200510 bytes[byte] &= ~(0x03 << off);
511
Thomas Gleixnerd740f452011-03-25 11:12:31 +0000512 type = irqd_get_trigger_type(idata);
513 if (type & IRQ_TYPE_EDGE_RISING)
David Brownella30d46c2008-10-20 23:46:28 +0200514 bytes[byte] |= BIT(off + 1);
Thomas Gleixnerd740f452011-03-25 11:12:31 +0000515 if (type & IRQ_TYPE_EDGE_FALLING)
David Brownella30d46c2008-10-20 23:46:28 +0200516 bytes[byte] |= BIT(off + 0);
David Brownella30d46c2008-10-20 23:46:28 +0200517
518 edge_change &= ~BIT(i);
519 }
520
521 /* Write */
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100522 status = twl_i2c_write(sih->module, bytes,
David Brownella30d46c2008-10-20 23:46:28 +0200523 sih->edr_offset, sih->bytes_edr);
524 if (status)
525 pr_err("twl4030: %s, %s --> %d\n", __func__,
526 "write", status);
527}
528
529/*----------------------------------------------------------------------*/
530
531/*
532 * All irq_chip methods get issued from code holding irq_desc[irq].lock,
533 * which can't perform the underlying I2C operations (because they sleep).
534 * So we must hand them off to a thread (workqueue) and cope with asynch
535 * completion, potentially including some re-ordering, of these requests.
536 */
537
Mark Brown845aeab2010-12-12 12:51:39 +0000538static void twl4030_sih_mask(struct irq_data *data)
David Brownella30d46c2008-10-20 23:46:28 +0200539{
Mark Brown845aeab2010-12-12 12:51:39 +0000540 struct sih_agent *sih = irq_data_get_irq_chip_data(data);
David Brownella30d46c2008-10-20 23:46:28 +0200541
Mark Brown845aeab2010-12-12 12:51:39 +0000542 sih->imr |= BIT(data->irq - sih->irq_base);
David Brownella30d46c2008-10-20 23:46:28 +0200543 sih->imr_change_pending = true;
544 queue_work(wq, &sih->mask_work);
David Brownella30d46c2008-10-20 23:46:28 +0200545}
546
Mark Brown845aeab2010-12-12 12:51:39 +0000547static void twl4030_sih_unmask(struct irq_data *data)
David Brownella30d46c2008-10-20 23:46:28 +0200548{
Mark Brown845aeab2010-12-12 12:51:39 +0000549 struct sih_agent *sih = irq_data_get_irq_chip_data(data);
David Brownella30d46c2008-10-20 23:46:28 +0200550
Mark Brown845aeab2010-12-12 12:51:39 +0000551 sih->imr &= ~BIT(data->irq - sih->irq_base);
David Brownella30d46c2008-10-20 23:46:28 +0200552 sih->imr_change_pending = true;
553 queue_work(wq, &sih->mask_work);
David Brownella30d46c2008-10-20 23:46:28 +0200554}
555
Mark Brown845aeab2010-12-12 12:51:39 +0000556static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger)
David Brownella30d46c2008-10-20 23:46:28 +0200557{
Mark Brown845aeab2010-12-12 12:51:39 +0000558 struct sih_agent *sih = irq_data_get_irq_chip_data(data);
David Brownella30d46c2008-10-20 23:46:28 +0200559
David Brownella30d46c2008-10-20 23:46:28 +0200560 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
561 return -EINVAL;
562
Thomas Gleixnerd740f452011-03-25 11:12:31 +0000563 if (irqd_get_trigger_type(data) != trigger) {
Mark Brown845aeab2010-12-12 12:51:39 +0000564 sih->edge_change |= BIT(data->irq - sih->irq_base);
David Brownella30d46c2008-10-20 23:46:28 +0200565 queue_work(wq, &sih->edge_work);
566 }
Felipe Balbi91e35692011-06-30 12:51:05 +0300567
David Brownella30d46c2008-10-20 23:46:28 +0200568 return 0;
569}
570
Felipe Balbi91e35692011-06-30 12:51:05 +0300571static void twl4030_sih_bus_lock(struct irq_data *data)
572{
573 struct sih_agent *sih = irq_data_get_irq_chip_data(data);
574
575 mutex_lock(&sih->irq_lock);
576}
577
578static void twl4030_sih_bus_sync_unlock(struct irq_data *data)
579{
580 struct sih_agent *sih = irq_data_get_irq_chip_data(data);
581
582 mutex_unlock(&sih->irq_lock);
583}
584
David Brownella30d46c2008-10-20 23:46:28 +0200585static struct irq_chip twl4030_sih_irq_chip = {
586 .name = "twl4030",
Felipe Balbi8cd6af22011-06-30 12:51:04 +0300587 .irq_mask = twl4030_sih_mask,
Mark Brown845aeab2010-12-12 12:51:39 +0000588 .irq_unmask = twl4030_sih_unmask,
589 .irq_set_type = twl4030_sih_set_type,
Felipe Balbi91e35692011-06-30 12:51:05 +0300590 .irq_bus_lock = twl4030_sih_bus_lock,
591 .irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock,
David Brownella30d46c2008-10-20 23:46:28 +0200592};
593
594/*----------------------------------------------------------------------*/
595
596static inline int sih_read_isr(const struct sih *sih)
597{
598 int status;
599 union {
600 u8 bytes[4];
601 u32 word;
602 } isr;
603
604 /* FIXME need retry-on-error ... */
605
606 isr.word = 0;
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100607 status = twl_i2c_read(sih->module, isr.bytes,
David Brownella30d46c2008-10-20 23:46:28 +0200608 sih->mask[irq_line].isr_offset, sih->bytes_ixr);
609
610 return (status < 0) ? status : le32_to_cpu(isr.word);
611}
612
613/*
614 * Generic handler for SIH interrupts ... we "know" this is called
615 * in task context, with IRQs enabled.
616 */
617static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc)
618{
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000619 struct sih_agent *agent = irq_get_handler_data(irq);
David Brownella30d46c2008-10-20 23:46:28 +0200620 const struct sih *sih = agent->sih;
621 int isr;
622
623 /* reading ISR acks the IRQs, using clear-on-read mode */
624 local_irq_enable();
625 isr = sih_read_isr(sih);
626 local_irq_disable();
627
628 if (isr < 0) {
629 pr_err("twl4030: %s SIH, read ISR error %d\n",
630 sih->name, isr);
631 /* REVISIT: recover; eventually mask it all, etc */
632 return;
633 }
634
635 while (isr) {
636 irq = fls(isr);
637 irq--;
638 isr &= ~BIT(irq);
639
640 if (irq < sih->bits)
641 generic_handle_irq(agent->irq_base + irq);
642 else
643 pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
644 sih->name, irq);
645 }
646}
647
648static unsigned twl4030_irq_next;
649
650/* returns the first IRQ used by this SIH bank,
651 * or negative errno
652 */
653int twl4030_sih_setup(int module)
654{
655 int sih_mod;
656 const struct sih *sih = NULL;
657 struct sih_agent *agent;
658 int i, irq;
659 int status = -EINVAL;
660 unsigned irq_base = twl4030_irq_next;
661
662 /* only support modules with standard clear-on-read for now */
663 for (sih_mod = 0, sih = sih_modules;
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200664 sih_mod < nr_sih_modules;
David Brownella30d46c2008-10-20 23:46:28 +0200665 sih_mod++, sih++) {
666 if (sih->module == module && sih->set_cor) {
667 if (!WARN((irq_base + sih->bits) > NR_IRQS,
668 "irq %d for %s too big\n",
669 irq_base + sih->bits,
670 sih->name))
671 status = 0;
672 break;
673 }
674 }
675 if (status < 0)
676 return status;
677
678 agent = kzalloc(sizeof *agent, GFP_KERNEL);
679 if (!agent)
680 return -ENOMEM;
681
682 status = 0;
683
684 agent->irq_base = irq_base;
685 agent->sih = sih;
686 agent->imr = ~0;
Felipe Balbi91e35692011-06-30 12:51:05 +0300687 mutex_init(&agent->irq_lock);
David Brownella30d46c2008-10-20 23:46:28 +0200688 INIT_WORK(&agent->mask_work, twl4030_sih_do_mask);
689 INIT_WORK(&agent->edge_work, twl4030_sih_do_edge);
690
691 for (i = 0; i < sih->bits; i++) {
692 irq = irq_base + i;
693
Felipe Balbi91e35692011-06-30 12:51:05 +0300694 irq_set_chip_data(irq, agent);
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000695 irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip,
696 handle_edge_irq);
David Brownella30d46c2008-10-20 23:46:28 +0200697 activate_irq(irq);
698 }
699
700 status = irq_base;
701 twl4030_irq_next += i;
702
703 /* replace generic PIH handler (handle_simple_irq) */
704 irq = sih_mod + twl4030_irq_base;
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000705 irq_set_handler_data(irq, agent);
706 irq_set_chained_handler(irq, handle_twl4030_sih);
David Brownella30d46c2008-10-20 23:46:28 +0200707
708 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name,
709 irq, irq_base, twl4030_irq_next - 1);
710
711 return status;
712}
713
714/* FIXME need a call to reverse twl4030_sih_setup() ... */
715
716
717/*----------------------------------------------------------------------*/
718
719/* FIXME pass in which interrupt line we'll use ... */
720#define twl_irq_line 0
721
Balaji T Ke8deb282009-12-14 00:25:31 +0100722int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
David Brownella30d46c2008-10-20 23:46:28 +0200723{
724 static struct irq_chip twl4030_irq_chip;
725
726 int status;
727 int i;
David Brownella30d46c2008-10-20 23:46:28 +0200728
729 /*
730 * Mask and clear all TWL4030 interrupts since initially we do
731 * not have any TWL4030 module interrupt handlers present
732 */
733 status = twl4030_init_sih_modules(twl_irq_line);
734 if (status < 0)
735 return status;
736
737 wq = create_singlethread_workqueue("twl4030-irqchip");
738 if (!wq) {
739 pr_err("twl4030: workqueue FAIL\n");
740 return -ESRCH;
741 }
742
743 twl4030_irq_base = irq_base;
744
745 /* install an irq handler for each of the SIH modules;
746 * clone dummy irq_chip since PIH can't *do* anything
747 */
748 twl4030_irq_chip = dummy_irq_chip;
749 twl4030_irq_chip.name = "twl4030";
750
Thomas Gleixnerfe212212010-10-08 15:33:01 +0200751 twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack;
David Brownella30d46c2008-10-20 23:46:28 +0200752
753 for (i = irq_base; i < irq_end; i++) {
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000754 irq_set_chip_and_handler(i, &twl4030_irq_chip,
755 handle_simple_irq);
David Brownella30d46c2008-10-20 23:46:28 +0200756 activate_irq(i);
757 }
758 twl4030_irq_next = i;
759 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
760 irq_num, irq_base, twl4030_irq_next - 1);
761
762 /* ... and the PWR_INT module ... */
763 status = twl4030_sih_setup(TWL4030_MODULE_INT);
764 if (status < 0) {
765 pr_err("twl4030: sih_setup PWR INT --> %d\n", status);
766 goto fail;
767 }
768
769 /* install an irq handler to demultiplex the TWL4030 interrupt */
Felipe Balbi7750c9b2011-06-30 12:51:06 +0300770 status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih,
771 IRQF_DISABLED, "TWL4030-PIH", NULL);
Russell King1cef8e42009-07-27 11:30:48 +0530772 if (status < 0) {
773 pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status);
774 goto fail_rqirq;
David Brownella30d46c2008-10-20 23:46:28 +0200775 }
776
David Brownella30d46c2008-10-20 23:46:28 +0200777 return status;
Russell King1cef8e42009-07-27 11:30:48 +0530778fail_rqirq:
779 /* clean up twl4030_sih_setup */
David Brownella30d46c2008-10-20 23:46:28 +0200780fail:
781 for (i = irq_base; i < irq_end; i++)
Thomas Gleixnerd5bb1222011-03-25 11:12:32 +0000782 irq_set_chip_and_handler(i, NULL, NULL);
David Brownella30d46c2008-10-20 23:46:28 +0200783 destroy_workqueue(wq);
784 wq = NULL;
785 return status;
786}
787
Balaji T Ke8deb282009-12-14 00:25:31 +0100788int twl4030_exit_irq(void)
David Brownella30d46c2008-10-20 23:46:28 +0200789{
790 /* FIXME undo twl_init_irq() */
791 if (twl4030_irq_base) {
792 pr_err("twl4030: can't yet clean up IRQs?\n");
793 return -ENOSYS;
794 }
795 return 0;
796}
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200797
Balaji T Ke8deb282009-12-14 00:25:31 +0100798int twl4030_init_chip_irq(const char *chip)
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200799{
800 if (!strcmp(chip, "twl5031")) {
801 sih_modules = sih_modules_twl5031;
802 nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031);
803 } else {
804 sih_modules = sih_modules_twl4030;
805 nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030);
806 }
807
808 return 0;
809}