Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include "drmP.h" |
| 25 | #include "radeon.h" |
| 26 | #include "cikd.h" |
| 27 | #include "r600_dpm.h" |
| 28 | #include "kv_dpm.h" |
Alex Deucher | ae3e40e | 2013-07-18 16:39:53 -0400 | [diff] [blame] | 29 | #include <linux/seq_file.h> |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 30 | |
| 31 | #define KV_MAX_DEEPSLEEP_DIVIDER_ID 5 |
| 32 | #define KV_MINIMUM_ENGINE_CLOCK 800 |
| 33 | #define SMC_RAM_END 0x40000 |
| 34 | |
| 35 | static void kv_init_graphics_levels(struct radeon_device *rdev); |
| 36 | static int kv_calculate_ds_divider(struct radeon_device *rdev); |
| 37 | static int kv_calculate_nbps_level_settings(struct radeon_device *rdev); |
| 38 | static int kv_calculate_dpm_settings(struct radeon_device *rdev); |
| 39 | static void kv_enable_new_levels(struct radeon_device *rdev); |
| 40 | static void kv_program_nbps_index_settings(struct radeon_device *rdev, |
| 41 | struct radeon_ps *new_rps); |
| 42 | static int kv_set_enabled_levels(struct radeon_device *rdev); |
Alex Deucher | 2b4c802 | 2013-07-18 16:48:46 -0400 | [diff] [blame] | 43 | static int kv_force_dpm_highest(struct radeon_device *rdev); |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 44 | static int kv_force_dpm_lowest(struct radeon_device *rdev); |
| 45 | static void kv_apply_state_adjust_rules(struct radeon_device *rdev, |
| 46 | struct radeon_ps *new_rps, |
| 47 | struct radeon_ps *old_rps); |
| 48 | static int kv_set_thermal_temperature_range(struct radeon_device *rdev, |
| 49 | int min_temp, int max_temp); |
| 50 | static int kv_init_fps_limits(struct radeon_device *rdev); |
| 51 | |
Alex Deucher | 77df508 | 2013-08-09 10:02:40 -0400 | [diff] [blame^] | 52 | void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 53 | static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate); |
| 54 | static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate); |
| 55 | static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate); |
| 56 | |
| 57 | extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev); |
| 58 | extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev); |
| 59 | extern void cik_update_cg(struct radeon_device *rdev, |
| 60 | u32 block, bool enable); |
| 61 | |
Alex Deucher | 77df508 | 2013-08-09 10:02:40 -0400 | [diff] [blame^] | 62 | extern void cik_uvd_resume(struct radeon_device *rdev); |
| 63 | extern int r600_uvd_init(struct radeon_device *rdev, bool ring_test); |
| 64 | extern void r600_do_uvd_stop(struct radeon_device *rdev); |
| 65 | |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 66 | static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] = |
| 67 | { |
| 68 | { 0, 4, 1 }, |
| 69 | { 1, 4, 1 }, |
| 70 | { 2, 5, 1 }, |
| 71 | { 3, 4, 2 }, |
| 72 | { 4, 1, 1 }, |
| 73 | { 5, 5, 2 }, |
| 74 | { 6, 6, 1 }, |
| 75 | { 7, 9, 2 }, |
| 76 | { 0xffffffff } |
| 77 | }; |
| 78 | |
| 79 | static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] = |
| 80 | { |
| 81 | { 0, 4, 1 }, |
| 82 | { 0xffffffff } |
| 83 | }; |
| 84 | |
| 85 | static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] = |
| 86 | { |
| 87 | { 0, 4, 1 }, |
| 88 | { 0xffffffff } |
| 89 | }; |
| 90 | |
| 91 | static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] = |
| 92 | { |
| 93 | { 0, 4, 1 }, |
| 94 | { 0xffffffff } |
| 95 | }; |
| 96 | |
| 97 | static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] = |
| 98 | { |
| 99 | { 0, 4, 1 }, |
| 100 | { 0xffffffff } |
| 101 | }; |
| 102 | |
| 103 | static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] = |
| 104 | { |
| 105 | { 0, 4, 1 }, |
| 106 | { 1, 4, 1 }, |
| 107 | { 2, 5, 1 }, |
| 108 | { 3, 4, 1 }, |
| 109 | { 4, 1, 1 }, |
| 110 | { 5, 5, 1 }, |
| 111 | { 6, 6, 1 }, |
| 112 | { 7, 9, 1 }, |
| 113 | { 8, 4, 1 }, |
| 114 | { 9, 2, 1 }, |
| 115 | { 10, 3, 1 }, |
| 116 | { 11, 6, 1 }, |
| 117 | { 12, 8, 2 }, |
| 118 | { 13, 1, 1 }, |
| 119 | { 14, 2, 1 }, |
| 120 | { 15, 3, 1 }, |
| 121 | { 16, 1, 1 }, |
| 122 | { 17, 4, 1 }, |
| 123 | { 18, 3, 1 }, |
| 124 | { 19, 1, 1 }, |
| 125 | { 20, 8, 1 }, |
| 126 | { 21, 5, 1 }, |
| 127 | { 22, 1, 1 }, |
| 128 | { 23, 1, 1 }, |
| 129 | { 24, 4, 1 }, |
| 130 | { 27, 6, 1 }, |
| 131 | { 28, 1, 1 }, |
| 132 | { 0xffffffff } |
| 133 | }; |
| 134 | |
| 135 | static const struct kv_lcac_config_reg sx0_cac_config_reg[] = |
| 136 | { |
| 137 | { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } |
| 138 | }; |
| 139 | |
| 140 | static const struct kv_lcac_config_reg mc0_cac_config_reg[] = |
| 141 | { |
| 142 | { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } |
| 143 | }; |
| 144 | |
| 145 | static const struct kv_lcac_config_reg mc1_cac_config_reg[] = |
| 146 | { |
| 147 | { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } |
| 148 | }; |
| 149 | |
| 150 | static const struct kv_lcac_config_reg mc2_cac_config_reg[] = |
| 151 | { |
| 152 | { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } |
| 153 | }; |
| 154 | |
| 155 | static const struct kv_lcac_config_reg mc3_cac_config_reg[] = |
| 156 | { |
| 157 | { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } |
| 158 | }; |
| 159 | |
| 160 | static const struct kv_lcac_config_reg cpl_cac_config_reg[] = |
| 161 | { |
| 162 | { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } |
| 163 | }; |
| 164 | |
| 165 | static const struct kv_pt_config_reg didt_config_kv[] = |
| 166 | { |
| 167 | { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 168 | { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 169 | { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 170 | { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 171 | { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 172 | { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 173 | { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 174 | { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 175 | { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 176 | { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 177 | { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 178 | { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 179 | { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, |
| 180 | { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, |
| 181 | { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, |
| 182 | { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, |
| 183 | { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, |
| 184 | { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 185 | { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 186 | { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 187 | { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 188 | { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 189 | { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 190 | { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 191 | { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 192 | { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 193 | { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 194 | { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 195 | { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 196 | { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 197 | { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, |
| 198 | { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, |
| 199 | { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, |
| 200 | { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, |
| 201 | { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, |
| 202 | { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 203 | { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 204 | { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 205 | { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 206 | { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 207 | { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 208 | { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 209 | { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 210 | { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 211 | { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 212 | { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 213 | { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 214 | { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 215 | { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, |
| 216 | { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, |
| 217 | { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, |
| 218 | { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, |
| 219 | { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, |
| 220 | { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 221 | { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 222 | { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 223 | { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 224 | { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 225 | { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 226 | { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 227 | { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 228 | { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 229 | { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 230 | { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 231 | { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 232 | { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 233 | { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, |
| 234 | { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, |
| 235 | { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, |
| 236 | { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, |
| 237 | { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, |
| 238 | { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, |
| 239 | { 0xFFFFFFFF } |
| 240 | }; |
| 241 | |
| 242 | static struct kv_ps *kv_get_ps(struct radeon_ps *rps) |
| 243 | { |
| 244 | struct kv_ps *ps = rps->ps_priv; |
| 245 | |
| 246 | return ps; |
| 247 | } |
| 248 | |
| 249 | static struct kv_power_info *kv_get_pi(struct radeon_device *rdev) |
| 250 | { |
| 251 | struct kv_power_info *pi = rdev->pm.dpm.priv; |
| 252 | |
| 253 | return pi; |
| 254 | } |
| 255 | |
| 256 | #if 0 |
| 257 | static void kv_program_local_cac_table(struct radeon_device *rdev, |
| 258 | const struct kv_lcac_config_values *local_cac_table, |
| 259 | const struct kv_lcac_config_reg *local_cac_reg) |
| 260 | { |
| 261 | u32 i, count, data; |
| 262 | const struct kv_lcac_config_values *values = local_cac_table; |
| 263 | |
| 264 | while (values->block_id != 0xffffffff) { |
| 265 | count = values->signal_id; |
| 266 | for (i = 0; i < count; i++) { |
| 267 | data = ((values->block_id << local_cac_reg->block_shift) & |
| 268 | local_cac_reg->block_mask); |
| 269 | data |= ((i << local_cac_reg->signal_shift) & |
| 270 | local_cac_reg->signal_mask); |
| 271 | data |= ((values->t << local_cac_reg->t_shift) & |
| 272 | local_cac_reg->t_mask); |
| 273 | data |= ((1 << local_cac_reg->enable_shift) & |
| 274 | local_cac_reg->enable_mask); |
| 275 | WREG32_SMC(local_cac_reg->cntl, data); |
| 276 | } |
| 277 | values++; |
| 278 | } |
| 279 | } |
| 280 | #endif |
| 281 | |
| 282 | static int kv_program_pt_config_registers(struct radeon_device *rdev, |
| 283 | const struct kv_pt_config_reg *cac_config_regs) |
| 284 | { |
| 285 | const struct kv_pt_config_reg *config_regs = cac_config_regs; |
| 286 | u32 data; |
| 287 | u32 cache = 0; |
| 288 | |
| 289 | if (config_regs == NULL) |
| 290 | return -EINVAL; |
| 291 | |
| 292 | while (config_regs->offset != 0xFFFFFFFF) { |
| 293 | if (config_regs->type == KV_CONFIGREG_CACHE) { |
| 294 | cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); |
| 295 | } else { |
| 296 | switch (config_regs->type) { |
| 297 | case KV_CONFIGREG_SMC_IND: |
| 298 | data = RREG32_SMC(config_regs->offset); |
| 299 | break; |
| 300 | case KV_CONFIGREG_DIDT_IND: |
| 301 | data = RREG32_DIDT(config_regs->offset); |
| 302 | break; |
| 303 | default: |
| 304 | data = RREG32(config_regs->offset << 2); |
| 305 | break; |
| 306 | } |
| 307 | |
| 308 | data &= ~config_regs->mask; |
| 309 | data |= ((config_regs->value << config_regs->shift) & config_regs->mask); |
| 310 | data |= cache; |
| 311 | cache = 0; |
| 312 | |
| 313 | switch (config_regs->type) { |
| 314 | case KV_CONFIGREG_SMC_IND: |
| 315 | WREG32_SMC(config_regs->offset, data); |
| 316 | break; |
| 317 | case KV_CONFIGREG_DIDT_IND: |
| 318 | WREG32_DIDT(config_regs->offset, data); |
| 319 | break; |
| 320 | default: |
| 321 | WREG32(config_regs->offset << 2, data); |
| 322 | break; |
| 323 | } |
| 324 | } |
| 325 | config_regs++; |
| 326 | } |
| 327 | |
| 328 | return 0; |
| 329 | } |
| 330 | |
| 331 | static void kv_do_enable_didt(struct radeon_device *rdev, bool enable) |
| 332 | { |
| 333 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 334 | u32 data; |
| 335 | |
| 336 | if (pi->caps_sq_ramping) { |
| 337 | data = RREG32_DIDT(DIDT_SQ_CTRL0); |
| 338 | if (enable) |
| 339 | data |= DIDT_CTRL_EN; |
| 340 | else |
| 341 | data &= ~DIDT_CTRL_EN; |
| 342 | WREG32_DIDT(DIDT_SQ_CTRL0, data); |
| 343 | } |
| 344 | |
| 345 | if (pi->caps_db_ramping) { |
| 346 | data = RREG32_DIDT(DIDT_DB_CTRL0); |
| 347 | if (enable) |
| 348 | data |= DIDT_CTRL_EN; |
| 349 | else |
| 350 | data &= ~DIDT_CTRL_EN; |
| 351 | WREG32_DIDT(DIDT_DB_CTRL0, data); |
| 352 | } |
| 353 | |
| 354 | if (pi->caps_td_ramping) { |
| 355 | data = RREG32_DIDT(DIDT_TD_CTRL0); |
| 356 | if (enable) |
| 357 | data |= DIDT_CTRL_EN; |
| 358 | else |
| 359 | data &= ~DIDT_CTRL_EN; |
| 360 | WREG32_DIDT(DIDT_TD_CTRL0, data); |
| 361 | } |
| 362 | |
| 363 | if (pi->caps_tcp_ramping) { |
| 364 | data = RREG32_DIDT(DIDT_TCP_CTRL0); |
| 365 | if (enable) |
| 366 | data |= DIDT_CTRL_EN; |
| 367 | else |
| 368 | data &= ~DIDT_CTRL_EN; |
| 369 | WREG32_DIDT(DIDT_TCP_CTRL0, data); |
| 370 | } |
| 371 | } |
| 372 | |
| 373 | static int kv_enable_didt(struct radeon_device *rdev, bool enable) |
| 374 | { |
| 375 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 376 | int ret; |
| 377 | |
| 378 | if (pi->caps_sq_ramping || |
| 379 | pi->caps_db_ramping || |
| 380 | pi->caps_td_ramping || |
| 381 | pi->caps_tcp_ramping) { |
| 382 | cik_enter_rlc_safe_mode(rdev); |
| 383 | |
| 384 | if (enable) { |
| 385 | ret = kv_program_pt_config_registers(rdev, didt_config_kv); |
| 386 | if (ret) { |
| 387 | cik_exit_rlc_safe_mode(rdev); |
| 388 | return ret; |
| 389 | } |
| 390 | } |
| 391 | |
| 392 | kv_do_enable_didt(rdev, enable); |
| 393 | |
| 394 | cik_exit_rlc_safe_mode(rdev); |
| 395 | } |
| 396 | |
| 397 | return 0; |
| 398 | } |
| 399 | |
| 400 | #if 0 |
| 401 | static void kv_initialize_hardware_cac_manager(struct radeon_device *rdev) |
| 402 | { |
| 403 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 404 | |
| 405 | if (pi->caps_cac) { |
| 406 | WREG32_SMC(LCAC_SX0_OVR_SEL, 0); |
| 407 | WREG32_SMC(LCAC_SX0_OVR_VAL, 0); |
| 408 | kv_program_local_cac_table(rdev, sx_local_cac_cfg_kv, sx0_cac_config_reg); |
| 409 | |
| 410 | WREG32_SMC(LCAC_MC0_OVR_SEL, 0); |
| 411 | WREG32_SMC(LCAC_MC0_OVR_VAL, 0); |
| 412 | kv_program_local_cac_table(rdev, mc0_local_cac_cfg_kv, mc0_cac_config_reg); |
| 413 | |
| 414 | WREG32_SMC(LCAC_MC1_OVR_SEL, 0); |
| 415 | WREG32_SMC(LCAC_MC1_OVR_VAL, 0); |
| 416 | kv_program_local_cac_table(rdev, mc1_local_cac_cfg_kv, mc1_cac_config_reg); |
| 417 | |
| 418 | WREG32_SMC(LCAC_MC2_OVR_SEL, 0); |
| 419 | WREG32_SMC(LCAC_MC2_OVR_VAL, 0); |
| 420 | kv_program_local_cac_table(rdev, mc2_local_cac_cfg_kv, mc2_cac_config_reg); |
| 421 | |
| 422 | WREG32_SMC(LCAC_MC3_OVR_SEL, 0); |
| 423 | WREG32_SMC(LCAC_MC3_OVR_VAL, 0); |
| 424 | kv_program_local_cac_table(rdev, mc3_local_cac_cfg_kv, mc3_cac_config_reg); |
| 425 | |
| 426 | WREG32_SMC(LCAC_CPL_OVR_SEL, 0); |
| 427 | WREG32_SMC(LCAC_CPL_OVR_VAL, 0); |
| 428 | kv_program_local_cac_table(rdev, cpl_local_cac_cfg_kv, cpl_cac_config_reg); |
| 429 | } |
| 430 | } |
| 431 | #endif |
| 432 | |
| 433 | static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable) |
| 434 | { |
| 435 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 436 | int ret = 0; |
| 437 | |
| 438 | if (pi->caps_cac) { |
| 439 | if (enable) { |
| 440 | ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableCac); |
| 441 | if (ret) |
| 442 | pi->cac_enabled = false; |
| 443 | else |
| 444 | pi->cac_enabled = true; |
| 445 | } else if (pi->cac_enabled) { |
| 446 | kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableCac); |
| 447 | pi->cac_enabled = false; |
| 448 | } |
| 449 | } |
| 450 | |
| 451 | return ret; |
| 452 | } |
| 453 | |
| 454 | static int kv_process_firmware_header(struct radeon_device *rdev) |
| 455 | { |
| 456 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 457 | u32 tmp; |
| 458 | int ret; |
| 459 | |
| 460 | ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION + |
| 461 | offsetof(SMU7_Firmware_Header, DpmTable), |
| 462 | &tmp, pi->sram_end); |
| 463 | |
| 464 | if (ret == 0) |
| 465 | pi->dpm_table_start = tmp; |
| 466 | |
| 467 | ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION + |
| 468 | offsetof(SMU7_Firmware_Header, SoftRegisters), |
| 469 | &tmp, pi->sram_end); |
| 470 | |
| 471 | if (ret == 0) |
| 472 | pi->soft_regs_start = tmp; |
| 473 | |
| 474 | return ret; |
| 475 | } |
| 476 | |
| 477 | static int kv_enable_dpm_voltage_scaling(struct radeon_device *rdev) |
| 478 | { |
| 479 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 480 | int ret; |
| 481 | |
| 482 | pi->graphics_voltage_change_enable = 1; |
| 483 | |
| 484 | ret = kv_copy_bytes_to_smc(rdev, |
| 485 | pi->dpm_table_start + |
| 486 | offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable), |
| 487 | &pi->graphics_voltage_change_enable, |
| 488 | sizeof(u8), pi->sram_end); |
| 489 | |
| 490 | return ret; |
| 491 | } |
| 492 | |
| 493 | static int kv_set_dpm_interval(struct radeon_device *rdev) |
| 494 | { |
| 495 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 496 | int ret; |
| 497 | |
| 498 | pi->graphics_interval = 1; |
| 499 | |
| 500 | ret = kv_copy_bytes_to_smc(rdev, |
| 501 | pi->dpm_table_start + |
| 502 | offsetof(SMU7_Fusion_DpmTable, GraphicsInterval), |
| 503 | &pi->graphics_interval, |
| 504 | sizeof(u8), pi->sram_end); |
| 505 | |
| 506 | return ret; |
| 507 | } |
| 508 | |
| 509 | static int kv_set_dpm_boot_state(struct radeon_device *rdev) |
| 510 | { |
| 511 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 512 | int ret; |
| 513 | |
| 514 | ret = kv_copy_bytes_to_smc(rdev, |
| 515 | pi->dpm_table_start + |
| 516 | offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel), |
| 517 | &pi->graphics_boot_level, |
| 518 | sizeof(u8), pi->sram_end); |
| 519 | |
| 520 | return ret; |
| 521 | } |
| 522 | |
| 523 | static void kv_program_vc(struct radeon_device *rdev) |
| 524 | { |
| 525 | WREG32_SMC(CG_FTV_0, 0x3FFFC000); |
| 526 | } |
| 527 | |
| 528 | static void kv_clear_vc(struct radeon_device *rdev) |
| 529 | { |
| 530 | WREG32_SMC(CG_FTV_0, 0); |
| 531 | } |
| 532 | |
| 533 | static int kv_set_divider_value(struct radeon_device *rdev, |
| 534 | u32 index, u32 sclk) |
| 535 | { |
| 536 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 537 | struct atom_clock_dividers dividers; |
| 538 | int ret; |
| 539 | |
| 540 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, |
| 541 | sclk, false, ÷rs); |
| 542 | if (ret) |
| 543 | return ret; |
| 544 | |
| 545 | pi->graphics_level[index].SclkDid = (u8)dividers.post_div; |
| 546 | pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); |
| 547 | |
| 548 | return 0; |
| 549 | } |
| 550 | |
| 551 | static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev, |
| 552 | u16 voltage) |
| 553 | { |
| 554 | return 6200 - (voltage * 25); |
| 555 | } |
| 556 | |
| 557 | static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev, |
| 558 | u32 vid_2bit) |
| 559 | { |
| 560 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 561 | u32 vid_8bit = sumo_convert_vid2_to_vid7(rdev, |
| 562 | &pi->sys_info.vid_mapping_table, |
| 563 | vid_2bit); |
| 564 | |
| 565 | return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit); |
| 566 | } |
| 567 | |
| 568 | |
| 569 | static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid) |
| 570 | { |
| 571 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 572 | |
| 573 | pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; |
| 574 | pi->graphics_level[index].MinVddNb = |
| 575 | cpu_to_be32(kv_convert_2bit_index_to_voltage(rdev, vid)); |
| 576 | |
| 577 | return 0; |
| 578 | } |
| 579 | |
| 580 | static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at) |
| 581 | { |
| 582 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 583 | |
| 584 | pi->graphics_level[index].AT = cpu_to_be16((u16)at); |
| 585 | |
| 586 | return 0; |
| 587 | } |
| 588 | |
| 589 | static void kv_dpm_power_level_enable(struct radeon_device *rdev, |
| 590 | u32 index, bool enable) |
| 591 | { |
| 592 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 593 | |
| 594 | pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; |
| 595 | } |
| 596 | |
| 597 | static void kv_start_dpm(struct radeon_device *rdev) |
| 598 | { |
| 599 | u32 tmp = RREG32_SMC(GENERAL_PWRMGT); |
| 600 | |
| 601 | tmp |= GLOBAL_PWRMGT_EN; |
| 602 | WREG32_SMC(GENERAL_PWRMGT, tmp); |
| 603 | |
| 604 | kv_smc_dpm_enable(rdev, true); |
| 605 | } |
| 606 | |
| 607 | static void kv_stop_dpm(struct radeon_device *rdev) |
| 608 | { |
| 609 | kv_smc_dpm_enable(rdev, false); |
| 610 | } |
| 611 | |
| 612 | static void kv_start_am(struct radeon_device *rdev) |
| 613 | { |
| 614 | u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); |
| 615 | |
| 616 | sclk_pwrmgt_cntl &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT); |
| 617 | sclk_pwrmgt_cntl |= DYNAMIC_PM_EN; |
| 618 | |
| 619 | WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); |
| 620 | } |
| 621 | |
| 622 | static void kv_reset_am(struct radeon_device *rdev) |
| 623 | { |
| 624 | u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); |
| 625 | |
| 626 | sclk_pwrmgt_cntl |= (RESET_SCLK_CNT | RESET_BUSY_CNT); |
| 627 | |
| 628 | WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); |
| 629 | } |
| 630 | |
| 631 | static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze) |
| 632 | { |
| 633 | return kv_notify_message_to_smu(rdev, freeze ? |
| 634 | PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel); |
| 635 | } |
| 636 | |
| 637 | static int kv_force_lowest_valid(struct radeon_device *rdev) |
| 638 | { |
| 639 | return kv_force_dpm_lowest(rdev); |
| 640 | } |
| 641 | |
| 642 | static int kv_unforce_levels(struct radeon_device *rdev) |
| 643 | { |
| 644 | return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel); |
| 645 | } |
| 646 | |
| 647 | static int kv_update_sclk_t(struct radeon_device *rdev) |
| 648 | { |
| 649 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 650 | u32 low_sclk_interrupt_t = 0; |
| 651 | int ret = 0; |
| 652 | |
| 653 | if (pi->caps_sclk_throttle_low_notification) { |
| 654 | low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); |
| 655 | |
| 656 | ret = kv_copy_bytes_to_smc(rdev, |
| 657 | pi->dpm_table_start + |
| 658 | offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT), |
| 659 | (u8 *)&low_sclk_interrupt_t, |
| 660 | sizeof(u32), pi->sram_end); |
| 661 | } |
| 662 | return ret; |
| 663 | } |
| 664 | |
| 665 | static int kv_program_bootup_state(struct radeon_device *rdev) |
| 666 | { |
| 667 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 668 | u32 i; |
| 669 | struct radeon_clock_voltage_dependency_table *table = |
| 670 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; |
| 671 | |
| 672 | if (table && table->count) { |
| 673 | for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) { |
| 674 | if ((table->entries[i].clk == pi->boot_pl.sclk) || |
| 675 | (i == 0)) |
| 676 | break; |
| 677 | } |
| 678 | |
| 679 | pi->graphics_boot_level = (u8)i; |
| 680 | kv_dpm_power_level_enable(rdev, i, true); |
| 681 | } else { |
| 682 | struct sumo_sclk_voltage_mapping_table *table = |
| 683 | &pi->sys_info.sclk_voltage_mapping_table; |
| 684 | |
| 685 | if (table->num_max_dpm_entries == 0) |
| 686 | return -EINVAL; |
| 687 | |
| 688 | for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) { |
| 689 | if ((table->entries[i].sclk_frequency == pi->boot_pl.sclk) || |
| 690 | (i == 0)) |
| 691 | break; |
| 692 | } |
| 693 | |
| 694 | pi->graphics_boot_level = (u8)i; |
| 695 | kv_dpm_power_level_enable(rdev, i, true); |
| 696 | } |
| 697 | return 0; |
| 698 | } |
| 699 | |
| 700 | static int kv_enable_auto_thermal_throttling(struct radeon_device *rdev) |
| 701 | { |
| 702 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 703 | int ret; |
| 704 | |
| 705 | pi->graphics_therm_throttle_enable = 1; |
| 706 | |
| 707 | ret = kv_copy_bytes_to_smc(rdev, |
| 708 | pi->dpm_table_start + |
| 709 | offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable), |
| 710 | &pi->graphics_therm_throttle_enable, |
| 711 | sizeof(u8), pi->sram_end); |
| 712 | |
| 713 | return ret; |
| 714 | } |
| 715 | |
| 716 | static int kv_upload_dpm_settings(struct radeon_device *rdev) |
| 717 | { |
| 718 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 719 | int ret; |
| 720 | |
| 721 | ret = kv_copy_bytes_to_smc(rdev, |
| 722 | pi->dpm_table_start + |
| 723 | offsetof(SMU7_Fusion_DpmTable, GraphicsLevel), |
| 724 | (u8 *)&pi->graphics_level, |
| 725 | sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS, |
| 726 | pi->sram_end); |
| 727 | |
| 728 | if (ret) |
| 729 | return ret; |
| 730 | |
| 731 | ret = kv_copy_bytes_to_smc(rdev, |
| 732 | pi->dpm_table_start + |
| 733 | offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount), |
| 734 | &pi->graphics_dpm_level_count, |
| 735 | sizeof(u8), pi->sram_end); |
| 736 | |
| 737 | return ret; |
| 738 | } |
| 739 | |
| 740 | static u32 kv_get_clock_difference(u32 a, u32 b) |
| 741 | { |
| 742 | return (a >= b) ? a - b : b - a; |
| 743 | } |
| 744 | |
| 745 | static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk) |
| 746 | { |
| 747 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 748 | u32 value; |
| 749 | |
| 750 | if (pi->caps_enable_dfs_bypass) { |
| 751 | if (kv_get_clock_difference(clk, 40000) < 200) |
| 752 | value = 3; |
| 753 | else if (kv_get_clock_difference(clk, 30000) < 200) |
| 754 | value = 2; |
| 755 | else if (kv_get_clock_difference(clk, 20000) < 200) |
| 756 | value = 7; |
| 757 | else if (kv_get_clock_difference(clk, 15000) < 200) |
| 758 | value = 6; |
| 759 | else if (kv_get_clock_difference(clk, 10000) < 200) |
| 760 | value = 8; |
| 761 | else |
| 762 | value = 0; |
| 763 | } else { |
| 764 | value = 0; |
| 765 | } |
| 766 | |
| 767 | return value; |
| 768 | } |
| 769 | |
| 770 | static int kv_populate_uvd_table(struct radeon_device *rdev) |
| 771 | { |
| 772 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 773 | struct radeon_uvd_clock_voltage_dependency_table *table = |
| 774 | &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; |
| 775 | struct atom_clock_dividers dividers; |
| 776 | int ret; |
| 777 | u32 i; |
| 778 | |
| 779 | if (table == NULL || table->count == 0) |
| 780 | return 0; |
| 781 | |
| 782 | pi->uvd_level_count = 0; |
| 783 | for (i = 0; i < table->count; i++) { |
| 784 | if (pi->high_voltage_t && |
| 785 | (pi->high_voltage_t < table->entries[i].v)) |
| 786 | break; |
| 787 | |
| 788 | pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); |
| 789 | pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); |
| 790 | pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); |
| 791 | |
| 792 | pi->uvd_level[i].VClkBypassCntl = |
| 793 | (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk); |
| 794 | pi->uvd_level[i].DClkBypassCntl = |
| 795 | (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk); |
| 796 | |
| 797 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, |
| 798 | table->entries[i].vclk, false, ÷rs); |
| 799 | if (ret) |
| 800 | return ret; |
| 801 | pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; |
| 802 | |
| 803 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, |
| 804 | table->entries[i].dclk, false, ÷rs); |
| 805 | if (ret) |
| 806 | return ret; |
| 807 | pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; |
| 808 | |
| 809 | pi->uvd_level_count++; |
| 810 | } |
| 811 | |
| 812 | ret = kv_copy_bytes_to_smc(rdev, |
| 813 | pi->dpm_table_start + |
| 814 | offsetof(SMU7_Fusion_DpmTable, UvdLevelCount), |
| 815 | (u8 *)&pi->uvd_level_count, |
| 816 | sizeof(u8), pi->sram_end); |
| 817 | if (ret) |
| 818 | return ret; |
| 819 | |
| 820 | pi->uvd_interval = 1; |
| 821 | |
| 822 | ret = kv_copy_bytes_to_smc(rdev, |
| 823 | pi->dpm_table_start + |
| 824 | offsetof(SMU7_Fusion_DpmTable, UVDInterval), |
| 825 | &pi->uvd_interval, |
| 826 | sizeof(u8), pi->sram_end); |
| 827 | if (ret) |
| 828 | return ret; |
| 829 | |
| 830 | ret = kv_copy_bytes_to_smc(rdev, |
| 831 | pi->dpm_table_start + |
| 832 | offsetof(SMU7_Fusion_DpmTable, UvdLevel), |
| 833 | (u8 *)&pi->uvd_level, |
| 834 | sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD, |
| 835 | pi->sram_end); |
| 836 | |
| 837 | return ret; |
| 838 | |
| 839 | } |
| 840 | |
| 841 | static int kv_populate_vce_table(struct radeon_device *rdev) |
| 842 | { |
| 843 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 844 | int ret; |
| 845 | u32 i; |
| 846 | struct radeon_vce_clock_voltage_dependency_table *table = |
| 847 | &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; |
| 848 | struct atom_clock_dividers dividers; |
| 849 | |
| 850 | if (table == NULL || table->count == 0) |
| 851 | return 0; |
| 852 | |
| 853 | pi->vce_level_count = 0; |
| 854 | for (i = 0; i < table->count; i++) { |
| 855 | if (pi->high_voltage_t && |
| 856 | pi->high_voltage_t < table->entries[i].v) |
| 857 | break; |
| 858 | |
| 859 | pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); |
| 860 | pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); |
| 861 | |
| 862 | pi->vce_level[i].ClkBypassCntl = |
| 863 | (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk); |
| 864 | |
| 865 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, |
| 866 | table->entries[i].evclk, false, ÷rs); |
| 867 | if (ret) |
| 868 | return ret; |
| 869 | pi->vce_level[i].Divider = (u8)dividers.post_div; |
| 870 | |
| 871 | pi->vce_level_count++; |
| 872 | } |
| 873 | |
| 874 | ret = kv_copy_bytes_to_smc(rdev, |
| 875 | pi->dpm_table_start + |
| 876 | offsetof(SMU7_Fusion_DpmTable, VceLevelCount), |
| 877 | (u8 *)&pi->vce_level_count, |
| 878 | sizeof(u8), |
| 879 | pi->sram_end); |
| 880 | if (ret) |
| 881 | return ret; |
| 882 | |
| 883 | pi->vce_interval = 1; |
| 884 | |
| 885 | ret = kv_copy_bytes_to_smc(rdev, |
| 886 | pi->dpm_table_start + |
| 887 | offsetof(SMU7_Fusion_DpmTable, VCEInterval), |
| 888 | (u8 *)&pi->vce_interval, |
| 889 | sizeof(u8), |
| 890 | pi->sram_end); |
| 891 | if (ret) |
| 892 | return ret; |
| 893 | |
| 894 | ret = kv_copy_bytes_to_smc(rdev, |
| 895 | pi->dpm_table_start + |
| 896 | offsetof(SMU7_Fusion_DpmTable, VceLevel), |
| 897 | (u8 *)&pi->vce_level, |
| 898 | sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE, |
| 899 | pi->sram_end); |
| 900 | |
| 901 | return ret; |
| 902 | } |
| 903 | |
| 904 | static int kv_populate_samu_table(struct radeon_device *rdev) |
| 905 | { |
| 906 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 907 | struct radeon_clock_voltage_dependency_table *table = |
| 908 | &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; |
| 909 | struct atom_clock_dividers dividers; |
| 910 | int ret; |
| 911 | u32 i; |
| 912 | |
| 913 | if (table == NULL || table->count == 0) |
| 914 | return 0; |
| 915 | |
| 916 | pi->samu_level_count = 0; |
| 917 | for (i = 0; i < table->count; i++) { |
| 918 | if (pi->high_voltage_t && |
| 919 | pi->high_voltage_t < table->entries[i].v) |
| 920 | break; |
| 921 | |
| 922 | pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); |
| 923 | pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); |
| 924 | |
| 925 | pi->samu_level[i].ClkBypassCntl = |
| 926 | (u8)kv_get_clk_bypass(rdev, table->entries[i].clk); |
| 927 | |
| 928 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, |
| 929 | table->entries[i].clk, false, ÷rs); |
| 930 | if (ret) |
| 931 | return ret; |
| 932 | pi->samu_level[i].Divider = (u8)dividers.post_div; |
| 933 | |
| 934 | pi->samu_level_count++; |
| 935 | } |
| 936 | |
| 937 | ret = kv_copy_bytes_to_smc(rdev, |
| 938 | pi->dpm_table_start + |
| 939 | offsetof(SMU7_Fusion_DpmTable, SamuLevelCount), |
| 940 | (u8 *)&pi->samu_level_count, |
| 941 | sizeof(u8), |
| 942 | pi->sram_end); |
| 943 | if (ret) |
| 944 | return ret; |
| 945 | |
| 946 | pi->samu_interval = 1; |
| 947 | |
| 948 | ret = kv_copy_bytes_to_smc(rdev, |
| 949 | pi->dpm_table_start + |
| 950 | offsetof(SMU7_Fusion_DpmTable, SAMUInterval), |
| 951 | (u8 *)&pi->samu_interval, |
| 952 | sizeof(u8), |
| 953 | pi->sram_end); |
| 954 | if (ret) |
| 955 | return ret; |
| 956 | |
| 957 | ret = kv_copy_bytes_to_smc(rdev, |
| 958 | pi->dpm_table_start + |
| 959 | offsetof(SMU7_Fusion_DpmTable, SamuLevel), |
| 960 | (u8 *)&pi->samu_level, |
| 961 | sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU, |
| 962 | pi->sram_end); |
| 963 | if (ret) |
| 964 | return ret; |
| 965 | |
| 966 | return ret; |
| 967 | } |
| 968 | |
| 969 | |
| 970 | static int kv_populate_acp_table(struct radeon_device *rdev) |
| 971 | { |
| 972 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 973 | struct radeon_clock_voltage_dependency_table *table = |
| 974 | &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; |
| 975 | struct atom_clock_dividers dividers; |
| 976 | int ret; |
| 977 | u32 i; |
| 978 | |
| 979 | if (table == NULL || table->count == 0) |
| 980 | return 0; |
| 981 | |
| 982 | pi->acp_level_count = 0; |
| 983 | for (i = 0; i < table->count; i++) { |
| 984 | pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); |
| 985 | pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); |
| 986 | |
| 987 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, |
| 988 | table->entries[i].clk, false, ÷rs); |
| 989 | if (ret) |
| 990 | return ret; |
| 991 | pi->acp_level[i].Divider = (u8)dividers.post_div; |
| 992 | |
| 993 | pi->acp_level_count++; |
| 994 | } |
| 995 | |
| 996 | ret = kv_copy_bytes_to_smc(rdev, |
| 997 | pi->dpm_table_start + |
| 998 | offsetof(SMU7_Fusion_DpmTable, AcpLevelCount), |
| 999 | (u8 *)&pi->acp_level_count, |
| 1000 | sizeof(u8), |
| 1001 | pi->sram_end); |
| 1002 | if (ret) |
| 1003 | return ret; |
| 1004 | |
| 1005 | pi->acp_interval = 1; |
| 1006 | |
| 1007 | ret = kv_copy_bytes_to_smc(rdev, |
| 1008 | pi->dpm_table_start + |
| 1009 | offsetof(SMU7_Fusion_DpmTable, ACPInterval), |
| 1010 | (u8 *)&pi->acp_interval, |
| 1011 | sizeof(u8), |
| 1012 | pi->sram_end); |
| 1013 | if (ret) |
| 1014 | return ret; |
| 1015 | |
| 1016 | ret = kv_copy_bytes_to_smc(rdev, |
| 1017 | pi->dpm_table_start + |
| 1018 | offsetof(SMU7_Fusion_DpmTable, AcpLevel), |
| 1019 | (u8 *)&pi->acp_level, |
| 1020 | sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP, |
| 1021 | pi->sram_end); |
| 1022 | if (ret) |
| 1023 | return ret; |
| 1024 | |
| 1025 | return ret; |
| 1026 | } |
| 1027 | |
| 1028 | static void kv_calculate_dfs_bypass_settings(struct radeon_device *rdev) |
| 1029 | { |
| 1030 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1031 | u32 i; |
| 1032 | struct radeon_clock_voltage_dependency_table *table = |
| 1033 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; |
| 1034 | |
| 1035 | if (table && table->count) { |
| 1036 | for (i = 0; i < pi->graphics_dpm_level_count; i++) { |
| 1037 | if (pi->caps_enable_dfs_bypass) { |
| 1038 | if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200) |
| 1039 | pi->graphics_level[i].ClkBypassCntl = 3; |
| 1040 | else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200) |
| 1041 | pi->graphics_level[i].ClkBypassCntl = 2; |
| 1042 | else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200) |
| 1043 | pi->graphics_level[i].ClkBypassCntl = 7; |
| 1044 | else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200) |
| 1045 | pi->graphics_level[i].ClkBypassCntl = 6; |
| 1046 | else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200) |
| 1047 | pi->graphics_level[i].ClkBypassCntl = 8; |
| 1048 | else |
| 1049 | pi->graphics_level[i].ClkBypassCntl = 0; |
| 1050 | } else { |
| 1051 | pi->graphics_level[i].ClkBypassCntl = 0; |
| 1052 | } |
| 1053 | } |
| 1054 | } else { |
| 1055 | struct sumo_sclk_voltage_mapping_table *table = |
| 1056 | &pi->sys_info.sclk_voltage_mapping_table; |
| 1057 | for (i = 0; i < pi->graphics_dpm_level_count; i++) { |
| 1058 | if (pi->caps_enable_dfs_bypass) { |
| 1059 | if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200) |
| 1060 | pi->graphics_level[i].ClkBypassCntl = 3; |
| 1061 | else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200) |
| 1062 | pi->graphics_level[i].ClkBypassCntl = 2; |
| 1063 | else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200) |
| 1064 | pi->graphics_level[i].ClkBypassCntl = 7; |
| 1065 | else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200) |
| 1066 | pi->graphics_level[i].ClkBypassCntl = 6; |
| 1067 | else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200) |
| 1068 | pi->graphics_level[i].ClkBypassCntl = 8; |
| 1069 | else |
| 1070 | pi->graphics_level[i].ClkBypassCntl = 0; |
| 1071 | } else { |
| 1072 | pi->graphics_level[i].ClkBypassCntl = 0; |
| 1073 | } |
| 1074 | } |
| 1075 | } |
| 1076 | } |
| 1077 | |
| 1078 | static int kv_enable_ulv(struct radeon_device *rdev, bool enable) |
| 1079 | { |
| 1080 | return kv_notify_message_to_smu(rdev, enable ? |
| 1081 | PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV); |
| 1082 | } |
| 1083 | |
| 1084 | static void kv_update_current_ps(struct radeon_device *rdev, |
| 1085 | struct radeon_ps *rps) |
| 1086 | { |
| 1087 | struct kv_ps *new_ps = kv_get_ps(rps); |
| 1088 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1089 | |
| 1090 | pi->current_rps = *rps; |
| 1091 | pi->current_ps = *new_ps; |
| 1092 | pi->current_rps.ps_priv = &pi->current_ps; |
| 1093 | } |
| 1094 | |
| 1095 | static void kv_update_requested_ps(struct radeon_device *rdev, |
| 1096 | struct radeon_ps *rps) |
| 1097 | { |
| 1098 | struct kv_ps *new_ps = kv_get_ps(rps); |
| 1099 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1100 | |
| 1101 | pi->requested_rps = *rps; |
| 1102 | pi->requested_ps = *new_ps; |
| 1103 | pi->requested_rps.ps_priv = &pi->requested_ps; |
| 1104 | } |
| 1105 | |
| 1106 | int kv_dpm_enable(struct radeon_device *rdev) |
| 1107 | { |
| 1108 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1109 | int ret; |
| 1110 | |
| 1111 | ret = kv_process_firmware_header(rdev); |
| 1112 | if (ret) { |
| 1113 | DRM_ERROR("kv_process_firmware_header failed\n"); |
| 1114 | return ret; |
| 1115 | } |
| 1116 | kv_init_fps_limits(rdev); |
| 1117 | kv_init_graphics_levels(rdev); |
| 1118 | ret = kv_program_bootup_state(rdev); |
| 1119 | if (ret) { |
| 1120 | DRM_ERROR("kv_program_bootup_state failed\n"); |
| 1121 | return ret; |
| 1122 | } |
| 1123 | kv_calculate_dfs_bypass_settings(rdev); |
| 1124 | ret = kv_upload_dpm_settings(rdev); |
| 1125 | if (ret) { |
| 1126 | DRM_ERROR("kv_upload_dpm_settings failed\n"); |
| 1127 | return ret; |
| 1128 | } |
| 1129 | ret = kv_populate_uvd_table(rdev); |
| 1130 | if (ret) { |
| 1131 | DRM_ERROR("kv_populate_uvd_table failed\n"); |
| 1132 | return ret; |
| 1133 | } |
| 1134 | ret = kv_populate_vce_table(rdev); |
| 1135 | if (ret) { |
| 1136 | DRM_ERROR("kv_populate_vce_table failed\n"); |
| 1137 | return ret; |
| 1138 | } |
| 1139 | ret = kv_populate_samu_table(rdev); |
| 1140 | if (ret) { |
| 1141 | DRM_ERROR("kv_populate_samu_table failed\n"); |
| 1142 | return ret; |
| 1143 | } |
| 1144 | ret = kv_populate_acp_table(rdev); |
| 1145 | if (ret) { |
| 1146 | DRM_ERROR("kv_populate_acp_table failed\n"); |
| 1147 | return ret; |
| 1148 | } |
| 1149 | kv_program_vc(rdev); |
| 1150 | #if 0 |
| 1151 | kv_initialize_hardware_cac_manager(rdev); |
| 1152 | #endif |
| 1153 | kv_start_am(rdev); |
| 1154 | if (pi->enable_auto_thermal_throttling) { |
| 1155 | ret = kv_enable_auto_thermal_throttling(rdev); |
| 1156 | if (ret) { |
| 1157 | DRM_ERROR("kv_enable_auto_thermal_throttling failed\n"); |
| 1158 | return ret; |
| 1159 | } |
| 1160 | } |
| 1161 | ret = kv_enable_dpm_voltage_scaling(rdev); |
| 1162 | if (ret) { |
| 1163 | DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n"); |
| 1164 | return ret; |
| 1165 | } |
| 1166 | ret = kv_set_dpm_interval(rdev); |
| 1167 | if (ret) { |
| 1168 | DRM_ERROR("kv_set_dpm_interval failed\n"); |
| 1169 | return ret; |
| 1170 | } |
| 1171 | ret = kv_set_dpm_boot_state(rdev); |
| 1172 | if (ret) { |
| 1173 | DRM_ERROR("kv_set_dpm_boot_state failed\n"); |
| 1174 | return ret; |
| 1175 | } |
| 1176 | ret = kv_enable_ulv(rdev, true); |
| 1177 | if (ret) { |
| 1178 | DRM_ERROR("kv_enable_ulv failed\n"); |
| 1179 | return ret; |
| 1180 | } |
| 1181 | kv_start_dpm(rdev); |
| 1182 | ret = kv_enable_didt(rdev, true); |
| 1183 | if (ret) { |
| 1184 | DRM_ERROR("kv_enable_didt failed\n"); |
| 1185 | return ret; |
| 1186 | } |
| 1187 | ret = kv_enable_smc_cac(rdev, true); |
| 1188 | if (ret) { |
| 1189 | DRM_ERROR("kv_enable_smc_cac failed\n"); |
| 1190 | return ret; |
| 1191 | } |
| 1192 | |
| 1193 | if (rdev->irq.installed && |
| 1194 | r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { |
| 1195 | ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); |
| 1196 | if (ret) { |
| 1197 | DRM_ERROR("kv_set_thermal_temperature_range failed\n"); |
| 1198 | return ret; |
| 1199 | } |
| 1200 | rdev->irq.dpm_thermal = true; |
| 1201 | radeon_irq_set(rdev); |
| 1202 | } |
| 1203 | |
| 1204 | /* powerdown unused blocks for now */ |
| 1205 | kv_dpm_powergate_acp(rdev, true); |
| 1206 | kv_dpm_powergate_samu(rdev, true); |
| 1207 | kv_dpm_powergate_vce(rdev, true); |
Alex Deucher | 77df508 | 2013-08-09 10:02:40 -0400 | [diff] [blame^] | 1208 | kv_dpm_powergate_uvd(rdev, true); |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 1209 | |
| 1210 | kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); |
| 1211 | |
| 1212 | return ret; |
| 1213 | } |
| 1214 | |
| 1215 | void kv_dpm_disable(struct radeon_device *rdev) |
| 1216 | { |
| 1217 | kv_enable_smc_cac(rdev, false); |
| 1218 | kv_enable_didt(rdev, false); |
| 1219 | kv_clear_vc(rdev); |
| 1220 | kv_stop_dpm(rdev); |
| 1221 | kv_enable_ulv(rdev, false); |
| 1222 | kv_reset_am(rdev); |
| 1223 | |
| 1224 | kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); |
| 1225 | } |
| 1226 | |
| 1227 | #if 0 |
| 1228 | static int kv_write_smc_soft_register(struct radeon_device *rdev, |
| 1229 | u16 reg_offset, u32 value) |
| 1230 | { |
| 1231 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1232 | |
| 1233 | return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset, |
| 1234 | (u8 *)&value, sizeof(u16), pi->sram_end); |
| 1235 | } |
| 1236 | |
| 1237 | static int kv_read_smc_soft_register(struct radeon_device *rdev, |
| 1238 | u16 reg_offset, u32 *value) |
| 1239 | { |
| 1240 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1241 | |
| 1242 | return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset, |
| 1243 | value, pi->sram_end); |
| 1244 | } |
| 1245 | #endif |
| 1246 | |
| 1247 | static void kv_init_sclk_t(struct radeon_device *rdev) |
| 1248 | { |
| 1249 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1250 | |
| 1251 | pi->low_sclk_interrupt_t = 0; |
| 1252 | } |
| 1253 | |
| 1254 | static int kv_init_fps_limits(struct radeon_device *rdev) |
| 1255 | { |
| 1256 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1257 | int ret = 0; |
| 1258 | |
| 1259 | if (pi->caps_fps) { |
| 1260 | u16 tmp; |
| 1261 | |
| 1262 | tmp = 45; |
| 1263 | pi->fps_high_t = cpu_to_be16(tmp); |
| 1264 | ret = kv_copy_bytes_to_smc(rdev, |
| 1265 | pi->dpm_table_start + |
| 1266 | offsetof(SMU7_Fusion_DpmTable, FpsHighT), |
| 1267 | (u8 *)&pi->fps_high_t, |
| 1268 | sizeof(u16), pi->sram_end); |
| 1269 | |
| 1270 | tmp = 30; |
| 1271 | pi->fps_low_t = cpu_to_be16(tmp); |
| 1272 | |
| 1273 | ret = kv_copy_bytes_to_smc(rdev, |
| 1274 | pi->dpm_table_start + |
| 1275 | offsetof(SMU7_Fusion_DpmTable, FpsLowT), |
| 1276 | (u8 *)&pi->fps_low_t, |
| 1277 | sizeof(u16), pi->sram_end); |
| 1278 | |
| 1279 | } |
| 1280 | return ret; |
| 1281 | } |
| 1282 | |
| 1283 | static void kv_init_powergate_state(struct radeon_device *rdev) |
| 1284 | { |
| 1285 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1286 | |
| 1287 | pi->uvd_power_gated = false; |
| 1288 | pi->vce_power_gated = false; |
| 1289 | pi->samu_power_gated = false; |
| 1290 | pi->acp_power_gated = false; |
| 1291 | |
| 1292 | } |
| 1293 | |
| 1294 | static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable) |
| 1295 | { |
| 1296 | return kv_notify_message_to_smu(rdev, enable ? |
| 1297 | PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable); |
| 1298 | } |
| 1299 | |
| 1300 | #if 0 |
| 1301 | static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable) |
| 1302 | { |
| 1303 | return kv_notify_message_to_smu(rdev, enable ? |
| 1304 | PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable); |
| 1305 | } |
| 1306 | #endif |
| 1307 | |
| 1308 | static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable) |
| 1309 | { |
| 1310 | return kv_notify_message_to_smu(rdev, enable ? |
| 1311 | PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable); |
| 1312 | } |
| 1313 | |
| 1314 | static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable) |
| 1315 | { |
| 1316 | return kv_notify_message_to_smu(rdev, enable ? |
| 1317 | PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable); |
| 1318 | } |
| 1319 | |
| 1320 | static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate) |
| 1321 | { |
| 1322 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1323 | struct radeon_uvd_clock_voltage_dependency_table *table = |
| 1324 | &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; |
| 1325 | int ret; |
| 1326 | |
| 1327 | if (!gate) { |
| 1328 | if (!pi->caps_uvd_dpm || table->count || pi->caps_stable_p_state) |
| 1329 | pi->uvd_boot_level = table->count - 1; |
| 1330 | else |
| 1331 | pi->uvd_boot_level = 0; |
| 1332 | |
| 1333 | ret = kv_copy_bytes_to_smc(rdev, |
| 1334 | pi->dpm_table_start + |
| 1335 | offsetof(SMU7_Fusion_DpmTable, UvdBootLevel), |
| 1336 | (uint8_t *)&pi->uvd_boot_level, |
| 1337 | sizeof(u8), pi->sram_end); |
| 1338 | if (ret) |
| 1339 | return ret; |
| 1340 | |
| 1341 | if (!pi->caps_uvd_dpm || |
| 1342 | pi->caps_stable_p_state) |
| 1343 | kv_send_msg_to_smc_with_parameter(rdev, |
| 1344 | PPSMC_MSG_UVDDPM_SetEnabledMask, |
| 1345 | (1 << pi->uvd_boot_level)); |
| 1346 | } |
| 1347 | |
| 1348 | return kv_enable_uvd_dpm(rdev, !gate); |
| 1349 | } |
| 1350 | |
| 1351 | #if 0 |
| 1352 | static u8 kv_get_vce_boot_level(struct radeon_device *rdev) |
| 1353 | { |
| 1354 | u8 i; |
| 1355 | struct radeon_vce_clock_voltage_dependency_table *table = |
| 1356 | &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; |
| 1357 | |
| 1358 | for (i = 0; i < table->count; i++) { |
| 1359 | if (table->entries[i].evclk >= 0) /* XXX */ |
| 1360 | break; |
| 1361 | } |
| 1362 | |
| 1363 | return i; |
| 1364 | } |
| 1365 | |
| 1366 | static int kv_update_vce_dpm(struct radeon_device *rdev, |
| 1367 | struct radeon_ps *radeon_new_state, |
| 1368 | struct radeon_ps *radeon_current_state) |
| 1369 | { |
| 1370 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1371 | struct radeon_vce_clock_voltage_dependency_table *table = |
| 1372 | &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; |
| 1373 | int ret; |
| 1374 | |
| 1375 | if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) { |
| 1376 | if (pi->caps_stable_p_state) |
| 1377 | pi->vce_boot_level = table->count - 1; |
| 1378 | else |
| 1379 | pi->vce_boot_level = kv_get_vce_boot_level(rdev); |
| 1380 | |
| 1381 | ret = kv_copy_bytes_to_smc(rdev, |
| 1382 | pi->dpm_table_start + |
| 1383 | offsetof(SMU7_Fusion_DpmTable, VceBootLevel), |
| 1384 | (u8 *)&pi->vce_boot_level, |
| 1385 | sizeof(u8), |
| 1386 | pi->sram_end); |
| 1387 | if (ret) |
| 1388 | return ret; |
| 1389 | |
| 1390 | if (pi->caps_stable_p_state) |
| 1391 | kv_send_msg_to_smc_with_parameter(rdev, |
| 1392 | PPSMC_MSG_VCEDPM_SetEnabledMask, |
| 1393 | (1 << pi->vce_boot_level)); |
| 1394 | |
| 1395 | kv_enable_vce_dpm(rdev, true); |
| 1396 | } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) { |
| 1397 | kv_enable_vce_dpm(rdev, false); |
| 1398 | } |
| 1399 | |
| 1400 | return 0; |
| 1401 | } |
| 1402 | #endif |
| 1403 | |
| 1404 | static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate) |
| 1405 | { |
| 1406 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1407 | struct radeon_clock_voltage_dependency_table *table = |
| 1408 | &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; |
| 1409 | int ret; |
| 1410 | |
| 1411 | if (!gate) { |
| 1412 | if (pi->caps_stable_p_state) |
| 1413 | pi->samu_boot_level = table->count - 1; |
| 1414 | else |
| 1415 | pi->samu_boot_level = 0; |
| 1416 | |
| 1417 | ret = kv_copy_bytes_to_smc(rdev, |
| 1418 | pi->dpm_table_start + |
| 1419 | offsetof(SMU7_Fusion_DpmTable, SamuBootLevel), |
| 1420 | (u8 *)&pi->samu_boot_level, |
| 1421 | sizeof(u8), |
| 1422 | pi->sram_end); |
| 1423 | if (ret) |
| 1424 | return ret; |
| 1425 | |
| 1426 | if (pi->caps_stable_p_state) |
| 1427 | kv_send_msg_to_smc_with_parameter(rdev, |
| 1428 | PPSMC_MSG_SAMUDPM_SetEnabledMask, |
| 1429 | (1 << pi->samu_boot_level)); |
| 1430 | } |
| 1431 | |
| 1432 | return kv_enable_samu_dpm(rdev, !gate); |
| 1433 | } |
| 1434 | |
| 1435 | static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate) |
| 1436 | { |
| 1437 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1438 | struct radeon_clock_voltage_dependency_table *table = |
| 1439 | &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; |
| 1440 | int ret; |
| 1441 | |
| 1442 | if (!gate) { |
| 1443 | if (pi->caps_stable_p_state) |
| 1444 | pi->acp_boot_level = table->count - 1; |
| 1445 | else |
| 1446 | pi->acp_boot_level = 0; |
| 1447 | |
| 1448 | ret = kv_copy_bytes_to_smc(rdev, |
| 1449 | pi->dpm_table_start + |
| 1450 | offsetof(SMU7_Fusion_DpmTable, AcpBootLevel), |
| 1451 | (u8 *)&pi->acp_boot_level, |
| 1452 | sizeof(u8), |
| 1453 | pi->sram_end); |
| 1454 | if (ret) |
| 1455 | return ret; |
| 1456 | |
| 1457 | if (pi->caps_stable_p_state) |
| 1458 | kv_send_msg_to_smc_with_parameter(rdev, |
| 1459 | PPSMC_MSG_ACPDPM_SetEnabledMask, |
| 1460 | (1 << pi->acp_boot_level)); |
| 1461 | } |
| 1462 | |
| 1463 | return kv_enable_acp_dpm(rdev, !gate); |
| 1464 | } |
| 1465 | |
Alex Deucher | 77df508 | 2013-08-09 10:02:40 -0400 | [diff] [blame^] | 1466 | void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate) |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 1467 | { |
| 1468 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1469 | |
| 1470 | if (pi->uvd_power_gated == gate) |
| 1471 | return; |
| 1472 | |
| 1473 | pi->uvd_power_gated = gate; |
| 1474 | |
| 1475 | if (gate) { |
Alex Deucher | 77df508 | 2013-08-09 10:02:40 -0400 | [diff] [blame^] | 1476 | r600_do_uvd_stop(rdev); |
| 1477 | cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, false); |
| 1478 | kv_update_uvd_dpm(rdev, gate); |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 1479 | if (pi->caps_uvd_pg) |
| 1480 | kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerOFF); |
| 1481 | } else { |
| 1482 | if (pi->caps_uvd_pg) |
| 1483 | kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerON); |
Alex Deucher | 77df508 | 2013-08-09 10:02:40 -0400 | [diff] [blame^] | 1484 | cik_uvd_resume(rdev); |
| 1485 | r600_uvd_init(rdev, false); |
| 1486 | cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, true); |
| 1487 | kv_update_uvd_dpm(rdev, gate); |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 1488 | } |
| 1489 | } |
| 1490 | |
| 1491 | static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate) |
| 1492 | { |
| 1493 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1494 | |
| 1495 | if (pi->vce_power_gated == gate) |
| 1496 | return; |
| 1497 | |
| 1498 | pi->vce_power_gated = gate; |
| 1499 | |
| 1500 | if (gate) { |
| 1501 | if (pi->caps_vce_pg) |
| 1502 | kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF); |
| 1503 | } else { |
| 1504 | if (pi->caps_vce_pg) |
| 1505 | kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON); |
| 1506 | } |
| 1507 | } |
| 1508 | |
| 1509 | static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate) |
| 1510 | { |
| 1511 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1512 | |
| 1513 | if (pi->samu_power_gated == gate) |
| 1514 | return; |
| 1515 | |
| 1516 | pi->samu_power_gated = gate; |
| 1517 | |
| 1518 | if (gate) { |
| 1519 | kv_update_samu_dpm(rdev, true); |
| 1520 | if (pi->caps_samu_pg) |
| 1521 | kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerOFF); |
| 1522 | } else { |
| 1523 | if (pi->caps_samu_pg) |
| 1524 | kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerON); |
| 1525 | kv_update_samu_dpm(rdev, false); |
| 1526 | } |
| 1527 | } |
| 1528 | |
| 1529 | static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate) |
| 1530 | { |
| 1531 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1532 | |
| 1533 | if (pi->acp_power_gated == gate) |
| 1534 | return; |
| 1535 | |
| 1536 | if (rdev->family == CHIP_KABINI) |
| 1537 | return; |
| 1538 | |
| 1539 | pi->acp_power_gated = gate; |
| 1540 | |
| 1541 | if (gate) { |
| 1542 | kv_update_acp_dpm(rdev, true); |
| 1543 | if (pi->caps_acp_pg) |
| 1544 | kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerOFF); |
| 1545 | } else { |
| 1546 | if (pi->caps_acp_pg) |
| 1547 | kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerON); |
| 1548 | kv_update_acp_dpm(rdev, false); |
| 1549 | } |
| 1550 | } |
| 1551 | |
| 1552 | static void kv_set_valid_clock_range(struct radeon_device *rdev, |
| 1553 | struct radeon_ps *new_rps) |
| 1554 | { |
| 1555 | struct kv_ps *new_ps = kv_get_ps(new_rps); |
| 1556 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1557 | u32 i; |
| 1558 | struct radeon_clock_voltage_dependency_table *table = |
| 1559 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; |
| 1560 | |
| 1561 | if (table && table->count) { |
| 1562 | for (i = 0; i < pi->graphics_dpm_level_count; i++) { |
| 1563 | if ((table->entries[i].clk >= new_ps->levels[0].sclk) || |
| 1564 | (i == (pi->graphics_dpm_level_count - 1))) { |
| 1565 | pi->lowest_valid = i; |
| 1566 | break; |
| 1567 | } |
| 1568 | } |
| 1569 | |
| 1570 | for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) { |
| 1571 | if ((table->entries[i].clk <= new_ps->levels[new_ps->num_levels -1].sclk) || |
| 1572 | (i == 0)) { |
| 1573 | pi->highest_valid = i; |
| 1574 | break; |
| 1575 | } |
| 1576 | } |
| 1577 | |
| 1578 | if (pi->lowest_valid > pi->highest_valid) { |
| 1579 | if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > |
| 1580 | (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) |
| 1581 | pi->highest_valid = pi->lowest_valid; |
| 1582 | else |
| 1583 | pi->lowest_valid = pi->highest_valid; |
| 1584 | } |
| 1585 | } else { |
| 1586 | struct sumo_sclk_voltage_mapping_table *table = |
| 1587 | &pi->sys_info.sclk_voltage_mapping_table; |
| 1588 | |
| 1589 | for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { |
| 1590 | if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || |
| 1591 | i == (int)(pi->graphics_dpm_level_count - 1)) { |
| 1592 | pi->lowest_valid = i; |
| 1593 | break; |
| 1594 | } |
| 1595 | } |
| 1596 | |
| 1597 | for (i = pi->graphics_dpm_level_count - 1; i >= 0; i--) { |
| 1598 | if (table->entries[i].sclk_frequency <= |
| 1599 | new_ps->levels[new_ps->num_levels - 1].sclk || |
| 1600 | i == 0) { |
| 1601 | pi->highest_valid = i; |
| 1602 | break; |
| 1603 | } |
| 1604 | } |
| 1605 | |
| 1606 | if (pi->lowest_valid > pi->highest_valid) { |
| 1607 | if ((new_ps->levels[0].sclk - |
| 1608 | table->entries[pi->highest_valid].sclk_frequency) > |
| 1609 | (table->entries[pi->lowest_valid].sclk_frequency - |
| 1610 | new_ps->levels[new_ps->num_levels -1].sclk)) |
| 1611 | pi->highest_valid = pi->lowest_valid; |
| 1612 | else |
| 1613 | pi->lowest_valid = pi->highest_valid; |
| 1614 | } |
| 1615 | } |
| 1616 | } |
| 1617 | |
| 1618 | static int kv_update_dfs_bypass_settings(struct radeon_device *rdev, |
| 1619 | struct radeon_ps *new_rps) |
| 1620 | { |
| 1621 | struct kv_ps *new_ps = kv_get_ps(new_rps); |
| 1622 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1623 | int ret = 0; |
| 1624 | u8 clk_bypass_cntl; |
| 1625 | |
| 1626 | if (pi->caps_enable_dfs_bypass) { |
| 1627 | clk_bypass_cntl = new_ps->need_dfs_bypass ? |
| 1628 | pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; |
| 1629 | ret = kv_copy_bytes_to_smc(rdev, |
| 1630 | (pi->dpm_table_start + |
| 1631 | offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) + |
| 1632 | (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + |
| 1633 | offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)), |
| 1634 | &clk_bypass_cntl, |
| 1635 | sizeof(u8), pi->sram_end); |
| 1636 | } |
| 1637 | |
| 1638 | return ret; |
| 1639 | } |
| 1640 | |
| 1641 | static int kv_enable_nb_dpm(struct radeon_device *rdev) |
| 1642 | { |
| 1643 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1644 | int ret = 0; |
| 1645 | |
| 1646 | if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { |
| 1647 | ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable); |
| 1648 | if (ret == 0) |
| 1649 | pi->nb_dpm_enabled = true; |
| 1650 | } |
| 1651 | |
| 1652 | return ret; |
| 1653 | } |
| 1654 | |
Alex Deucher | 2b4c802 | 2013-07-18 16:48:46 -0400 | [diff] [blame] | 1655 | int kv_dpm_force_performance_level(struct radeon_device *rdev, |
| 1656 | enum radeon_dpm_forced_level level) |
| 1657 | { |
| 1658 | int ret; |
| 1659 | |
| 1660 | if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { |
| 1661 | ret = kv_force_dpm_highest(rdev); |
| 1662 | if (ret) |
| 1663 | return ret; |
| 1664 | } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { |
| 1665 | ret = kv_force_dpm_lowest(rdev); |
| 1666 | if (ret) |
| 1667 | return ret; |
| 1668 | } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { |
| 1669 | ret = kv_unforce_levels(rdev); |
| 1670 | if (ret) |
| 1671 | return ret; |
| 1672 | } |
| 1673 | |
| 1674 | rdev->pm.dpm.forced_level = level; |
| 1675 | |
| 1676 | return 0; |
| 1677 | } |
| 1678 | |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 1679 | int kv_dpm_pre_set_power_state(struct radeon_device *rdev) |
| 1680 | { |
| 1681 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1682 | struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; |
| 1683 | struct radeon_ps *new_ps = &requested_ps; |
| 1684 | |
| 1685 | kv_update_requested_ps(rdev, new_ps); |
| 1686 | |
| 1687 | kv_apply_state_adjust_rules(rdev, |
| 1688 | &pi->requested_rps, |
| 1689 | &pi->current_rps); |
| 1690 | |
| 1691 | return 0; |
| 1692 | } |
| 1693 | |
| 1694 | int kv_dpm_set_power_state(struct radeon_device *rdev) |
| 1695 | { |
| 1696 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1697 | struct radeon_ps *new_ps = &pi->requested_rps; |
| 1698 | /*struct radeon_ps *old_ps = &pi->current_rps;*/ |
| 1699 | int ret; |
| 1700 | |
| 1701 | if (rdev->family == CHIP_KABINI) { |
| 1702 | if (pi->enable_dpm) { |
| 1703 | kv_set_valid_clock_range(rdev, new_ps); |
| 1704 | kv_update_dfs_bypass_settings(rdev, new_ps); |
| 1705 | ret = kv_calculate_ds_divider(rdev); |
| 1706 | if (ret) { |
| 1707 | DRM_ERROR("kv_calculate_ds_divider failed\n"); |
| 1708 | return ret; |
| 1709 | } |
| 1710 | kv_calculate_nbps_level_settings(rdev); |
| 1711 | kv_calculate_dpm_settings(rdev); |
| 1712 | kv_force_lowest_valid(rdev); |
| 1713 | kv_enable_new_levels(rdev); |
| 1714 | kv_upload_dpm_settings(rdev); |
| 1715 | kv_program_nbps_index_settings(rdev, new_ps); |
| 1716 | kv_unforce_levels(rdev); |
| 1717 | kv_set_enabled_levels(rdev); |
| 1718 | kv_force_lowest_valid(rdev); |
| 1719 | kv_unforce_levels(rdev); |
| 1720 | #if 0 |
| 1721 | ret = kv_update_vce_dpm(rdev, new_ps, old_ps); |
| 1722 | if (ret) { |
| 1723 | DRM_ERROR("kv_update_vce_dpm failed\n"); |
| 1724 | return ret; |
| 1725 | } |
| 1726 | #endif |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 1727 | kv_update_sclk_t(rdev); |
| 1728 | } |
| 1729 | } else { |
| 1730 | if (pi->enable_dpm) { |
| 1731 | kv_set_valid_clock_range(rdev, new_ps); |
| 1732 | kv_update_dfs_bypass_settings(rdev, new_ps); |
| 1733 | ret = kv_calculate_ds_divider(rdev); |
| 1734 | if (ret) { |
| 1735 | DRM_ERROR("kv_calculate_ds_divider failed\n"); |
| 1736 | return ret; |
| 1737 | } |
| 1738 | kv_calculate_nbps_level_settings(rdev); |
| 1739 | kv_calculate_dpm_settings(rdev); |
| 1740 | kv_freeze_sclk_dpm(rdev, true); |
| 1741 | kv_upload_dpm_settings(rdev); |
| 1742 | kv_program_nbps_index_settings(rdev, new_ps); |
| 1743 | kv_freeze_sclk_dpm(rdev, false); |
| 1744 | kv_set_enabled_levels(rdev); |
| 1745 | #if 0 |
| 1746 | ret = kv_update_vce_dpm(rdev, new_ps, old_ps); |
| 1747 | if (ret) { |
| 1748 | DRM_ERROR("kv_update_vce_dpm failed\n"); |
| 1749 | return ret; |
| 1750 | } |
| 1751 | #endif |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 1752 | kv_update_sclk_t(rdev); |
| 1753 | kv_enable_nb_dpm(rdev); |
| 1754 | } |
| 1755 | } |
Alex Deucher | 2b4c802 | 2013-07-18 16:48:46 -0400 | [diff] [blame] | 1756 | rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 1757 | return 0; |
| 1758 | } |
| 1759 | |
| 1760 | void kv_dpm_post_set_power_state(struct radeon_device *rdev) |
| 1761 | { |
| 1762 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1763 | struct radeon_ps *new_ps = &pi->requested_rps; |
| 1764 | |
| 1765 | kv_update_current_ps(rdev, new_ps); |
| 1766 | } |
| 1767 | |
| 1768 | void kv_dpm_setup_asic(struct radeon_device *rdev) |
| 1769 | { |
| 1770 | sumo_take_smu_control(rdev, true); |
| 1771 | kv_init_powergate_state(rdev); |
| 1772 | kv_init_sclk_t(rdev); |
| 1773 | } |
| 1774 | |
| 1775 | void kv_dpm_reset_asic(struct radeon_device *rdev) |
| 1776 | { |
| 1777 | kv_force_lowest_valid(rdev); |
| 1778 | kv_init_graphics_levels(rdev); |
| 1779 | kv_program_bootup_state(rdev); |
| 1780 | kv_upload_dpm_settings(rdev); |
| 1781 | kv_force_lowest_valid(rdev); |
| 1782 | kv_unforce_levels(rdev); |
| 1783 | } |
| 1784 | |
| 1785 | //XXX use sumo_dpm_display_configuration_changed |
| 1786 | |
| 1787 | static void kv_construct_max_power_limits_table(struct radeon_device *rdev, |
| 1788 | struct radeon_clock_and_voltage_limits *table) |
| 1789 | { |
| 1790 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1791 | |
| 1792 | if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { |
| 1793 | int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; |
| 1794 | table->sclk = |
| 1795 | pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; |
| 1796 | table->vddc = |
| 1797 | kv_convert_2bit_index_to_voltage(rdev, |
| 1798 | pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); |
| 1799 | } |
| 1800 | |
| 1801 | table->mclk = pi->sys_info.nbp_memory_clock[0]; |
| 1802 | } |
| 1803 | |
| 1804 | static void kv_patch_voltage_values(struct radeon_device *rdev) |
| 1805 | { |
| 1806 | int i; |
| 1807 | struct radeon_uvd_clock_voltage_dependency_table *table = |
| 1808 | &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; |
| 1809 | |
| 1810 | if (table->count) { |
| 1811 | for (i = 0; i < table->count; i++) |
| 1812 | table->entries[i].v = |
| 1813 | kv_convert_8bit_index_to_voltage(rdev, |
| 1814 | table->entries[i].v); |
| 1815 | } |
| 1816 | |
| 1817 | } |
| 1818 | |
| 1819 | static void kv_construct_boot_state(struct radeon_device *rdev) |
| 1820 | { |
| 1821 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1822 | |
| 1823 | pi->boot_pl.sclk = pi->sys_info.bootup_sclk; |
| 1824 | pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; |
| 1825 | pi->boot_pl.ds_divider_index = 0; |
| 1826 | pi->boot_pl.ss_divider_index = 0; |
| 1827 | pi->boot_pl.allow_gnb_slow = 1; |
| 1828 | pi->boot_pl.force_nbp_state = 0; |
| 1829 | pi->boot_pl.display_wm = 0; |
| 1830 | pi->boot_pl.vce_wm = 0; |
| 1831 | } |
| 1832 | |
Alex Deucher | 2b4c802 | 2013-07-18 16:48:46 -0400 | [diff] [blame] | 1833 | static int kv_force_dpm_highest(struct radeon_device *rdev) |
| 1834 | { |
| 1835 | int ret; |
| 1836 | u32 enable_mask, i; |
| 1837 | |
| 1838 | ret = kv_dpm_get_enable_mask(rdev, &enable_mask); |
| 1839 | if (ret) |
| 1840 | return ret; |
| 1841 | |
| 1842 | for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i >= 0; i--) { |
| 1843 | if (enable_mask & (1 << i)) |
| 1844 | break; |
| 1845 | } |
| 1846 | |
| 1847 | return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i); |
| 1848 | } |
| 1849 | |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 1850 | static int kv_force_dpm_lowest(struct radeon_device *rdev) |
| 1851 | { |
| 1852 | int ret; |
| 1853 | u32 enable_mask, i; |
| 1854 | |
| 1855 | ret = kv_dpm_get_enable_mask(rdev, &enable_mask); |
| 1856 | if (ret) |
| 1857 | return ret; |
| 1858 | |
| 1859 | for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) { |
| 1860 | if (enable_mask & (1 << i)) |
| 1861 | break; |
| 1862 | } |
| 1863 | |
| 1864 | return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i); |
| 1865 | } |
| 1866 | |
| 1867 | static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev, |
| 1868 | u32 sclk, u32 min_sclk_in_sr) |
| 1869 | { |
| 1870 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1871 | u32 i; |
| 1872 | u32 temp; |
| 1873 | u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ? |
| 1874 | min_sclk_in_sr : KV_MINIMUM_ENGINE_CLOCK; |
| 1875 | |
| 1876 | if (sclk < min) |
| 1877 | return 0; |
| 1878 | |
| 1879 | if (!pi->caps_sclk_ds) |
| 1880 | return 0; |
| 1881 | |
| 1882 | for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i <= 0; i--) { |
| 1883 | temp = sclk / sumo_get_sleep_divider_from_id(i); |
| 1884 | if ((temp >= min) || (i == 0)) |
| 1885 | break; |
| 1886 | } |
| 1887 | |
| 1888 | return (u8)i; |
| 1889 | } |
| 1890 | |
| 1891 | static int kv_get_high_voltage_limit(struct radeon_device *rdev, int *limit) |
| 1892 | { |
| 1893 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1894 | struct radeon_clock_voltage_dependency_table *table = |
| 1895 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; |
| 1896 | int i; |
| 1897 | |
| 1898 | if (table && table->count) { |
| 1899 | for (i = table->count - 1; i >= 0; i--) { |
| 1900 | if (pi->high_voltage_t && |
| 1901 | (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <= |
| 1902 | pi->high_voltage_t)) { |
| 1903 | *limit = i; |
| 1904 | return 0; |
| 1905 | } |
| 1906 | } |
| 1907 | } else { |
| 1908 | struct sumo_sclk_voltage_mapping_table *table = |
| 1909 | &pi->sys_info.sclk_voltage_mapping_table; |
| 1910 | |
| 1911 | for (i = table->num_max_dpm_entries - 1; i >= 0; i--) { |
| 1912 | if (pi->high_voltage_t && |
| 1913 | (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <= |
| 1914 | pi->high_voltage_t)) { |
| 1915 | *limit = i; |
| 1916 | return 0; |
| 1917 | } |
| 1918 | } |
| 1919 | } |
| 1920 | |
| 1921 | *limit = 0; |
| 1922 | return 0; |
| 1923 | } |
| 1924 | |
| 1925 | static void kv_apply_state_adjust_rules(struct radeon_device *rdev, |
| 1926 | struct radeon_ps *new_rps, |
| 1927 | struct radeon_ps *old_rps) |
| 1928 | { |
| 1929 | struct kv_ps *ps = kv_get_ps(new_rps); |
| 1930 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 1931 | u32 min_sclk = 10000; /* ??? */ |
| 1932 | u32 sclk, mclk = 0; |
| 1933 | int i, limit; |
| 1934 | bool force_high; |
| 1935 | struct radeon_clock_voltage_dependency_table *table = |
| 1936 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; |
| 1937 | u32 stable_p_state_sclk = 0; |
| 1938 | struct radeon_clock_and_voltage_limits *max_limits = |
| 1939 | &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
| 1940 | |
| 1941 | mclk = max_limits->mclk; |
| 1942 | sclk = min_sclk; |
| 1943 | |
| 1944 | if (pi->caps_stable_p_state) { |
| 1945 | stable_p_state_sclk = (max_limits->sclk * 75) / 100; |
| 1946 | |
| 1947 | for (i = table->count - 1; i >= 0; i++) { |
| 1948 | if (stable_p_state_sclk >= table->entries[i].clk) { |
| 1949 | stable_p_state_sclk = table->entries[i].clk; |
| 1950 | break; |
| 1951 | } |
| 1952 | } |
| 1953 | |
| 1954 | if (i > 0) |
| 1955 | stable_p_state_sclk = table->entries[0].clk; |
| 1956 | |
| 1957 | sclk = stable_p_state_sclk; |
| 1958 | } |
| 1959 | |
| 1960 | ps->need_dfs_bypass = true; |
| 1961 | |
| 1962 | for (i = 0; i < ps->num_levels; i++) { |
| 1963 | if (ps->levels[i].sclk < sclk) |
| 1964 | ps->levels[i].sclk = sclk; |
| 1965 | } |
| 1966 | |
| 1967 | if (table && table->count) { |
| 1968 | for (i = 0; i < ps->num_levels; i++) { |
| 1969 | if (pi->high_voltage_t && |
| 1970 | (pi->high_voltage_t < |
| 1971 | kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) { |
| 1972 | kv_get_high_voltage_limit(rdev, &limit); |
| 1973 | ps->levels[i].sclk = table->entries[limit].clk; |
| 1974 | } |
| 1975 | } |
| 1976 | } else { |
| 1977 | struct sumo_sclk_voltage_mapping_table *table = |
| 1978 | &pi->sys_info.sclk_voltage_mapping_table; |
| 1979 | |
| 1980 | for (i = 0; i < ps->num_levels; i++) { |
| 1981 | if (pi->high_voltage_t && |
| 1982 | (pi->high_voltage_t < |
| 1983 | kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) { |
| 1984 | kv_get_high_voltage_limit(rdev, &limit); |
| 1985 | ps->levels[i].sclk = table->entries[limit].sclk_frequency; |
| 1986 | } |
| 1987 | } |
| 1988 | } |
| 1989 | |
| 1990 | if (pi->caps_stable_p_state) { |
| 1991 | for (i = 0; i < ps->num_levels; i++) { |
| 1992 | ps->levels[i].sclk = stable_p_state_sclk; |
| 1993 | } |
| 1994 | } |
| 1995 | |
| 1996 | pi->video_start = new_rps->dclk || new_rps->vclk; |
| 1997 | |
| 1998 | if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == |
| 1999 | ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) |
| 2000 | pi->battery_state = true; |
| 2001 | else |
| 2002 | pi->battery_state = false; |
| 2003 | |
| 2004 | if (rdev->family == CHIP_KABINI) { |
| 2005 | ps->dpm0_pg_nb_ps_lo = 0x1; |
| 2006 | ps->dpm0_pg_nb_ps_hi = 0x0; |
| 2007 | ps->dpmx_nb_ps_lo = 0x1; |
| 2008 | ps->dpmx_nb_ps_hi = 0x0; |
| 2009 | } else { |
| 2010 | ps->dpm0_pg_nb_ps_lo = 0x1; |
| 2011 | ps->dpm0_pg_nb_ps_hi = 0x0; |
| 2012 | ps->dpmx_nb_ps_lo = 0x2; |
| 2013 | ps->dpmx_nb_ps_hi = 0x1; |
| 2014 | |
| 2015 | if (pi->sys_info.nb_dpm_enable && pi->battery_state) { |
| 2016 | force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || |
| 2017 | pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) || |
| 2018 | pi->disable_nb_ps3_in_battery; |
| 2019 | ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3; |
| 2020 | ps->dpm0_pg_nb_ps_hi = 0x2; |
| 2021 | ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3; |
| 2022 | ps->dpmx_nb_ps_hi = 0x2; |
| 2023 | } |
| 2024 | } |
| 2025 | } |
| 2026 | |
| 2027 | static void kv_dpm_power_level_enabled_for_throttle(struct radeon_device *rdev, |
| 2028 | u32 index, bool enable) |
| 2029 | { |
| 2030 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 2031 | |
| 2032 | pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; |
| 2033 | } |
| 2034 | |
| 2035 | static int kv_calculate_ds_divider(struct radeon_device *rdev) |
| 2036 | { |
| 2037 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 2038 | u32 sclk_in_sr = 10000; /* ??? */ |
| 2039 | u32 i; |
| 2040 | |
| 2041 | if (pi->lowest_valid > pi->highest_valid) |
| 2042 | return -EINVAL; |
| 2043 | |
| 2044 | for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { |
| 2045 | pi->graphics_level[i].DeepSleepDivId = |
| 2046 | kv_get_sleep_divider_id_from_clock(rdev, |
| 2047 | be32_to_cpu(pi->graphics_level[i].SclkFrequency), |
| 2048 | sclk_in_sr); |
| 2049 | } |
| 2050 | return 0; |
| 2051 | } |
| 2052 | |
| 2053 | static int kv_calculate_nbps_level_settings(struct radeon_device *rdev) |
| 2054 | { |
| 2055 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 2056 | u32 i; |
| 2057 | bool force_high; |
| 2058 | struct radeon_clock_and_voltage_limits *max_limits = |
| 2059 | &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
| 2060 | u32 mclk = max_limits->mclk; |
| 2061 | |
| 2062 | if (pi->lowest_valid > pi->highest_valid) |
| 2063 | return -EINVAL; |
| 2064 | |
| 2065 | if (rdev->family == CHIP_KABINI) { |
| 2066 | for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { |
| 2067 | pi->graphics_level[i].GnbSlow = 1; |
| 2068 | pi->graphics_level[i].ForceNbPs1 = 0; |
| 2069 | pi->graphics_level[i].UpH = 0; |
| 2070 | } |
| 2071 | |
| 2072 | if (!pi->sys_info.nb_dpm_enable) |
| 2073 | return 0; |
| 2074 | |
| 2075 | force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || |
| 2076 | (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); |
| 2077 | |
| 2078 | if (force_high) { |
| 2079 | for (i = pi->lowest_valid; i <= pi->highest_valid; i++) |
| 2080 | pi->graphics_level[i].GnbSlow = 0; |
| 2081 | } else { |
| 2082 | if (pi->battery_state) |
| 2083 | pi->graphics_level[0].ForceNbPs1 = 1; |
| 2084 | |
| 2085 | pi->graphics_level[1].GnbSlow = 0; |
| 2086 | pi->graphics_level[2].GnbSlow = 0; |
| 2087 | pi->graphics_level[3].GnbSlow = 0; |
| 2088 | pi->graphics_level[4].GnbSlow = 0; |
| 2089 | } |
| 2090 | } else { |
| 2091 | for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { |
| 2092 | pi->graphics_level[i].GnbSlow = 1; |
| 2093 | pi->graphics_level[i].ForceNbPs1 = 0; |
| 2094 | pi->graphics_level[i].UpH = 0; |
| 2095 | } |
| 2096 | |
| 2097 | if (pi->sys_info.nb_dpm_enable && pi->battery_state) { |
| 2098 | pi->graphics_level[pi->lowest_valid].UpH = 0x28; |
| 2099 | pi->graphics_level[pi->lowest_valid].GnbSlow = 0; |
| 2100 | if (pi->lowest_valid != pi->highest_valid) |
| 2101 | pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; |
| 2102 | } |
| 2103 | } |
| 2104 | return 0; |
| 2105 | } |
| 2106 | |
| 2107 | static int kv_calculate_dpm_settings(struct radeon_device *rdev) |
| 2108 | { |
| 2109 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 2110 | u32 i; |
| 2111 | |
| 2112 | if (pi->lowest_valid > pi->highest_valid) |
| 2113 | return -EINVAL; |
| 2114 | |
| 2115 | for (i = pi->lowest_valid; i <= pi->highest_valid; i++) |
| 2116 | pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; |
| 2117 | |
| 2118 | return 0; |
| 2119 | } |
| 2120 | |
| 2121 | static void kv_init_graphics_levels(struct radeon_device *rdev) |
| 2122 | { |
| 2123 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 2124 | u32 i; |
| 2125 | struct radeon_clock_voltage_dependency_table *table = |
| 2126 | &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; |
| 2127 | |
| 2128 | if (table && table->count) { |
| 2129 | u32 vid_2bit; |
| 2130 | |
| 2131 | pi->graphics_dpm_level_count = 0; |
| 2132 | for (i = 0; i < table->count; i++) { |
| 2133 | if (pi->high_voltage_t && |
| 2134 | (pi->high_voltage_t < |
| 2135 | kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v))) |
| 2136 | break; |
| 2137 | |
| 2138 | kv_set_divider_value(rdev, i, table->entries[i].clk); |
| 2139 | vid_2bit = sumo_convert_vid7_to_vid2(rdev, |
| 2140 | &pi->sys_info.vid_mapping_table, |
| 2141 | table->entries[i].v); |
| 2142 | kv_set_vid(rdev, i, vid_2bit); |
| 2143 | kv_set_at(rdev, i, pi->at[i]); |
| 2144 | kv_dpm_power_level_enabled_for_throttle(rdev, i, true); |
| 2145 | pi->graphics_dpm_level_count++; |
| 2146 | } |
| 2147 | } else { |
| 2148 | struct sumo_sclk_voltage_mapping_table *table = |
| 2149 | &pi->sys_info.sclk_voltage_mapping_table; |
| 2150 | |
| 2151 | pi->graphics_dpm_level_count = 0; |
| 2152 | for (i = 0; i < table->num_max_dpm_entries; i++) { |
| 2153 | if (pi->high_voltage_t && |
| 2154 | pi->high_voltage_t < |
| 2155 | kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit)) |
| 2156 | break; |
| 2157 | |
| 2158 | kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency); |
| 2159 | kv_set_vid(rdev, i, table->entries[i].vid_2bit); |
| 2160 | kv_set_at(rdev, i, pi->at[i]); |
| 2161 | kv_dpm_power_level_enabled_for_throttle(rdev, i, true); |
| 2162 | pi->graphics_dpm_level_count++; |
| 2163 | } |
| 2164 | } |
| 2165 | |
| 2166 | for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) |
| 2167 | kv_dpm_power_level_enable(rdev, i, false); |
| 2168 | } |
| 2169 | |
| 2170 | static void kv_enable_new_levels(struct radeon_device *rdev) |
| 2171 | { |
| 2172 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 2173 | u32 i; |
| 2174 | |
| 2175 | for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) { |
| 2176 | if (i >= pi->lowest_valid && i <= pi->highest_valid) |
| 2177 | kv_dpm_power_level_enable(rdev, i, true); |
| 2178 | } |
| 2179 | } |
| 2180 | |
| 2181 | static int kv_set_enabled_levels(struct radeon_device *rdev) |
| 2182 | { |
| 2183 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 2184 | u32 i, new_mask = 0; |
| 2185 | |
| 2186 | for (i = pi->lowest_valid; i <= pi->highest_valid; i++) |
| 2187 | new_mask |= (1 << i); |
| 2188 | |
| 2189 | return kv_send_msg_to_smc_with_parameter(rdev, |
| 2190 | PPSMC_MSG_SCLKDPM_SetEnabledMask, |
| 2191 | new_mask); |
| 2192 | } |
| 2193 | |
| 2194 | static void kv_program_nbps_index_settings(struct radeon_device *rdev, |
| 2195 | struct radeon_ps *new_rps) |
| 2196 | { |
| 2197 | struct kv_ps *new_ps = kv_get_ps(new_rps); |
| 2198 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 2199 | u32 nbdpmconfig1; |
| 2200 | |
| 2201 | if (rdev->family == CHIP_KABINI) |
| 2202 | return; |
| 2203 | |
| 2204 | if (pi->sys_info.nb_dpm_enable) { |
| 2205 | nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1); |
| 2206 | nbdpmconfig1 &= ~(Dpm0PgNbPsLo_MASK | Dpm0PgNbPsHi_MASK | |
| 2207 | DpmXNbPsLo_MASK | DpmXNbPsHi_MASK); |
| 2208 | nbdpmconfig1 |= (Dpm0PgNbPsLo(new_ps->dpm0_pg_nb_ps_lo) | |
| 2209 | Dpm0PgNbPsHi(new_ps->dpm0_pg_nb_ps_hi) | |
| 2210 | DpmXNbPsLo(new_ps->dpmx_nb_ps_lo) | |
| 2211 | DpmXNbPsHi(new_ps->dpmx_nb_ps_hi)); |
| 2212 | WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1); |
| 2213 | } |
| 2214 | } |
| 2215 | |
| 2216 | static int kv_set_thermal_temperature_range(struct radeon_device *rdev, |
| 2217 | int min_temp, int max_temp) |
| 2218 | { |
| 2219 | int low_temp = 0 * 1000; |
| 2220 | int high_temp = 255 * 1000; |
| 2221 | u32 tmp; |
| 2222 | |
| 2223 | if (low_temp < min_temp) |
| 2224 | low_temp = min_temp; |
| 2225 | if (high_temp > max_temp) |
| 2226 | high_temp = max_temp; |
| 2227 | if (high_temp < low_temp) { |
| 2228 | DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); |
| 2229 | return -EINVAL; |
| 2230 | } |
| 2231 | |
| 2232 | tmp = RREG32_SMC(CG_THERMAL_INT_CTRL); |
| 2233 | tmp &= ~(DIG_THERM_INTH_MASK | DIG_THERM_INTL_MASK); |
| 2234 | tmp |= (DIG_THERM_INTH(49 + (high_temp / 1000)) | |
| 2235 | DIG_THERM_INTL(49 + (low_temp / 1000))); |
| 2236 | WREG32_SMC(CG_THERMAL_INT_CTRL, tmp); |
| 2237 | |
| 2238 | rdev->pm.dpm.thermal.min_temp = low_temp; |
| 2239 | rdev->pm.dpm.thermal.max_temp = high_temp; |
| 2240 | |
| 2241 | return 0; |
| 2242 | } |
| 2243 | |
| 2244 | union igp_info { |
| 2245 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; |
| 2246 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; |
| 2247 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5; |
| 2248 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; |
| 2249 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; |
| 2250 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; |
| 2251 | }; |
| 2252 | |
| 2253 | static int kv_parse_sys_info_table(struct radeon_device *rdev) |
| 2254 | { |
| 2255 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 2256 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 2257 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); |
| 2258 | union igp_info *igp_info; |
| 2259 | u8 frev, crev; |
| 2260 | u16 data_offset; |
| 2261 | int i; |
| 2262 | |
| 2263 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 2264 | &frev, &crev, &data_offset)) { |
| 2265 | igp_info = (union igp_info *)(mode_info->atom_context->bios + |
| 2266 | data_offset); |
| 2267 | |
| 2268 | if (crev != 8) { |
| 2269 | DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); |
| 2270 | return -EINVAL; |
| 2271 | } |
| 2272 | pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); |
| 2273 | pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); |
| 2274 | pi->sys_info.bootup_nb_voltage_index = |
| 2275 | le16_to_cpu(igp_info->info_8.usBootUpNBVoltage); |
| 2276 | if (igp_info->info_8.ucHtcTmpLmt == 0) |
| 2277 | pi->sys_info.htc_tmp_lmt = 203; |
| 2278 | else |
| 2279 | pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; |
| 2280 | if (igp_info->info_8.ucHtcHystLmt == 0) |
| 2281 | pi->sys_info.htc_hyst_lmt = 5; |
| 2282 | else |
| 2283 | pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; |
| 2284 | if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { |
| 2285 | DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n"); |
| 2286 | } |
| 2287 | |
| 2288 | if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3)) |
| 2289 | pi->sys_info.nb_dpm_enable = true; |
| 2290 | else |
| 2291 | pi->sys_info.nb_dpm_enable = false; |
| 2292 | |
| 2293 | for (i = 0; i < KV_NUM_NBPSTATES; i++) { |
| 2294 | pi->sys_info.nbp_memory_clock[i] = |
| 2295 | le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]); |
| 2296 | pi->sys_info.nbp_n_clock[i] = |
| 2297 | le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]); |
| 2298 | } |
| 2299 | if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) & |
| 2300 | SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) |
| 2301 | pi->caps_enable_dfs_bypass = true; |
| 2302 | |
| 2303 | sumo_construct_sclk_voltage_mapping_table(rdev, |
| 2304 | &pi->sys_info.sclk_voltage_mapping_table, |
| 2305 | igp_info->info_8.sAvail_SCLK); |
| 2306 | |
| 2307 | sumo_construct_vid_mapping_table(rdev, |
| 2308 | &pi->sys_info.vid_mapping_table, |
| 2309 | igp_info->info_8.sAvail_SCLK); |
| 2310 | |
| 2311 | kv_construct_max_power_limits_table(rdev, |
| 2312 | &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); |
| 2313 | } |
| 2314 | return 0; |
| 2315 | } |
| 2316 | |
| 2317 | union power_info { |
| 2318 | struct _ATOM_POWERPLAY_INFO info; |
| 2319 | struct _ATOM_POWERPLAY_INFO_V2 info_2; |
| 2320 | struct _ATOM_POWERPLAY_INFO_V3 info_3; |
| 2321 | struct _ATOM_PPLIB_POWERPLAYTABLE pplib; |
| 2322 | struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; |
| 2323 | struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; |
| 2324 | }; |
| 2325 | |
| 2326 | union pplib_clock_info { |
| 2327 | struct _ATOM_PPLIB_R600_CLOCK_INFO r600; |
| 2328 | struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; |
| 2329 | struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; |
| 2330 | struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; |
| 2331 | }; |
| 2332 | |
| 2333 | union pplib_power_state { |
| 2334 | struct _ATOM_PPLIB_STATE v1; |
| 2335 | struct _ATOM_PPLIB_STATE_V2 v2; |
| 2336 | }; |
| 2337 | |
| 2338 | static void kv_patch_boot_state(struct radeon_device *rdev, |
| 2339 | struct kv_ps *ps) |
| 2340 | { |
| 2341 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 2342 | |
| 2343 | ps->num_levels = 1; |
| 2344 | ps->levels[0] = pi->boot_pl; |
| 2345 | } |
| 2346 | |
| 2347 | static void kv_parse_pplib_non_clock_info(struct radeon_device *rdev, |
| 2348 | struct radeon_ps *rps, |
| 2349 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, |
| 2350 | u8 table_rev) |
| 2351 | { |
| 2352 | struct kv_ps *ps = kv_get_ps(rps); |
| 2353 | |
| 2354 | rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); |
| 2355 | rps->class = le16_to_cpu(non_clock_info->usClassification); |
| 2356 | rps->class2 = le16_to_cpu(non_clock_info->usClassification2); |
| 2357 | |
| 2358 | if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { |
| 2359 | rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); |
| 2360 | rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); |
| 2361 | } else { |
| 2362 | rps->vclk = 0; |
| 2363 | rps->dclk = 0; |
| 2364 | } |
| 2365 | |
| 2366 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { |
| 2367 | rdev->pm.dpm.boot_ps = rps; |
| 2368 | kv_patch_boot_state(rdev, ps); |
| 2369 | } |
| 2370 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) |
| 2371 | rdev->pm.dpm.uvd_ps = rps; |
| 2372 | } |
| 2373 | |
| 2374 | static void kv_parse_pplib_clock_info(struct radeon_device *rdev, |
| 2375 | struct radeon_ps *rps, int index, |
| 2376 | union pplib_clock_info *clock_info) |
| 2377 | { |
| 2378 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 2379 | struct kv_ps *ps = kv_get_ps(rps); |
| 2380 | struct kv_pl *pl = &ps->levels[index]; |
| 2381 | u32 sclk; |
| 2382 | |
| 2383 | sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); |
| 2384 | sclk |= clock_info->sumo.ucEngineClockHigh << 16; |
| 2385 | pl->sclk = sclk; |
| 2386 | pl->vddc_index = clock_info->sumo.vddcIndex; |
| 2387 | |
| 2388 | ps->num_levels = index + 1; |
| 2389 | |
| 2390 | if (pi->caps_sclk_ds) { |
| 2391 | pl->ds_divider_index = 5; |
| 2392 | pl->ss_divider_index = 5; |
| 2393 | } |
| 2394 | } |
| 2395 | |
| 2396 | static int kv_parse_power_table(struct radeon_device *rdev) |
| 2397 | { |
| 2398 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 2399 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; |
| 2400 | union pplib_power_state *power_state; |
| 2401 | int i, j, k, non_clock_array_index, clock_array_index; |
| 2402 | union pplib_clock_info *clock_info; |
| 2403 | struct _StateArray *state_array; |
| 2404 | struct _ClockInfoArray *clock_info_array; |
| 2405 | struct _NonClockInfoArray *non_clock_info_array; |
| 2406 | union power_info *power_info; |
| 2407 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); |
| 2408 | u16 data_offset; |
| 2409 | u8 frev, crev; |
| 2410 | u8 *power_state_offset; |
| 2411 | struct kv_ps *ps; |
| 2412 | |
| 2413 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 2414 | &frev, &crev, &data_offset)) |
| 2415 | return -EINVAL; |
| 2416 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); |
| 2417 | |
| 2418 | state_array = (struct _StateArray *) |
| 2419 | (mode_info->atom_context->bios + data_offset + |
| 2420 | le16_to_cpu(power_info->pplib.usStateArrayOffset)); |
| 2421 | clock_info_array = (struct _ClockInfoArray *) |
| 2422 | (mode_info->atom_context->bios + data_offset + |
| 2423 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); |
| 2424 | non_clock_info_array = (struct _NonClockInfoArray *) |
| 2425 | (mode_info->atom_context->bios + data_offset + |
| 2426 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); |
| 2427 | |
| 2428 | rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * |
| 2429 | state_array->ucNumEntries, GFP_KERNEL); |
| 2430 | if (!rdev->pm.dpm.ps) |
| 2431 | return -ENOMEM; |
| 2432 | power_state_offset = (u8 *)state_array->states; |
| 2433 | rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); |
| 2434 | rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); |
| 2435 | rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); |
| 2436 | for (i = 0; i < state_array->ucNumEntries; i++) { |
| 2437 | power_state = (union pplib_power_state *)power_state_offset; |
| 2438 | non_clock_array_index = power_state->v2.nonClockInfoIndex; |
| 2439 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) |
| 2440 | &non_clock_info_array->nonClockInfo[non_clock_array_index]; |
| 2441 | if (!rdev->pm.power_state[i].clock_info) |
| 2442 | return -EINVAL; |
| 2443 | ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL); |
| 2444 | if (ps == NULL) { |
| 2445 | kfree(rdev->pm.dpm.ps); |
| 2446 | return -ENOMEM; |
| 2447 | } |
| 2448 | rdev->pm.dpm.ps[i].ps_priv = ps; |
| 2449 | k = 0; |
| 2450 | for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { |
| 2451 | clock_array_index = power_state->v2.clockInfoIndex[j]; |
| 2452 | if (clock_array_index >= clock_info_array->ucNumEntries) |
| 2453 | continue; |
| 2454 | if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) |
| 2455 | break; |
| 2456 | clock_info = (union pplib_clock_info *) |
| 2457 | &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; |
| 2458 | kv_parse_pplib_clock_info(rdev, |
| 2459 | &rdev->pm.dpm.ps[i], k, |
| 2460 | clock_info); |
| 2461 | k++; |
| 2462 | } |
| 2463 | kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], |
| 2464 | non_clock_info, |
| 2465 | non_clock_info_array->ucEntrySize); |
| 2466 | power_state_offset += 2 + power_state->v2.ucNumDPMLevels; |
| 2467 | } |
| 2468 | rdev->pm.dpm.num_ps = state_array->ucNumEntries; |
| 2469 | return 0; |
| 2470 | } |
| 2471 | |
| 2472 | int kv_dpm_init(struct radeon_device *rdev) |
| 2473 | { |
| 2474 | struct kv_power_info *pi; |
| 2475 | int ret, i; |
| 2476 | |
| 2477 | pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); |
| 2478 | if (pi == NULL) |
| 2479 | return -ENOMEM; |
| 2480 | rdev->pm.dpm.priv = pi; |
| 2481 | |
| 2482 | ret = r600_parse_extended_power_table(rdev); |
| 2483 | if (ret) |
| 2484 | return ret; |
| 2485 | |
| 2486 | for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) |
| 2487 | pi->at[i] = TRINITY_AT_DFLT; |
| 2488 | |
| 2489 | pi->sram_end = SMC_RAM_END; |
| 2490 | |
| 2491 | if (rdev->family == CHIP_KABINI) |
| 2492 | pi->high_voltage_t = 4001; |
| 2493 | |
| 2494 | pi->enable_nb_dpm = true; |
| 2495 | |
| 2496 | pi->caps_power_containment = true; |
| 2497 | pi->caps_cac = true; |
| 2498 | pi->enable_didt = false; |
| 2499 | if (pi->enable_didt) { |
| 2500 | pi->caps_sq_ramping = true; |
| 2501 | pi->caps_db_ramping = true; |
| 2502 | pi->caps_td_ramping = true; |
| 2503 | pi->caps_tcp_ramping = true; |
| 2504 | } |
| 2505 | |
| 2506 | pi->caps_sclk_ds = true; |
| 2507 | pi->enable_auto_thermal_throttling = true; |
| 2508 | pi->disable_nb_ps3_in_battery = false; |
| 2509 | pi->bapm_enable = true; |
| 2510 | pi->voltage_drop_t = 0; |
| 2511 | pi->caps_sclk_throttle_low_notification = false; |
| 2512 | pi->caps_fps = false; /* true? */ |
Alex Deucher | 77df508 | 2013-08-09 10:02:40 -0400 | [diff] [blame^] | 2513 | pi->caps_uvd_pg = true; |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 2514 | pi->caps_uvd_dpm = true; |
| 2515 | pi->caps_vce_pg = false; |
| 2516 | pi->caps_samu_pg = false; |
| 2517 | pi->caps_acp_pg = false; |
| 2518 | pi->caps_stable_p_state = false; |
| 2519 | |
| 2520 | ret = kv_parse_sys_info_table(rdev); |
| 2521 | if (ret) |
| 2522 | return ret; |
| 2523 | |
| 2524 | kv_patch_voltage_values(rdev); |
| 2525 | kv_construct_boot_state(rdev); |
| 2526 | |
| 2527 | ret = kv_parse_power_table(rdev); |
| 2528 | if (ret) |
| 2529 | return ret; |
| 2530 | |
| 2531 | pi->enable_dpm = true; |
| 2532 | |
| 2533 | return 0; |
| 2534 | } |
| 2535 | |
Alex Deucher | ae3e40e | 2013-07-18 16:39:53 -0400 | [diff] [blame] | 2536 | void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, |
| 2537 | struct seq_file *m) |
| 2538 | { |
| 2539 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 2540 | u32 current_index = |
| 2541 | (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> |
| 2542 | CURR_SCLK_INDEX_SHIFT; |
| 2543 | u32 sclk, tmp; |
| 2544 | u16 vddc; |
| 2545 | |
| 2546 | if (current_index >= SMU__NUM_SCLK_DPM_STATE) { |
| 2547 | seq_printf(m, "invalid dpm profile %d\n", current_index); |
| 2548 | } else { |
| 2549 | sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); |
| 2550 | tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> |
| 2551 | SMU_VOLTAGE_CURRENT_LEVEL_SHIFT; |
| 2552 | vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp); |
| 2553 | seq_printf(m, "power level %d sclk: %u vddc: %u\n", |
| 2554 | current_index, sclk, vddc); |
| 2555 | } |
| 2556 | } |
| 2557 | |
Alex Deucher | 41a524a | 2013-08-14 01:01:40 -0400 | [diff] [blame] | 2558 | void kv_dpm_print_power_state(struct radeon_device *rdev, |
| 2559 | struct radeon_ps *rps) |
| 2560 | { |
| 2561 | int i; |
| 2562 | struct kv_ps *ps = kv_get_ps(rps); |
| 2563 | |
| 2564 | r600_dpm_print_class_info(rps->class, rps->class2); |
| 2565 | r600_dpm_print_cap_info(rps->caps); |
| 2566 | printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); |
| 2567 | for (i = 0; i < ps->num_levels; i++) { |
| 2568 | struct kv_pl *pl = &ps->levels[i]; |
| 2569 | printk("\t\tpower level %d sclk: %u vddc: %u\n", |
| 2570 | i, pl->sclk, |
| 2571 | kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index)); |
| 2572 | } |
| 2573 | r600_dpm_print_ps_status(rdev, rps); |
| 2574 | } |
| 2575 | |
| 2576 | void kv_dpm_fini(struct radeon_device *rdev) |
| 2577 | { |
| 2578 | int i; |
| 2579 | |
| 2580 | for (i = 0; i < rdev->pm.dpm.num_ps; i++) { |
| 2581 | kfree(rdev->pm.dpm.ps[i].ps_priv); |
| 2582 | } |
| 2583 | kfree(rdev->pm.dpm.ps); |
| 2584 | kfree(rdev->pm.dpm.priv); |
| 2585 | r600_free_extended_power_table(rdev); |
| 2586 | } |
| 2587 | |
| 2588 | void kv_dpm_display_configuration_changed(struct radeon_device *rdev) |
| 2589 | { |
| 2590 | |
| 2591 | } |
| 2592 | |
| 2593 | u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low) |
| 2594 | { |
| 2595 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 2596 | struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); |
| 2597 | |
| 2598 | if (low) |
| 2599 | return requested_state->levels[0].sclk; |
| 2600 | else |
| 2601 | return requested_state->levels[requested_state->num_levels - 1].sclk; |
| 2602 | } |
| 2603 | |
| 2604 | u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low) |
| 2605 | { |
| 2606 | struct kv_power_info *pi = kv_get_pi(rdev); |
| 2607 | |
| 2608 | return pi->sys_info.bootup_uma_clk; |
| 2609 | } |
| 2610 | |