Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | #include <dt-bindings/clock/imx6sx-clock.h> |
| 10 | #include <dt-bindings/gpio/gpio.h> |
| 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 12 | #include "imx6sx-pinfunc.h" |
| 13 | #include "skeleton.dtsi" |
| 14 | |
| 15 | / { |
| 16 | aliases { |
| 17 | can0 = &flexcan1; |
| 18 | can1 = &flexcan2; |
| 19 | ethernet0 = &fec1; |
| 20 | ethernet1 = &fec2; |
| 21 | gpio0 = &gpio1; |
| 22 | gpio1 = &gpio2; |
| 23 | gpio2 = &gpio3; |
| 24 | gpio3 = &gpio4; |
| 25 | gpio4 = &gpio5; |
| 26 | gpio5 = &gpio6; |
| 27 | gpio6 = &gpio7; |
| 28 | i2c0 = &i2c1; |
| 29 | i2c1 = &i2c2; |
| 30 | i2c2 = &i2c3; |
| 31 | i2c3 = &i2c4; |
| 32 | mmc0 = &usdhc1; |
| 33 | mmc1 = &usdhc2; |
| 34 | mmc2 = &usdhc3; |
| 35 | mmc3 = &usdhc4; |
| 36 | serial0 = &uart1; |
| 37 | serial1 = &uart2; |
| 38 | serial2 = &uart3; |
| 39 | serial3 = &uart4; |
| 40 | serial4 = &uart5; |
| 41 | serial5 = &uart6; |
| 42 | spi0 = &ecspi1; |
| 43 | spi1 = &ecspi2; |
| 44 | spi2 = &ecspi3; |
| 45 | spi3 = &ecspi4; |
| 46 | spi4 = &ecspi5; |
| 47 | usbphy0 = &usbphy1; |
| 48 | usbphy1 = &usbphy2; |
| 49 | }; |
| 50 | |
| 51 | cpus { |
| 52 | #address-cells = <1>; |
| 53 | #size-cells = <0>; |
| 54 | |
| 55 | cpu0: cpu@0 { |
| 56 | compatible = "arm,cortex-a9"; |
| 57 | device_type = "cpu"; |
| 58 | reg = <0>; |
| 59 | next-level-cache = <&L2>; |
| 60 | operating-points = < |
| 61 | /* kHz uV */ |
| 62 | 996000 1250000 |
| 63 | 792000 1175000 |
| 64 | 396000 1075000 |
| 65 | >; |
| 66 | fsl,soc-operating-points = < |
| 67 | /* ARM kHz SOC uV */ |
| 68 | 996000 1175000 |
| 69 | 792000 1175000 |
| 70 | 396000 1175000 |
| 71 | >; |
| 72 | clock-latency = <61036>; /* two CLK32 periods */ |
| 73 | clocks = <&clks IMX6SX_CLK_ARM>, |
| 74 | <&clks IMX6SX_CLK_PLL2_PFD2>, |
| 75 | <&clks IMX6SX_CLK_STEP>, |
| 76 | <&clks IMX6SX_CLK_PLL1_SW>, |
| 77 | <&clks IMX6SX_CLK_PLL1_SYS>; |
| 78 | clock-names = "arm", "pll2_pfd2_396m", "step", |
| 79 | "pll1_sw", "pll1_sys"; |
| 80 | arm-supply = <®_arm>; |
| 81 | soc-supply = <®_soc>; |
| 82 | }; |
| 83 | }; |
| 84 | |
| 85 | intc: interrupt-controller@00a01000 { |
| 86 | compatible = "arm,cortex-a9-gic"; |
| 87 | #interrupt-cells = <3>; |
| 88 | interrupt-controller; |
| 89 | reg = <0x00a01000 0x1000>, |
| 90 | <0x00a00100 0x100>; |
| 91 | }; |
| 92 | |
| 93 | clocks { |
| 94 | #address-cells = <1>; |
| 95 | #size-cells = <0>; |
| 96 | |
| 97 | ckil: clock@0 { |
| 98 | compatible = "fixed-clock"; |
| 99 | reg = <0>; |
| 100 | #clock-cells = <0>; |
| 101 | clock-frequency = <32768>; |
| 102 | clock-output-names = "ckil"; |
| 103 | }; |
| 104 | |
| 105 | osc: clock@1 { |
| 106 | compatible = "fixed-clock"; |
| 107 | reg = <1>; |
| 108 | #clock-cells = <0>; |
| 109 | clock-frequency = <24000000>; |
| 110 | clock-output-names = "osc"; |
| 111 | }; |
| 112 | |
| 113 | ipp_di0: clock@2 { |
| 114 | compatible = "fixed-clock"; |
| 115 | reg = <2>; |
| 116 | #clock-cells = <0>; |
| 117 | clock-frequency = <0>; |
| 118 | clock-output-names = "ipp_di0"; |
| 119 | }; |
| 120 | |
| 121 | ipp_di1: clock@3 { |
| 122 | compatible = "fixed-clock"; |
| 123 | reg = <3>; |
| 124 | #clock-cells = <0>; |
| 125 | clock-frequency = <0>; |
| 126 | clock-output-names = "ipp_di1"; |
| 127 | }; |
| 128 | }; |
| 129 | |
| 130 | soc { |
| 131 | #address-cells = <1>; |
| 132 | #size-cells = <1>; |
| 133 | compatible = "simple-bus"; |
| 134 | interrupt-parent = <&intc>; |
| 135 | ranges; |
| 136 | |
| 137 | pmu { |
| 138 | compatible = "arm,cortex-a9-pmu"; |
| 139 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 140 | }; |
| 141 | |
| 142 | ocram: sram@00900000 { |
| 143 | compatible = "mmio-sram"; |
| 144 | reg = <0x00900000 0x20000>; |
| 145 | clocks = <&clks IMX6SX_CLK_OCRAM>; |
| 146 | }; |
| 147 | |
| 148 | L2: l2-cache@00a02000 { |
| 149 | compatible = "arm,pl310-cache"; |
| 150 | reg = <0x00a02000 0x1000>; |
| 151 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 152 | cache-unified; |
| 153 | cache-level = <2>; |
| 154 | arm,tag-latency = <4 2 3>; |
| 155 | arm,data-latency = <4 2 3>; |
| 156 | }; |
| 157 | |
| 158 | dma_apbh: dma-apbh@01804000 { |
| 159 | compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; |
| 160 | reg = <0x01804000 0x2000>; |
| 161 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 162 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 163 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 164 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 165 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; |
| 166 | #dma-cells = <1>; |
| 167 | dma-channels = <4>; |
| 168 | clocks = <&clks IMX6SX_CLK_APBH_DMA>; |
| 169 | }; |
| 170 | |
| 171 | gpmi: gpmi-nand@01806000{ |
| 172 | compatible = "fsl,imx6sx-gpmi-nand"; |
| 173 | #address-cells = <1>; |
| 174 | #size-cells = <1>; |
| 175 | reg = <0x01806000 0x2000>, <0x01808000 0x4000>; |
| 176 | reg-names = "gpmi-nand", "bch"; |
| 177 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 178 | interrupt-names = "bch"; |
| 179 | clocks = <&clks IMX6SX_CLK_GPMI_IO>, |
| 180 | <&clks IMX6SX_CLK_GPMI_APB>, |
| 181 | <&clks IMX6SX_CLK_GPMI_BCH>, |
| 182 | <&clks IMX6SX_CLK_GPMI_BCH_APB>, |
| 183 | <&clks IMX6SX_CLK_PER1_BCH>; |
| 184 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", |
| 185 | "gpmi_bch_apb", "per1_bch"; |
| 186 | dmas = <&dma_apbh 0>; |
| 187 | dma-names = "rx-tx"; |
| 188 | status = "disabled"; |
| 189 | }; |
| 190 | |
| 191 | aips1: aips-bus@02000000 { |
| 192 | compatible = "fsl,aips-bus", "simple-bus"; |
| 193 | #address-cells = <1>; |
| 194 | #size-cells = <1>; |
| 195 | reg = <0x02000000 0x100000>; |
| 196 | ranges; |
| 197 | |
| 198 | spba-bus@02000000 { |
| 199 | compatible = "fsl,spba-bus", "simple-bus"; |
| 200 | #address-cells = <1>; |
| 201 | #size-cells = <1>; |
| 202 | reg = <0x02000000 0x40000>; |
| 203 | ranges; |
| 204 | |
| 205 | spdif: spdif@02004000 { |
| 206 | compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; |
| 207 | reg = <0x02004000 0x4000>; |
| 208 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
| 209 | dmas = <&sdma 14 18 0>, |
| 210 | <&sdma 15 18 0>; |
| 211 | dma-names = "rx", "tx"; |
| 212 | clocks = <&clks IMX6SX_CLK_SPDIF>, |
| 213 | <&clks IMX6SX_CLK_OSC>, |
| 214 | <&clks IMX6SX_CLK_SPDIF>, |
| 215 | <&clks 0>, <&clks 0>, <&clks 0>, |
| 216 | <&clks IMX6SX_CLK_IPG>, |
| 217 | <&clks 0>, <&clks 0>, |
| 218 | <&clks IMX6SX_CLK_SPBA>; |
| 219 | clock-names = "core", "rxtx0", |
| 220 | "rxtx1", "rxtx2", |
| 221 | "rxtx3", "rxtx4", |
| 222 | "rxtx5", "rxtx6", |
| 223 | "rxtx7", "dma"; |
| 224 | status = "disabled"; |
| 225 | }; |
| 226 | |
| 227 | ecspi1: ecspi@02008000 { |
| 228 | #address-cells = <1>; |
| 229 | #size-cells = <0>; |
| 230 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; |
| 231 | reg = <0x02008000 0x4000>; |
| 232 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| 233 | clocks = <&clks IMX6SX_CLK_ECSPI1>, |
| 234 | <&clks IMX6SX_CLK_ECSPI1>; |
| 235 | clock-names = "ipg", "per"; |
| 236 | status = "disabled"; |
| 237 | }; |
| 238 | |
| 239 | ecspi2: ecspi@0200c000 { |
| 240 | #address-cells = <1>; |
| 241 | #size-cells = <0>; |
| 242 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; |
| 243 | reg = <0x0200c000 0x4000>; |
| 244 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| 245 | clocks = <&clks IMX6SX_CLK_ECSPI2>, |
| 246 | <&clks IMX6SX_CLK_ECSPI2>; |
| 247 | clock-names = "ipg", "per"; |
| 248 | status = "disabled"; |
| 249 | }; |
| 250 | |
| 251 | ecspi3: ecspi@02010000 { |
| 252 | #address-cells = <1>; |
| 253 | #size-cells = <0>; |
| 254 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; |
| 255 | reg = <0x02010000 0x4000>; |
| 256 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| 257 | clocks = <&clks IMX6SX_CLK_ECSPI3>, |
| 258 | <&clks IMX6SX_CLK_ECSPI3>; |
| 259 | clock-names = "ipg", "per"; |
| 260 | status = "disabled"; |
| 261 | }; |
| 262 | |
| 263 | ecspi4: ecspi@02014000 { |
| 264 | #address-cells = <1>; |
| 265 | #size-cells = <0>; |
| 266 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; |
| 267 | reg = <0x02014000 0x4000>; |
| 268 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| 269 | clocks = <&clks IMX6SX_CLK_ECSPI4>, |
| 270 | <&clks IMX6SX_CLK_ECSPI4>; |
| 271 | clock-names = "ipg", "per"; |
| 272 | status = "disabled"; |
| 273 | }; |
| 274 | |
| 275 | uart1: serial@02020000 { |
| 276 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; |
| 277 | reg = <0x02020000 0x4000>; |
| 278 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| 279 | clocks = <&clks IMX6SX_CLK_UART_IPG>, |
| 280 | <&clks IMX6SX_CLK_UART_SERIAL>; |
| 281 | clock-names = "ipg", "per"; |
| 282 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
| 283 | dma-names = "rx", "tx"; |
| 284 | status = "disabled"; |
| 285 | }; |
| 286 | |
| 287 | esai: esai@02024000 { |
| 288 | reg = <0x02024000 0x4000>; |
| 289 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
| 290 | clocks = <&clks IMX6SX_CLK_ESAI_IPG>, |
| 291 | <&clks IMX6SX_CLK_ESAI_MEM>, |
| 292 | <&clks IMX6SX_CLK_ESAI_EXTAL>, |
| 293 | <&clks IMX6SX_CLK_ESAI_IPG>, |
| 294 | <&clks IMX6SX_CLK_SPBA>; |
| 295 | clock-names = "core", "mem", "extal", |
| 296 | "fsys", "dma"; |
| 297 | status = "disabled"; |
| 298 | }; |
| 299 | |
| 300 | ssi1: ssi@02028000 { |
| 301 | compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi"; |
| 302 | reg = <0x02028000 0x4000>; |
| 303 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| 304 | clocks = <&clks IMX6SX_CLK_SSI1_IPG>, |
| 305 | <&clks IMX6SX_CLK_SSI1>; |
| 306 | clock-names = "ipg", "baud"; |
| 307 | dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; |
| 308 | dma-names = "rx", "tx"; |
| 309 | status = "disabled"; |
| 310 | }; |
| 311 | |
| 312 | ssi2: ssi@0202c000 { |
| 313 | compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi"; |
| 314 | reg = <0x0202c000 0x4000>; |
| 315 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| 316 | clocks = <&clks IMX6SX_CLK_SSI2_IPG>, |
| 317 | <&clks IMX6SX_CLK_SSI2>; |
| 318 | clock-names = "ipg", "baud"; |
| 319 | dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; |
| 320 | dma-names = "rx", "tx"; |
| 321 | status = "disabled"; |
| 322 | }; |
| 323 | |
| 324 | ssi3: ssi@02030000 { |
| 325 | compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi"; |
| 326 | reg = <0x02030000 0x4000>; |
| 327 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
| 328 | clocks = <&clks IMX6SX_CLK_SSI3_IPG>, |
| 329 | <&clks IMX6SX_CLK_SSI3>; |
| 330 | clock-names = "ipg", "baud"; |
| 331 | dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; |
| 332 | dma-names = "rx", "tx"; |
| 333 | status = "disabled"; |
| 334 | }; |
| 335 | |
| 336 | asrc: asrc@02034000 { |
| 337 | reg = <0x02034000 0x4000>; |
| 338 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
| 339 | clocks = <&clks IMX6SX_CLK_ASRC_MEM>, |
| 340 | <&clks IMX6SX_CLK_ASRC_IPG>, |
| 341 | <&clks IMX6SX_CLK_SPDIF>, |
| 342 | <&clks IMX6SX_CLK_SPBA>; |
| 343 | clock-names = "mem", "ipg", "asrck", "dma"; |
| 344 | dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, |
| 345 | <&sdma 19 20 1>, <&sdma 20 20 1>, |
| 346 | <&sdma 21 20 1>, <&sdma 22 20 1>; |
| 347 | dma-names = "rxa", "rxb", "rxc", |
| 348 | "txa", "txb", "txc"; |
| 349 | status = "okay"; |
| 350 | }; |
| 351 | }; |
| 352 | |
| 353 | pwm1: pwm@02080000 { |
| 354 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 355 | reg = <0x02080000 0x4000>; |
| 356 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 357 | clocks = <&clks IMX6SX_CLK_PWM1>, |
| 358 | <&clks IMX6SX_CLK_PWM1>; |
| 359 | clock-names = "ipg", "per"; |
| 360 | #pwm-cells = <2>; |
| 361 | }; |
| 362 | |
| 363 | pwm2: pwm@02084000 { |
| 364 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 365 | reg = <0x02084000 0x4000>; |
| 366 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| 367 | clocks = <&clks IMX6SX_CLK_PWM2>, |
| 368 | <&clks IMX6SX_CLK_PWM2>; |
| 369 | clock-names = "ipg", "per"; |
| 370 | #pwm-cells = <2>; |
| 371 | }; |
| 372 | |
| 373 | pwm3: pwm@02088000 { |
| 374 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 375 | reg = <0x02088000 0x4000>; |
| 376 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| 377 | clocks = <&clks IMX6SX_CLK_PWM3>, |
| 378 | <&clks IMX6SX_CLK_PWM3>; |
| 379 | clock-names = "ipg", "per"; |
| 380 | #pwm-cells = <2>; |
| 381 | }; |
| 382 | |
| 383 | pwm4: pwm@0208c000 { |
| 384 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 385 | reg = <0x0208c000 0x4000>; |
| 386 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 387 | clocks = <&clks IMX6SX_CLK_PWM4>, |
| 388 | <&clks IMX6SX_CLK_PWM4>; |
| 389 | clock-names = "ipg", "per"; |
| 390 | #pwm-cells = <2>; |
| 391 | }; |
| 392 | |
| 393 | flexcan1: can@02090000 { |
| 394 | compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; |
| 395 | reg = <0x02090000 0x4000>; |
| 396 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| 397 | clocks = <&clks IMX6SX_CLK_CAN1_IPG>, |
| 398 | <&clks IMX6SX_CLK_CAN1_SERIAL>; |
| 399 | clock-names = "ipg", "per"; |
| 400 | status = "disabled"; |
| 401 | }; |
| 402 | |
| 403 | flexcan2: can@02094000 { |
| 404 | compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; |
| 405 | reg = <0x02094000 0x4000>; |
| 406 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| 407 | clocks = <&clks IMX6SX_CLK_CAN2_IPG>, |
| 408 | <&clks IMX6SX_CLK_CAN2_SERIAL>; |
| 409 | clock-names = "ipg", "per"; |
| 410 | status = "disabled"; |
| 411 | }; |
| 412 | |
| 413 | gpt: gpt@02098000 { |
| 414 | compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt"; |
| 415 | reg = <0x02098000 0x4000>; |
| 416 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
| 417 | clocks = <&clks IMX6SX_CLK_GPT_BUS>, |
| 418 | <&clks IMX6SX_CLK_GPT_SERIAL>; |
| 419 | clock-names = "ipg", "per"; |
| 420 | }; |
| 421 | |
| 422 | gpio1: gpio@0209c000 { |
| 423 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; |
| 424 | reg = <0x0209c000 0x4000>; |
| 425 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, |
| 426 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| 427 | gpio-controller; |
| 428 | #gpio-cells = <2>; |
| 429 | interrupt-controller; |
| 430 | #interrupt-cells = <2>; |
| 431 | }; |
| 432 | |
| 433 | gpio2: gpio@020a0000 { |
| 434 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; |
| 435 | reg = <0x020a0000 0x4000>; |
| 436 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, |
| 437 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| 438 | gpio-controller; |
| 439 | #gpio-cells = <2>; |
| 440 | interrupt-controller; |
| 441 | #interrupt-cells = <2>; |
| 442 | }; |
| 443 | |
| 444 | gpio3: gpio@020a4000 { |
| 445 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; |
| 446 | reg = <0x020a4000 0x4000>; |
| 447 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, |
| 448 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| 449 | gpio-controller; |
| 450 | #gpio-cells = <2>; |
| 451 | interrupt-controller; |
| 452 | #interrupt-cells = <2>; |
| 453 | }; |
| 454 | |
| 455 | gpio4: gpio@020a8000 { |
| 456 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; |
| 457 | reg = <0x020a8000 0x4000>; |
| 458 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
| 459 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 460 | gpio-controller; |
| 461 | #gpio-cells = <2>; |
| 462 | interrupt-controller; |
| 463 | #interrupt-cells = <2>; |
| 464 | }; |
| 465 | |
| 466 | gpio5: gpio@020ac000 { |
| 467 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; |
| 468 | reg = <0x020ac000 0x4000>; |
| 469 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, |
| 470 | <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| 471 | gpio-controller; |
| 472 | #gpio-cells = <2>; |
| 473 | interrupt-controller; |
| 474 | #interrupt-cells = <2>; |
| 475 | }; |
| 476 | |
| 477 | gpio6: gpio@020b0000 { |
| 478 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; |
| 479 | reg = <0x020b0000 0x4000>; |
| 480 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, |
| 481 | <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 482 | gpio-controller; |
| 483 | #gpio-cells = <2>; |
| 484 | interrupt-controller; |
| 485 | #interrupt-cells = <2>; |
| 486 | }; |
| 487 | |
| 488 | gpio7: gpio@020b4000 { |
| 489 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; |
| 490 | reg = <0x020b4000 0x4000>; |
| 491 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, |
| 492 | <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| 493 | gpio-controller; |
| 494 | #gpio-cells = <2>; |
| 495 | interrupt-controller; |
| 496 | #interrupt-cells = <2>; |
| 497 | }; |
| 498 | |
| 499 | kpp: kpp@020b8000 { |
| 500 | compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; |
| 501 | reg = <0x020b8000 0x4000>; |
| 502 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 503 | clocks = <&clks IMX6SX_CLK_DUMMY>; |
| 504 | status = "disabled"; |
| 505 | }; |
| 506 | |
| 507 | wdog1: wdog@020bc000 { |
| 508 | compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; |
| 509 | reg = <0x020bc000 0x4000>; |
| 510 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
| 511 | clocks = <&clks IMX6SX_CLK_DUMMY>; |
| 512 | }; |
| 513 | |
| 514 | wdog2: wdog@020c0000 { |
| 515 | compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; |
| 516 | reg = <0x020c0000 0x4000>; |
| 517 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| 518 | clocks = <&clks IMX6SX_CLK_DUMMY>; |
| 519 | status = "disabled"; |
| 520 | }; |
| 521 | |
| 522 | clks: ccm@020c4000 { |
| 523 | compatible = "fsl,imx6sx-ccm"; |
| 524 | reg = <0x020c4000 0x4000>; |
| 525 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 526 | <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
| 527 | #clock-cells = <1>; |
| 528 | clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; |
| 529 | clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; |
| 530 | }; |
| 531 | |
| 532 | anatop: anatop@020c8000 { |
| 533 | compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", |
| 534 | "syscon", "simple-bus"; |
| 535 | reg = <0x020c8000 0x1000>; |
| 536 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, |
| 537 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
| 538 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; |
| 539 | |
| 540 | regulator-1p1@110 { |
| 541 | compatible = "fsl,anatop-regulator"; |
| 542 | regulator-name = "vdd1p1"; |
| 543 | regulator-min-microvolt = <800000>; |
| 544 | regulator-max-microvolt = <1375000>; |
| 545 | regulator-always-on; |
| 546 | anatop-reg-offset = <0x110>; |
| 547 | anatop-vol-bit-shift = <8>; |
| 548 | anatop-vol-bit-width = <5>; |
| 549 | anatop-min-bit-val = <4>; |
| 550 | anatop-min-voltage = <800000>; |
| 551 | anatop-max-voltage = <1375000>; |
| 552 | }; |
| 553 | |
| 554 | regulator-3p0@120 { |
| 555 | compatible = "fsl,anatop-regulator"; |
| 556 | regulator-name = "vdd3p0"; |
| 557 | regulator-min-microvolt = <2800000>; |
| 558 | regulator-max-microvolt = <3150000>; |
| 559 | regulator-always-on; |
| 560 | anatop-reg-offset = <0x120>; |
| 561 | anatop-vol-bit-shift = <8>; |
| 562 | anatop-vol-bit-width = <5>; |
| 563 | anatop-min-bit-val = <0>; |
| 564 | anatop-min-voltage = <2625000>; |
| 565 | anatop-max-voltage = <3400000>; |
| 566 | }; |
| 567 | |
| 568 | regulator-2p5@130 { |
| 569 | compatible = "fsl,anatop-regulator"; |
| 570 | regulator-name = "vdd2p5"; |
| 571 | regulator-min-microvolt = <2100000>; |
| 572 | regulator-max-microvolt = <2875000>; |
| 573 | regulator-always-on; |
| 574 | anatop-reg-offset = <0x130>; |
| 575 | anatop-vol-bit-shift = <8>; |
| 576 | anatop-vol-bit-width = <5>; |
| 577 | anatop-min-bit-val = <0>; |
| 578 | anatop-min-voltage = <2100000>; |
| 579 | anatop-max-voltage = <2875000>; |
| 580 | }; |
| 581 | |
| 582 | reg_arm: regulator-vddcore@140 { |
| 583 | compatible = "fsl,anatop-regulator"; |
Fabio Estevam | f78a597 | 2014-06-17 01:07:35 -0300 | [diff] [blame] | 584 | regulator-name = "vddarm"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 585 | regulator-min-microvolt = <725000>; |
| 586 | regulator-max-microvolt = <1450000>; |
| 587 | regulator-always-on; |
| 588 | anatop-reg-offset = <0x140>; |
| 589 | anatop-vol-bit-shift = <0>; |
| 590 | anatop-vol-bit-width = <5>; |
| 591 | anatop-delay-reg-offset = <0x170>; |
| 592 | anatop-delay-bit-shift = <24>; |
| 593 | anatop-delay-bit-width = <2>; |
| 594 | anatop-min-bit-val = <1>; |
| 595 | anatop-min-voltage = <725000>; |
| 596 | anatop-max-voltage = <1450000>; |
| 597 | }; |
| 598 | |
| 599 | reg_pcie: regulator-vddpcie@140 { |
| 600 | compatible = "fsl,anatop-regulator"; |
| 601 | regulator-name = "vddpcie"; |
| 602 | regulator-min-microvolt = <725000>; |
| 603 | regulator-max-microvolt = <1450000>; |
| 604 | anatop-reg-offset = <0x140>; |
| 605 | anatop-vol-bit-shift = <9>; |
| 606 | anatop-vol-bit-width = <5>; |
| 607 | anatop-delay-reg-offset = <0x170>; |
| 608 | anatop-delay-bit-shift = <26>; |
| 609 | anatop-delay-bit-width = <2>; |
| 610 | anatop-min-bit-val = <1>; |
| 611 | anatop-min-voltage = <725000>; |
| 612 | anatop-max-voltage = <1450000>; |
| 613 | }; |
| 614 | |
| 615 | reg_soc: regulator-vddsoc@140 { |
| 616 | compatible = "fsl,anatop-regulator"; |
| 617 | regulator-name = "vddsoc"; |
| 618 | regulator-min-microvolt = <725000>; |
| 619 | regulator-max-microvolt = <1450000>; |
| 620 | regulator-always-on; |
| 621 | anatop-reg-offset = <0x140>; |
| 622 | anatop-vol-bit-shift = <18>; |
| 623 | anatop-vol-bit-width = <5>; |
| 624 | anatop-delay-reg-offset = <0x170>; |
| 625 | anatop-delay-bit-shift = <28>; |
| 626 | anatop-delay-bit-width = <2>; |
| 627 | anatop-min-bit-val = <1>; |
| 628 | anatop-min-voltage = <725000>; |
| 629 | anatop-max-voltage = <1450000>; |
| 630 | }; |
| 631 | }; |
| 632 | |
| 633 | tempmon: tempmon { |
| 634 | compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; |
| 635 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
| 636 | fsl,tempmon = <&anatop>; |
| 637 | fsl,tempmon-data = <&ocotp>; |
| 638 | clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; |
| 639 | }; |
| 640 | |
| 641 | usbphy1: usbphy@020c9000 { |
| 642 | compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; |
| 643 | reg = <0x020c9000 0x1000>; |
| 644 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
| 645 | clocks = <&clks IMX6SX_CLK_USBPHY1>; |
| 646 | fsl,anatop = <&anatop>; |
| 647 | }; |
| 648 | |
| 649 | usbphy2: usbphy@020ca000 { |
| 650 | compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; |
| 651 | reg = <0x020ca000 0x1000>; |
| 652 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| 653 | clocks = <&clks IMX6SX_CLK_USBPHY2>; |
| 654 | fsl,anatop = <&anatop>; |
| 655 | }; |
| 656 | |
| 657 | snvs: snvs@020cc000 { |
| 658 | compatible = "fsl,sec-v4.0-mon", "simple-bus"; |
| 659 | #address-cells = <1>; |
| 660 | #size-cells = <1>; |
| 661 | ranges = <0 0x020cc000 0x4000>; |
| 662 | |
| 663 | snvs-rtc-lp@34 { |
| 664 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
| 665 | reg = <0x34 0x58>; |
| 666 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 667 | }; |
| 668 | }; |
| 669 | |
| 670 | epit1: epit@020d0000 { |
| 671 | reg = <0x020d0000 0x4000>; |
| 672 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| 673 | }; |
| 674 | |
| 675 | epit2: epit@020d4000 { |
| 676 | reg = <0x020d4000 0x4000>; |
| 677 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
| 678 | }; |
| 679 | |
| 680 | src: src@020d8000 { |
| 681 | compatible = "fsl,imx6sx-src", "fsl,imx51-src"; |
| 682 | reg = <0x020d8000 0x4000>; |
| 683 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, |
| 684 | <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 685 | #reset-cells = <1>; |
| 686 | }; |
| 687 | |
| 688 | gpc: gpc@020dc000 { |
| 689 | compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; |
| 690 | reg = <0x020dc000 0x4000>; |
| 691 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
| 692 | }; |
| 693 | |
| 694 | iomuxc: iomuxc@020e0000 { |
| 695 | compatible = "fsl,imx6sx-iomuxc"; |
| 696 | reg = <0x020e0000 0x4000>; |
| 697 | }; |
| 698 | |
| 699 | gpr: iomuxc-gpr@020e4000 { |
Anson Huang | 77e0d1c | 2014-06-23 14:04:01 +0800 | [diff] [blame^] | 700 | compatible = "fsl,imx6sx-iomuxc-gpr", |
| 701 | "fsl,imx6q-iomuxc-gpr", "syscon"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 702 | reg = <0x020e4000 0x4000>; |
| 703 | }; |
| 704 | |
| 705 | sdma: sdma@020ec000 { |
| 706 | compatible = "fsl,imx6sx-sdma"; |
| 707 | reg = <0x020ec000 0x4000>; |
| 708 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| 709 | clocks = <&clks IMX6SX_CLK_SDMA>, |
| 710 | <&clks IMX6SX_CLK_SDMA>; |
| 711 | clock-names = "ipg", "ahb"; |
| 712 | #dma-cells = <3>; |
| 713 | }; |
| 714 | }; |
| 715 | |
| 716 | aips2: aips-bus@02100000 { |
| 717 | compatible = "fsl,aips-bus", "simple-bus"; |
| 718 | #address-cells = <1>; |
| 719 | #size-cells = <1>; |
| 720 | reg = <0x02100000 0x100000>; |
| 721 | ranges; |
| 722 | |
| 723 | usbotg1: usb@02184000 { |
| 724 | compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; |
| 725 | reg = <0x02184000 0x200>; |
| 726 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
| 727 | clocks = <&clks IMX6SX_CLK_USBOH3>; |
| 728 | fsl,usbphy = <&usbphy1>; |
| 729 | fsl,usbmisc = <&usbmisc 0>; |
| 730 | fsl,anatop = <&anatop>; |
| 731 | status = "disabled"; |
| 732 | }; |
| 733 | |
| 734 | usbotg2: usb@02184200 { |
| 735 | compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; |
| 736 | reg = <0x02184200 0x200>; |
| 737 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| 738 | clocks = <&clks IMX6SX_CLK_USBOH3>; |
| 739 | fsl,usbphy = <&usbphy2>; |
| 740 | fsl,usbmisc = <&usbmisc 1>; |
| 741 | status = "disabled"; |
| 742 | }; |
| 743 | |
| 744 | usbh: usb@02184400 { |
| 745 | compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; |
| 746 | reg = <0x02184400 0x200>; |
| 747 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| 748 | clocks = <&clks IMX6SX_CLK_USBOH3>; |
| 749 | fsl,usbmisc = <&usbmisc 2>; |
| 750 | phy_type = "hsic"; |
| 751 | fsl,anatop = <&anatop>; |
| 752 | status = "disabled"; |
| 753 | }; |
| 754 | |
| 755 | usbmisc: usbmisc@02184800 { |
| 756 | #index-cells = <1>; |
| 757 | compatible = "fsl,imx6sx-usbmisc"; |
| 758 | reg = <0x02184800 0x200>; |
| 759 | clocks = <&clks IMX6SX_CLK_USBOH3>; |
| 760 | }; |
| 761 | |
| 762 | fec1: ethernet@02188000 { |
| 763 | compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; |
| 764 | reg = <0x02188000 0x4000>; |
| 765 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 766 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
| 767 | clocks = <&clks IMX6SX_CLK_ENET>, |
| 768 | <&clks IMX6SX_CLK_ENET_AHB>, |
| 769 | <&clks IMX6SX_CLK_ENET_PTP>, |
| 770 | <&clks IMX6SX_CLK_ENET_REF>, |
| 771 | <&clks IMX6SX_CLK_ENET_PTP>; |
| 772 | clock-names = "ipg", "ahb", "ptp", |
| 773 | "enet_clk_ref", "enet_out"; |
| 774 | status = "disabled"; |
| 775 | }; |
| 776 | |
| 777 | mlb: mlb@0218c000 { |
| 778 | reg = <0x0218c000 0x4000>; |
| 779 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| 780 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 781 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; |
| 782 | clocks = <&clks IMX6SX_CLK_MLB>; |
| 783 | status = "disabled"; |
| 784 | }; |
| 785 | |
| 786 | usdhc1: usdhc@02190000 { |
| 787 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; |
| 788 | reg = <0x02190000 0x4000>; |
| 789 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| 790 | clocks = <&clks IMX6SX_CLK_USDHC1>, |
| 791 | <&clks IMX6SX_CLK_USDHC1>, |
| 792 | <&clks IMX6SX_CLK_USDHC1>; |
| 793 | clock-names = "ipg", "ahb", "per"; |
| 794 | bus-width = <4>; |
| 795 | status = "disabled"; |
| 796 | }; |
| 797 | |
| 798 | usdhc2: usdhc@02194000 { |
| 799 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; |
| 800 | reg = <0x02194000 0x4000>; |
| 801 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| 802 | clocks = <&clks IMX6SX_CLK_USDHC2>, |
| 803 | <&clks IMX6SX_CLK_USDHC2>, |
| 804 | <&clks IMX6SX_CLK_USDHC2>; |
| 805 | clock-names = "ipg", "ahb", "per"; |
| 806 | bus-width = <4>; |
| 807 | status = "disabled"; |
| 808 | }; |
| 809 | |
| 810 | usdhc3: usdhc@02198000 { |
| 811 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; |
| 812 | reg = <0x02198000 0x4000>; |
| 813 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
| 814 | clocks = <&clks IMX6SX_CLK_USDHC3>, |
| 815 | <&clks IMX6SX_CLK_USDHC3>, |
| 816 | <&clks IMX6SX_CLK_USDHC3>; |
| 817 | clock-names = "ipg", "ahb", "per"; |
| 818 | bus-width = <4>; |
| 819 | status = "disabled"; |
| 820 | }; |
| 821 | |
| 822 | usdhc4: usdhc@0219c000 { |
| 823 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; |
| 824 | reg = <0x0219c000 0x4000>; |
| 825 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| 826 | clocks = <&clks IMX6SX_CLK_USDHC4>, |
| 827 | <&clks IMX6SX_CLK_USDHC4>, |
| 828 | <&clks IMX6SX_CLK_USDHC4>; |
| 829 | clock-names = "ipg", "ahb", "per"; |
| 830 | bus-width = <4>; |
| 831 | status = "disabled"; |
| 832 | }; |
| 833 | |
| 834 | i2c1: i2c@021a0000 { |
| 835 | #address-cells = <1>; |
| 836 | #size-cells = <0>; |
| 837 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; |
| 838 | reg = <0x021a0000 0x4000>; |
| 839 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| 840 | clocks = <&clks IMX6SX_CLK_I2C1>; |
| 841 | status = "disabled"; |
| 842 | }; |
| 843 | |
| 844 | i2c2: i2c@021a4000 { |
| 845 | #address-cells = <1>; |
| 846 | #size-cells = <0>; |
| 847 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; |
| 848 | reg = <0x021a4000 0x4000>; |
| 849 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| 850 | clocks = <&clks IMX6SX_CLK_I2C2>; |
| 851 | status = "disabled"; |
| 852 | }; |
| 853 | |
| 854 | i2c3: i2c@021a8000 { |
| 855 | #address-cells = <1>; |
| 856 | #size-cells = <0>; |
| 857 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; |
| 858 | reg = <0x021a8000 0x4000>; |
| 859 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 860 | clocks = <&clks IMX6SX_CLK_I2C3>; |
| 861 | status = "disabled"; |
| 862 | }; |
| 863 | |
| 864 | mmdc: mmdc@021b0000 { |
| 865 | compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; |
| 866 | reg = <0x021b0000 0x4000>; |
| 867 | }; |
| 868 | |
| 869 | fec2: ethernet@021b4000 { |
| 870 | compatible = "fsl,imx6sx-fec"; |
| 871 | reg = <0x021b4000 0x4000>; |
| 872 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| 873 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| 874 | clocks = <&clks IMX6SX_CLK_ENET>, |
| 875 | <&clks IMX6SX_CLK_ENET_AHB>, |
| 876 | <&clks IMX6SX_CLK_ENET_PTP>, |
| 877 | <&clks IMX6SX_CLK_ENET2_REF_125M>, |
| 878 | <&clks IMX6SX_CLK_ENET_PTP>; |
| 879 | clock-names = "ipg", "ahb", "ptp", |
| 880 | "enet_clk_ref", "enet_out"; |
| 881 | status = "disabled"; |
| 882 | }; |
| 883 | |
| 884 | weim: weim@021b8000 { |
| 885 | compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; |
| 886 | reg = <0x021b8000 0x4000>; |
| 887 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 888 | clocks = <&clks IMX6SX_CLK_EIM_SLOW>; |
| 889 | }; |
| 890 | |
| 891 | ocotp: ocotp@021bc000 { |
| 892 | compatible = "fsl,imx6sx-ocotp", "syscon"; |
| 893 | reg = <0x021bc000 0x4000>; |
| 894 | clocks = <&clks IMX6SX_CLK_OCOTP>; |
| 895 | }; |
| 896 | |
| 897 | sai1: sai@021d4000 { |
| 898 | compatible = "fsl,imx6sx-sai"; |
| 899 | reg = <0x021d4000 0x4000>; |
| 900 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 901 | clocks = <&clks IMX6SX_CLK_SAI1_IPG>, |
| 902 | <&clks IMX6SX_CLK_SAI1>, |
| 903 | <&clks 0>, <&clks 0>; |
| 904 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| 905 | dma-names = "rx", "tx"; |
| 906 | dmas = <&sdma 31 23 0>, <&sdma 32 23 0>; |
| 907 | dma-source = <&gpr 0 15 0 16>; |
| 908 | status = "disabled"; |
| 909 | }; |
| 910 | |
| 911 | audmux: audmux@021d8000 { |
| 912 | compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; |
| 913 | reg = <0x021d8000 0x4000>; |
| 914 | status = "disabled"; |
| 915 | }; |
| 916 | |
| 917 | sai2: sai@021dc000 { |
| 918 | compatible = "fsl,imx6sx-sai"; |
| 919 | reg = <0x021dc000 0x4000>; |
| 920 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| 921 | clocks = <&clks IMX6SX_CLK_SAI2_IPG>, |
| 922 | <&clks IMX6SX_CLK_SAI2>, |
| 923 | <&clks 0>, <&clks 0>; |
| 924 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| 925 | dma-names = "rx", "tx"; |
| 926 | dmas = <&sdma 33 23 0>, <&sdma 34 23 0>; |
| 927 | dma-source = <&gpr 0 17 0 18>; |
| 928 | status = "disabled"; |
| 929 | }; |
| 930 | |
| 931 | qspi1: qspi@021e0000 { |
| 932 | #address-cells = <1>; |
| 933 | #size-cells = <0>; |
| 934 | compatible = "fsl,imx6sx-qspi"; |
| 935 | reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; |
| 936 | reg-names = "QuadSPI", "QuadSPI-memory"; |
| 937 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| 938 | clocks = <&clks IMX6SX_CLK_QSPI1>, |
| 939 | <&clks IMX6SX_CLK_QSPI1>; |
| 940 | clock-names = "qspi_en", "qspi"; |
| 941 | status = "disabled"; |
| 942 | }; |
| 943 | |
| 944 | qspi2: qspi@021e4000 { |
| 945 | #address-cells = <1>; |
| 946 | #size-cells = <0>; |
| 947 | compatible = "fsl,imx6sx-qspi"; |
| 948 | reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; |
| 949 | reg-names = "QuadSPI", "QuadSPI-memory"; |
| 950 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
| 951 | clocks = <&clks IMX6SX_CLK_QSPI2>, |
| 952 | <&clks IMX6SX_CLK_QSPI2>; |
| 953 | clock-names = "qspi_en", "qspi"; |
| 954 | status = "disabled"; |
| 955 | }; |
| 956 | |
| 957 | uart2: serial@021e8000 { |
| 958 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; |
| 959 | reg = <0x021e8000 0x4000>; |
| 960 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
| 961 | clocks = <&clks IMX6SX_CLK_UART_IPG>, |
| 962 | <&clks IMX6SX_CLK_UART_SERIAL>; |
| 963 | clock-names = "ipg", "per"; |
| 964 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
| 965 | dma-names = "rx", "tx"; |
| 966 | status = "disabled"; |
| 967 | }; |
| 968 | |
| 969 | uart3: serial@021ec000 { |
| 970 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; |
| 971 | reg = <0x021ec000 0x4000>; |
| 972 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| 973 | clocks = <&clks IMX6SX_CLK_UART_IPG>, |
| 974 | <&clks IMX6SX_CLK_UART_SERIAL>; |
| 975 | clock-names = "ipg", "per"; |
| 976 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
| 977 | dma-names = "rx", "tx"; |
| 978 | status = "disabled"; |
| 979 | }; |
| 980 | |
| 981 | uart4: serial@021f0000 { |
| 982 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; |
| 983 | reg = <0x021f0000 0x4000>; |
| 984 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| 985 | clocks = <&clks IMX6SX_CLK_UART_IPG>, |
| 986 | <&clks IMX6SX_CLK_UART_SERIAL>; |
| 987 | clock-names = "ipg", "per"; |
| 988 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
| 989 | dma-names = "rx", "tx"; |
| 990 | status = "disabled"; |
| 991 | }; |
| 992 | |
| 993 | uart5: serial@021f4000 { |
| 994 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; |
| 995 | reg = <0x021f4000 0x4000>; |
| 996 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| 997 | clocks = <&clks IMX6SX_CLK_UART_IPG>, |
| 998 | <&clks IMX6SX_CLK_UART_SERIAL>; |
| 999 | clock-names = "ipg", "per"; |
| 1000 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
| 1001 | dma-names = "rx", "tx"; |
| 1002 | status = "disabled"; |
| 1003 | }; |
| 1004 | |
| 1005 | i2c4: i2c@021f8000 { |
| 1006 | #address-cells = <1>; |
| 1007 | #size-cells = <0>; |
| 1008 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; |
| 1009 | reg = <0x021f8000 0x4000>; |
| 1010 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| 1011 | clocks = <&clks IMX6SX_CLK_I2C4>; |
| 1012 | status = "disabled"; |
| 1013 | }; |
| 1014 | }; |
| 1015 | |
| 1016 | aips3: aips-bus@02200000 { |
| 1017 | compatible = "fsl,aips-bus", "simple-bus"; |
| 1018 | #address-cells = <1>; |
| 1019 | #size-cells = <1>; |
| 1020 | reg = <0x02200000 0x100000>; |
| 1021 | ranges; |
| 1022 | |
| 1023 | spba-bus@02200000 { |
| 1024 | compatible = "fsl,spba-bus", "simple-bus"; |
| 1025 | #address-cells = <1>; |
| 1026 | #size-cells = <1>; |
| 1027 | reg = <0x02240000 0x40000>; |
| 1028 | ranges; |
| 1029 | |
| 1030 | csi1: csi@02214000 { |
| 1031 | reg = <0x02214000 0x4000>; |
| 1032 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 1033 | clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, |
| 1034 | <&clks IMX6SX_CLK_CSI>, |
| 1035 | <&clks IMX6SX_CLK_DCIC1>; |
| 1036 | clock-names = "disp-axi", "csi_mclk", "dcic"; |
| 1037 | status = "disabled"; |
| 1038 | }; |
| 1039 | |
| 1040 | pxp: pxp@02218000 { |
| 1041 | reg = <0x02218000 0x4000>; |
| 1042 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| 1043 | clocks = <&clks IMX6SX_CLK_PXP_AXI>, |
| 1044 | <&clks IMX6SX_CLK_DISPLAY_AXI>; |
| 1045 | clock-names = "pxp-axi", "disp-axi"; |
| 1046 | status = "disabled"; |
| 1047 | }; |
| 1048 | |
| 1049 | csi2: csi@0221c000 { |
| 1050 | reg = <0x0221c000 0x4000>; |
| 1051 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| 1052 | clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, |
| 1053 | <&clks IMX6SX_CLK_CSI>, |
| 1054 | <&clks IMX6SX_CLK_DCIC2>; |
| 1055 | clock-names = "disp-axi", "csi_mclk", "dcic"; |
| 1056 | status = "disabled"; |
| 1057 | }; |
| 1058 | |
| 1059 | lcdif1: lcdif@02220000 { |
| 1060 | reg = <0x02220000 0x4000>; |
| 1061 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| 1062 | clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, |
| 1063 | <&clks IMX6SX_CLK_LCDIF_APB>, |
| 1064 | <&clks IMX6SX_CLK_DISPLAY_AXI>; |
| 1065 | clock-names = "pix", "axi", "disp_axi"; |
| 1066 | status = "disabled"; |
| 1067 | }; |
| 1068 | |
| 1069 | lcdif2: lcdif@02224000 { |
| 1070 | reg = <0x02224000 0x4000>; |
| 1071 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| 1072 | clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, |
| 1073 | <&clks IMX6SX_CLK_LCDIF_APB>, |
| 1074 | <&clks IMX6SX_CLK_DISPLAY_AXI>; |
| 1075 | clock-names = "pix", "axi", "disp_axi"; |
| 1076 | status = "disabled"; |
| 1077 | }; |
| 1078 | |
| 1079 | vadc: vadc@02228000 { |
| 1080 | reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; |
| 1081 | reg-names = "vadc-vafe", "vadc-vdec"; |
| 1082 | clocks = <&clks IMX6SX_CLK_VADC>, |
| 1083 | <&clks IMX6SX_CLK_CSI>; |
| 1084 | clock-names = "vadc", "csi"; |
| 1085 | status = "disabled"; |
| 1086 | }; |
| 1087 | }; |
| 1088 | |
| 1089 | adc1: adc@02280000 { |
| 1090 | compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; |
| 1091 | reg = <0x02280000 0x4000>; |
| 1092 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| 1093 | clocks = <&clks IMX6SX_CLK_IPG>; |
| 1094 | clock-names = "adc"; |
| 1095 | status = "disabled"; |
| 1096 | }; |
| 1097 | |
| 1098 | adc2: adc@02284000 { |
| 1099 | compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; |
| 1100 | reg = <0x02284000 0x4000>; |
| 1101 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
| 1102 | clocks = <&clks IMX6SX_CLK_IPG>; |
| 1103 | clock-names = "adc"; |
| 1104 | status = "disabled"; |
| 1105 | }; |
| 1106 | |
| 1107 | wdog3: wdog@02288000 { |
| 1108 | compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; |
| 1109 | reg = <0x02288000 0x4000>; |
| 1110 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| 1111 | clocks = <&clks IMX6SX_CLK_DUMMY>; |
| 1112 | status = "disabled"; |
| 1113 | }; |
| 1114 | |
| 1115 | ecspi5: ecspi@0228c000 { |
| 1116 | #address-cells = <1>; |
| 1117 | #size-cells = <0>; |
| 1118 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; |
| 1119 | reg = <0x0228c000 0x4000>; |
| 1120 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; |
| 1121 | clocks = <&clks IMX6SX_CLK_ECSPI5>, |
| 1122 | <&clks IMX6SX_CLK_ECSPI5>; |
| 1123 | clock-names = "ipg", "per"; |
| 1124 | status = "disabled"; |
| 1125 | }; |
| 1126 | |
| 1127 | uart6: serial@022a0000 { |
| 1128 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; |
| 1129 | reg = <0x022a0000 0x4000>; |
| 1130 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| 1131 | clocks = <&clks IMX6SX_CLK_UART_IPG>, |
| 1132 | <&clks IMX6SX_CLK_UART_SERIAL>; |
| 1133 | clock-names = "ipg", "per"; |
| 1134 | dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; |
| 1135 | dma-names = "rx", "tx"; |
| 1136 | status = "disabled"; |
| 1137 | }; |
| 1138 | |
| 1139 | pwm5: pwm@022a4000 { |
| 1140 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 1141 | reg = <0x022a4000 0x4000>; |
| 1142 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 1143 | clocks = <&clks IMX6SX_CLK_PWM5>, |
| 1144 | <&clks IMX6SX_CLK_PWM5>; |
| 1145 | clock-names = "ipg", "per"; |
| 1146 | #pwm-cells = <2>; |
| 1147 | }; |
| 1148 | |
| 1149 | pwm6: pwm@022a8000 { |
| 1150 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 1151 | reg = <0x022a8000 0x4000>; |
| 1152 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| 1153 | clocks = <&clks IMX6SX_CLK_PWM6>, |
| 1154 | <&clks IMX6SX_CLK_PWM6>; |
| 1155 | clock-names = "ipg", "per"; |
| 1156 | #pwm-cells = <2>; |
| 1157 | }; |
| 1158 | |
| 1159 | pwm7: pwm@022ac000 { |
| 1160 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 1161 | reg = <0x022ac000 0x4000>; |
| 1162 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| 1163 | clocks = <&clks IMX6SX_CLK_PWM7>, |
| 1164 | <&clks IMX6SX_CLK_PWM7>; |
| 1165 | clock-names = "ipg", "per"; |
| 1166 | #pwm-cells = <2>; |
| 1167 | }; |
| 1168 | |
| 1169 | pwm8: pwm@0022b0000 { |
| 1170 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 1171 | reg = <0x0022b0000 0x4000>; |
| 1172 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 1173 | clocks = <&clks IMX6SX_CLK_PWM8>, |
| 1174 | <&clks IMX6SX_CLK_PWM8>; |
| 1175 | clock-names = "ipg", "per"; |
| 1176 | #pwm-cells = <2>; |
| 1177 | }; |
| 1178 | }; |
| 1179 | |
| 1180 | pcie: pcie@0x08000000 { |
| 1181 | compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; |
| 1182 | reg = <0x08ffc000 0x4000>; /* DBI */ |
| 1183 | #address-cells = <3>; |
| 1184 | #size-cells = <2>; |
| 1185 | device_type = "pci"; |
| 1186 | /* configuration space */ |
| 1187 | ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 |
| 1188 | /* downstream I/O */ |
| 1189 | 0x81000000 0 0 0x08f80000 0 0x00010000 |
| 1190 | /* non-prefetchable memory */ |
| 1191 | 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; |
| 1192 | num-lanes = <1>; |
| 1193 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
| 1194 | clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, |
| 1195 | <&clks IMX6SX_CLK_PCIE_AXI>, |
| 1196 | <&clks IMX6SX_CLK_LVDS1_OUT>, |
| 1197 | <&clks IMX6SX_CLK_DISPLAY_AXI>; |
| 1198 | clock-names = "pcie_ref_125m", "pcie_axi", |
| 1199 | "lvds_gate", "display_axi"; |
| 1200 | status = "disabled"; |
| 1201 | }; |
| 1202 | }; |
| 1203 | }; |