blob: 924e156a85abdf61627336e41e97283393e8709f [file] [log] [blame]
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -08001# Put here option for CPU selection and depending optimization
2if !X86_ELAN
3
4choice
5 prompt "Processor family"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +01006 default M686 if X86_32
7 default GENERIC_CPU if X86_64
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -08008
9config M386
10 bool "386"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010011 depends on X86_32 && !UML
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080012 ---help---
13 This is the processor type of your CPU. This information is used for
14 optimizing purposes. In order to compile a kernel that can run on
15 all x86 CPU types (albeit not optimally fast), you can specify
16 "386" here.
17
18 The kernel will not necessarily run on earlier architectures than
19 the one you have chosen, e.g. a Pentium optimized kernel will run on
20 a PPro, but not necessarily on a i486.
21
22 Here are the settings recommended for greatest speed:
23 - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI
Dmitri Vorobievf7f17a62008-04-21 00:47:55 +040024 486DLC/DLC2, and UMC 486SX-S. Only "386" kernels will run on a 386
25 class machine.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080026 - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
27 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
28 - "586" for generic Pentium CPUs lacking the TSC
29 (time stamp counter) register.
30 - "Pentium-Classic" for the Intel Pentium.
31 - "Pentium-MMX" for the Intel Pentium MMX.
32 - "Pentium-Pro" for the Intel Pentium Pro.
33 - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
34 - "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
35 - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
36 - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
37 - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
38 - "Crusoe" for the Transmeta Crusoe series.
39 - "Efficeon" for the Transmeta Efficeon series.
40 - "Winchip-C6" for original IDT Winchip.
Krzysztof Helt69d45dd2008-09-28 21:28:15 +020041 - "Winchip-2" for IDT Winchips with 3dNow! capabilities.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080042 - "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
Jordan Crousef90b8112006-01-06 00:12:14 -080043 - "Geode GX/LX" For AMD Geode GX and LX processors.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080044 - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
Egry Gabor48a12042006-06-26 18:47:15 +020045 - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above).
Simon Arlott0949be32007-05-02 19:27:05 +020046 - "VIA C7" for VIA C7.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080047
48 If you don't know what to do, choose "386".
49
50config M486
51 bool "486"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010052 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010053 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080054 Select this for a 486 series processor, either Intel or one of the
55 compatible processors from AMD, Cyrix, IBM, or Intel. Includes DX,
56 DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or
57 U5S.
58
59config M586
60 bool "586/K5/5x86/6x86/6x86MX"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010061 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010062 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080063 Select this for an 586 or 686 series processor such as the AMD K5,
64 the Cyrix 5x86, 6x86 and 6x86MX. This choice does not
65 assume the RDTSC (Read Time Stamp Counter) instruction.
66
67config M586TSC
68 bool "Pentium-Classic"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010069 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010070 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080071 Select this for a Pentium Classic processor with the RDTSC (Read
72 Time Stamp Counter) instruction for benchmarking.
73
74config M586MMX
75 bool "Pentium-MMX"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010076 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010077 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080078 Select this for a Pentium with the MMX graphics/multimedia
79 extended instructions.
80
81config M686
82 bool "Pentium-Pro"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010083 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010084 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080085 Select this for Intel Pentium Pro chips. This enables the use of
86 Pentium Pro extended instructions, and disables the init-time guard
87 against the f00f bug found in earlier Pentiums.
88
89config MPENTIUMII
90 bool "Pentium-II/Celeron(pre-Coppermine)"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010091 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010092 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080093 Select this for Intel chips based on the Pentium-II and
94 pre-Coppermine Celeron core. This option enables an unaligned
95 copy optimization, compiles the kernel with optimization flags
96 tailored for the chip, and applies any applicable Pentium Pro
97 optimizations.
98
99config MPENTIUMIII
100 bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100101 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100102 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800103 Select this for Intel chips based on the Pentium-III and
104 Celeron-Coppermine core. This option enables use of some
105 extended prefetch instructions in addition to the Pentium II
106 extensions.
107
108config MPENTIUMM
109 bool "Pentium M"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100110 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100111 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800112 Select this for Intel Pentium M (not Pentium-4 M)
113 notebook chips.
114
115config MPENTIUM4
Andi Kleenc55d92d2006-12-07 02:14:09 +0100116 bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100117 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100118 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800119 Select this for Intel Pentium 4 chips. This includes the
Oliver Pinter75e38082007-10-17 18:04:36 +0200120 Pentium 4, Pentium D, P4-based Celeron and Xeon, and
121 Pentium-4 M (not Pentium M) chips. This option enables compile
122 flags optimized for the chip, uses the correct cache line size, and
123 applies any applicable optimizations.
124
125 CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 )
126
127 Select this for:
128 Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename:
129 -Willamette
130 -Northwood
131 -Mobile Pentium 4
132 -Mobile Pentium 4 M
133 -Extreme Edition (Gallatin)
134 -Prescott
135 -Prescott 2M
136 -Cedar Mill
137 -Presler
138 -Smithfiled
139 Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename:
140 -Foster
141 -Prestonia
142 -Gallatin
143 -Nocona
144 -Irwindale
145 -Cranford
146 -Potomac
147 -Paxville
148 -Dempsey
149
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800150
151config MK6
152 bool "K6/K6-II/K6-III"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100153 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100154 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800155 Select this for an AMD K6-family processor. Enables use of
156 some extended instructions, and passes appropriate optimization
157 flags to GCC.
158
159config MK7
160 bool "Athlon/Duron/K7"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100161 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100162 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800163 Select this for an AMD Athlon K7-family processor. Enables use of
164 some extended instructions, and passes appropriate optimization
165 flags to GCC.
166
167config MK8
168 bool "Opteron/Athlon64/Hammer/K8"
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100169 ---help---
Borislav Petkov36723bf2009-02-04 21:44:04 +0100170 Select this for an AMD Opteron or Athlon64 Hammer-family processor.
171 Enables use of some extended instructions, and passes appropriate
172 optimization flags to GCC.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800173
174config MCRUSOE
175 bool "Crusoe"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100176 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100177 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800178 Select this for a Transmeta Crusoe processor. Treats the processor
179 like a 586 with TSC, and sets some GCC optimization flags (like a
180 Pentium Pro with no alignment requirements).
181
182config MEFFICEON
183 bool "Efficeon"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100184 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100185 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800186 Select this for a Transmeta Efficeon processor.
187
188config MWINCHIPC6
189 bool "Winchip-C6"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100190 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100191 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800192 Select this for an IDT Winchip C6 chip. Linux and GCC
193 treat this chip as a 586TSC with some extended instructions
194 and alignment requirements.
195
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800196config MWINCHIP3D
Krzysztof Helt69d45dd2008-09-28 21:28:15 +0200197 bool "Winchip-2/Winchip-2A/Winchip-3"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100198 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100199 ---help---
Krzysztof Helt69d45dd2008-09-28 21:28:15 +0200200 Select this for an IDT Winchip-2, 2A or 3. Linux and GCC
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800201 treat this chip as a 586TSC with some extended instructions
David Sterba3dde6ad2007-05-09 07:12:20 +0200202 and alignment requirements. Also enable out of order memory
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800203 stores for this CPU, which can increase performance of some
204 operations.
205
206config MGEODEGX1
207 bool "GeodeGX1"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100208 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100209 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800210 Select this for a Geode GX1 (Cyrix MediaGX) chip.
211
Jordan Crousef90b8112006-01-06 00:12:14 -0800212config MGEODE_LX
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100213 bool "Geode GX/LX"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100214 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100215 ---help---
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100216 Select this for AMD Geode GX and LX processors.
Jordan Crousef90b8112006-01-06 00:12:14 -0800217
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800218config MCYRIXIII
219 bool "CyrixIII/VIA-C3"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100220 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100221 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800222 Select this for a Cyrix III or C3 chip. Presently Linux and GCC
223 treat this chip as a generic 586. Whilst the CPU is 686 class,
224 it lacks the cmov extension which gcc assumes is present when
225 generating 686 code.
226 Note that Nehemiah (Model 9) and above will not boot with this
227 kernel due to them lacking the 3DNow! instructions used in earlier
228 incarnations of the CPU.
229
230config MVIAC3_2
231 bool "VIA C3-2 (Nehemiah)"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100232 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100233 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800234 Select this for a VIA C3 "Nehemiah". Selecting this enables usage
235 of SSE and tells gcc to treat the CPU as a 686.
236 Note, this kernel will not boot on older (pre model 9) C3s.
237
Simon Arlott0949be32007-05-02 19:27:05 +0200238config MVIAC7
239 bool "VIA C7"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100240 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100241 ---help---
Simon Arlott0949be32007-05-02 19:27:05 +0200242 Select this for a VIA C7. Selecting this uses the correct cache
243 shift and tells gcc to treat the CPU as a 686.
244
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100245config MPSC
246 bool "Intel P4 / older Netburst based Xeon"
247 depends on X86_64
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100248 ---help---
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100249 Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
250 Xeon CPUs with Intel 64bit which is compatible with x86-64.
251 Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100252 Netburst core and shouldn't use this option. You can distinguish them
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100253 using the cpu family field
254 in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
255
256config MCORE2
257 bool "Core 2/newer Xeon"
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100258 ---help---
Borislav Petkov36723bf2009-02-04 21:44:04 +0100259
260 Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
261 53xx) CPUs. You can distinguish newer from older Xeons by the CPU
262 family in /proc/cpuinfo. Newer ones have 6 and older ones 15
263 (not a typo)
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100264
265config GENERIC_CPU
266 bool "Generic-x86-64"
267 depends on X86_64
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100268 ---help---
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100269 Generic x86-64 CPU.
270 Run equally well on all x86-64 CPUs.
271
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800272endchoice
273
274config X86_GENERIC
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100275 bool "Generic x86 support"
276 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100277 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800278 Instead of just including optimizations for the selected
279 x86 variant (e.g. PII, Crusoe or Athlon), include some more
280 generic optimizations as well. This will make the kernel
281 perform better on x86 CPUs other than that selected.
282
283 This is really intended for distributors who need more
284 generic optimizations.
285
286endif
287
Ingo Molnaracbaa932008-04-30 08:58:27 +0200288config X86_CPU
289 def_bool y
290 select GENERIC_FIND_FIRST_BIT
291 select GENERIC_FIND_NEXT_BIT
292
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800293#
294# Define implied options from the CPU selection here
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100295config X86_L1_CACHE_BYTES
296 int
Ingo Molnarace6c6c2009-01-21 10:32:44 +0100297 default "128" if MPSC
298 default "64" if GENERIC_CPU || MK8 || MCORE2 || X86_32
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100299
300config X86_INTERNODE_CACHE_BYTES
301 int
302 default "4096" if X86_VSMP
303 default X86_L1_CACHE_BYTES if !X86_VSMP
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100304
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800305config X86_CMPXCHG
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100306 def_bool X86_64 || (X86_32 && !M386)
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800307
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800308config X86_L1_CACHE_SHIFT
309 int
Ingo Molnar0a2a18b72009-01-12 23:37:16 +0100310 default "7" if MPENTIUM4 || MPSC
Jordan Crousef90b8112006-01-06 00:12:14 -0800311 default "4" if X86_ELAN || M486 || M386 || MGEODEGX1
Krzysztof Helt69d45dd2008-09-28 21:28:15 +0200312 default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
Ingo Molnar0a2a18b72009-01-12 23:37:16 +0100313 default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MVIAC7 || X86_GENERIC || GENERIC_CPU
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800314
Andi Kleenc7f81c92007-05-02 19:27:20 +0200315config X86_XADD
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100316 def_bool y
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100317 depends on X86_32 && !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800318
319config X86_PPRO_FENCE
Nick Pigginfb0328e2008-01-30 13:32:31 +0100320 bool "PentiumPro memory ordering errata workaround"
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800321 depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100322 ---help---
Borislav Petkov36723bf2009-02-04 21:44:04 +0100323 Old PentiumPro multiprocessor systems had errata that could cause
324 memory operations to violate the x86 ordering standard in rare cases.
325 Enabling this option will attempt to work around some (but not all)
326 occurances of this problem, at the cost of much heavier spinlock and
327 memory barrier operations.
Nick Pigginfb0328e2008-01-30 13:32:31 +0100328
Borislav Petkov36723bf2009-02-04 21:44:04 +0100329 If unsure, say n here. Even distro kernels should think twice before
330 enabling this: there are few systems, and an unlikely bug.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800331
332config X86_F00F_BUG
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100333 def_bool y
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800334 depends on M586MMX || M586TSC || M586 || M486 || M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800335
336config X86_WP_WORKS_OK
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100337 def_bool y
Glauber Costa293e6a22008-06-25 11:40:42 -0300338 depends on !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800339
340config X86_INVLPG
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100341 def_bool y
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100342 depends on X86_32 && !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800343
344config X86_BSWAP
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100345 def_bool y
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100346 depends on X86_32 && !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800347
348config X86_POPAD_OK
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100349 def_bool y
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100350 depends on X86_32 && !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800351
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800352config X86_ALIGNMENT_16
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100353 def_bool y
Krzysztof Helt69d45dd2008-09-28 21:28:15 +0200354 depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800355
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800356config X86_INTEL_USERCOPY
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100357 def_bool y
Andi Kleenc55d92d2006-12-07 02:14:09 +0100358 depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800359
360config X86_USE_PPRO_CHECKSUM
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100361 def_bool y
Krzysztof Helt69d45dd2008-09-28 21:28:15 +0200362 depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX || MCORE2
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800363
364config X86_USE_3DNOW
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100365 def_bool y
Paolo 'Blaisorblade' Giarrusso1b4ad242006-10-11 01:21:35 -0700366 depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800367
368config X86_OOSTORE
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100369 def_bool y
Krzysztof Helt69d45dd2008-09-28 21:28:15 +0200370 depends on (MWINCHIP3D || MWINCHIPC6) && MTRR
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800371
H. Peter Anvin959b3be2008-02-14 14:56:45 -0800372#
373# P6_NOPs are a relatively minor optimization that require a family >=
374# 6 processor, except that it is broken on certain VIA chips.
375# Furthermore, AMD chips prefer a totally different sequence of NOPs
Linus Torvalds14469a82008-09-05 09:30:14 -0700376# (which work on all CPUs). In addition, it looks like Virtual PC
377# does not understand them.
378#
379# As a result, disallow these if we're not compiling for X86_64 (these
380# NOPs do work on all x86-64 capable chips); the list of processors in
381# the right-hand clause are the cores that benefit from this optimization.
H. Peter Anvin959b3be2008-02-14 14:56:45 -0800382#
H. Peter Anvin7343b3b2008-02-14 14:52:05 -0800383config X86_P6_NOP
384 def_bool y
Linus Torvalds14469a82008-09-05 09:30:14 -0700385 depends on X86_64
386 depends on (MCORE2 || MPENTIUM4 || MPSC)
H. Peter Anvin7343b3b2008-02-14 14:52:05 -0800387
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800388config X86_TSC
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100389 def_bool y
Krzysztof Helt69d45dd2008-09-28 21:28:15 +0200390 depends on ((MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2) && !X86_NUMAQ) || X86_64
Andi Kleenc7f81c92007-05-02 19:27:20 +0200391
Jan Beulichf8096f92008-04-22 16:27:29 +0100392config X86_CMPXCHG64
393 def_bool y
394 depends on X86_PAE || X86_64
395
Andi Kleenc7f81c92007-05-02 19:27:20 +0200396# this should be set for all -march=.. options where the compiler
397# generates cmov.
398config X86_CMOV
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100399 def_bool y
Jan Beulich79aa10d2008-08-29 12:50:38 +0100400 depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64)
Andi Kleenc7f81c92007-05-02 19:27:20 +0200401
H. Peter Anvinde32e042007-07-11 12:18:30 -0700402config X86_MINIMUM_CPU_FAMILY
Andi Kleenc7f81c92007-05-02 19:27:20 +0200403 int
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100404 default "64" if X86_64
H. Peter Anvin7343b3b2008-02-14 14:52:05 -0800405 default "6" if X86_32 && X86_P6_NOP
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100406 default "4" if X86_32 && (X86_XADD || X86_CMPXCHG || X86_BSWAP || X86_WP_WORKS_OK)
H. Peter Anvinde32e042007-07-11 12:18:30 -0700407 default "3"
Andi Kleenc7f81c92007-05-02 19:27:20 +0200408
Roland McGrath0a049bb2008-01-30 13:30:54 +0100409config X86_DEBUGCTLMSR
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100410 def_bool y
Al Viro5641f1f2009-01-05 17:19:02 +0000411 depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486 || M386) && !UML
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200412
413menuconfig PROCESSOR_SELECT
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200414 bool "Supported processor vendors" if EMBEDDED
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100415 ---help---
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200416 This lets you choose what x86 vendor support code your kernel
417 will include.
418
Yinghai Lu879d7922008-09-09 16:40:37 -0700419config CPU_SUP_INTEL
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200420 default y
421 bool "Support Intel processors" if PROCESSOR_SELECT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100422 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200423 This enables detection, tunings and quirks for Intel processors
424
425 You need this enabled if you want your kernel to run on an
426 Intel CPU. Disabling this option on other types of CPUs
427 makes the kernel a tiny bit smaller. Disabling it on an Intel
428 CPU might render the kernel unbootable.
429
430 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200431
432config CPU_SUP_CYRIX_32
433 default y
434 bool "Support Cyrix processors" if PROCESSOR_SELECT
435 depends on !64BIT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100436 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200437 This enables detection, tunings and quirks for Cyrix processors
438
439 You need this enabled if you want your kernel to run on a
440 Cyrix CPU. Disabling this option on other types of CPUs
441 makes the kernel a tiny bit smaller. Disabling it on a Cyrix
442 CPU might render the kernel unbootable.
443
444 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200445
Yinghai Luff731522008-09-07 17:58:56 -0700446config CPU_SUP_AMD
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200447 default y
448 bool "Support AMD processors" if PROCESSOR_SELECT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100449 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200450 This enables detection, tunings and quirks for AMD processors
451
452 You need this enabled if you want your kernel to run on an
453 AMD CPU. Disabling this option on other types of CPUs
454 makes the kernel a tiny bit smaller. Disabling it on an AMD
455 CPU might render the kernel unbootable.
456
457 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200458
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100459config CPU_SUP_CENTAUR
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200460 default y
461 bool "Support Centaur processors" if PROCESSOR_SELECT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100462 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200463 This enables detection, tunings and quirks for Centaur processors
464
465 You need this enabled if you want your kernel to run on a
466 Centaur CPU. Disabling this option on other types of CPUs
467 makes the kernel a tiny bit smaller. Disabling it on a Centaur
468 CPU might render the kernel unbootable.
469
470 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200471
472config CPU_SUP_TRANSMETA_32
473 default y
474 bool "Support Transmeta processors" if PROCESSOR_SELECT
475 depends on !64BIT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100476 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200477 This enables detection, tunings and quirks for Transmeta processors
478
479 You need this enabled if you want your kernel to run on a
480 Transmeta CPU. Disabling this option on other types of CPUs
481 makes the kernel a tiny bit smaller. Disabling it on a Transmeta
482 CPU might render the kernel unbootable.
483
484 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200485
486config CPU_SUP_UMC_32
487 default y
488 bool "Support UMC processors" if PROCESSOR_SELECT
489 depends on !64BIT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100490 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200491 This enables detection, tunings and quirks for UMC processors
492
493 You need this enabled if you want your kernel to run on a
494 UMC CPU. Disabling this option on other types of CPUs
495 makes the kernel a tiny bit smaller. Disabling it on a UMC
496 CPU might render the kernel unbootable.
497
498 If unsure, say N.
Ingo Molnar81faaae2008-09-10 08:20:51 +0200499
Markus Metzger93fa7632008-04-08 11:01:58 +0200500config X86_DS
Markus Metzger531f6ed2008-10-17 09:09:27 +0200501 def_bool X86_PTRACE_BTS
502 depends on X86_DEBUGCTLMSR
Markus Metzger1e9b51c2008-11-25 09:24:15 +0100503 select HAVE_HW_BRANCH_TRACER
Markus Metzger93fa7632008-04-08 11:01:58 +0200504
505config X86_PTRACE_BTS
Markus Metzger531f6ed2008-10-17 09:09:27 +0200506 bool "Branch Trace Store"
Markus Metzger93fa7632008-04-08 11:01:58 +0200507 default y
Markus Metzger531f6ed2008-10-17 09:09:27 +0200508 depends on X86_DEBUGCTLMSR
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100509 ---help---
Markus Metzger531f6ed2008-10-17 09:09:27 +0200510 This adds a ptrace interface to the hardware's branch trace store.
511
512 Debuggers may use it to collect an execution trace of the debugged
513 application in order to answer the question 'how did I get here?'.
514 Debuggers may trace user mode as well as kernel mode.
515
516 Say Y unless there is no application development on this machine
517 and you want to save a small amount of code size.