blob: 7323f1b493ad561da03debeded54c495b1da9dae [file] [log] [blame]
Doug Thompsoncfe40fd2009-05-04 19:25:34 +02001/*
2 * AMD64 class Memory Controller kernel module
3 *
4 * Copyright (c) 2009 SoftwareBitMaker.
5 * Copyright (c) 2009 Advanced Micro Devices, Inc.
6 *
7 * This file may be distributed under the terms of the
8 * GNU General Public License.
9 *
10 * Originally Written by Thayne Harbaugh
11 *
12 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
13 * - K8 CPU Revision D and greater support
14 *
15 * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>:
16 * - Module largely rewritten, with new (and hopefully correct)
17 * code for dealing with node and chip select interleaving,
18 * various code cleanup, and bug fixes
19 * - Added support for memory hoisting using DRAM hole address
20 * register
21 *
22 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
23 * -K8 Rev (1207) revision support added, required Revision
24 * specific mini-driver code to support Rev F as well as
25 * prior revisions
26 *
27 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
28 * -Family 10h revision support added. New PCI Device IDs,
29 * indicating new changes. Actual registers modified
30 * were slight, less than the Rev E to Rev F transition
31 * but changing the PCI Device ID was the proper thing to
32 * do, as it provides for almost automactic family
33 * detection. The mods to Rev F required more family
34 * information detection.
35 *
36 * Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>:
37 * - misc fixes and code cleanups
38 *
39 * This module is based on the following documents
40 * (available from http://www.amd.com/):
41 *
42 * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
43 * Opteron Processors
44 * AMD publication #: 26094
45 *` Revision: 3.26
46 *
47 * Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
48 * Processors
49 * AMD publication #: 32559
50 * Revision: 3.00
51 * Issue Date: May 2006
52 *
53 * Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
54 * Processors
55 * AMD publication #: 31116
56 * Revision: 3.00
57 * Issue Date: September 07, 2007
58 *
59 * Sections in the first 2 documents are no longer in sync with each other.
60 * The Family 10h BKDG was totally re-written from scratch with a new
61 * presentation model.
62 * Therefore, comments that refer to a Document section might be off.
63 */
64
65#include <linux/module.h>
66#include <linux/ctype.h>
67#include <linux/init.h>
68#include <linux/pci.h>
69#include <linux/pci_ids.h>
70#include <linux/slab.h>
71#include <linux/mmzone.h>
72#include <linux/edac.h>
Doug Thompsonf9431992009-04-27 19:46:08 +020073#include <asm/msr.h>
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020074#include "edac_core.h"
Borislav Petkov47ca08a2010-09-27 15:30:39 +020075#include "mce_amd.h"
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020076
Borislav Petkov24f9a7f2010-10-07 18:29:15 +020077#define amd64_debug(fmt, arg...) \
78 edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020079
Borislav Petkov24f9a7f2010-10-07 18:29:15 +020080#define amd64_info(fmt, arg...) \
81 edac_printk(KERN_INFO, "amd64", fmt, ##arg)
82
83#define amd64_notice(fmt, arg...) \
84 edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)
85
86#define amd64_warn(fmt, arg...) \
87 edac_printk(KERN_WARNING, "amd64", fmt, ##arg)
88
89#define amd64_err(fmt, arg...) \
90 edac_printk(KERN_ERR, "amd64", fmt, ##arg)
91
92#define amd64_mc_warn(mci, fmt, arg...) \
93 edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
94
95#define amd64_mc_err(mci, fmt, arg...) \
96 edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020097
98/*
99 * Throughout the comments in this code, the following terms are used:
100 *
101 * SysAddr, DramAddr, and InputAddr
102 *
103 * These terms come directly from the amd64 documentation
104 * (AMD publication #26094). They are defined as follows:
105 *
106 * SysAddr:
107 * This is a physical address generated by a CPU core or a device
108 * doing DMA. If generated by a CPU core, a SysAddr is the result of
109 * a virtual to physical address translation by the CPU core's address
110 * translation mechanism (MMU).
111 *
112 * DramAddr:
113 * A DramAddr is derived from a SysAddr by subtracting an offset that
114 * depends on which node the SysAddr maps to and whether the SysAddr
115 * is within a range affected by memory hoisting. The DRAM Base
116 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
117 * determine which node a SysAddr maps to.
118 *
119 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
120 * is within the range of addresses specified by this register, then
121 * a value x from the DHAR is subtracted from the SysAddr to produce a
122 * DramAddr. Here, x represents the base address for the node that
123 * the SysAddr maps to plus an offset due to memory hoisting. See
124 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and
125 * sys_addr_to_dram_addr() below for more information.
126 *
127 * If the SysAddr is not affected by the DHAR then a value y is
128 * subtracted from the SysAddr to produce a DramAddr. Here, y is the
129 * base address for the node that the SysAddr maps to. See section
130 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
131 * information.
132 *
133 * InputAddr:
134 * A DramAddr is translated to an InputAddr before being passed to the
135 * memory controller for the node that the DramAddr is associated
136 * with. The memory controller then maps the InputAddr to a csrow.
137 * If node interleaving is not in use, then the InputAddr has the same
138 * value as the DramAddr. Otherwise, the InputAddr is produced by
139 * discarding the bits used for node interleaving from the DramAddr.
140 * See section 3.4.4 for more information.
141 *
142 * The memory controller for a given node uses its DRAM CS Base and
143 * DRAM CS Mask registers to map an InputAddr to a csrow. See
144 * sections 3.5.4 and 3.5.5 for more information.
145 */
146
Borislav Petkov24f9a7f2010-10-07 18:29:15 +0200147#define EDAC_AMD64_VERSION "v3.3.0"
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200148#define EDAC_MOD_STR "amd64_edac"
149
150/* Extended Model from CPUID, for CPU Revision numbers */
Borislav Petkov1433eb92009-10-21 13:44:36 +0200151#define K8_REV_D 1
152#define K8_REV_E 2
153#define K8_REV_F 4
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200154
155/* Hardware limit on ChipSelect rows per MC and processors per system */
Borislav Petkov7f19bf72010-10-21 18:52:53 +0200156#define NUM_CHIPSELECTS 8
157#define DRAM_RANGES 8
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200158
Borislav Petkovf6d6ae92009-11-03 15:29:26 +0100159#define ON true
160#define OFF false
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200161
162/*
Borislav Petkov11c75ea2010-11-29 19:49:02 +0100163 * Create a contiguous bitmask starting at bit position @lo and ending at
164 * position @hi. For example
165 *
166 * GENMASK(21, 39) gives us the 64bit vector 0x000000ffffe00000.
167 */
168#define GENMASK(lo, hi) (((1ULL << ((hi) - (lo) + 1)) - 1) << (lo))
169
170/*
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200171 * PCI-defined configuration space registers
172 */
173
174
175/*
176 * Function 1 - Address Map
177 */
Borislav Petkov7f19bf72010-10-21 18:52:53 +0200178#define DRAM_BASE_LO 0x40
179#define DRAM_LIMIT_LO 0x44
180
181#define dram_intlv_en(pvt, i) ((pvt->ranges[i].base.lo >> 8) & 0x7)
182#define dram_rw(pvt, i) (pvt->ranges[i].base.lo & 0x3)
183#define dram_intlv_sel(pvt, i) ((pvt->ranges[i].lim.lo >> 8) & 0x7)
184#define dram_dst_node(pvt, i) (pvt->ranges[i].lim.lo & 0x7)
185
Borislav Petkovbc21fa52010-11-11 17:29:13 +0100186#define DHAR 0xf0
Borislav Petkovc8e518d2010-12-10 19:49:19 +0100187#define dhar_valid(pvt) ((pvt)->dhar & BIT(0))
188#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
189#define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
190#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200191
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200192 /* NOTE: Extra mask bit vs K8 */
Borislav Petkovc8e518d2010-12-10 19:49:19 +0100193#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200194
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200195#define DCT_CFG_SEL 0x10C
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200196
Borislav Petkov7f19bf72010-10-21 18:52:53 +0200197#define DRAM_BASE_HI 0x140
198#define DRAM_LIMIT_HI 0x144
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200199
200
201/*
202 * Function 2 - DRAM controller
203 */
Borislav Petkov11c75ea2010-11-29 19:49:02 +0100204#define DCSB0 0x40
205#define DCSB1 0x140
206#define DCSB_CS_ENABLE BIT(0)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200207
Borislav Petkov11c75ea2010-11-29 19:49:02 +0100208#define DCSM0 0x60
209#define DCSM1 0x160
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200210
Borislav Petkov11c75ea2010-11-29 19:49:02 +0100211#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200212
213#define DBAM0 0x80
214#define DBAM1 0x180
215
216/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
217#define DBAM_DIMM(i, reg) ((((reg) >> (4*i))) & 0xF)
218
219#define DBAM_MAX_VALUE 11
220
Borislav Petkovcb328502010-12-22 14:28:24 +0100221#define DCLR0 0x90
222#define DCLR1 0x190
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200223#define REVE_WIDTH_128 BIT(16)
224#define F10_WIDTH_128 BIT(11)
225
Borislav Petkovcb328502010-12-22 14:28:24 +0100226#define DCHR0 0x94
227#define DCHR1 0x194
Borislav Petkov1433eb92009-10-21 13:44:36 +0200228#define DDR3_MODE BIT(8)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200229
230#define F10_DCTL_SEL_LOW 0x110
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200231#define dct_sel_baseaddr(pvt) ((pvt->dct_sel_low) & 0xFFFFF800)
232#define dct_sel_interleave_addr(pvt) (((pvt->dct_sel_low) >> 6) & 0x3)
233#define dct_high_range_enabled(pvt) (pvt->dct_sel_low & BIT(0))
234#define dct_interleave_enabled(pvt) (pvt->dct_sel_low & BIT(2))
Borislav Petkovcb328502010-12-22 14:28:24 +0100235
236#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_low & BIT(4)))
237
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200238#define dct_data_intlv_enabled(pvt) (pvt->dct_sel_low & BIT(5))
239#define dct_dram_enabled(pvt) (pvt->dct_sel_low & BIT(8))
240#define dct_memory_cleared(pvt) (pvt->dct_sel_low & BIT(10))
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200241
242#define F10_DCTL_SEL_HIGH 0x114
243
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200244/*
245 * Function 3 - Misc Control
246 */
247#define K8_NBCTL 0x40
248
249/* Correctable ECC error reporting enable */
250#define K8_NBCTL_CECCEn BIT(0)
251
252/* UnCorrectable ECC error reporting enable */
253#define K8_NBCTL_UECCEn BIT(1)
254
255#define K8_NBCFG 0x44
256#define K8_NBCFG_CHIPKILL BIT(23)
257#define K8_NBCFG_ECC_ENABLE BIT(22)
258
259#define K8_NBSL 0x48
260
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200261/* Family F10h: Normalized Extended Error Codes */
262#define F10_NBSL_EXT_ERR_RES 0x0
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200263#define F10_NBSL_EXT_ERR_ECC 0x8
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200264
265/* Next two are overloaded values */
266#define F10_NBSL_EXT_ERR_LINK_PROTO 0xB
267#define F10_NBSL_EXT_ERR_L3_PROTO 0xB
268
269#define F10_NBSL_EXT_ERR_NB_ARRAY 0xC
270#define F10_NBSL_EXT_ERR_DRAM_PARITY 0xD
271#define F10_NBSL_EXT_ERR_LINK_RETRY 0xE
272
273/* Next two are overloaded values */
274#define F10_NBSL_EXT_ERR_GART_WALK 0xF
275#define F10_NBSL_EXT_ERR_DEV_WALK 0xF
276
277/* 0x10 to 0x1B: Reserved */
278#define F10_NBSL_EXT_ERR_L3_DATA 0x1C
279#define F10_NBSL_EXT_ERR_L3_TAG 0x1D
280#define F10_NBSL_EXT_ERR_L3_LRU 0x1E
281
282/* K8: Normalized Extended Error Codes */
283#define K8_NBSL_EXT_ERR_ECC 0x0
284#define K8_NBSL_EXT_ERR_CRC 0x1
285#define K8_NBSL_EXT_ERR_SYNC 0x2
286#define K8_NBSL_EXT_ERR_MST 0x3
287#define K8_NBSL_EXT_ERR_TGT 0x4
288#define K8_NBSL_EXT_ERR_GART 0x5
289#define K8_NBSL_EXT_ERR_RMW 0x6
290#define K8_NBSL_EXT_ERR_WDT 0x7
291#define K8_NBSL_EXT_ERR_CHIPKILL_ECC 0x8
292#define K8_NBSL_EXT_ERR_DRAM_PARITY 0xD
293
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200294/*
295 * The following are for BUS type errors AFTER values have been normalized by
296 * shifting right
297 */
298#define K8_NBSL_PP_SRC 0x0
299#define K8_NBSL_PP_RES 0x1
300#define K8_NBSL_PP_OBS 0x2
301#define K8_NBSL_PP_GENERIC 0x3
302
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200303#define EXTRACT_ERR_CPU_MAP(x) ((x) & 0xF)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200304
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200305#define K8_NBEAL 0x50
306#define K8_NBEAH 0x54
307#define K8_SCRCTRL 0x58
308
309#define F10_NB_CFG_LOW 0x88
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200310
311#define F10_ONLINE_SPARE 0xB0
312#define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1))
313#define F10_ONLINE_SPARE_SWAPDONE1(x) ((x) & BIT(3))
314#define F10_ONLINE_SPARE_BADDRAM_CS0(x) (((x) >> 4) & 0x00000007)
315#define F10_ONLINE_SPARE_BADDRAM_CS1(x) (((x) >> 8) & 0x00000007)
316
317#define F10_NB_ARRAY_ADDR 0xB8
318
319#define F10_NB_ARRAY_DRAM_ECC 0x80000000
320
321/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
322#define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1)
323
324#define F10_NB_ARRAY_DATA 0xBC
325
326#define SET_NB_DRAM_INJECTION_WRITE(word, bits) \
327 (BIT(((word) & 0xF) + 20) | \
Borislav Petkov94baaee2009-09-24 11:05:30 +0200328 BIT(17) | bits)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200329
330#define SET_NB_DRAM_INJECTION_READ(word, bits) \
331 (BIT(((word) & 0xF) + 20) | \
Borislav Petkov94baaee2009-09-24 11:05:30 +0200332 BIT(16) | bits)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200333
334#define K8_NBCAP 0xE8
335#define K8_NBCAP_CORES (BIT(12)|BIT(13))
336#define K8_NBCAP_CHIPKILL BIT(4)
337#define K8_NBCAP_SECDED BIT(3)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200338#define K8_NBCAP_DCT_DUAL BIT(0)
339
Borislav Petkovad6a32e2010-03-09 12:46:00 +0100340#define EXT_NB_MCA_CFG 0x180
341
Borislav Petkovf6d6ae92009-11-03 15:29:26 +0100342/* MSRs */
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200343#define K8_MSR_MCGCTL_NBE BIT(4)
344
345#define K8_MSR_MC4CTL 0x0410
346#define K8_MSR_MC4STAT 0x0411
347#define K8_MSR_MC4ADDR 0x0412
348
349/* AMD sets the first MC device at device ID 0x18. */
Borislav Petkov37da0452009-06-10 17:36:57 +0200350static inline int get_node_id(struct pci_dev *pdev)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200351{
352 return PCI_SLOT(pdev->devfn) - 0x18;
353}
354
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200355enum amd_families {
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200356 K8_CPUS = 0,
357 F10_CPUS,
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200358 F15_CPUS,
359 NUM_FAMILIES,
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200360};
361
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200362/* Error injection control structure */
363struct error_injection {
364 u32 section;
365 u32 word;
366 u32 bit_map;
367};
368
Borislav Petkov7f19bf72010-10-21 18:52:53 +0200369/* low and high part of PCI config space regs */
370struct reg_pair {
371 u32 lo, hi;
372};
373
374/*
375 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
376 */
377struct dram_range {
378 struct reg_pair base;
379 struct reg_pair lim;
380};
381
Borislav Petkov11c75ea2010-11-29 19:49:02 +0100382/* A DCT chip selects collection */
383struct chip_select {
384 u32 csbases[NUM_CHIPSELECTS];
385 u8 b_cnt;
386
387 u32 csmasks[NUM_CHIPSELECTS];
388 u8 m_cnt;
389};
390
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200391struct amd64_pvt {
Borislav Petkovb8cfa022010-10-01 19:35:38 +0200392 struct low_ops *ops;
393
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200394 /* pci_device handles which we utilize */
Borislav Petkov8d5b5d92010-10-01 20:11:07 +0200395 struct pci_dev *F1, *F2, *F3;
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200396
397 int mc_node_id; /* MC index of this MC node */
398 int ext_model; /* extended model value of this node */
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200399 int channel_count;
400
401 /* Raw registers */
402 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
403 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
404 u32 dchr0; /* DRAM Configuration High DCT0 reg */
405 u32 dchr1; /* DRAM Configuration High DCT1 reg */
406 u32 nbcap; /* North Bridge Capabilities */
407 u32 nbcfg; /* F10 North Bridge Configuration */
408 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
409 u32 dhar; /* DRAM Hoist reg */
410 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
411 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
412
Borislav Petkov11c75ea2010-11-29 19:49:02 +0100413 /* one for each DCT */
414 struct chip_select csels[2];
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200415
Borislav Petkov7f19bf72010-10-21 18:52:53 +0200416 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
417 struct dram_range ranges[DRAM_RANGES];
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200418
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200419 u64 top_mem; /* top of memory below 4GB */
420 u64 top_mem2; /* top of memory above 4GB */
421
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200422 u32 dct_sel_low; /* DRAM Controller Select Low Reg */
423 u32 dct_sel_hi; /* DRAM Controller Select High Reg */
424 u32 online_spare; /* On-Line spare Reg */
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200425
Borislav Petkovad6a32e2010-03-09 12:46:00 +0100426 /* x4 or x8 syndromes in use */
427 u8 syn_type;
428
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200429 /* temp storage for when input is received from sysfs */
Borislav Petkovef44cc42009-07-23 14:45:48 +0200430 struct err_regs ctl_error_info;
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200431
432 /* place to store error injection parameters prior to issue */
433 struct error_injection injection;
434
Borislav Petkov395ae782010-10-01 18:38:19 +0200435 /* DCT per-family scrubrate setting */
436 u32 min_scrubrate;
437
Borislav Petkov0092b202010-10-01 19:20:05 +0200438 /* family name this instance is running on */
439 const char *ctl_name;
440
Borislav Petkovae7bb7c2010-10-14 16:01:30 +0200441};
442
Borislav Petkov7f19bf72010-10-21 18:52:53 +0200443static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i)
444{
445 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
446
447 if (boot_cpu_data.x86 == 0xf)
448 return addr;
449
450 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
451}
452
453static inline u64 get_dram_limit(struct amd64_pvt *pvt, unsigned i)
454{
455 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
456
457 if (boot_cpu_data.x86 == 0xf)
458 return lim;
459
460 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
461}
462
Borislav Petkovae7bb7c2010-10-14 16:01:30 +0200463/*
464 * per-node ECC settings descriptor
465 */
466struct ecc_settings {
467 u32 old_nbctl;
468 bool nbctl_valid;
469
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200470 struct flags {
Borislav Petkovd95cf4d2010-02-24 14:49:47 +0100471 unsigned long nb_mce_enable:1;
472 unsigned long nb_ecc_prev:1;
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200473 } flags;
474};
475
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200476extern const char *tt_msgs[4];
477extern const char *ll_msgs[4];
478extern const char *rrrr_msgs[16];
479extern const char *to_msgs[2];
480extern const char *pp_msgs[4];
481extern const char *ii_msgs[4];
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200482extern const char *htlink_msgs[8];
483
Doug Thompson7d6034d2009-04-27 20:01:01 +0200484#ifdef CONFIG_EDAC_DEBUG
Borislav Petkov9cdeb402010-09-02 18:33:24 +0200485#define NUM_DBG_ATTRS 5
Doug Thompson7d6034d2009-04-27 20:01:01 +0200486#else
487#define NUM_DBG_ATTRS 0
488#endif
489
490#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
491#define NUM_INJ_ATTRS 5
492#else
493#define NUM_INJ_ATTRS 0
494#endif
495
496extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
497 amd64_inj_attrs[NUM_INJ_ATTRS];
498
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200499/*
500 * Each of the PCI Device IDs types have their own set of hardware accessor
501 * functions and per device encoding/decoding logic.
502 */
503struct low_ops {
Borislav Petkov1433eb92009-10-21 13:44:36 +0200504 int (*early_channel_count) (struct amd64_pvt *pvt);
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200505
Borislav Petkov1433eb92009-10-21 13:44:36 +0200506 u64 (*get_error_address) (struct mem_ctl_info *mci,
507 struct err_regs *info);
Borislav Petkov1433eb92009-10-21 13:44:36 +0200508 void (*read_dram_ctl_register) (struct amd64_pvt *pvt);
509 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci,
510 struct err_regs *info, u64 SystemAddr);
511 int (*dbam_to_cs) (struct amd64_pvt *pvt, int cs_mode);
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200512 int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset,
513 u32 *val, const char *func);
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200514};
515
516struct amd64_family_type {
517 const char *ctl_name;
Borislav Petkov8d5b5d92010-10-01 20:11:07 +0200518 u16 f1_id, f3_id;
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200519 struct low_ops ops;
520};
521
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200522int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
523 u32 val, const char *func);
Borislav Petkov6ba5dcd2009-10-13 19:26:55 +0200524
525#define amd64_read_pci_cfg(pdev, offset, val) \
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200526 __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
527
528#define amd64_write_pci_cfg(pdev, offset, val) \
529 __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
530
531#define amd64_read_dct_pci_cfg(pvt, offset, val) \
532 pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)
Borislav Petkov6ba5dcd2009-10-13 19:26:55 +0200533
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200534/*
535 * For future CPU versions, verify the following as new 'slow' rates appear and
536 * modify the necessary skip values for the supported CPU.
537 */
538#define K8_MIN_SCRUB_RATE_BITS 0x0
539#define F10_MIN_SCRUB_RATE_BITS 0x5
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200540
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200541int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
542 u64 *hole_offset, u64 *hole_size);