blob: c39d09874e74d5d05a7f59e437ce5bb1f0ef8199 [file] [log] [blame]
Stephen Boydd33faa92014-01-15 10:47:30 -08001/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-msm8974.h>
26#include <dt-bindings/reset/qcom,gcc-msm8974.h>
27
Stephen Boyd49fc8252014-03-21 17:59:37 -070028#include "common.h"
Stephen Boydd33faa92014-01-15 10:47:30 -080029#include "clk-regmap.h"
30#include "clk-pll.h"
31#include "clk-rcg.h"
32#include "clk-branch.h"
33#include "reset.h"
34
Georgi Djakov293d2e972015-03-20 18:30:26 +020035enum {
36 P_XO,
37 P_GPLL0,
38 P_GPLL1,
39 P_GPLL4,
40};
Stephen Boydd33faa92014-01-15 10:47:30 -080041
Georgi Djakov293d2e972015-03-20 18:30:26 +020042static const struct parent_map gcc_xo_gpll0_map[] = {
43 { P_XO, 0 },
44 { P_GPLL0, 1 }
Stephen Boydd33faa92014-01-15 10:47:30 -080045};
46
47static const char *gcc_xo_gpll0[] = {
48 "xo",
49 "gpll0_vote",
50};
51
Georgi Djakov293d2e972015-03-20 18:30:26 +020052static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
53 { P_XO, 0 },
54 { P_GPLL0, 1 },
55 { P_GPLL4, 5 }
Stephen Boydc6858412014-05-16 16:07:13 -070056};
57
58static const char *gcc_xo_gpll0_gpll4[] = {
59 "xo",
60 "gpll0_vote",
61 "gpll4_vote",
62};
63
Stephen Boydd33faa92014-01-15 10:47:30 -080064#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
65
66static struct clk_pll gpll0 = {
67 .l_reg = 0x0004,
68 .m_reg = 0x0008,
69 .n_reg = 0x000c,
70 .config_reg = 0x0014,
71 .mode_reg = 0x0000,
72 .status_reg = 0x001c,
73 .status_bit = 17,
74 .clkr.hw.init = &(struct clk_init_data){
75 .name = "gpll0",
76 .parent_names = (const char *[]){ "xo" },
77 .num_parents = 1,
78 .ops = &clk_pll_ops,
79 },
80};
81
82static struct clk_regmap gpll0_vote = {
83 .enable_reg = 0x1480,
84 .enable_mask = BIT(0),
85 .hw.init = &(struct clk_init_data){
86 .name = "gpll0_vote",
87 .parent_names = (const char *[]){ "gpll0" },
88 .num_parents = 1,
89 .ops = &clk_pll_vote_ops,
90 },
91};
92
93static struct clk_rcg2 config_noc_clk_src = {
94 .cmd_rcgr = 0x0150,
95 .hid_width = 5,
96 .parent_map = gcc_xo_gpll0_map,
97 .clkr.hw.init = &(struct clk_init_data){
98 .name = "config_noc_clk_src",
99 .parent_names = gcc_xo_gpll0,
100 .num_parents = 2,
101 .ops = &clk_rcg2_ops,
102 },
103};
104
105static struct clk_rcg2 periph_noc_clk_src = {
106 .cmd_rcgr = 0x0190,
107 .hid_width = 5,
108 .parent_map = gcc_xo_gpll0_map,
109 .clkr.hw.init = &(struct clk_init_data){
110 .name = "periph_noc_clk_src",
111 .parent_names = gcc_xo_gpll0,
112 .num_parents = 2,
113 .ops = &clk_rcg2_ops,
114 },
115};
116
117static struct clk_rcg2 system_noc_clk_src = {
118 .cmd_rcgr = 0x0120,
119 .hid_width = 5,
120 .parent_map = gcc_xo_gpll0_map,
121 .clkr.hw.init = &(struct clk_init_data){
122 .name = "system_noc_clk_src",
123 .parent_names = gcc_xo_gpll0,
124 .num_parents = 2,
125 .ops = &clk_rcg2_ops,
126 },
127};
128
129static struct clk_pll gpll1 = {
130 .l_reg = 0x0044,
131 .m_reg = 0x0048,
132 .n_reg = 0x004c,
133 .config_reg = 0x0054,
134 .mode_reg = 0x0040,
135 .status_reg = 0x005c,
136 .status_bit = 17,
137 .clkr.hw.init = &(struct clk_init_data){
138 .name = "gpll1",
139 .parent_names = (const char *[]){ "xo" },
140 .num_parents = 1,
141 .ops = &clk_pll_ops,
142 },
143};
144
145static struct clk_regmap gpll1_vote = {
146 .enable_reg = 0x1480,
147 .enable_mask = BIT(1),
148 .hw.init = &(struct clk_init_data){
149 .name = "gpll1_vote",
150 .parent_names = (const char *[]){ "gpll1" },
151 .num_parents = 1,
152 .ops = &clk_pll_vote_ops,
153 },
154};
155
Stephen Boydc6858412014-05-16 16:07:13 -0700156static struct clk_pll gpll4 = {
157 .l_reg = 0x1dc4,
158 .m_reg = 0x1dc8,
159 .n_reg = 0x1dcc,
160 .config_reg = 0x1dd4,
161 .mode_reg = 0x1dc0,
162 .status_reg = 0x1ddc,
163 .status_bit = 17,
164 .clkr.hw.init = &(struct clk_init_data){
165 .name = "gpll4",
166 .parent_names = (const char *[]){ "xo" },
167 .num_parents = 1,
168 .ops = &clk_pll_ops,
169 },
170};
171
172static struct clk_regmap gpll4_vote = {
173 .enable_reg = 0x1480,
174 .enable_mask = BIT(4),
175 .hw.init = &(struct clk_init_data){
176 .name = "gpll4_vote",
177 .parent_names = (const char *[]){ "gpll4" },
178 .num_parents = 1,
179 .ops = &clk_pll_vote_ops,
180 },
181};
182
Stephen Boydd33faa92014-01-15 10:47:30 -0800183static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
184 F(125000000, P_GPLL0, 1, 5, 24),
185 { }
186};
187
188static struct clk_rcg2 usb30_master_clk_src = {
189 .cmd_rcgr = 0x03d4,
190 .mnd_width = 8,
191 .hid_width = 5,
192 .parent_map = gcc_xo_gpll0_map,
193 .freq_tbl = ftbl_gcc_usb30_master_clk,
194 .clkr.hw.init = &(struct clk_init_data){
195 .name = "usb30_master_clk_src",
196 .parent_names = gcc_xo_gpll0,
197 .num_parents = 2,
198 .ops = &clk_rcg2_ops,
199 },
200};
201
202static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
203 F(19200000, P_XO, 1, 0, 0),
204 F(37500000, P_GPLL0, 16, 0, 0),
205 F(50000000, P_GPLL0, 12, 0, 0),
206 { }
207};
208
209static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
210 .cmd_rcgr = 0x0660,
211 .hid_width = 5,
212 .parent_map = gcc_xo_gpll0_map,
213 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
214 .clkr.hw.init = &(struct clk_init_data){
215 .name = "blsp1_qup1_i2c_apps_clk_src",
216 .parent_names = gcc_xo_gpll0,
217 .num_parents = 2,
218 .ops = &clk_rcg2_ops,
219 },
220};
221
222static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
223 F(960000, P_XO, 10, 1, 2),
224 F(4800000, P_XO, 4, 0, 0),
225 F(9600000, P_XO, 2, 0, 0),
226 F(15000000, P_GPLL0, 10, 1, 4),
227 F(19200000, P_XO, 1, 0, 0),
228 F(25000000, P_GPLL0, 12, 1, 2),
229 F(50000000, P_GPLL0, 12, 0, 0),
230 { }
231};
232
233static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
234 .cmd_rcgr = 0x064c,
235 .mnd_width = 8,
236 .hid_width = 5,
237 .parent_map = gcc_xo_gpll0_map,
238 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
239 .clkr.hw.init = &(struct clk_init_data){
240 .name = "blsp1_qup1_spi_apps_clk_src",
241 .parent_names = gcc_xo_gpll0,
242 .num_parents = 2,
243 .ops = &clk_rcg2_ops,
244 },
245};
246
247static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
248 .cmd_rcgr = 0x06e0,
249 .hid_width = 5,
250 .parent_map = gcc_xo_gpll0_map,
251 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
252 .clkr.hw.init = &(struct clk_init_data){
253 .name = "blsp1_qup2_i2c_apps_clk_src",
254 .parent_names = gcc_xo_gpll0,
255 .num_parents = 2,
256 .ops = &clk_rcg2_ops,
257 },
258};
259
260static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
261 .cmd_rcgr = 0x06cc,
262 .mnd_width = 8,
263 .hid_width = 5,
264 .parent_map = gcc_xo_gpll0_map,
265 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
266 .clkr.hw.init = &(struct clk_init_data){
267 .name = "blsp1_qup2_spi_apps_clk_src",
268 .parent_names = gcc_xo_gpll0,
269 .num_parents = 2,
270 .ops = &clk_rcg2_ops,
271 },
272};
273
274static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
275 .cmd_rcgr = 0x0760,
276 .hid_width = 5,
277 .parent_map = gcc_xo_gpll0_map,
278 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
279 .clkr.hw.init = &(struct clk_init_data){
280 .name = "blsp1_qup3_i2c_apps_clk_src",
281 .parent_names = gcc_xo_gpll0,
282 .num_parents = 2,
283 .ops = &clk_rcg2_ops,
284 },
285};
286
287static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
288 .cmd_rcgr = 0x074c,
289 .mnd_width = 8,
290 .hid_width = 5,
291 .parent_map = gcc_xo_gpll0_map,
292 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
293 .clkr.hw.init = &(struct clk_init_data){
294 .name = "blsp1_qup3_spi_apps_clk_src",
295 .parent_names = gcc_xo_gpll0,
296 .num_parents = 2,
297 .ops = &clk_rcg2_ops,
298 },
299};
300
301static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
302 .cmd_rcgr = 0x07e0,
303 .hid_width = 5,
304 .parent_map = gcc_xo_gpll0_map,
305 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
306 .clkr.hw.init = &(struct clk_init_data){
307 .name = "blsp1_qup4_i2c_apps_clk_src",
308 .parent_names = gcc_xo_gpll0,
309 .num_parents = 2,
310 .ops = &clk_rcg2_ops,
311 },
312};
313
314static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
315 .cmd_rcgr = 0x07cc,
316 .mnd_width = 8,
317 .hid_width = 5,
318 .parent_map = gcc_xo_gpll0_map,
319 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
320 .clkr.hw.init = &(struct clk_init_data){
321 .name = "blsp1_qup4_spi_apps_clk_src",
322 .parent_names = gcc_xo_gpll0,
323 .num_parents = 2,
324 .ops = &clk_rcg2_ops,
325 },
326};
327
328static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
329 .cmd_rcgr = 0x0860,
330 .hid_width = 5,
331 .parent_map = gcc_xo_gpll0_map,
332 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
333 .clkr.hw.init = &(struct clk_init_data){
334 .name = "blsp1_qup5_i2c_apps_clk_src",
335 .parent_names = gcc_xo_gpll0,
336 .num_parents = 2,
337 .ops = &clk_rcg2_ops,
338 },
339};
340
341static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
342 .cmd_rcgr = 0x084c,
343 .mnd_width = 8,
344 .hid_width = 5,
345 .parent_map = gcc_xo_gpll0_map,
346 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
347 .clkr.hw.init = &(struct clk_init_data){
348 .name = "blsp1_qup5_spi_apps_clk_src",
349 .parent_names = gcc_xo_gpll0,
350 .num_parents = 2,
351 .ops = &clk_rcg2_ops,
352 },
353};
354
355static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
356 .cmd_rcgr = 0x08e0,
357 .hid_width = 5,
358 .parent_map = gcc_xo_gpll0_map,
359 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
360 .clkr.hw.init = &(struct clk_init_data){
361 .name = "blsp1_qup6_i2c_apps_clk_src",
362 .parent_names = gcc_xo_gpll0,
363 .num_parents = 2,
364 .ops = &clk_rcg2_ops,
365 },
366};
367
368static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
369 .cmd_rcgr = 0x08cc,
370 .mnd_width = 8,
371 .hid_width = 5,
372 .parent_map = gcc_xo_gpll0_map,
373 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
374 .clkr.hw.init = &(struct clk_init_data){
375 .name = "blsp1_qup6_spi_apps_clk_src",
376 .parent_names = gcc_xo_gpll0,
377 .num_parents = 2,
378 .ops = &clk_rcg2_ops,
379 },
380};
381
382static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
383 F(3686400, P_GPLL0, 1, 96, 15625),
384 F(7372800, P_GPLL0, 1, 192, 15625),
385 F(14745600, P_GPLL0, 1, 384, 15625),
386 F(16000000, P_GPLL0, 5, 2, 15),
387 F(19200000, P_XO, 1, 0, 0),
388 F(24000000, P_GPLL0, 5, 1, 5),
389 F(32000000, P_GPLL0, 1, 4, 75),
390 F(40000000, P_GPLL0, 15, 0, 0),
391 F(46400000, P_GPLL0, 1, 29, 375),
392 F(48000000, P_GPLL0, 12.5, 0, 0),
393 F(51200000, P_GPLL0, 1, 32, 375),
394 F(56000000, P_GPLL0, 1, 7, 75),
395 F(58982400, P_GPLL0, 1, 1536, 15625),
396 F(60000000, P_GPLL0, 10, 0, 0),
397 F(63160000, P_GPLL0, 9.5, 0, 0),
398 { }
399};
400
401static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
402 .cmd_rcgr = 0x068c,
403 .mnd_width = 16,
404 .hid_width = 5,
405 .parent_map = gcc_xo_gpll0_map,
406 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
407 .clkr.hw.init = &(struct clk_init_data){
408 .name = "blsp1_uart1_apps_clk_src",
409 .parent_names = gcc_xo_gpll0,
410 .num_parents = 2,
411 .ops = &clk_rcg2_ops,
412 },
413};
414
415static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
416 .cmd_rcgr = 0x070c,
417 .mnd_width = 16,
418 .hid_width = 5,
419 .parent_map = gcc_xo_gpll0_map,
420 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
421 .clkr.hw.init = &(struct clk_init_data){
422 .name = "blsp1_uart2_apps_clk_src",
423 .parent_names = gcc_xo_gpll0,
424 .num_parents = 2,
425 .ops = &clk_rcg2_ops,
426 },
427};
428
429static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
430 .cmd_rcgr = 0x078c,
431 .mnd_width = 16,
432 .hid_width = 5,
433 .parent_map = gcc_xo_gpll0_map,
434 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
435 .clkr.hw.init = &(struct clk_init_data){
436 .name = "blsp1_uart3_apps_clk_src",
437 .parent_names = gcc_xo_gpll0,
438 .num_parents = 2,
439 .ops = &clk_rcg2_ops,
440 },
441};
442
443static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
444 .cmd_rcgr = 0x080c,
445 .mnd_width = 16,
446 .hid_width = 5,
447 .parent_map = gcc_xo_gpll0_map,
448 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
449 .clkr.hw.init = &(struct clk_init_data){
450 .name = "blsp1_uart4_apps_clk_src",
451 .parent_names = gcc_xo_gpll0,
452 .num_parents = 2,
453 .ops = &clk_rcg2_ops,
454 },
455};
456
457static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
458 .cmd_rcgr = 0x088c,
459 .mnd_width = 16,
460 .hid_width = 5,
461 .parent_map = gcc_xo_gpll0_map,
462 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
463 .clkr.hw.init = &(struct clk_init_data){
464 .name = "blsp1_uart5_apps_clk_src",
465 .parent_names = gcc_xo_gpll0,
466 .num_parents = 2,
467 .ops = &clk_rcg2_ops,
468 },
469};
470
471static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
472 .cmd_rcgr = 0x090c,
473 .mnd_width = 16,
474 .hid_width = 5,
475 .parent_map = gcc_xo_gpll0_map,
476 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
477 .clkr.hw.init = &(struct clk_init_data){
478 .name = "blsp1_uart6_apps_clk_src",
479 .parent_names = gcc_xo_gpll0,
480 .num_parents = 2,
481 .ops = &clk_rcg2_ops,
482 },
483};
484
485static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
486 .cmd_rcgr = 0x09a0,
487 .hid_width = 5,
488 .parent_map = gcc_xo_gpll0_map,
489 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
490 .clkr.hw.init = &(struct clk_init_data){
491 .name = "blsp2_qup1_i2c_apps_clk_src",
492 .parent_names = gcc_xo_gpll0,
493 .num_parents = 2,
494 .ops = &clk_rcg2_ops,
495 },
496};
497
498static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
499 .cmd_rcgr = 0x098c,
500 .mnd_width = 8,
501 .hid_width = 5,
502 .parent_map = gcc_xo_gpll0_map,
503 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
504 .clkr.hw.init = &(struct clk_init_data){
505 .name = "blsp2_qup1_spi_apps_clk_src",
506 .parent_names = gcc_xo_gpll0,
507 .num_parents = 2,
508 .ops = &clk_rcg2_ops,
509 },
510};
511
512static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
513 .cmd_rcgr = 0x0a20,
514 .hid_width = 5,
515 .parent_map = gcc_xo_gpll0_map,
516 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
517 .clkr.hw.init = &(struct clk_init_data){
518 .name = "blsp2_qup2_i2c_apps_clk_src",
519 .parent_names = gcc_xo_gpll0,
520 .num_parents = 2,
521 .ops = &clk_rcg2_ops,
522 },
523};
524
525static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
526 .cmd_rcgr = 0x0a0c,
527 .mnd_width = 8,
528 .hid_width = 5,
529 .parent_map = gcc_xo_gpll0_map,
530 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
531 .clkr.hw.init = &(struct clk_init_data){
532 .name = "blsp2_qup2_spi_apps_clk_src",
533 .parent_names = gcc_xo_gpll0,
534 .num_parents = 2,
535 .ops = &clk_rcg2_ops,
536 },
537};
538
539static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
540 .cmd_rcgr = 0x0aa0,
541 .hid_width = 5,
542 .parent_map = gcc_xo_gpll0_map,
543 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
544 .clkr.hw.init = &(struct clk_init_data){
545 .name = "blsp2_qup3_i2c_apps_clk_src",
546 .parent_names = gcc_xo_gpll0,
547 .num_parents = 2,
548 .ops = &clk_rcg2_ops,
549 },
550};
551
552static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
553 .cmd_rcgr = 0x0a8c,
554 .mnd_width = 8,
555 .hid_width = 5,
556 .parent_map = gcc_xo_gpll0_map,
557 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
558 .clkr.hw.init = &(struct clk_init_data){
559 .name = "blsp2_qup3_spi_apps_clk_src",
560 .parent_names = gcc_xo_gpll0,
561 .num_parents = 2,
562 .ops = &clk_rcg2_ops,
563 },
564};
565
566static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
567 .cmd_rcgr = 0x0b20,
568 .hid_width = 5,
569 .parent_map = gcc_xo_gpll0_map,
570 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
571 .clkr.hw.init = &(struct clk_init_data){
572 .name = "blsp2_qup4_i2c_apps_clk_src",
573 .parent_names = gcc_xo_gpll0,
574 .num_parents = 2,
575 .ops = &clk_rcg2_ops,
576 },
577};
578
579static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
580 .cmd_rcgr = 0x0b0c,
581 .mnd_width = 8,
582 .hid_width = 5,
583 .parent_map = gcc_xo_gpll0_map,
584 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
585 .clkr.hw.init = &(struct clk_init_data){
586 .name = "blsp2_qup4_spi_apps_clk_src",
587 .parent_names = gcc_xo_gpll0,
588 .num_parents = 2,
589 .ops = &clk_rcg2_ops,
590 },
591};
592
593static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
594 .cmd_rcgr = 0x0ba0,
595 .hid_width = 5,
596 .parent_map = gcc_xo_gpll0_map,
597 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
598 .clkr.hw.init = &(struct clk_init_data){
599 .name = "blsp2_qup5_i2c_apps_clk_src",
600 .parent_names = gcc_xo_gpll0,
601 .num_parents = 2,
602 .ops = &clk_rcg2_ops,
603 },
604};
605
606static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
607 .cmd_rcgr = 0x0b8c,
608 .mnd_width = 8,
609 .hid_width = 5,
610 .parent_map = gcc_xo_gpll0_map,
611 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
612 .clkr.hw.init = &(struct clk_init_data){
613 .name = "blsp2_qup5_spi_apps_clk_src",
614 .parent_names = gcc_xo_gpll0,
615 .num_parents = 2,
616 .ops = &clk_rcg2_ops,
617 },
618};
619
620static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
621 .cmd_rcgr = 0x0c20,
622 .hid_width = 5,
623 .parent_map = gcc_xo_gpll0_map,
624 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
625 .clkr.hw.init = &(struct clk_init_data){
626 .name = "blsp2_qup6_i2c_apps_clk_src",
627 .parent_names = gcc_xo_gpll0,
628 .num_parents = 2,
629 .ops = &clk_rcg2_ops,
630 },
631};
632
633static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
634 .cmd_rcgr = 0x0c0c,
635 .mnd_width = 8,
636 .hid_width = 5,
637 .parent_map = gcc_xo_gpll0_map,
638 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
639 .clkr.hw.init = &(struct clk_init_data){
640 .name = "blsp2_qup6_spi_apps_clk_src",
641 .parent_names = gcc_xo_gpll0,
642 .num_parents = 2,
643 .ops = &clk_rcg2_ops,
644 },
645};
646
647static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
648 .cmd_rcgr = 0x09cc,
649 .mnd_width = 16,
650 .hid_width = 5,
651 .parent_map = gcc_xo_gpll0_map,
652 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
653 .clkr.hw.init = &(struct clk_init_data){
654 .name = "blsp2_uart1_apps_clk_src",
655 .parent_names = gcc_xo_gpll0,
656 .num_parents = 2,
657 .ops = &clk_rcg2_ops,
658 },
659};
660
661static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
662 .cmd_rcgr = 0x0a4c,
663 .mnd_width = 16,
664 .hid_width = 5,
665 .parent_map = gcc_xo_gpll0_map,
666 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
667 .clkr.hw.init = &(struct clk_init_data){
668 .name = "blsp2_uart2_apps_clk_src",
669 .parent_names = gcc_xo_gpll0,
670 .num_parents = 2,
671 .ops = &clk_rcg2_ops,
672 },
673};
674
675static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
676 .cmd_rcgr = 0x0acc,
677 .mnd_width = 16,
678 .hid_width = 5,
679 .parent_map = gcc_xo_gpll0_map,
680 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
681 .clkr.hw.init = &(struct clk_init_data){
682 .name = "blsp2_uart3_apps_clk_src",
683 .parent_names = gcc_xo_gpll0,
684 .num_parents = 2,
685 .ops = &clk_rcg2_ops,
686 },
687};
688
689static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
690 .cmd_rcgr = 0x0b4c,
691 .mnd_width = 16,
692 .hid_width = 5,
693 .parent_map = gcc_xo_gpll0_map,
694 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
695 .clkr.hw.init = &(struct clk_init_data){
696 .name = "blsp2_uart4_apps_clk_src",
697 .parent_names = gcc_xo_gpll0,
698 .num_parents = 2,
699 .ops = &clk_rcg2_ops,
700 },
701};
702
703static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
704 .cmd_rcgr = 0x0bcc,
705 .mnd_width = 16,
706 .hid_width = 5,
707 .parent_map = gcc_xo_gpll0_map,
708 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
709 .clkr.hw.init = &(struct clk_init_data){
710 .name = "blsp2_uart5_apps_clk_src",
711 .parent_names = gcc_xo_gpll0,
712 .num_parents = 2,
713 .ops = &clk_rcg2_ops,
714 },
715};
716
717static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
718 .cmd_rcgr = 0x0c4c,
719 .mnd_width = 16,
720 .hid_width = 5,
721 .parent_map = gcc_xo_gpll0_map,
722 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
723 .clkr.hw.init = &(struct clk_init_data){
724 .name = "blsp2_uart6_apps_clk_src",
725 .parent_names = gcc_xo_gpll0,
726 .num_parents = 2,
727 .ops = &clk_rcg2_ops,
728 },
729};
730
731static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
732 F(50000000, P_GPLL0, 12, 0, 0),
733 F(75000000, P_GPLL0, 8, 0, 0),
734 F(100000000, P_GPLL0, 6, 0, 0),
735 F(150000000, P_GPLL0, 4, 0, 0),
736 { }
737};
738
739static struct clk_rcg2 ce1_clk_src = {
740 .cmd_rcgr = 0x1050,
741 .hid_width = 5,
742 .parent_map = gcc_xo_gpll0_map,
743 .freq_tbl = ftbl_gcc_ce1_clk,
744 .clkr.hw.init = &(struct clk_init_data){
745 .name = "ce1_clk_src",
746 .parent_names = gcc_xo_gpll0,
747 .num_parents = 2,
748 .ops = &clk_rcg2_ops,
749 },
750};
751
752static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
753 F(50000000, P_GPLL0, 12, 0, 0),
754 F(75000000, P_GPLL0, 8, 0, 0),
755 F(100000000, P_GPLL0, 6, 0, 0),
756 F(150000000, P_GPLL0, 4, 0, 0),
757 { }
758};
759
760static struct clk_rcg2 ce2_clk_src = {
761 .cmd_rcgr = 0x1090,
762 .hid_width = 5,
763 .parent_map = gcc_xo_gpll0_map,
764 .freq_tbl = ftbl_gcc_ce2_clk,
765 .clkr.hw.init = &(struct clk_init_data){
766 .name = "ce2_clk_src",
767 .parent_names = gcc_xo_gpll0,
768 .num_parents = 2,
769 .ops = &clk_rcg2_ops,
770 },
771};
772
773static const struct freq_tbl ftbl_gcc_gp_clk[] = {
774 F(4800000, P_XO, 4, 0, 0),
775 F(6000000, P_GPLL0, 10, 1, 10),
776 F(6750000, P_GPLL0, 1, 1, 89),
777 F(8000000, P_GPLL0, 15, 1, 5),
778 F(9600000, P_XO, 2, 0, 0),
779 F(16000000, P_GPLL0, 1, 2, 75),
780 F(19200000, P_XO, 1, 0, 0),
781 F(24000000, P_GPLL0, 5, 1, 5),
782 { }
783};
784
785
786static struct clk_rcg2 gp1_clk_src = {
787 .cmd_rcgr = 0x1904,
788 .mnd_width = 8,
789 .hid_width = 5,
790 .parent_map = gcc_xo_gpll0_map,
791 .freq_tbl = ftbl_gcc_gp_clk,
792 .clkr.hw.init = &(struct clk_init_data){
793 .name = "gp1_clk_src",
794 .parent_names = gcc_xo_gpll0,
795 .num_parents = 2,
796 .ops = &clk_rcg2_ops,
797 },
798};
799
800static struct clk_rcg2 gp2_clk_src = {
801 .cmd_rcgr = 0x1944,
802 .mnd_width = 8,
803 .hid_width = 5,
804 .parent_map = gcc_xo_gpll0_map,
805 .freq_tbl = ftbl_gcc_gp_clk,
806 .clkr.hw.init = &(struct clk_init_data){
807 .name = "gp2_clk_src",
808 .parent_names = gcc_xo_gpll0,
809 .num_parents = 2,
810 .ops = &clk_rcg2_ops,
811 },
812};
813
814static struct clk_rcg2 gp3_clk_src = {
815 .cmd_rcgr = 0x1984,
816 .mnd_width = 8,
817 .hid_width = 5,
818 .parent_map = gcc_xo_gpll0_map,
819 .freq_tbl = ftbl_gcc_gp_clk,
820 .clkr.hw.init = &(struct clk_init_data){
821 .name = "gp3_clk_src",
822 .parent_names = gcc_xo_gpll0,
823 .num_parents = 2,
824 .ops = &clk_rcg2_ops,
825 },
826};
827
828static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
829 F(60000000, P_GPLL0, 10, 0, 0),
830 { }
831};
832
833static struct clk_rcg2 pdm2_clk_src = {
834 .cmd_rcgr = 0x0cd0,
835 .hid_width = 5,
836 .parent_map = gcc_xo_gpll0_map,
837 .freq_tbl = ftbl_gcc_pdm2_clk,
838 .clkr.hw.init = &(struct clk_init_data){
839 .name = "pdm2_clk_src",
840 .parent_names = gcc_xo_gpll0,
841 .num_parents = 2,
842 .ops = &clk_rcg2_ops,
843 },
844};
845
846static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
847 F(144000, P_XO, 16, 3, 25),
848 F(400000, P_XO, 12, 1, 4),
849 F(20000000, P_GPLL0, 15, 1, 2),
850 F(25000000, P_GPLL0, 12, 1, 2),
851 F(50000000, P_GPLL0, 12, 0, 0),
852 F(100000000, P_GPLL0, 6, 0, 0),
853 F(200000000, P_GPLL0, 3, 0, 0),
854 { }
855};
856
Stephen Boydc6858412014-05-16 16:07:13 -0700857static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = {
858 F(144000, P_XO, 16, 3, 25),
859 F(400000, P_XO, 12, 1, 4),
860 F(20000000, P_GPLL0, 15, 1, 2),
861 F(25000000, P_GPLL0, 12, 1, 2),
862 F(50000000, P_GPLL0, 12, 0, 0),
863 F(100000000, P_GPLL0, 6, 0, 0),
864 F(192000000, P_GPLL4, 4, 0, 0),
865 F(200000000, P_GPLL0, 3, 0, 0),
866 F(384000000, P_GPLL4, 2, 0, 0),
867 { }
868};
869
870static struct clk_init_data sdcc1_apps_clk_src_init = {
871 .name = "sdcc1_apps_clk_src",
872 .parent_names = gcc_xo_gpll0,
873 .num_parents = 2,
874 .ops = &clk_rcg2_ops,
875};
876
Stephen Boydd33faa92014-01-15 10:47:30 -0800877static struct clk_rcg2 sdcc1_apps_clk_src = {
878 .cmd_rcgr = 0x04d0,
879 .mnd_width = 8,
880 .hid_width = 5,
881 .parent_map = gcc_xo_gpll0_map,
882 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
Stephen Boydc6858412014-05-16 16:07:13 -0700883 .clkr.hw.init = &sdcc1_apps_clk_src_init,
Stephen Boydd33faa92014-01-15 10:47:30 -0800884};
885
886static struct clk_rcg2 sdcc2_apps_clk_src = {
887 .cmd_rcgr = 0x0510,
888 .mnd_width = 8,
889 .hid_width = 5,
890 .parent_map = gcc_xo_gpll0_map,
891 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
892 .clkr.hw.init = &(struct clk_init_data){
893 .name = "sdcc2_apps_clk_src",
894 .parent_names = gcc_xo_gpll0,
895 .num_parents = 2,
896 .ops = &clk_rcg2_ops,
897 },
898};
899
900static struct clk_rcg2 sdcc3_apps_clk_src = {
901 .cmd_rcgr = 0x0550,
902 .mnd_width = 8,
903 .hid_width = 5,
904 .parent_map = gcc_xo_gpll0_map,
905 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
906 .clkr.hw.init = &(struct clk_init_data){
907 .name = "sdcc3_apps_clk_src",
908 .parent_names = gcc_xo_gpll0,
909 .num_parents = 2,
910 .ops = &clk_rcg2_ops,
911 },
912};
913
914static struct clk_rcg2 sdcc4_apps_clk_src = {
915 .cmd_rcgr = 0x0590,
916 .mnd_width = 8,
917 .hid_width = 5,
918 .parent_map = gcc_xo_gpll0_map,
919 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
920 .clkr.hw.init = &(struct clk_init_data){
921 .name = "sdcc4_apps_clk_src",
922 .parent_names = gcc_xo_gpll0,
923 .num_parents = 2,
924 .ops = &clk_rcg2_ops,
925 },
926};
927
928static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
929 F(105000, P_XO, 2, 1, 91),
930 { }
931};
932
933static struct clk_rcg2 tsif_ref_clk_src = {
934 .cmd_rcgr = 0x0d90,
935 .mnd_width = 8,
936 .hid_width = 5,
937 .parent_map = gcc_xo_gpll0_map,
938 .freq_tbl = ftbl_gcc_tsif_ref_clk,
939 .clkr.hw.init = &(struct clk_init_data){
940 .name = "tsif_ref_clk_src",
941 .parent_names = gcc_xo_gpll0,
942 .num_parents = 2,
943 .ops = &clk_rcg2_ops,
944 },
945};
946
947static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
948 F(60000000, P_GPLL0, 10, 0, 0),
949 { }
950};
951
952static struct clk_rcg2 usb30_mock_utmi_clk_src = {
953 .cmd_rcgr = 0x03e8,
954 .hid_width = 5,
955 .parent_map = gcc_xo_gpll0_map,
956 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
957 .clkr.hw.init = &(struct clk_init_data){
958 .name = "usb30_mock_utmi_clk_src",
959 .parent_names = gcc_xo_gpll0,
960 .num_parents = 2,
961 .ops = &clk_rcg2_ops,
962 },
963};
964
965static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
966 F(60000000, P_GPLL0, 10, 0, 0),
967 F(75000000, P_GPLL0, 8, 0, 0),
968 { }
969};
970
971static struct clk_rcg2 usb_hs_system_clk_src = {
972 .cmd_rcgr = 0x0490,
973 .hid_width = 5,
974 .parent_map = gcc_xo_gpll0_map,
975 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
976 .clkr.hw.init = &(struct clk_init_data){
977 .name = "usb_hs_system_clk_src",
978 .parent_names = gcc_xo_gpll0,
979 .num_parents = 2,
980 .ops = &clk_rcg2_ops,
981 },
982};
983
984static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
985 F(480000000, P_GPLL1, 1, 0, 0),
986 { }
987};
988
Georgi Djakov293d2e972015-03-20 18:30:26 +0200989static const struct parent_map usb_hsic_clk_src_map[] = {
990 { P_XO, 0 },
991 { P_GPLL1, 4 }
Stephen Boydd33faa92014-01-15 10:47:30 -0800992};
993
994static struct clk_rcg2 usb_hsic_clk_src = {
995 .cmd_rcgr = 0x0440,
996 .hid_width = 5,
997 .parent_map = usb_hsic_clk_src_map,
998 .freq_tbl = ftbl_gcc_usb_hsic_clk,
999 .clkr.hw.init = &(struct clk_init_data){
1000 .name = "usb_hsic_clk_src",
1001 .parent_names = (const char *[]){
1002 "xo",
1003 "gpll1_vote",
1004 },
1005 .num_parents = 2,
1006 .ops = &clk_rcg2_ops,
1007 },
1008};
1009
1010static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
1011 F(9600000, P_XO, 2, 0, 0),
1012 { }
1013};
1014
1015static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
1016 .cmd_rcgr = 0x0458,
1017 .hid_width = 5,
1018 .parent_map = gcc_xo_gpll0_map,
1019 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
1020 .clkr.hw.init = &(struct clk_init_data){
1021 .name = "usb_hsic_io_cal_clk_src",
1022 .parent_names = gcc_xo_gpll0,
1023 .num_parents = 1,
1024 .ops = &clk_rcg2_ops,
1025 },
1026};
1027
1028static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
1029 F(60000000, P_GPLL0, 10, 0, 0),
1030 F(75000000, P_GPLL0, 8, 0, 0),
1031 { }
1032};
1033
1034static struct clk_rcg2 usb_hsic_system_clk_src = {
1035 .cmd_rcgr = 0x041c,
1036 .hid_width = 5,
1037 .parent_map = gcc_xo_gpll0_map,
1038 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
1039 .clkr.hw.init = &(struct clk_init_data){
1040 .name = "usb_hsic_system_clk_src",
1041 .parent_names = gcc_xo_gpll0,
1042 .num_parents = 2,
1043 .ops = &clk_rcg2_ops,
1044 },
1045};
1046
1047static struct clk_regmap gcc_mmss_gpll0_clk_src = {
1048 .enable_reg = 0x1484,
1049 .enable_mask = BIT(26),
1050 .hw.init = &(struct clk_init_data){
1051 .name = "mmss_gpll0_vote",
1052 .parent_names = (const char *[]){
1053 "gpll0_vote",
1054 },
1055 .num_parents = 1,
1056 .ops = &clk_branch_simple_ops,
1057 },
1058};
1059
1060static struct clk_branch gcc_bam_dma_ahb_clk = {
1061 .halt_reg = 0x0d44,
1062 .halt_check = BRANCH_HALT_VOTED,
1063 .clkr = {
1064 .enable_reg = 0x1484,
1065 .enable_mask = BIT(12),
1066 .hw.init = &(struct clk_init_data){
1067 .name = "gcc_bam_dma_ahb_clk",
1068 .parent_names = (const char *[]){
1069 "periph_noc_clk_src",
1070 },
1071 .num_parents = 1,
1072 .ops = &clk_branch2_ops,
1073 },
1074 },
1075};
1076
1077static struct clk_branch gcc_blsp1_ahb_clk = {
1078 .halt_reg = 0x05c4,
1079 .halt_check = BRANCH_HALT_VOTED,
1080 .clkr = {
1081 .enable_reg = 0x1484,
1082 .enable_mask = BIT(17),
1083 .hw.init = &(struct clk_init_data){
1084 .name = "gcc_blsp1_ahb_clk",
1085 .parent_names = (const char *[]){
1086 "periph_noc_clk_src",
1087 },
1088 .num_parents = 1,
1089 .ops = &clk_branch2_ops,
1090 },
1091 },
1092};
1093
1094static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1095 .halt_reg = 0x0648,
1096 .clkr = {
1097 .enable_reg = 0x0648,
1098 .enable_mask = BIT(0),
1099 .hw.init = &(struct clk_init_data){
1100 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1101 .parent_names = (const char *[]){
1102 "blsp1_qup1_i2c_apps_clk_src",
1103 },
1104 .num_parents = 1,
1105 .flags = CLK_SET_RATE_PARENT,
1106 .ops = &clk_branch2_ops,
1107 },
1108 },
1109};
1110
1111static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1112 .halt_reg = 0x0644,
1113 .clkr = {
1114 .enable_reg = 0x0644,
1115 .enable_mask = BIT(0),
1116 .hw.init = &(struct clk_init_data){
1117 .name = "gcc_blsp1_qup1_spi_apps_clk",
1118 .parent_names = (const char *[]){
1119 "blsp1_qup1_spi_apps_clk_src",
1120 },
1121 .num_parents = 1,
1122 .flags = CLK_SET_RATE_PARENT,
1123 .ops = &clk_branch2_ops,
1124 },
1125 },
1126};
1127
1128static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1129 .halt_reg = 0x06c8,
1130 .clkr = {
1131 .enable_reg = 0x06c8,
1132 .enable_mask = BIT(0),
1133 .hw.init = &(struct clk_init_data){
1134 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1135 .parent_names = (const char *[]){
1136 "blsp1_qup2_i2c_apps_clk_src",
1137 },
1138 .num_parents = 1,
1139 .flags = CLK_SET_RATE_PARENT,
1140 .ops = &clk_branch2_ops,
1141 },
1142 },
1143};
1144
1145static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1146 .halt_reg = 0x06c4,
1147 .clkr = {
1148 .enable_reg = 0x06c4,
1149 .enable_mask = BIT(0),
1150 .hw.init = &(struct clk_init_data){
1151 .name = "gcc_blsp1_qup2_spi_apps_clk",
1152 .parent_names = (const char *[]){
1153 "blsp1_qup2_spi_apps_clk_src",
1154 },
1155 .num_parents = 1,
1156 .flags = CLK_SET_RATE_PARENT,
1157 .ops = &clk_branch2_ops,
1158 },
1159 },
1160};
1161
1162static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1163 .halt_reg = 0x0748,
1164 .clkr = {
1165 .enable_reg = 0x0748,
1166 .enable_mask = BIT(0),
1167 .hw.init = &(struct clk_init_data){
1168 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1169 .parent_names = (const char *[]){
1170 "blsp1_qup3_i2c_apps_clk_src",
1171 },
1172 .num_parents = 1,
1173 .flags = CLK_SET_RATE_PARENT,
1174 .ops = &clk_branch2_ops,
1175 },
1176 },
1177};
1178
1179static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1180 .halt_reg = 0x0744,
1181 .clkr = {
1182 .enable_reg = 0x0744,
1183 .enable_mask = BIT(0),
1184 .hw.init = &(struct clk_init_data){
1185 .name = "gcc_blsp1_qup3_spi_apps_clk",
1186 .parent_names = (const char *[]){
1187 "blsp1_qup3_spi_apps_clk_src",
1188 },
1189 .num_parents = 1,
1190 .flags = CLK_SET_RATE_PARENT,
1191 .ops = &clk_branch2_ops,
1192 },
1193 },
1194};
1195
1196static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1197 .halt_reg = 0x07c8,
1198 .clkr = {
1199 .enable_reg = 0x07c8,
1200 .enable_mask = BIT(0),
1201 .hw.init = &(struct clk_init_data){
1202 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1203 .parent_names = (const char *[]){
1204 "blsp1_qup4_i2c_apps_clk_src",
1205 },
1206 .num_parents = 1,
1207 .flags = CLK_SET_RATE_PARENT,
1208 .ops = &clk_branch2_ops,
1209 },
1210 },
1211};
1212
1213static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1214 .halt_reg = 0x07c4,
1215 .clkr = {
1216 .enable_reg = 0x07c4,
1217 .enable_mask = BIT(0),
1218 .hw.init = &(struct clk_init_data){
1219 .name = "gcc_blsp1_qup4_spi_apps_clk",
1220 .parent_names = (const char *[]){
1221 "blsp1_qup4_spi_apps_clk_src",
1222 },
1223 .num_parents = 1,
1224 .flags = CLK_SET_RATE_PARENT,
1225 .ops = &clk_branch2_ops,
1226 },
1227 },
1228};
1229
1230static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1231 .halt_reg = 0x0848,
1232 .clkr = {
1233 .enable_reg = 0x0848,
1234 .enable_mask = BIT(0),
1235 .hw.init = &(struct clk_init_data){
1236 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1237 .parent_names = (const char *[]){
1238 "blsp1_qup5_i2c_apps_clk_src",
1239 },
1240 .num_parents = 1,
1241 .flags = CLK_SET_RATE_PARENT,
1242 .ops = &clk_branch2_ops,
1243 },
1244 },
1245};
1246
1247static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1248 .halt_reg = 0x0844,
1249 .clkr = {
1250 .enable_reg = 0x0844,
1251 .enable_mask = BIT(0),
1252 .hw.init = &(struct clk_init_data){
1253 .name = "gcc_blsp1_qup5_spi_apps_clk",
1254 .parent_names = (const char *[]){
1255 "blsp1_qup5_spi_apps_clk_src",
1256 },
1257 .num_parents = 1,
1258 .flags = CLK_SET_RATE_PARENT,
1259 .ops = &clk_branch2_ops,
1260 },
1261 },
1262};
1263
1264static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1265 .halt_reg = 0x08c8,
1266 .clkr = {
1267 .enable_reg = 0x08c8,
1268 .enable_mask = BIT(0),
1269 .hw.init = &(struct clk_init_data){
1270 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1271 .parent_names = (const char *[]){
1272 "blsp1_qup6_i2c_apps_clk_src",
1273 },
1274 .num_parents = 1,
1275 .flags = CLK_SET_RATE_PARENT,
1276 .ops = &clk_branch2_ops,
1277 },
1278 },
1279};
1280
1281static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1282 .halt_reg = 0x08c4,
1283 .clkr = {
1284 .enable_reg = 0x08c4,
1285 .enable_mask = BIT(0),
1286 .hw.init = &(struct clk_init_data){
1287 .name = "gcc_blsp1_qup6_spi_apps_clk",
1288 .parent_names = (const char *[]){
1289 "blsp1_qup6_spi_apps_clk_src",
1290 },
1291 .num_parents = 1,
1292 .flags = CLK_SET_RATE_PARENT,
1293 .ops = &clk_branch2_ops,
1294 },
1295 },
1296};
1297
1298static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1299 .halt_reg = 0x0684,
1300 .clkr = {
1301 .enable_reg = 0x0684,
1302 .enable_mask = BIT(0),
1303 .hw.init = &(struct clk_init_data){
1304 .name = "gcc_blsp1_uart1_apps_clk",
1305 .parent_names = (const char *[]){
1306 "blsp1_uart1_apps_clk_src",
1307 },
1308 .num_parents = 1,
1309 .flags = CLK_SET_RATE_PARENT,
1310 .ops = &clk_branch2_ops,
1311 },
1312 },
1313};
1314
1315static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1316 .halt_reg = 0x0704,
1317 .clkr = {
1318 .enable_reg = 0x0704,
1319 .enable_mask = BIT(0),
1320 .hw.init = &(struct clk_init_data){
1321 .name = "gcc_blsp1_uart2_apps_clk",
1322 .parent_names = (const char *[]){
1323 "blsp1_uart2_apps_clk_src",
1324 },
1325 .num_parents = 1,
1326 .flags = CLK_SET_RATE_PARENT,
1327 .ops = &clk_branch2_ops,
1328 },
1329 },
1330};
1331
1332static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1333 .halt_reg = 0x0784,
1334 .clkr = {
1335 .enable_reg = 0x0784,
1336 .enable_mask = BIT(0),
1337 .hw.init = &(struct clk_init_data){
1338 .name = "gcc_blsp1_uart3_apps_clk",
1339 .parent_names = (const char *[]){
1340 "blsp1_uart3_apps_clk_src",
1341 },
1342 .num_parents = 1,
1343 .flags = CLK_SET_RATE_PARENT,
1344 .ops = &clk_branch2_ops,
1345 },
1346 },
1347};
1348
1349static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1350 .halt_reg = 0x0804,
1351 .clkr = {
1352 .enable_reg = 0x0804,
1353 .enable_mask = BIT(0),
1354 .hw.init = &(struct clk_init_data){
1355 .name = "gcc_blsp1_uart4_apps_clk",
1356 .parent_names = (const char *[]){
1357 "blsp1_uart4_apps_clk_src",
1358 },
1359 .num_parents = 1,
1360 .flags = CLK_SET_RATE_PARENT,
1361 .ops = &clk_branch2_ops,
1362 },
1363 },
1364};
1365
1366static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1367 .halt_reg = 0x0884,
1368 .clkr = {
1369 .enable_reg = 0x0884,
1370 .enable_mask = BIT(0),
1371 .hw.init = &(struct clk_init_data){
1372 .name = "gcc_blsp1_uart5_apps_clk",
1373 .parent_names = (const char *[]){
1374 "blsp1_uart5_apps_clk_src",
1375 },
1376 .num_parents = 1,
1377 .flags = CLK_SET_RATE_PARENT,
1378 .ops = &clk_branch2_ops,
1379 },
1380 },
1381};
1382
1383static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1384 .halt_reg = 0x0904,
1385 .clkr = {
1386 .enable_reg = 0x0904,
1387 .enable_mask = BIT(0),
1388 .hw.init = &(struct clk_init_data){
1389 .name = "gcc_blsp1_uart6_apps_clk",
1390 .parent_names = (const char *[]){
1391 "blsp1_uart6_apps_clk_src",
1392 },
1393 .num_parents = 1,
1394 .flags = CLK_SET_RATE_PARENT,
1395 .ops = &clk_branch2_ops,
1396 },
1397 },
1398};
1399
1400static struct clk_branch gcc_blsp2_ahb_clk = {
Georgi Djakov63a00262014-05-20 19:50:54 +03001401 .halt_reg = 0x0944,
Stephen Boydd33faa92014-01-15 10:47:30 -08001402 .halt_check = BRANCH_HALT_VOTED,
1403 .clkr = {
1404 .enable_reg = 0x1484,
1405 .enable_mask = BIT(15),
1406 .hw.init = &(struct clk_init_data){
1407 .name = "gcc_blsp2_ahb_clk",
1408 .parent_names = (const char *[]){
1409 "periph_noc_clk_src",
1410 },
1411 .num_parents = 1,
1412 .ops = &clk_branch2_ops,
1413 },
1414 },
1415};
1416
1417static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1418 .halt_reg = 0x0988,
1419 .clkr = {
1420 .enable_reg = 0x0988,
1421 .enable_mask = BIT(0),
1422 .hw.init = &(struct clk_init_data){
1423 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1424 .parent_names = (const char *[]){
1425 "blsp2_qup1_i2c_apps_clk_src",
1426 },
1427 .num_parents = 1,
1428 .flags = CLK_SET_RATE_PARENT,
1429 .ops = &clk_branch2_ops,
1430 },
1431 },
1432};
1433
1434static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1435 .halt_reg = 0x0984,
1436 .clkr = {
1437 .enable_reg = 0x0984,
1438 .enable_mask = BIT(0),
1439 .hw.init = &(struct clk_init_data){
1440 .name = "gcc_blsp2_qup1_spi_apps_clk",
1441 .parent_names = (const char *[]){
1442 "blsp2_qup1_spi_apps_clk_src",
1443 },
1444 .num_parents = 1,
1445 .flags = CLK_SET_RATE_PARENT,
1446 .ops = &clk_branch2_ops,
1447 },
1448 },
1449};
1450
1451static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1452 .halt_reg = 0x0a08,
1453 .clkr = {
1454 .enable_reg = 0x0a08,
1455 .enable_mask = BIT(0),
1456 .hw.init = &(struct clk_init_data){
1457 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1458 .parent_names = (const char *[]){
1459 "blsp2_qup2_i2c_apps_clk_src",
1460 },
1461 .num_parents = 1,
1462 .flags = CLK_SET_RATE_PARENT,
1463 .ops = &clk_branch2_ops,
1464 },
1465 },
1466};
1467
1468static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1469 .halt_reg = 0x0a04,
1470 .clkr = {
1471 .enable_reg = 0x0a04,
1472 .enable_mask = BIT(0),
1473 .hw.init = &(struct clk_init_data){
1474 .name = "gcc_blsp2_qup2_spi_apps_clk",
1475 .parent_names = (const char *[]){
1476 "blsp2_qup2_spi_apps_clk_src",
1477 },
1478 .num_parents = 1,
1479 .flags = CLK_SET_RATE_PARENT,
1480 .ops = &clk_branch2_ops,
1481 },
1482 },
1483};
1484
1485static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1486 .halt_reg = 0x0a88,
1487 .clkr = {
1488 .enable_reg = 0x0a88,
1489 .enable_mask = BIT(0),
1490 .hw.init = &(struct clk_init_data){
1491 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1492 .parent_names = (const char *[]){
1493 "blsp2_qup3_i2c_apps_clk_src",
1494 },
1495 .num_parents = 1,
1496 .flags = CLK_SET_RATE_PARENT,
1497 .ops = &clk_branch2_ops,
1498 },
1499 },
1500};
1501
1502static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1503 .halt_reg = 0x0a84,
1504 .clkr = {
1505 .enable_reg = 0x0a84,
1506 .enable_mask = BIT(0),
1507 .hw.init = &(struct clk_init_data){
1508 .name = "gcc_blsp2_qup3_spi_apps_clk",
1509 .parent_names = (const char *[]){
1510 "blsp2_qup3_spi_apps_clk_src",
1511 },
1512 .num_parents = 1,
1513 .flags = CLK_SET_RATE_PARENT,
1514 .ops = &clk_branch2_ops,
1515 },
1516 },
1517};
1518
1519static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1520 .halt_reg = 0x0b08,
1521 .clkr = {
1522 .enable_reg = 0x0b08,
1523 .enable_mask = BIT(0),
1524 .hw.init = &(struct clk_init_data){
1525 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1526 .parent_names = (const char *[]){
1527 "blsp2_qup4_i2c_apps_clk_src",
1528 },
1529 .num_parents = 1,
1530 .flags = CLK_SET_RATE_PARENT,
1531 .ops = &clk_branch2_ops,
1532 },
1533 },
1534};
1535
1536static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1537 .halt_reg = 0x0b04,
1538 .clkr = {
1539 .enable_reg = 0x0b04,
1540 .enable_mask = BIT(0),
1541 .hw.init = &(struct clk_init_data){
1542 .name = "gcc_blsp2_qup4_spi_apps_clk",
1543 .parent_names = (const char *[]){
1544 "blsp2_qup4_spi_apps_clk_src",
1545 },
1546 .num_parents = 1,
1547 .flags = CLK_SET_RATE_PARENT,
1548 .ops = &clk_branch2_ops,
1549 },
1550 },
1551};
1552
1553static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1554 .halt_reg = 0x0b88,
1555 .clkr = {
1556 .enable_reg = 0x0b88,
1557 .enable_mask = BIT(0),
1558 .hw.init = &(struct clk_init_data){
1559 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1560 .parent_names = (const char *[]){
1561 "blsp2_qup5_i2c_apps_clk_src",
1562 },
1563 .num_parents = 1,
1564 .flags = CLK_SET_RATE_PARENT,
1565 .ops = &clk_branch2_ops,
1566 },
1567 },
1568};
1569
1570static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1571 .halt_reg = 0x0b84,
1572 .clkr = {
1573 .enable_reg = 0x0b84,
1574 .enable_mask = BIT(0),
1575 .hw.init = &(struct clk_init_data){
1576 .name = "gcc_blsp2_qup5_spi_apps_clk",
1577 .parent_names = (const char *[]){
1578 "blsp2_qup5_spi_apps_clk_src",
1579 },
1580 .num_parents = 1,
1581 .flags = CLK_SET_RATE_PARENT,
1582 .ops = &clk_branch2_ops,
1583 },
1584 },
1585};
1586
1587static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1588 .halt_reg = 0x0c08,
1589 .clkr = {
1590 .enable_reg = 0x0c08,
1591 .enable_mask = BIT(0),
1592 .hw.init = &(struct clk_init_data){
1593 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1594 .parent_names = (const char *[]){
1595 "blsp2_qup6_i2c_apps_clk_src",
1596 },
1597 .num_parents = 1,
1598 .flags = CLK_SET_RATE_PARENT,
1599 .ops = &clk_branch2_ops,
1600 },
1601 },
1602};
1603
1604static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1605 .halt_reg = 0x0c04,
1606 .clkr = {
1607 .enable_reg = 0x0c04,
1608 .enable_mask = BIT(0),
1609 .hw.init = &(struct clk_init_data){
1610 .name = "gcc_blsp2_qup6_spi_apps_clk",
1611 .parent_names = (const char *[]){
1612 "blsp2_qup6_spi_apps_clk_src",
1613 },
1614 .num_parents = 1,
1615 .flags = CLK_SET_RATE_PARENT,
1616 .ops = &clk_branch2_ops,
1617 },
1618 },
1619};
1620
1621static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1622 .halt_reg = 0x09c4,
1623 .clkr = {
1624 .enable_reg = 0x09c4,
1625 .enable_mask = BIT(0),
1626 .hw.init = &(struct clk_init_data){
1627 .name = "gcc_blsp2_uart1_apps_clk",
1628 .parent_names = (const char *[]){
1629 "blsp2_uart1_apps_clk_src",
1630 },
1631 .num_parents = 1,
1632 .flags = CLK_SET_RATE_PARENT,
1633 .ops = &clk_branch2_ops,
1634 },
1635 },
1636};
1637
1638static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1639 .halt_reg = 0x0a44,
1640 .clkr = {
1641 .enable_reg = 0x0a44,
1642 .enable_mask = BIT(0),
1643 .hw.init = &(struct clk_init_data){
1644 .name = "gcc_blsp2_uart2_apps_clk",
1645 .parent_names = (const char *[]){
1646 "blsp2_uart2_apps_clk_src",
1647 },
1648 .num_parents = 1,
1649 .flags = CLK_SET_RATE_PARENT,
1650 .ops = &clk_branch2_ops,
1651 },
1652 },
1653};
1654
1655static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1656 .halt_reg = 0x0ac4,
1657 .clkr = {
1658 .enable_reg = 0x0ac4,
1659 .enable_mask = BIT(0),
1660 .hw.init = &(struct clk_init_data){
1661 .name = "gcc_blsp2_uart3_apps_clk",
1662 .parent_names = (const char *[]){
1663 "blsp2_uart3_apps_clk_src",
1664 },
1665 .num_parents = 1,
1666 .flags = CLK_SET_RATE_PARENT,
1667 .ops = &clk_branch2_ops,
1668 },
1669 },
1670};
1671
1672static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1673 .halt_reg = 0x0b44,
1674 .clkr = {
1675 .enable_reg = 0x0b44,
1676 .enable_mask = BIT(0),
1677 .hw.init = &(struct clk_init_data){
1678 .name = "gcc_blsp2_uart4_apps_clk",
1679 .parent_names = (const char *[]){
1680 "blsp2_uart4_apps_clk_src",
1681 },
1682 .num_parents = 1,
1683 .flags = CLK_SET_RATE_PARENT,
1684 .ops = &clk_branch2_ops,
1685 },
1686 },
1687};
1688
1689static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1690 .halt_reg = 0x0bc4,
1691 .clkr = {
1692 .enable_reg = 0x0bc4,
1693 .enable_mask = BIT(0),
1694 .hw.init = &(struct clk_init_data){
1695 .name = "gcc_blsp2_uart5_apps_clk",
1696 .parent_names = (const char *[]){
1697 "blsp2_uart5_apps_clk_src",
1698 },
1699 .num_parents = 1,
1700 .flags = CLK_SET_RATE_PARENT,
1701 .ops = &clk_branch2_ops,
1702 },
1703 },
1704};
1705
1706static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1707 .halt_reg = 0x0c44,
1708 .clkr = {
1709 .enable_reg = 0x0c44,
1710 .enable_mask = BIT(0),
1711 .hw.init = &(struct clk_init_data){
1712 .name = "gcc_blsp2_uart6_apps_clk",
1713 .parent_names = (const char *[]){
1714 "blsp2_uart6_apps_clk_src",
1715 },
1716 .num_parents = 1,
1717 .flags = CLK_SET_RATE_PARENT,
1718 .ops = &clk_branch2_ops,
1719 },
1720 },
1721};
1722
1723static struct clk_branch gcc_boot_rom_ahb_clk = {
1724 .halt_reg = 0x0e04,
1725 .halt_check = BRANCH_HALT_VOTED,
1726 .clkr = {
1727 .enable_reg = 0x1484,
1728 .enable_mask = BIT(10),
1729 .hw.init = &(struct clk_init_data){
1730 .name = "gcc_boot_rom_ahb_clk",
1731 .parent_names = (const char *[]){
1732 "config_noc_clk_src",
1733 },
1734 .num_parents = 1,
1735 .ops = &clk_branch2_ops,
1736 },
1737 },
1738};
1739
1740static struct clk_branch gcc_ce1_ahb_clk = {
1741 .halt_reg = 0x104c,
1742 .halt_check = BRANCH_HALT_VOTED,
1743 .clkr = {
1744 .enable_reg = 0x1484,
1745 .enable_mask = BIT(3),
1746 .hw.init = &(struct clk_init_data){
1747 .name = "gcc_ce1_ahb_clk",
1748 .parent_names = (const char *[]){
1749 "config_noc_clk_src",
1750 },
1751 .num_parents = 1,
1752 .ops = &clk_branch2_ops,
1753 },
1754 },
1755};
1756
1757static struct clk_branch gcc_ce1_axi_clk = {
1758 .halt_reg = 0x1048,
1759 .halt_check = BRANCH_HALT_VOTED,
1760 .clkr = {
1761 .enable_reg = 0x1484,
1762 .enable_mask = BIT(4),
1763 .hw.init = &(struct clk_init_data){
1764 .name = "gcc_ce1_axi_clk",
1765 .parent_names = (const char *[]){
1766 "system_noc_clk_src",
1767 },
1768 .num_parents = 1,
1769 .ops = &clk_branch2_ops,
1770 },
1771 },
1772};
1773
1774static struct clk_branch gcc_ce1_clk = {
1775 .halt_reg = 0x1050,
1776 .halt_check = BRANCH_HALT_VOTED,
1777 .clkr = {
1778 .enable_reg = 0x1484,
1779 .enable_mask = BIT(5),
1780 .hw.init = &(struct clk_init_data){
1781 .name = "gcc_ce1_clk",
1782 .parent_names = (const char *[]){
1783 "ce1_clk_src",
1784 },
1785 .num_parents = 1,
1786 .ops = &clk_branch2_ops,
1787 },
1788 },
1789};
1790
1791static struct clk_branch gcc_ce2_ahb_clk = {
1792 .halt_reg = 0x108c,
1793 .halt_check = BRANCH_HALT_VOTED,
1794 .clkr = {
1795 .enable_reg = 0x1484,
1796 .enable_mask = BIT(0),
1797 .hw.init = &(struct clk_init_data){
1798 .name = "gcc_ce2_ahb_clk",
1799 .parent_names = (const char *[]){
1800 "config_noc_clk_src",
1801 },
1802 .num_parents = 1,
1803 .ops = &clk_branch2_ops,
1804 },
1805 },
1806};
1807
1808static struct clk_branch gcc_ce2_axi_clk = {
1809 .halt_reg = 0x1088,
1810 .halt_check = BRANCH_HALT_VOTED,
1811 .clkr = {
1812 .enable_reg = 0x1484,
1813 .enable_mask = BIT(1),
1814 .hw.init = &(struct clk_init_data){
1815 .name = "gcc_ce2_axi_clk",
1816 .parent_names = (const char *[]){
1817 "system_noc_clk_src",
1818 },
1819 .num_parents = 1,
1820 .ops = &clk_branch2_ops,
1821 },
1822 },
1823};
1824
1825static struct clk_branch gcc_ce2_clk = {
1826 .halt_reg = 0x1090,
1827 .halt_check = BRANCH_HALT_VOTED,
1828 .clkr = {
1829 .enable_reg = 0x1484,
1830 .enable_mask = BIT(2),
1831 .hw.init = &(struct clk_init_data){
1832 .name = "gcc_ce2_clk",
1833 .parent_names = (const char *[]){
1834 "ce2_clk_src",
1835 },
1836 .num_parents = 1,
1837 .flags = CLK_SET_RATE_PARENT,
1838 .ops = &clk_branch2_ops,
1839 },
1840 },
1841};
1842
1843static struct clk_branch gcc_gp1_clk = {
1844 .halt_reg = 0x1900,
1845 .clkr = {
1846 .enable_reg = 0x1900,
1847 .enable_mask = BIT(0),
1848 .hw.init = &(struct clk_init_data){
1849 .name = "gcc_gp1_clk",
1850 .parent_names = (const char *[]){
1851 "gp1_clk_src",
1852 },
1853 .num_parents = 1,
1854 .flags = CLK_SET_RATE_PARENT,
1855 .ops = &clk_branch2_ops,
1856 },
1857 },
1858};
1859
1860static struct clk_branch gcc_gp2_clk = {
1861 .halt_reg = 0x1940,
1862 .clkr = {
1863 .enable_reg = 0x1940,
1864 .enable_mask = BIT(0),
1865 .hw.init = &(struct clk_init_data){
1866 .name = "gcc_gp2_clk",
1867 .parent_names = (const char *[]){
1868 "gp2_clk_src",
1869 },
1870 .num_parents = 1,
1871 .flags = CLK_SET_RATE_PARENT,
1872 .ops = &clk_branch2_ops,
1873 },
1874 },
1875};
1876
1877static struct clk_branch gcc_gp3_clk = {
1878 .halt_reg = 0x1980,
1879 .clkr = {
1880 .enable_reg = 0x1980,
1881 .enable_mask = BIT(0),
1882 .hw.init = &(struct clk_init_data){
1883 .name = "gcc_gp3_clk",
1884 .parent_names = (const char *[]){
1885 "gp3_clk_src",
1886 },
1887 .num_parents = 1,
1888 .flags = CLK_SET_RATE_PARENT,
1889 .ops = &clk_branch2_ops,
1890 },
1891 },
1892};
1893
1894static struct clk_branch gcc_lpass_q6_axi_clk = {
1895 .halt_reg = 0x11c0,
1896 .clkr = {
1897 .enable_reg = 0x11c0,
1898 .enable_mask = BIT(0),
1899 .hw.init = &(struct clk_init_data){
1900 .name = "gcc_lpass_q6_axi_clk",
1901 .parent_names = (const char *[]){
1902 "system_noc_clk_src",
1903 },
1904 .num_parents = 1,
1905 .ops = &clk_branch2_ops,
1906 },
1907 },
1908};
1909
1910static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1911 .halt_reg = 0x024c,
1912 .clkr = {
1913 .enable_reg = 0x024c,
1914 .enable_mask = BIT(0),
1915 .hw.init = &(struct clk_init_data){
1916 .name = "gcc_mmss_noc_cfg_ahb_clk",
1917 .parent_names = (const char *[]){
1918 "config_noc_clk_src",
1919 },
1920 .num_parents = 1,
1921 .ops = &clk_branch2_ops,
1922 .flags = CLK_IGNORE_UNUSED,
1923 },
1924 },
1925};
1926
1927static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
1928 .halt_reg = 0x0248,
1929 .clkr = {
1930 .enable_reg = 0x0248,
1931 .enable_mask = BIT(0),
1932 .hw.init = &(struct clk_init_data){
1933 .name = "gcc_ocmem_noc_cfg_ahb_clk",
1934 .parent_names = (const char *[]){
1935 "config_noc_clk_src",
1936 },
1937 .num_parents = 1,
1938 .ops = &clk_branch2_ops,
1939 },
1940 },
1941};
1942
1943static struct clk_branch gcc_mss_cfg_ahb_clk = {
1944 .halt_reg = 0x0280,
1945 .clkr = {
1946 .enable_reg = 0x0280,
1947 .enable_mask = BIT(0),
1948 .hw.init = &(struct clk_init_data){
1949 .name = "gcc_mss_cfg_ahb_clk",
1950 .parent_names = (const char *[]){
1951 "config_noc_clk_src",
1952 },
1953 .num_parents = 1,
1954 .ops = &clk_branch2_ops,
1955 },
1956 },
1957};
1958
1959static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1960 .halt_reg = 0x0284,
1961 .clkr = {
1962 .enable_reg = 0x0284,
1963 .enable_mask = BIT(0),
1964 .hw.init = &(struct clk_init_data){
1965 .name = "gcc_mss_q6_bimc_axi_clk",
1966 .flags = CLK_IS_ROOT,
1967 .ops = &clk_branch2_ops,
1968 },
1969 },
1970};
1971
1972static struct clk_branch gcc_pdm2_clk = {
1973 .halt_reg = 0x0ccc,
1974 .clkr = {
1975 .enable_reg = 0x0ccc,
1976 .enable_mask = BIT(0),
1977 .hw.init = &(struct clk_init_data){
1978 .name = "gcc_pdm2_clk",
1979 .parent_names = (const char *[]){
1980 "pdm2_clk_src",
1981 },
1982 .num_parents = 1,
1983 .flags = CLK_SET_RATE_PARENT,
1984 .ops = &clk_branch2_ops,
1985 },
1986 },
1987};
1988
1989static struct clk_branch gcc_pdm_ahb_clk = {
1990 .halt_reg = 0x0cc4,
1991 .clkr = {
1992 .enable_reg = 0x0cc4,
1993 .enable_mask = BIT(0),
1994 .hw.init = &(struct clk_init_data){
1995 .name = "gcc_pdm_ahb_clk",
1996 .parent_names = (const char *[]){
1997 "periph_noc_clk_src",
1998 },
1999 .num_parents = 1,
2000 .ops = &clk_branch2_ops,
2001 },
2002 },
2003};
2004
2005static struct clk_branch gcc_prng_ahb_clk = {
2006 .halt_reg = 0x0d04,
2007 .halt_check = BRANCH_HALT_VOTED,
2008 .clkr = {
2009 .enable_reg = 0x1484,
2010 .enable_mask = BIT(13),
2011 .hw.init = &(struct clk_init_data){
2012 .name = "gcc_prng_ahb_clk",
2013 .parent_names = (const char *[]){
2014 "periph_noc_clk_src",
2015 },
2016 .num_parents = 1,
2017 .ops = &clk_branch2_ops,
2018 },
2019 },
2020};
2021
2022static struct clk_branch gcc_sdcc1_ahb_clk = {
2023 .halt_reg = 0x04c8,
2024 .clkr = {
2025 .enable_reg = 0x04c8,
2026 .enable_mask = BIT(0),
2027 .hw.init = &(struct clk_init_data){
2028 .name = "gcc_sdcc1_ahb_clk",
2029 .parent_names = (const char *[]){
2030 "periph_noc_clk_src",
2031 },
2032 .num_parents = 1,
2033 .ops = &clk_branch2_ops,
2034 },
2035 },
2036};
2037
2038static struct clk_branch gcc_sdcc1_apps_clk = {
2039 .halt_reg = 0x04c4,
2040 .clkr = {
2041 .enable_reg = 0x04c4,
2042 .enable_mask = BIT(0),
2043 .hw.init = &(struct clk_init_data){
2044 .name = "gcc_sdcc1_apps_clk",
2045 .parent_names = (const char *[]){
2046 "sdcc1_apps_clk_src",
2047 },
2048 .num_parents = 1,
2049 .flags = CLK_SET_RATE_PARENT,
2050 .ops = &clk_branch2_ops,
2051 },
2052 },
2053};
2054
Stephen Boydc6858412014-05-16 16:07:13 -07002055static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
2056 .halt_reg = 0x04e8,
2057 .clkr = {
2058 .enable_reg = 0x04e8,
2059 .enable_mask = BIT(0),
2060 .hw.init = &(struct clk_init_data){
2061 .name = "gcc_sdcc1_cdccal_ff_clk",
2062 .parent_names = (const char *[]){
2063 "xo"
2064 },
2065 .num_parents = 1,
2066 .ops = &clk_branch2_ops,
2067 },
2068 },
2069};
2070
2071static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
2072 .halt_reg = 0x04e4,
2073 .clkr = {
2074 .enable_reg = 0x04e4,
2075 .enable_mask = BIT(0),
2076 .hw.init = &(struct clk_init_data){
2077 .name = "gcc_sdcc1_cdccal_sleep_clk",
2078 .parent_names = (const char *[]){
2079 "sleep_clk_src"
2080 },
2081 .num_parents = 1,
2082 .ops = &clk_branch2_ops,
2083 },
2084 },
2085};
2086
Stephen Boydd33faa92014-01-15 10:47:30 -08002087static struct clk_branch gcc_sdcc2_ahb_clk = {
2088 .halt_reg = 0x0508,
2089 .clkr = {
2090 .enable_reg = 0x0508,
2091 .enable_mask = BIT(0),
2092 .hw.init = &(struct clk_init_data){
2093 .name = "gcc_sdcc2_ahb_clk",
2094 .parent_names = (const char *[]){
2095 "periph_noc_clk_src",
2096 },
2097 .num_parents = 1,
2098 .ops = &clk_branch2_ops,
2099 },
2100 },
2101};
2102
2103static struct clk_branch gcc_sdcc2_apps_clk = {
2104 .halt_reg = 0x0504,
2105 .clkr = {
2106 .enable_reg = 0x0504,
2107 .enable_mask = BIT(0),
2108 .hw.init = &(struct clk_init_data){
2109 .name = "gcc_sdcc2_apps_clk",
2110 .parent_names = (const char *[]){
2111 "sdcc2_apps_clk_src",
2112 },
2113 .num_parents = 1,
2114 .flags = CLK_SET_RATE_PARENT,
2115 .ops = &clk_branch2_ops,
2116 },
2117 },
2118};
2119
2120static struct clk_branch gcc_sdcc3_ahb_clk = {
2121 .halt_reg = 0x0548,
2122 .clkr = {
2123 .enable_reg = 0x0548,
2124 .enable_mask = BIT(0),
2125 .hw.init = &(struct clk_init_data){
2126 .name = "gcc_sdcc3_ahb_clk",
2127 .parent_names = (const char *[]){
2128 "periph_noc_clk_src",
2129 },
2130 .num_parents = 1,
2131 .ops = &clk_branch2_ops,
2132 },
2133 },
2134};
2135
2136static struct clk_branch gcc_sdcc3_apps_clk = {
2137 .halt_reg = 0x0544,
2138 .clkr = {
2139 .enable_reg = 0x0544,
2140 .enable_mask = BIT(0),
2141 .hw.init = &(struct clk_init_data){
2142 .name = "gcc_sdcc3_apps_clk",
2143 .parent_names = (const char *[]){
2144 "sdcc3_apps_clk_src",
2145 },
2146 .num_parents = 1,
2147 .flags = CLK_SET_RATE_PARENT,
2148 .ops = &clk_branch2_ops,
2149 },
2150 },
2151};
2152
2153static struct clk_branch gcc_sdcc4_ahb_clk = {
2154 .halt_reg = 0x0588,
2155 .clkr = {
2156 .enable_reg = 0x0588,
2157 .enable_mask = BIT(0),
2158 .hw.init = &(struct clk_init_data){
2159 .name = "gcc_sdcc4_ahb_clk",
2160 .parent_names = (const char *[]){
2161 "periph_noc_clk_src",
2162 },
2163 .num_parents = 1,
2164 .ops = &clk_branch2_ops,
2165 },
2166 },
2167};
2168
2169static struct clk_branch gcc_sdcc4_apps_clk = {
2170 .halt_reg = 0x0584,
2171 .clkr = {
2172 .enable_reg = 0x0584,
2173 .enable_mask = BIT(0),
2174 .hw.init = &(struct clk_init_data){
2175 .name = "gcc_sdcc4_apps_clk",
2176 .parent_names = (const char *[]){
2177 "sdcc4_apps_clk_src",
2178 },
2179 .num_parents = 1,
2180 .flags = CLK_SET_RATE_PARENT,
2181 .ops = &clk_branch2_ops,
2182 },
2183 },
2184};
2185
2186static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2187 .halt_reg = 0x0108,
2188 .clkr = {
2189 .enable_reg = 0x0108,
2190 .enable_mask = BIT(0),
2191 .hw.init = &(struct clk_init_data){
2192 .name = "gcc_sys_noc_usb3_axi_clk",
2193 .parent_names = (const char *[]){
2194 "usb30_master_clk_src",
2195 },
2196 .num_parents = 1,
2197 .flags = CLK_SET_RATE_PARENT,
2198 .ops = &clk_branch2_ops,
2199 },
2200 },
2201};
2202
2203static struct clk_branch gcc_tsif_ahb_clk = {
2204 .halt_reg = 0x0d84,
2205 .clkr = {
2206 .enable_reg = 0x0d84,
2207 .enable_mask = BIT(0),
2208 .hw.init = &(struct clk_init_data){
2209 .name = "gcc_tsif_ahb_clk",
2210 .parent_names = (const char *[]){
2211 "periph_noc_clk_src",
2212 },
2213 .num_parents = 1,
2214 .ops = &clk_branch2_ops,
2215 },
2216 },
2217};
2218
2219static struct clk_branch gcc_tsif_ref_clk = {
2220 .halt_reg = 0x0d88,
2221 .clkr = {
2222 .enable_reg = 0x0d88,
2223 .enable_mask = BIT(0),
2224 .hw.init = &(struct clk_init_data){
2225 .name = "gcc_tsif_ref_clk",
2226 .parent_names = (const char *[]){
2227 "tsif_ref_clk_src",
2228 },
2229 .num_parents = 1,
2230 .flags = CLK_SET_RATE_PARENT,
2231 .ops = &clk_branch2_ops,
2232 },
2233 },
2234};
2235
2236static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2237 .halt_reg = 0x04ac,
2238 .clkr = {
2239 .enable_reg = 0x04ac,
2240 .enable_mask = BIT(0),
2241 .hw.init = &(struct clk_init_data){
2242 .name = "gcc_usb2a_phy_sleep_clk",
2243 .parent_names = (const char *[]){
2244 "sleep_clk_src",
2245 },
2246 .num_parents = 1,
2247 .ops = &clk_branch2_ops,
2248 },
2249 },
2250};
2251
2252static struct clk_branch gcc_usb2b_phy_sleep_clk = {
2253 .halt_reg = 0x04b4,
2254 .clkr = {
2255 .enable_reg = 0x04b4,
2256 .enable_mask = BIT(0),
2257 .hw.init = &(struct clk_init_data){
2258 .name = "gcc_usb2b_phy_sleep_clk",
2259 .parent_names = (const char *[]){
2260 "sleep_clk_src",
2261 },
2262 .num_parents = 1,
2263 .ops = &clk_branch2_ops,
2264 },
2265 },
2266};
2267
2268static struct clk_branch gcc_usb30_master_clk = {
2269 .halt_reg = 0x03c8,
2270 .clkr = {
2271 .enable_reg = 0x03c8,
2272 .enable_mask = BIT(0),
2273 .hw.init = &(struct clk_init_data){
2274 .name = "gcc_usb30_master_clk",
2275 .parent_names = (const char *[]){
2276 "usb30_master_clk_src",
2277 },
2278 .num_parents = 1,
2279 .flags = CLK_SET_RATE_PARENT,
2280 .ops = &clk_branch2_ops,
2281 },
2282 },
2283};
2284
2285static struct clk_branch gcc_usb30_mock_utmi_clk = {
2286 .halt_reg = 0x03d0,
2287 .clkr = {
2288 .enable_reg = 0x03d0,
2289 .enable_mask = BIT(0),
2290 .hw.init = &(struct clk_init_data){
2291 .name = "gcc_usb30_mock_utmi_clk",
2292 .parent_names = (const char *[]){
2293 "usb30_mock_utmi_clk_src",
2294 },
2295 .num_parents = 1,
2296 .flags = CLK_SET_RATE_PARENT,
2297 .ops = &clk_branch2_ops,
2298 },
2299 },
2300};
2301
2302static struct clk_branch gcc_usb30_sleep_clk = {
2303 .halt_reg = 0x03cc,
2304 .clkr = {
2305 .enable_reg = 0x03cc,
2306 .enable_mask = BIT(0),
2307 .hw.init = &(struct clk_init_data){
2308 .name = "gcc_usb30_sleep_clk",
2309 .parent_names = (const char *[]){
2310 "sleep_clk_src",
2311 },
2312 .num_parents = 1,
2313 .ops = &clk_branch2_ops,
2314 },
2315 },
2316};
2317
2318static struct clk_branch gcc_usb_hs_ahb_clk = {
2319 .halt_reg = 0x0488,
2320 .clkr = {
2321 .enable_reg = 0x0488,
2322 .enable_mask = BIT(0),
2323 .hw.init = &(struct clk_init_data){
2324 .name = "gcc_usb_hs_ahb_clk",
2325 .parent_names = (const char *[]){
2326 "periph_noc_clk_src",
2327 },
2328 .num_parents = 1,
2329 .ops = &clk_branch2_ops,
2330 },
2331 },
2332};
2333
2334static struct clk_branch gcc_usb_hs_system_clk = {
2335 .halt_reg = 0x0484,
2336 .clkr = {
2337 .enable_reg = 0x0484,
2338 .enable_mask = BIT(0),
2339 .hw.init = &(struct clk_init_data){
2340 .name = "gcc_usb_hs_system_clk",
2341 .parent_names = (const char *[]){
2342 "usb_hs_system_clk_src",
2343 },
2344 .num_parents = 1,
2345 .flags = CLK_SET_RATE_PARENT,
2346 .ops = &clk_branch2_ops,
2347 },
2348 },
2349};
2350
2351static struct clk_branch gcc_usb_hsic_ahb_clk = {
2352 .halt_reg = 0x0408,
2353 .clkr = {
2354 .enable_reg = 0x0408,
2355 .enable_mask = BIT(0),
2356 .hw.init = &(struct clk_init_data){
2357 .name = "gcc_usb_hsic_ahb_clk",
2358 .parent_names = (const char *[]){
2359 "periph_noc_clk_src",
2360 },
2361 .num_parents = 1,
2362 .ops = &clk_branch2_ops,
2363 },
2364 },
2365};
2366
2367static struct clk_branch gcc_usb_hsic_clk = {
2368 .halt_reg = 0x0410,
2369 .clkr = {
2370 .enable_reg = 0x0410,
2371 .enable_mask = BIT(0),
2372 .hw.init = &(struct clk_init_data){
2373 .name = "gcc_usb_hsic_clk",
2374 .parent_names = (const char *[]){
2375 "usb_hsic_clk_src",
2376 },
2377 .num_parents = 1,
2378 .flags = CLK_SET_RATE_PARENT,
2379 .ops = &clk_branch2_ops,
2380 },
2381 },
2382};
2383
2384static struct clk_branch gcc_usb_hsic_io_cal_clk = {
2385 .halt_reg = 0x0414,
2386 .clkr = {
2387 .enable_reg = 0x0414,
2388 .enable_mask = BIT(0),
2389 .hw.init = &(struct clk_init_data){
2390 .name = "gcc_usb_hsic_io_cal_clk",
2391 .parent_names = (const char *[]){
2392 "usb_hsic_io_cal_clk_src",
2393 },
2394 .num_parents = 1,
2395 .flags = CLK_SET_RATE_PARENT,
2396 .ops = &clk_branch2_ops,
2397 },
2398 },
2399};
2400
2401static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
2402 .halt_reg = 0x0418,
2403 .clkr = {
2404 .enable_reg = 0x0418,
2405 .enable_mask = BIT(0),
2406 .hw.init = &(struct clk_init_data){
2407 .name = "gcc_usb_hsic_io_cal_sleep_clk",
2408 .parent_names = (const char *[]){
2409 "sleep_clk_src",
2410 },
2411 .num_parents = 1,
2412 .ops = &clk_branch2_ops,
2413 },
2414 },
2415};
2416
2417static struct clk_branch gcc_usb_hsic_system_clk = {
2418 .halt_reg = 0x040c,
2419 .clkr = {
2420 .enable_reg = 0x040c,
2421 .enable_mask = BIT(0),
2422 .hw.init = &(struct clk_init_data){
2423 .name = "gcc_usb_hsic_system_clk",
2424 .parent_names = (const char *[]){
2425 "usb_hsic_system_clk_src",
2426 },
2427 .num_parents = 1,
2428 .flags = CLK_SET_RATE_PARENT,
2429 .ops = &clk_branch2_ops,
2430 },
2431 },
2432};
2433
2434static struct clk_regmap *gcc_msm8974_clocks[] = {
2435 [GPLL0] = &gpll0.clkr,
2436 [GPLL0_VOTE] = &gpll0_vote,
2437 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
2438 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
2439 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
2440 [GPLL1] = &gpll1.clkr,
2441 [GPLL1_VOTE] = &gpll1_vote,
2442 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2443 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2444 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2445 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2446 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2447 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2448 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2449 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2450 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2451 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2452 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2453 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2454 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2455 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2456 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2457 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2458 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2459 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2460 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2461 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2462 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2463 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2464 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2465 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2466 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2467 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2468 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2469 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2470 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2471 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2472 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2473 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2474 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2475 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2476 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2477 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2478 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2479 [CE1_CLK_SRC] = &ce1_clk_src.clkr,
2480 [CE2_CLK_SRC] = &ce2_clk_src.clkr,
2481 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2482 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2483 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2484 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2485 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2486 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2487 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2488 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2489 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2490 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2491 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2492 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
2493 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
2494 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
2495 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
2496 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2497 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2498 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2499 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2500 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2501 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2502 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2503 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2504 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2505 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2506 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2507 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2508 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2509 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2510 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2511 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2512 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2513 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2514 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2515 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2516 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2517 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2518 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2519 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2520 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2521 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2522 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2523 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2524 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2525 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2526 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2527 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2528 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2529 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2530 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2531 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2532 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2533 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2534 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2535 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2536 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2537 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2538 [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
2539 [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
2540 [GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
2541 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2542 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2543 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2544 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2545 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2546 [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
2547 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2548 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2549 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2550 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2551 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2552 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2553 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2554 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2555 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2556 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2557 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2558 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2559 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2560 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2561 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2562 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2563 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2564 [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
2565 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2566 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2567 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2568 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2569 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2570 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
2571 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
2572 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
2573 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
2574 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
2575 [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
Stephen Boydc6858412014-05-16 16:07:13 -07002576 [GPLL4] = NULL,
2577 [GPLL4_VOTE] = NULL,
2578 [GCC_SDCC1_CDCCAL_SLEEP_CLK] = NULL,
2579 [GCC_SDCC1_CDCCAL_FF_CLK] = NULL,
Stephen Boydd33faa92014-01-15 10:47:30 -08002580};
2581
2582static const struct qcom_reset_map gcc_msm8974_resets[] = {
2583 [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
2584 [GCC_CONFIG_NOC_BCR] = { 0x0140 },
2585 [GCC_PERIPH_NOC_BCR] = { 0x0180 },
2586 [GCC_IMEM_BCR] = { 0x0200 },
2587 [GCC_MMSS_BCR] = { 0x0240 },
2588 [GCC_QDSS_BCR] = { 0x0300 },
2589 [GCC_USB_30_BCR] = { 0x03c0 },
2590 [GCC_USB3_PHY_BCR] = { 0x03fc },
2591 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2592 [GCC_USB_HS_BCR] = { 0x0480 },
2593 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
2594 [GCC_USB2B_PHY_BCR] = { 0x04b0 },
2595 [GCC_SDCC1_BCR] = { 0x04c0 },
2596 [GCC_SDCC2_BCR] = { 0x0500 },
2597 [GCC_SDCC3_BCR] = { 0x0540 },
2598 [GCC_SDCC4_BCR] = { 0x0580 },
2599 [GCC_BLSP1_BCR] = { 0x05c0 },
2600 [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
2601 [GCC_BLSP1_UART1_BCR] = { 0x0680 },
2602 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
2603 [GCC_BLSP1_UART2_BCR] = { 0x0700 },
2604 [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
2605 [GCC_BLSP1_UART3_BCR] = { 0x0780 },
2606 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
2607 [GCC_BLSP1_UART4_BCR] = { 0x0800 },
2608 [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
2609 [GCC_BLSP1_UART5_BCR] = { 0x0880 },
2610 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
2611 [GCC_BLSP1_UART6_BCR] = { 0x0900 },
2612 [GCC_BLSP2_BCR] = { 0x0940 },
2613 [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
2614 [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
2615 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
2616 [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
2617 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
2618 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
2619 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
2620 [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
2621 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
2622 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
2623 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
2624 [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
2625 [GCC_PDM_BCR] = { 0x0cc0 },
2626 [GCC_BAM_DMA_BCR] = { 0x0d40 },
2627 [GCC_TSIF_BCR] = { 0x0d80 },
2628 [GCC_TCSR_BCR] = { 0x0dc0 },
2629 [GCC_BOOT_ROM_BCR] = { 0x0e00 },
2630 [GCC_MSG_RAM_BCR] = { 0x0e40 },
2631 [GCC_TLMM_BCR] = { 0x0e80 },
2632 [GCC_MPM_BCR] = { 0x0ec0 },
2633 [GCC_SEC_CTRL_BCR] = { 0x0f40 },
2634 [GCC_SPMI_BCR] = { 0x0fc0 },
2635 [GCC_SPDM_BCR] = { 0x1000 },
2636 [GCC_CE1_BCR] = { 0x1040 },
2637 [GCC_CE2_BCR] = { 0x1080 },
2638 [GCC_BIMC_BCR] = { 0x1100 },
2639 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
2640 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
2641 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
2642 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
2643 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
2644 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
2645 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
2646 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
2647 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
2648 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
2649 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
2650 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
2651 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
2652 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
2653 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
2654 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
2655 [GCC_DEHR_BCR] = { 0x1300 },
2656 [GCC_RBCPR_BCR] = { 0x1380 },
2657 [GCC_MSS_RESTART] = { 0x1680 },
2658 [GCC_LPASS_RESTART] = { 0x16c0 },
2659 [GCC_WCSS_RESTART] = { 0x1700 },
2660 [GCC_VENUS_RESTART] = { 0x1740 },
2661};
2662
2663static const struct regmap_config gcc_msm8974_regmap_config = {
2664 .reg_bits = 32,
2665 .reg_stride = 4,
2666 .val_bits = 32,
2667 .max_register = 0x1fc0,
2668 .fast_io = true,
2669};
2670
Stephen Boyd49fc8252014-03-21 17:59:37 -07002671static const struct qcom_cc_desc gcc_msm8974_desc = {
2672 .config = &gcc_msm8974_regmap_config,
2673 .clks = gcc_msm8974_clocks,
2674 .num_clks = ARRAY_SIZE(gcc_msm8974_clocks),
2675 .resets = gcc_msm8974_resets,
2676 .num_resets = ARRAY_SIZE(gcc_msm8974_resets),
2677};
2678
Stephen Boydd33faa92014-01-15 10:47:30 -08002679static const struct of_device_id gcc_msm8974_match_table[] = {
2680 { .compatible = "qcom,gcc-msm8974" },
Stephen Boydc6858412014-05-16 16:07:13 -07002681 { .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL },
2682 { .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL },
Stephen Boydd33faa92014-01-15 10:47:30 -08002683 { }
2684};
2685MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
2686
Stephen Boydc6858412014-05-16 16:07:13 -07002687static void msm8974_pro_clock_override(void)
2688{
2689 sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4;
2690 sdcc1_apps_clk_src_init.num_parents = 3;
2691 sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro;
2692 sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map;
2693
2694 gcc_msm8974_clocks[GPLL4] = &gpll4.clkr;
2695 gcc_msm8974_clocks[GPLL4_VOTE] = &gpll4_vote;
2696 gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_SLEEP_CLK] =
2697 &gcc_sdcc1_cdccal_sleep_clk.clkr;
2698 gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_FF_CLK] =
2699 &gcc_sdcc1_cdccal_ff_clk.clkr;
2700}
2701
Stephen Boydd33faa92014-01-15 10:47:30 -08002702static int gcc_msm8974_probe(struct platform_device *pdev)
2703{
Stephen Boydd33faa92014-01-15 10:47:30 -08002704 struct clk *clk;
Stephen Boyd49fc8252014-03-21 17:59:37 -07002705 struct device *dev = &pdev->dev;
Stephen Boydc6858412014-05-16 16:07:13 -07002706 bool pro;
2707 const struct of_device_id *id;
2708
2709 id = of_match_device(gcc_msm8974_match_table, dev);
2710 if (!id)
2711 return -ENODEV;
2712 pro = !!(id->data);
2713
2714 if (pro)
2715 msm8974_pro_clock_override();
Stephen Boydd33faa92014-01-15 10:47:30 -08002716
2717 /* Temporary until RPM clocks supported */
2718 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
2719 if (IS_ERR(clk))
2720 return PTR_ERR(clk);
2721
2722 /* Should move to DT node? */
2723 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
2724 CLK_IS_ROOT, 32768);
2725 if (IS_ERR(clk))
2726 return PTR_ERR(clk);
2727
Stephen Boyd49fc8252014-03-21 17:59:37 -07002728 return qcom_cc_probe(pdev, &gcc_msm8974_desc);
Stephen Boydd33faa92014-01-15 10:47:30 -08002729}
2730
2731static int gcc_msm8974_remove(struct platform_device *pdev)
2732{
Stephen Boyd49fc8252014-03-21 17:59:37 -07002733 qcom_cc_remove(pdev);
Stephen Boydd33faa92014-01-15 10:47:30 -08002734 return 0;
2735}
2736
2737static struct platform_driver gcc_msm8974_driver = {
2738 .probe = gcc_msm8974_probe,
2739 .remove = gcc_msm8974_remove,
2740 .driver = {
2741 .name = "gcc-msm8974",
Stephen Boydd33faa92014-01-15 10:47:30 -08002742 .of_match_table = gcc_msm8974_match_table,
2743 },
2744};
2745
2746static int __init gcc_msm8974_init(void)
2747{
2748 return platform_driver_register(&gcc_msm8974_driver);
2749}
2750core_initcall(gcc_msm8974_init);
2751
2752static void __exit gcc_msm8974_exit(void)
2753{
2754 platform_driver_unregister(&gcc_msm8974_driver);
2755}
2756module_exit(gcc_msm8974_exit);
2757
2758MODULE_DESCRIPTION("QCOM GCC MSM8974 Driver");
2759MODULE_LICENSE("GPL v2");
2760MODULE_ALIAS("platform:gcc-msm8974");