Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/clock.h |
| 3 | * |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
Paul Walmsley | 530e544 | 2011-02-25 15:39:28 -0700 | [diff] [blame] | 5 | * Copyright (C) 2004-2011 Nokia Corporation |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 6 | * |
| 7 | * Contacts: |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 9 | * Paul Walmsley |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
| 16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H |
| 17 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H |
| 18 | |
Paul Walmsley | 12706c5 | 2011-07-10 05:57:06 -0600 | [diff] [blame] | 19 | #include <linux/kernel.h> |
Paul Walmsley | a135eaa | 2012-09-27 10:33:34 -0600 | [diff] [blame] | 20 | #include <linux/list.h> |
Paul Walmsley | 12706c5 | 2011-07-10 05:57:06 -0600 | [diff] [blame] | 21 | |
Paul Walmsley | e10dd62 | 2012-09-27 10:33:35 -0600 | [diff] [blame] | 22 | #include <linux/clkdev.h> |
Mike Turquette | f9ae32a | 2012-11-07 13:14:47 -0800 | [diff] [blame] | 23 | #include <linux/clk-provider.h> |
Paul Walmsley | e10dd62 | 2012-09-27 10:33:35 -0600 | [diff] [blame] | 24 | |
| 25 | struct omap_clk { |
| 26 | u16 cpu; |
| 27 | struct clk_lookup lk; |
| 28 | }; |
| 29 | |
J Keerthy | 78e52e0 | 2013-03-18 09:57:39 -0600 | [diff] [blame^] | 30 | #define CLK(dev, con, ck) \ |
Paul Walmsley | e10dd62 | 2012-09-27 10:33:35 -0600 | [diff] [blame] | 31 | { \ |
Paul Walmsley | e10dd62 | 2012-09-27 10:33:35 -0600 | [diff] [blame] | 32 | .lk = { \ |
| 33 | .dev_id = dev, \ |
| 34 | .con_id = con, \ |
| 35 | .clk = ck, \ |
| 36 | }, \ |
| 37 | } |
| 38 | |
Rajendra Nayak | b5a2366 | 2012-11-10 16:58:40 -0700 | [diff] [blame] | 39 | struct clockdomain; |
| 40 | #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) |
| 41 | |
Paul Walmsley | 8c725dc | 2012-09-16 10:45:54 -0600 | [diff] [blame] | 42 | #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ |
| 43 | static struct clk _name = { \ |
| 44 | .name = #_name, \ |
| 45 | .hw = &_name##_hw.hw, \ |
| 46 | .parent_names = _parent_array_name, \ |
| 47 | .num_parents = ARRAY_SIZE(_parent_array_name), \ |
| 48 | .ops = &_clkops_name, \ |
| 49 | }; |
| 50 | |
Afzal Mohammed | 601155b | 2013-01-23 17:12:05 +0530 | [diff] [blame] | 51 | #define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \ |
| 52 | _clkops_name, _flags) \ |
| 53 | static struct clk _name = { \ |
| 54 | .name = #_name, \ |
| 55 | .hw = &_name##_hw.hw, \ |
| 56 | .parent_names = _parent_array_name, \ |
| 57 | .num_parents = ARRAY_SIZE(_parent_array_name), \ |
| 58 | .ops = &_clkops_name, \ |
| 59 | .flags = _flags, \ |
| 60 | }; |
| 61 | |
Paul Walmsley | 8c725dc | 2012-09-16 10:45:54 -0600 | [diff] [blame] | 62 | #define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \ |
| 63 | static struct clk_hw_omap _name##_hw = { \ |
| 64 | .hw = { \ |
| 65 | .clk = &_name, \ |
| 66 | }, \ |
| 67 | .clkdm_name = _clkdm_name, \ |
| 68 | }; |
| 69 | |
| 70 | #define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \ |
| 71 | _clksel_reg, _clksel_mask, \ |
| 72 | _parent_names, _ops) \ |
| 73 | static struct clk _name; \ |
| 74 | static struct clk_hw_omap _name##_hw = { \ |
| 75 | .hw = { \ |
| 76 | .clk = &_name, \ |
| 77 | }, \ |
| 78 | .clksel = _clksel, \ |
| 79 | .clksel_reg = _clksel_reg, \ |
| 80 | .clksel_mask = _clksel_mask, \ |
| 81 | .clkdm_name = _clkdm_name, \ |
| 82 | }; \ |
| 83 | DEFINE_STRUCT_CLK(_name, _parent_names, _ops); |
| 84 | |
| 85 | #define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \ |
| 86 | _clksel_reg, _clksel_mask, \ |
| 87 | _enable_reg, _enable_bit, \ |
| 88 | _hwops, _parent_names, _ops) \ |
| 89 | static struct clk _name; \ |
| 90 | static struct clk_hw_omap _name##_hw = { \ |
| 91 | .hw = { \ |
| 92 | .clk = &_name, \ |
| 93 | }, \ |
| 94 | .ops = _hwops, \ |
| 95 | .enable_reg = _enable_reg, \ |
| 96 | .enable_bit = _enable_bit, \ |
| 97 | .clksel = _clksel, \ |
| 98 | .clksel_reg = _clksel_reg, \ |
| 99 | .clksel_mask = _clksel_mask, \ |
| 100 | .clkdm_name = _clkdm_name, \ |
| 101 | }; \ |
| 102 | DEFINE_STRUCT_CLK(_name, _parent_names, _ops); |
| 103 | |
| 104 | #define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \ |
| 105 | _parent_ptr, _flags, \ |
| 106 | _clksel_reg, _clksel_mask) \ |
| 107 | static const struct clksel _name##_div[] = { \ |
| 108 | { \ |
| 109 | .parent = _parent_ptr, \ |
| 110 | .rates = div31_1to31_rates \ |
| 111 | }, \ |
| 112 | { .parent = NULL }, \ |
| 113 | }; \ |
| 114 | static struct clk _name; \ |
| 115 | static const char *_name##_parent_names[] = { \ |
| 116 | _parent_name, \ |
| 117 | }; \ |
| 118 | static struct clk_hw_omap _name##_hw = { \ |
| 119 | .hw = { \ |
| 120 | .clk = &_name, \ |
| 121 | }, \ |
| 122 | .clksel = _name##_div, \ |
| 123 | .clksel_reg = _clksel_reg, \ |
| 124 | .clksel_mask = _clksel_mask, \ |
| 125 | .ops = &clkhwops_omap4_dpllmx, \ |
| 126 | }; \ |
| 127 | DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops); |
| 128 | |
Paul Walmsley | a135eaa | 2012-09-27 10:33:34 -0600 | [diff] [blame] | 129 | /* struct clksel_rate.flags possibilities */ |
| 130 | #define RATE_IN_242X (1 << 0) |
| 131 | #define RATE_IN_243X (1 << 1) |
| 132 | #define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */ |
| 133 | #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ |
| 134 | #define RATE_IN_36XX (1 << 4) |
| 135 | #define RATE_IN_4430 (1 << 5) |
| 136 | #define RATE_IN_TI816X (1 << 6) |
| 137 | #define RATE_IN_4460 (1 << 7) |
| 138 | #define RATE_IN_AM33XX (1 << 8) |
| 139 | #define RATE_IN_TI814X (1 << 9) |
| 140 | |
| 141 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) |
| 142 | #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) |
| 143 | #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) |
| 144 | #define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460) |
| 145 | |
| 146 | /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ |
| 147 | #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) |
| 148 | |
| 149 | |
| 150 | /** |
| 151 | * struct clksel_rate - register bitfield values corresponding to clk divisors |
| 152 | * @val: register bitfield value (shifted to bit 0) |
| 153 | * @div: clock divisor corresponding to @val |
| 154 | * @flags: (see "struct clksel_rate.flags possibilities" above) |
| 155 | * |
| 156 | * @val should match the value of a read from struct clk.clksel_reg |
| 157 | * AND'ed with struct clk.clksel_mask, shifted right to bit 0. |
| 158 | * |
| 159 | * @div is the divisor that should be applied to the parent clock's rate |
| 160 | * to produce the current clock's rate. |
| 161 | */ |
| 162 | struct clksel_rate { |
| 163 | u32 val; |
| 164 | u8 div; |
| 165 | u16 flags; |
| 166 | }; |
| 167 | |
| 168 | /** |
| 169 | * struct clksel - available parent clocks, and a pointer to their divisors |
| 170 | * @parent: struct clk * to a possible parent clock |
| 171 | * @rates: available divisors for this parent clock |
| 172 | * |
| 173 | * A struct clksel is always associated with one or more struct clks |
| 174 | * and one or more struct clksel_rates. |
| 175 | */ |
| 176 | struct clksel { |
| 177 | struct clk *parent; |
| 178 | const struct clksel_rate *rates; |
| 179 | }; |
| 180 | |
| 181 | /** |
| 182 | * struct dpll_data - DPLL registers and integration data |
| 183 | * @mult_div1_reg: register containing the DPLL M and N bitfields |
| 184 | * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg |
| 185 | * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg |
| 186 | * @clk_bypass: struct clk pointer to the clock's bypass clock input |
| 187 | * @clk_ref: struct clk pointer to the clock's reference clock input |
| 188 | * @control_reg: register containing the DPLL mode bitfield |
| 189 | * @enable_mask: mask of the DPLL mode bitfield in @control_reg |
| 190 | * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() |
| 191 | * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() |
Jon Hunter | 3ff51ed | 2012-12-15 01:35:46 -0700 | [diff] [blame] | 192 | * @last_rounded_m4xen: cache of the last M4X result of |
| 193 | * omap4_dpll_regm4xen_round_rate() |
| 194 | * @last_rounded_lpmode: cache of the last lpmode result of |
| 195 | * omap4_dpll_lpmode_recalc() |
Paul Walmsley | a135eaa | 2012-09-27 10:33:34 -0600 | [diff] [blame] | 196 | * @max_multiplier: maximum valid non-bypass multiplier value (actual) |
| 197 | * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() |
| 198 | * @min_divider: minimum valid non-bypass divider value (actual) |
| 199 | * @max_divider: maximum valid non-bypass divider value (actual) |
| 200 | * @modes: possible values of @enable_mask |
| 201 | * @autoidle_reg: register containing the DPLL autoidle mode bitfield |
| 202 | * @idlest_reg: register containing the DPLL idle status bitfield |
| 203 | * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg |
| 204 | * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg |
| 205 | * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg |
Jon Hunter | 3ff51ed | 2012-12-15 01:35:46 -0700 | [diff] [blame] | 206 | * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg |
| 207 | * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg |
Paul Walmsley | a135eaa | 2012-09-27 10:33:34 -0600 | [diff] [blame] | 208 | * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg |
| 209 | * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs |
| 210 | * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs |
| 211 | * @flags: DPLL type/features (see below) |
| 212 | * |
| 213 | * Possible values for @flags: |
| 214 | * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) |
| 215 | * |
| 216 | * @freqsel_mask is only used on the OMAP34xx family and AM35xx. |
| 217 | * |
| 218 | * XXX Some DPLLs have multiple bypass inputs, so it's not technically |
| 219 | * correct to only have one @clk_bypass pointer. |
| 220 | * |
| 221 | * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, |
| 222 | * @last_rounded_n) should be separated from the runtime-fixed fields |
| 223 | * and placed into a different structure, so that the runtime-fixed data |
| 224 | * can be placed into read-only space. |
| 225 | */ |
| 226 | struct dpll_data { |
| 227 | void __iomem *mult_div1_reg; |
| 228 | u32 mult_mask; |
| 229 | u32 div1_mask; |
| 230 | struct clk *clk_bypass; |
| 231 | struct clk *clk_ref; |
| 232 | void __iomem *control_reg; |
| 233 | u32 enable_mask; |
| 234 | unsigned long last_rounded_rate; |
| 235 | u16 last_rounded_m; |
Jon Hunter | 3ff51ed | 2012-12-15 01:35:46 -0700 | [diff] [blame] | 236 | u8 last_rounded_m4xen; |
| 237 | u8 last_rounded_lpmode; |
Paul Walmsley | a135eaa | 2012-09-27 10:33:34 -0600 | [diff] [blame] | 238 | u16 max_multiplier; |
| 239 | u8 last_rounded_n; |
| 240 | u8 min_divider; |
| 241 | u16 max_divider; |
| 242 | u8 modes; |
| 243 | void __iomem *autoidle_reg; |
| 244 | void __iomem *idlest_reg; |
| 245 | u32 autoidle_mask; |
| 246 | u32 freqsel_mask; |
| 247 | u32 idlest_mask; |
| 248 | u32 dco_mask; |
| 249 | u32 sddiv_mask; |
Jon Hunter | 3ff51ed | 2012-12-15 01:35:46 -0700 | [diff] [blame] | 250 | u32 lpmode_mask; |
| 251 | u32 m4xen_mask; |
Paul Walmsley | a135eaa | 2012-09-27 10:33:34 -0600 | [diff] [blame] | 252 | u8 auto_recal_bit; |
| 253 | u8 recal_en_bit; |
| 254 | u8 recal_st_bit; |
| 255 | u8 flags; |
| 256 | }; |
| 257 | |
| 258 | /* |
| 259 | * struct clk.flags possibilities |
| 260 | * |
| 261 | * XXX document the rest of the clock flags here |
| 262 | * |
| 263 | * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL |
| 264 | * bits share the same register. This flag allows the |
| 265 | * omap4_dpllmx*() code to determine which GATE_CTRL bit field |
| 266 | * should be used. This is a temporary solution - a better approach |
| 267 | * would be to associate clock type-specific data with the clock, |
| 268 | * similar to the struct dpll_data approach. |
| 269 | */ |
| 270 | #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ |
| 271 | #define CLOCK_IDLE_CONTROL (1 << 1) |
| 272 | #define CLOCK_NO_IDLE_PARENT (1 << 2) |
| 273 | #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ |
| 274 | #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ |
| 275 | #define CLOCK_CLKOUTX2 (1 << 5) |
| 276 | |
Rajendra Nayak | b5a2366 | 2012-11-10 16:58:40 -0700 | [diff] [blame] | 277 | /** |
| 278 | * struct clk_hw_omap - OMAP struct clk |
| 279 | * @node: list_head connecting this clock into the full clock list |
| 280 | * @enable_reg: register to write to enable the clock (see @enable_bit) |
| 281 | * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) |
| 282 | * @flags: see "struct clk.flags possibilities" above |
| 283 | * @clksel_reg: for clksel clks, register va containing src/divisor select |
| 284 | * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector |
| 285 | * @clksel: for clksel clks, pointer to struct clksel for this clock |
| 286 | * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock |
| 287 | * @clkdm_name: clockdomain name that this clock is contained in |
| 288 | * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime |
| 289 | * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) |
| 290 | * @src_offset: bitshift for source selection bitfield (OMAP1 only) |
| 291 | * |
| 292 | * XXX @rate_offset, @src_offset should probably be removed and OMAP1 |
| 293 | * clock code converted to use clksel. |
| 294 | * |
| 295 | */ |
| 296 | |
| 297 | struct clk_hw_omap_ops; |
| 298 | |
| 299 | struct clk_hw_omap { |
| 300 | struct clk_hw hw; |
| 301 | struct list_head node; |
| 302 | unsigned long fixed_rate; |
| 303 | u8 fixed_div; |
| 304 | void __iomem *enable_reg; |
| 305 | u8 enable_bit; |
| 306 | u8 flags; |
| 307 | void __iomem *clksel_reg; |
| 308 | u32 clksel_mask; |
| 309 | const struct clksel *clksel; |
| 310 | struct dpll_data *dpll_data; |
| 311 | const char *clkdm_name; |
| 312 | struct clockdomain *clkdm; |
| 313 | const struct clk_hw_omap_ops *ops; |
| 314 | }; |
| 315 | |
| 316 | struct clk_hw_omap_ops { |
| 317 | void (*find_idlest)(struct clk_hw_omap *oclk, |
| 318 | void __iomem **idlest_reg, |
| 319 | u8 *idlest_bit, u8 *idlest_val); |
| 320 | void (*find_companion)(struct clk_hw_omap *oclk, |
| 321 | void __iomem **other_reg, |
| 322 | u8 *other_bit); |
| 323 | void (*allow_idle)(struct clk_hw_omap *oclk); |
| 324 | void (*deny_idle)(struct clk_hw_omap *oclk); |
| 325 | }; |
| 326 | |
| 327 | unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, |
| 328 | unsigned long parent_rate); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 329 | |
Russell King | c0bf313 | 2009-02-19 13:29:22 +0000 | [diff] [blame] | 330 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ |
| 331 | #define CORE_CLK_SRC_32K 0x0 |
| 332 | #define CORE_CLK_SRC_DPLL 0x1 |
| 333 | #define CORE_CLK_SRC_DPLL_X2 0x2 |
| 334 | |
| 335 | /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ |
| 336 | #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 |
| 337 | #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 |
| 338 | #define OMAP2XXX_EN_DPLL_LOCKED 0x3 |
| 339 | |
| 340 | /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ |
| 341 | #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 |
| 342 | #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 |
| 343 | #define OMAP3XXX_EN_DPLL_LOCKED 0x7 |
| 344 | |
Rajendra Nayak | 16975a7 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 345 | /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ |
| 346 | #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 |
| 347 | #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 |
| 348 | #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 |
| 349 | #define OMAP4XXX_EN_DPLL_LOCKED 0x7 |
| 350 | |
Rajendra Nayak | a1391d2 | 2009-12-08 18:47:16 -0700 | [diff] [blame] | 351 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
| 352 | #define DPLL_LOW_POWER_STOP 0x1 |
| 353 | #define DPLL_LOW_POWER_BYPASS 0x5 |
| 354 | #define DPLL_LOCKED 0x7 |
| 355 | |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 356 | /* DPLL Type and DCO Selection Flags */ |
| 357 | #define DPLL_J_TYPE 0x1 |
Richard Woodruff | 358965d | 2010-02-22 22:09:08 -0700 | [diff] [blame] | 358 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 359 | long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, |
| 360 | unsigned long *parent_rate); |
| 361 | unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); |
| 362 | int omap3_noncore_dpll_enable(struct clk_hw *hw); |
| 363 | void omap3_noncore_dpll_disable(struct clk_hw *hw); |
| 364 | int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, |
| 365 | unsigned long parent_rate); |
| 366 | u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); |
| 367 | void omap3_dpll_allow_idle(struct clk_hw_omap *clk); |
| 368 | void omap3_dpll_deny_idle(struct clk_hw_omap *clk); |
| 369 | unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, |
| 370 | unsigned long parent_rate); |
| 371 | int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk); |
| 372 | void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); |
| 373 | void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); |
| 374 | unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, |
| 375 | unsigned long parent_rate); |
| 376 | long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, |
| 377 | unsigned long target_rate, |
| 378 | unsigned long *parent_rate); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 379 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 380 | void omap2_init_clk_clkdm(struct clk_hw *clk); |
Paul Walmsley | 12706c5 | 2011-07-10 05:57:06 -0600 | [diff] [blame] | 381 | void __init omap2_clk_disable_clkdm_control(void); |
Paul Walmsley | 435699d | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 382 | |
| 383 | /* clkt_clksel.c public functions */ |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 384 | u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, |
| 385 | unsigned long target_rate, |
| 386 | u32 *new_div); |
| 387 | u8 omap2_clksel_find_parent_index(struct clk_hw *hw); |
| 388 | unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate); |
| 389 | long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, |
| 390 | unsigned long *parent_rate); |
| 391 | int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, |
| 392 | unsigned long parent_rate); |
| 393 | int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); |
Paul Walmsley | 435699d | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 394 | |
Paul Walmsley | 530e544 | 2011-02-25 15:39:28 -0700 | [diff] [blame] | 395 | /* clkt_iclk.c public functions */ |
Rajendra Nayak | b4777a2 | 2012-04-27 15:53:48 +0530 | [diff] [blame] | 396 | extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); |
| 397 | extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); |
Paul Walmsley | 530e544 | 2011-02-25 15:39:28 -0700 | [diff] [blame] | 398 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 399 | u8 omap2_init_dpll_parent(struct clk_hw *hw); |
| 400 | unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); |
Paul Walmsley | 435699d | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 401 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 402 | int omap2_dflt_clk_enable(struct clk_hw *hw); |
| 403 | void omap2_dflt_clk_disable(struct clk_hw *hw); |
| 404 | int omap2_dflt_clk_is_enabled(struct clk_hw *hw); |
| 405 | void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, |
| 406 | void __iomem **other_reg, |
| 407 | u8 *other_bit); |
| 408 | void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, |
| 409 | void __iomem **idlest_reg, |
| 410 | u8 *idlest_bit, u8 *idlest_val); |
Rajendra Nayak | 23fb8ba | 2012-06-01 14:02:49 +0530 | [diff] [blame] | 411 | void omap2_init_clk_hw_omap_clocks(struct clk *clk); |
| 412 | int omap2_clk_enable_autoidle_all(void); |
| 413 | int omap2_clk_disable_autoidle_all(void); |
Rajendra Nayak | 8577413 | 2012-06-01 14:02:49 +0530 | [diff] [blame] | 414 | void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); |
Paul Walmsley | 4d30e82 | 2010-02-22 22:09:36 -0700 | [diff] [blame] | 415 | int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); |
| 416 | void omap2_clk_print_new_rates(const char *hfclkin_ck_name, |
| 417 | const char *core_ck_name, |
| 418 | const char *mpu_ck_name); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 419 | |
Afzal Mohammed | 9954119 | 2011-12-13 10:46:43 -0800 | [diff] [blame] | 420 | extern u16 cpu_mask; |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 421 | |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 422 | extern const struct clkops clkops_omap2_dflt_wait; |
Santosh Shilimkar | 7c43d54 | 2010-02-22 22:09:40 -0700 | [diff] [blame] | 423 | extern const struct clkops clkops_dummy; |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 424 | extern const struct clkops clkops_omap2_dflt; |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 425 | |
Paul Walmsley | 82e9bd5 | 2009-12-08 16:18:47 -0700 | [diff] [blame] | 426 | extern struct clk_functions omap2_clk_functions; |
| 427 | |
Paul Walmsley | d8a9445 | 2009-12-08 16:21:29 -0700 | [diff] [blame] | 428 | extern const struct clksel_rate gpt_32k_rates[]; |
| 429 | extern const struct clksel_rate gpt_sys_rates[]; |
| 430 | extern const struct clksel_rate gfx_l3_rates[]; |
Paul Walmsley | 2241139 | 2011-02-25 15:52:04 -0700 | [diff] [blame] | 431 | extern const struct clksel_rate dsp_ick_rates[]; |
Rajendra Nayak | cb26867 | 2012-11-06 15:41:08 -0700 | [diff] [blame] | 432 | extern struct clk dummy_ck; |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 433 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 434 | extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; |
| 435 | extern const struct clk_hw_omap_ops clkhwops_iclk_wait; |
| 436 | extern const struct clk_hw_omap_ops clkhwops_wait; |
| 437 | extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; |
Rajendra Nayak | b4777a2 | 2012-04-27 15:53:48 +0530 | [diff] [blame] | 438 | extern const struct clk_hw_omap_ops clkhwops_iclk; |
| 439 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; |
| 440 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; |
| 441 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; |
| 442 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; |
| 443 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; |
| 444 | extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait; |
| 445 | extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; |
| 446 | extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; |
| 447 | extern const struct clk_hw_omap_ops clkhwops_apll54; |
| 448 | extern const struct clk_hw_omap_ops clkhwops_apll96; |
| 449 | extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; |
| 450 | extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 451 | |
Paul Walmsley | 571efa0 | 2012-05-29 15:26:40 +0530 | [diff] [blame] | 452 | /* clksel_rate blocks shared between OMAP44xx and AM33xx */ |
| 453 | extern const struct clksel_rate div_1_0_rates[]; |
Rajendra Nayak | cb26867 | 2012-11-06 15:41:08 -0700 | [diff] [blame] | 454 | extern const struct clksel_rate div3_1to4_rates[]; |
Paul Walmsley | 571efa0 | 2012-05-29 15:26:40 +0530 | [diff] [blame] | 455 | extern const struct clksel_rate div_1_1_rates[]; |
| 456 | extern const struct clksel_rate div_1_2_rates[]; |
| 457 | extern const struct clksel_rate div_1_3_rates[]; |
| 458 | extern const struct clksel_rate div_1_4_rates[]; |
| 459 | extern const struct clksel_rate div31_1to31_rates[]; |
| 460 | |
Vaibhav Hiremath | e30384a | 2012-05-29 15:26:41 +0530 | [diff] [blame] | 461 | extern int am33xx_clk_init(void); |
| 462 | |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 463 | extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); |
| 464 | extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); |
Mike Turquette | 32cc002 | 2012-11-10 16:58:41 -0700 | [diff] [blame] | 465 | |
J Keerthy | 78e52e0 | 2013-03-18 09:57:39 -0600 | [diff] [blame^] | 466 | extern void omap_clocks_register(struct omap_clk *oclks, int cnt); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 467 | #endif |