Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | #include <dt-bindings/clock/imx6sx-clock.h> |
| 10 | #include <dt-bindings/gpio/gpio.h> |
Frank Li | 93db055 | 2015-05-27 00:26:02 +0800 | [diff] [blame] | 11 | #include <dt-bindings/input/input.h> |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 13 | #include "imx6sx-pinfunc.h" |
| 14 | #include "skeleton.dtsi" |
| 15 | |
| 16 | / { |
| 17 | aliases { |
| 18 | can0 = &flexcan1; |
| 19 | can1 = &flexcan2; |
| 20 | ethernet0 = &fec1; |
| 21 | ethernet1 = &fec2; |
| 22 | gpio0 = &gpio1; |
| 23 | gpio1 = &gpio2; |
| 24 | gpio2 = &gpio3; |
| 25 | gpio3 = &gpio4; |
| 26 | gpio4 = &gpio5; |
| 27 | gpio5 = &gpio6; |
| 28 | gpio6 = &gpio7; |
| 29 | i2c0 = &i2c1; |
| 30 | i2c1 = &i2c2; |
| 31 | i2c2 = &i2c3; |
| 32 | i2c3 = &i2c4; |
| 33 | mmc0 = &usdhc1; |
| 34 | mmc1 = &usdhc2; |
| 35 | mmc2 = &usdhc3; |
| 36 | mmc3 = &usdhc4; |
| 37 | serial0 = &uart1; |
| 38 | serial1 = &uart2; |
| 39 | serial2 = &uart3; |
| 40 | serial3 = &uart4; |
| 41 | serial4 = &uart5; |
| 42 | serial5 = &uart6; |
| 43 | spi0 = &ecspi1; |
| 44 | spi1 = &ecspi2; |
| 45 | spi2 = &ecspi3; |
| 46 | spi3 = &ecspi4; |
| 47 | spi4 = &ecspi5; |
| 48 | usbphy0 = &usbphy1; |
| 49 | usbphy1 = &usbphy2; |
| 50 | }; |
| 51 | |
| 52 | cpus { |
| 53 | #address-cells = <1>; |
| 54 | #size-cells = <0>; |
| 55 | |
| 56 | cpu0: cpu@0 { |
| 57 | compatible = "arm,cortex-a9"; |
| 58 | device_type = "cpu"; |
| 59 | reg = <0>; |
| 60 | next-level-cache = <&L2>; |
| 61 | operating-points = < |
| 62 | /* kHz uV */ |
| 63 | 996000 1250000 |
| 64 | 792000 1175000 |
| 65 | 396000 1075000 |
| 66 | >; |
| 67 | fsl,soc-operating-points = < |
| 68 | /* ARM kHz SOC uV */ |
| 69 | 996000 1175000 |
| 70 | 792000 1175000 |
| 71 | 396000 1175000 |
| 72 | >; |
| 73 | clock-latency = <61036>; /* two CLK32 periods */ |
| 74 | clocks = <&clks IMX6SX_CLK_ARM>, |
| 75 | <&clks IMX6SX_CLK_PLL2_PFD2>, |
| 76 | <&clks IMX6SX_CLK_STEP>, |
| 77 | <&clks IMX6SX_CLK_PLL1_SW>, |
| 78 | <&clks IMX6SX_CLK_PLL1_SYS>; |
| 79 | clock-names = "arm", "pll2_pfd2_396m", "step", |
| 80 | "pll1_sw", "pll1_sys"; |
| 81 | arm-supply = <®_arm>; |
| 82 | soc-supply = <®_soc>; |
| 83 | }; |
| 84 | }; |
| 85 | |
| 86 | intc: interrupt-controller@00a01000 { |
| 87 | compatible = "arm,cortex-a9-gic"; |
| 88 | #interrupt-cells = <3>; |
| 89 | interrupt-controller; |
| 90 | reg = <0x00a01000 0x1000>, |
| 91 | <0x00a00100 0x100>; |
Marc Zyngier | b923ff6 | 2015-02-23 17:45:18 +0000 | [diff] [blame] | 92 | interrupt-parent = <&intc>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 93 | }; |
| 94 | |
| 95 | clocks { |
| 96 | #address-cells = <1>; |
| 97 | #size-cells = <0>; |
| 98 | |
| 99 | ckil: clock@0 { |
| 100 | compatible = "fixed-clock"; |
| 101 | reg = <0>; |
| 102 | #clock-cells = <0>; |
| 103 | clock-frequency = <32768>; |
| 104 | clock-output-names = "ckil"; |
| 105 | }; |
| 106 | |
| 107 | osc: clock@1 { |
| 108 | compatible = "fixed-clock"; |
| 109 | reg = <1>; |
| 110 | #clock-cells = <0>; |
| 111 | clock-frequency = <24000000>; |
| 112 | clock-output-names = "osc"; |
| 113 | }; |
| 114 | |
| 115 | ipp_di0: clock@2 { |
| 116 | compatible = "fixed-clock"; |
| 117 | reg = <2>; |
| 118 | #clock-cells = <0>; |
| 119 | clock-frequency = <0>; |
| 120 | clock-output-names = "ipp_di0"; |
| 121 | }; |
| 122 | |
| 123 | ipp_di1: clock@3 { |
| 124 | compatible = "fixed-clock"; |
| 125 | reg = <3>; |
| 126 | #clock-cells = <0>; |
| 127 | clock-frequency = <0>; |
| 128 | clock-output-names = "ipp_di1"; |
| 129 | }; |
| 130 | }; |
| 131 | |
| 132 | soc { |
| 133 | #address-cells = <1>; |
| 134 | #size-cells = <1>; |
| 135 | compatible = "simple-bus"; |
Marc Zyngier | b923ff6 | 2015-02-23 17:45:18 +0000 | [diff] [blame] | 136 | interrupt-parent = <&gpc>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 137 | ranges; |
| 138 | |
| 139 | pmu { |
| 140 | compatible = "arm,cortex-a9-pmu"; |
| 141 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 142 | }; |
| 143 | |
| 144 | ocram: sram@00900000 { |
| 145 | compatible = "mmio-sram"; |
| 146 | reg = <0x00900000 0x20000>; |
| 147 | clocks = <&clks IMX6SX_CLK_OCRAM>; |
| 148 | }; |
| 149 | |
| 150 | L2: l2-cache@00a02000 { |
| 151 | compatible = "arm,pl310-cache"; |
| 152 | reg = <0x00a02000 0x1000>; |
| 153 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 154 | cache-unified; |
| 155 | cache-level = <2>; |
| 156 | arm,tag-latency = <4 2 3>; |
| 157 | arm,data-latency = <4 2 3>; |
| 158 | }; |
| 159 | |
| 160 | dma_apbh: dma-apbh@01804000 { |
| 161 | compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; |
| 162 | reg = <0x01804000 0x2000>; |
| 163 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 164 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 165 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 166 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 167 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; |
| 168 | #dma-cells = <1>; |
| 169 | dma-channels = <4>; |
| 170 | clocks = <&clks IMX6SX_CLK_APBH_DMA>; |
| 171 | }; |
| 172 | |
| 173 | gpmi: gpmi-nand@01806000{ |
| 174 | compatible = "fsl,imx6sx-gpmi-nand"; |
| 175 | #address-cells = <1>; |
| 176 | #size-cells = <1>; |
| 177 | reg = <0x01806000 0x2000>, <0x01808000 0x4000>; |
| 178 | reg-names = "gpmi-nand", "bch"; |
| 179 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 180 | interrupt-names = "bch"; |
| 181 | clocks = <&clks IMX6SX_CLK_GPMI_IO>, |
| 182 | <&clks IMX6SX_CLK_GPMI_APB>, |
| 183 | <&clks IMX6SX_CLK_GPMI_BCH>, |
| 184 | <&clks IMX6SX_CLK_GPMI_BCH_APB>, |
| 185 | <&clks IMX6SX_CLK_PER1_BCH>; |
| 186 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", |
| 187 | "gpmi_bch_apb", "per1_bch"; |
| 188 | dmas = <&dma_apbh 0>; |
| 189 | dma-names = "rx-tx"; |
| 190 | status = "disabled"; |
| 191 | }; |
| 192 | |
| 193 | aips1: aips-bus@02000000 { |
| 194 | compatible = "fsl,aips-bus", "simple-bus"; |
| 195 | #address-cells = <1>; |
| 196 | #size-cells = <1>; |
| 197 | reg = <0x02000000 0x100000>; |
| 198 | ranges; |
| 199 | |
| 200 | spba-bus@02000000 { |
| 201 | compatible = "fsl,spba-bus", "simple-bus"; |
| 202 | #address-cells = <1>; |
| 203 | #size-cells = <1>; |
| 204 | reg = <0x02000000 0x40000>; |
| 205 | ranges; |
| 206 | |
| 207 | spdif: spdif@02004000 { |
| 208 | compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; |
| 209 | reg = <0x02004000 0x4000>; |
| 210 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
| 211 | dmas = <&sdma 14 18 0>, |
| 212 | <&sdma 15 18 0>; |
| 213 | dma-names = "rx", "tx"; |
Shengjiu Wang | 833f2cb | 2015-10-10 18:15:07 +0800 | [diff] [blame] | 214 | clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 215 | <&clks IMX6SX_CLK_OSC>, |
| 216 | <&clks IMX6SX_CLK_SPDIF>, |
| 217 | <&clks 0>, <&clks 0>, <&clks 0>, |
| 218 | <&clks IMX6SX_CLK_IPG>, |
| 219 | <&clks 0>, <&clks 0>, |
| 220 | <&clks IMX6SX_CLK_SPBA>; |
| 221 | clock-names = "core", "rxtx0", |
| 222 | "rxtx1", "rxtx2", |
| 223 | "rxtx3", "rxtx4", |
| 224 | "rxtx5", "rxtx6", |
Shengjiu Wang | 09d3059 | 2015-11-26 10:39:30 +0800 | [diff] [blame] | 225 | "rxtx7", "spba"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 226 | status = "disabled"; |
| 227 | }; |
| 228 | |
| 229 | ecspi1: ecspi@02008000 { |
| 230 | #address-cells = <1>; |
| 231 | #size-cells = <0>; |
| 232 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; |
| 233 | reg = <0x02008000 0x4000>; |
| 234 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| 235 | clocks = <&clks IMX6SX_CLK_ECSPI1>, |
| 236 | <&clks IMX6SX_CLK_ECSPI1>; |
| 237 | clock-names = "ipg", "per"; |
| 238 | status = "disabled"; |
| 239 | }; |
| 240 | |
| 241 | ecspi2: ecspi@0200c000 { |
| 242 | #address-cells = <1>; |
| 243 | #size-cells = <0>; |
| 244 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; |
| 245 | reg = <0x0200c000 0x4000>; |
| 246 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| 247 | clocks = <&clks IMX6SX_CLK_ECSPI2>, |
| 248 | <&clks IMX6SX_CLK_ECSPI2>; |
| 249 | clock-names = "ipg", "per"; |
| 250 | status = "disabled"; |
| 251 | }; |
| 252 | |
| 253 | ecspi3: ecspi@02010000 { |
| 254 | #address-cells = <1>; |
| 255 | #size-cells = <0>; |
| 256 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; |
| 257 | reg = <0x02010000 0x4000>; |
| 258 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| 259 | clocks = <&clks IMX6SX_CLK_ECSPI3>, |
| 260 | <&clks IMX6SX_CLK_ECSPI3>; |
| 261 | clock-names = "ipg", "per"; |
| 262 | status = "disabled"; |
| 263 | }; |
| 264 | |
| 265 | ecspi4: ecspi@02014000 { |
| 266 | #address-cells = <1>; |
| 267 | #size-cells = <0>; |
| 268 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; |
| 269 | reg = <0x02014000 0x4000>; |
| 270 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| 271 | clocks = <&clks IMX6SX_CLK_ECSPI4>, |
| 272 | <&clks IMX6SX_CLK_ECSPI4>; |
| 273 | clock-names = "ipg", "per"; |
| 274 | status = "disabled"; |
| 275 | }; |
| 276 | |
| 277 | uart1: serial@02020000 { |
| 278 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; |
| 279 | reg = <0x02020000 0x4000>; |
| 280 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| 281 | clocks = <&clks IMX6SX_CLK_UART_IPG>, |
| 282 | <&clks IMX6SX_CLK_UART_SERIAL>; |
| 283 | clock-names = "ipg", "per"; |
| 284 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
| 285 | dma-names = "rx", "tx"; |
| 286 | status = "disabled"; |
| 287 | }; |
| 288 | |
| 289 | esai: esai@02024000 { |
| 290 | reg = <0x02024000 0x4000>; |
| 291 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
| 292 | clocks = <&clks IMX6SX_CLK_ESAI_IPG>, |
| 293 | <&clks IMX6SX_CLK_ESAI_MEM>, |
| 294 | <&clks IMX6SX_CLK_ESAI_EXTAL>, |
| 295 | <&clks IMX6SX_CLK_ESAI_IPG>, |
| 296 | <&clks IMX6SX_CLK_SPBA>; |
| 297 | clock-names = "core", "mem", "extal", |
Shengjiu Wang | 09d3059 | 2015-11-26 10:39:30 +0800 | [diff] [blame] | 298 | "fsys", "spba"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 299 | status = "disabled"; |
| 300 | }; |
| 301 | |
| 302 | ssi1: ssi@02028000 { |
Alexander Shiyan | 6ff7f51 | 2014-08-19 20:00:09 +0400 | [diff] [blame] | 303 | #sound-dai-cells = <0>; |
Fabio Estevam | 4c03527 | 2014-07-07 10:04:52 -0300 | [diff] [blame] | 304 | compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 305 | reg = <0x02028000 0x4000>; |
| 306 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| 307 | clocks = <&clks IMX6SX_CLK_SSI1_IPG>, |
| 308 | <&clks IMX6SX_CLK_SSI1>; |
| 309 | clock-names = "ipg", "baud"; |
| 310 | dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; |
| 311 | dma-names = "rx", "tx"; |
Fabio Estevam | 3a462a6 | 2014-07-02 11:58:50 -0300 | [diff] [blame] | 312 | fsl,fifo-depth = <15>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 313 | status = "disabled"; |
| 314 | }; |
| 315 | |
| 316 | ssi2: ssi@0202c000 { |
Alexander Shiyan | 6ff7f51 | 2014-08-19 20:00:09 +0400 | [diff] [blame] | 317 | #sound-dai-cells = <0>; |
Fabio Estevam | 4c03527 | 2014-07-07 10:04:52 -0300 | [diff] [blame] | 318 | compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 319 | reg = <0x0202c000 0x4000>; |
| 320 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| 321 | clocks = <&clks IMX6SX_CLK_SSI2_IPG>, |
| 322 | <&clks IMX6SX_CLK_SSI2>; |
| 323 | clock-names = "ipg", "baud"; |
| 324 | dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; |
| 325 | dma-names = "rx", "tx"; |
Fabio Estevam | 3a462a6 | 2014-07-02 11:58:50 -0300 | [diff] [blame] | 326 | fsl,fifo-depth = <15>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 327 | status = "disabled"; |
| 328 | }; |
| 329 | |
| 330 | ssi3: ssi@02030000 { |
Alexander Shiyan | 6ff7f51 | 2014-08-19 20:00:09 +0400 | [diff] [blame] | 331 | #sound-dai-cells = <0>; |
Fabio Estevam | 4c03527 | 2014-07-07 10:04:52 -0300 | [diff] [blame] | 332 | compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 333 | reg = <0x02030000 0x4000>; |
| 334 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
| 335 | clocks = <&clks IMX6SX_CLK_SSI3_IPG>, |
| 336 | <&clks IMX6SX_CLK_SSI3>; |
| 337 | clock-names = "ipg", "baud"; |
| 338 | dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; |
| 339 | dma-names = "rx", "tx"; |
Fabio Estevam | 3a462a6 | 2014-07-02 11:58:50 -0300 | [diff] [blame] | 340 | fsl,fifo-depth = <15>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 341 | status = "disabled"; |
| 342 | }; |
| 343 | |
| 344 | asrc: asrc@02034000 { |
| 345 | reg = <0x02034000 0x4000>; |
| 346 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
| 347 | clocks = <&clks IMX6SX_CLK_ASRC_MEM>, |
| 348 | <&clks IMX6SX_CLK_ASRC_IPG>, |
| 349 | <&clks IMX6SX_CLK_SPDIF>, |
| 350 | <&clks IMX6SX_CLK_SPBA>; |
Shengjiu Wang | 09d3059 | 2015-11-26 10:39:30 +0800 | [diff] [blame] | 351 | clock-names = "mem", "ipg", "asrck", "spba"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 352 | dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, |
| 353 | <&sdma 19 20 1>, <&sdma 20 20 1>, |
| 354 | <&sdma 21 20 1>, <&sdma 22 20 1>; |
| 355 | dma-names = "rxa", "rxb", "rxc", |
| 356 | "txa", "txb", "txc"; |
| 357 | status = "okay"; |
| 358 | }; |
| 359 | }; |
| 360 | |
| 361 | pwm1: pwm@02080000 { |
| 362 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 363 | reg = <0x02080000 0x4000>; |
| 364 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 365 | clocks = <&clks IMX6SX_CLK_PWM1>, |
| 366 | <&clks IMX6SX_CLK_PWM1>; |
| 367 | clock-names = "ipg", "per"; |
| 368 | #pwm-cells = <2>; |
| 369 | }; |
| 370 | |
| 371 | pwm2: pwm@02084000 { |
| 372 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 373 | reg = <0x02084000 0x4000>; |
| 374 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| 375 | clocks = <&clks IMX6SX_CLK_PWM2>, |
| 376 | <&clks IMX6SX_CLK_PWM2>; |
| 377 | clock-names = "ipg", "per"; |
| 378 | #pwm-cells = <2>; |
| 379 | }; |
| 380 | |
| 381 | pwm3: pwm@02088000 { |
| 382 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 383 | reg = <0x02088000 0x4000>; |
| 384 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| 385 | clocks = <&clks IMX6SX_CLK_PWM3>, |
| 386 | <&clks IMX6SX_CLK_PWM3>; |
| 387 | clock-names = "ipg", "per"; |
| 388 | #pwm-cells = <2>; |
| 389 | }; |
| 390 | |
| 391 | pwm4: pwm@0208c000 { |
| 392 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 393 | reg = <0x0208c000 0x4000>; |
| 394 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 395 | clocks = <&clks IMX6SX_CLK_PWM4>, |
| 396 | <&clks IMX6SX_CLK_PWM4>; |
| 397 | clock-names = "ipg", "per"; |
| 398 | #pwm-cells = <2>; |
| 399 | }; |
| 400 | |
| 401 | flexcan1: can@02090000 { |
| 402 | compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; |
| 403 | reg = <0x02090000 0x4000>; |
| 404 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| 405 | clocks = <&clks IMX6SX_CLK_CAN1_IPG>, |
| 406 | <&clks IMX6SX_CLK_CAN1_SERIAL>; |
| 407 | clock-names = "ipg", "per"; |
| 408 | status = "disabled"; |
| 409 | }; |
| 410 | |
| 411 | flexcan2: can@02094000 { |
| 412 | compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; |
| 413 | reg = <0x02094000 0x4000>; |
| 414 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| 415 | clocks = <&clks IMX6SX_CLK_CAN2_IPG>, |
| 416 | <&clks IMX6SX_CLK_CAN2_SERIAL>; |
| 417 | clock-names = "ipg", "per"; |
| 418 | status = "disabled"; |
| 419 | }; |
| 420 | |
| 421 | gpt: gpt@02098000 { |
| 422 | compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt"; |
| 423 | reg = <0x02098000 0x4000>; |
| 424 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
| 425 | clocks = <&clks IMX6SX_CLK_GPT_BUS>, |
Anson Huang | 2b2244a | 2014-09-11 11:29:41 +0800 | [diff] [blame] | 426 | <&clks IMX6SX_CLK_GPT_3M>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 427 | clock-names = "ipg", "per"; |
| 428 | }; |
| 429 | |
| 430 | gpio1: gpio@0209c000 { |
| 431 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; |
| 432 | reg = <0x0209c000 0x4000>; |
| 433 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, |
| 434 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| 435 | gpio-controller; |
| 436 | #gpio-cells = <2>; |
| 437 | interrupt-controller; |
| 438 | #interrupt-cells = <2>; |
| 439 | }; |
| 440 | |
| 441 | gpio2: gpio@020a0000 { |
| 442 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; |
| 443 | reg = <0x020a0000 0x4000>; |
| 444 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, |
| 445 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| 446 | gpio-controller; |
| 447 | #gpio-cells = <2>; |
| 448 | interrupt-controller; |
| 449 | #interrupt-cells = <2>; |
| 450 | }; |
| 451 | |
| 452 | gpio3: gpio@020a4000 { |
| 453 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; |
| 454 | reg = <0x020a4000 0x4000>; |
| 455 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, |
| 456 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| 457 | gpio-controller; |
| 458 | #gpio-cells = <2>; |
| 459 | interrupt-controller; |
| 460 | #interrupt-cells = <2>; |
| 461 | }; |
| 462 | |
| 463 | gpio4: gpio@020a8000 { |
| 464 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; |
| 465 | reg = <0x020a8000 0x4000>; |
| 466 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
| 467 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 468 | gpio-controller; |
| 469 | #gpio-cells = <2>; |
| 470 | interrupt-controller; |
| 471 | #interrupt-cells = <2>; |
| 472 | }; |
| 473 | |
| 474 | gpio5: gpio@020ac000 { |
| 475 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; |
| 476 | reg = <0x020ac000 0x4000>; |
| 477 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, |
| 478 | <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| 479 | gpio-controller; |
| 480 | #gpio-cells = <2>; |
| 481 | interrupt-controller; |
| 482 | #interrupt-cells = <2>; |
| 483 | }; |
| 484 | |
| 485 | gpio6: gpio@020b0000 { |
| 486 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; |
| 487 | reg = <0x020b0000 0x4000>; |
| 488 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, |
| 489 | <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 490 | gpio-controller; |
| 491 | #gpio-cells = <2>; |
| 492 | interrupt-controller; |
| 493 | #interrupt-cells = <2>; |
| 494 | }; |
| 495 | |
| 496 | gpio7: gpio@020b4000 { |
| 497 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; |
| 498 | reg = <0x020b4000 0x4000>; |
| 499 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, |
| 500 | <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| 501 | gpio-controller; |
| 502 | #gpio-cells = <2>; |
| 503 | interrupt-controller; |
| 504 | #interrupt-cells = <2>; |
| 505 | }; |
| 506 | |
| 507 | kpp: kpp@020b8000 { |
| 508 | compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; |
| 509 | reg = <0x020b8000 0x4000>; |
| 510 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 511 | clocks = <&clks IMX6SX_CLK_DUMMY>; |
| 512 | status = "disabled"; |
| 513 | }; |
| 514 | |
| 515 | wdog1: wdog@020bc000 { |
| 516 | compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; |
| 517 | reg = <0x020bc000 0x4000>; |
| 518 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
| 519 | clocks = <&clks IMX6SX_CLK_DUMMY>; |
| 520 | }; |
| 521 | |
| 522 | wdog2: wdog@020c0000 { |
| 523 | compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; |
| 524 | reg = <0x020c0000 0x4000>; |
| 525 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| 526 | clocks = <&clks IMX6SX_CLK_DUMMY>; |
| 527 | status = "disabled"; |
| 528 | }; |
| 529 | |
| 530 | clks: ccm@020c4000 { |
| 531 | compatible = "fsl,imx6sx-ccm"; |
| 532 | reg = <0x020c4000 0x4000>; |
| 533 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 534 | <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
| 535 | #clock-cells = <1>; |
| 536 | clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; |
| 537 | clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; |
| 538 | }; |
| 539 | |
| 540 | anatop: anatop@020c8000 { |
| 541 | compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", |
| 542 | "syscon", "simple-bus"; |
| 543 | reg = <0x020c8000 0x1000>; |
| 544 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, |
| 545 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
| 546 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; |
| 547 | |
| 548 | regulator-1p1@110 { |
| 549 | compatible = "fsl,anatop-regulator"; |
| 550 | regulator-name = "vdd1p1"; |
| 551 | regulator-min-microvolt = <800000>; |
| 552 | regulator-max-microvolt = <1375000>; |
| 553 | regulator-always-on; |
| 554 | anatop-reg-offset = <0x110>; |
| 555 | anatop-vol-bit-shift = <8>; |
| 556 | anatop-vol-bit-width = <5>; |
| 557 | anatop-min-bit-val = <4>; |
| 558 | anatop-min-voltage = <800000>; |
| 559 | anatop-max-voltage = <1375000>; |
| 560 | }; |
| 561 | |
| 562 | regulator-3p0@120 { |
| 563 | compatible = "fsl,anatop-regulator"; |
| 564 | regulator-name = "vdd3p0"; |
| 565 | regulator-min-microvolt = <2800000>; |
| 566 | regulator-max-microvolt = <3150000>; |
| 567 | regulator-always-on; |
| 568 | anatop-reg-offset = <0x120>; |
| 569 | anatop-vol-bit-shift = <8>; |
| 570 | anatop-vol-bit-width = <5>; |
| 571 | anatop-min-bit-val = <0>; |
| 572 | anatop-min-voltage = <2625000>; |
| 573 | anatop-max-voltage = <3400000>; |
| 574 | }; |
| 575 | |
| 576 | regulator-2p5@130 { |
| 577 | compatible = "fsl,anatop-regulator"; |
| 578 | regulator-name = "vdd2p5"; |
| 579 | regulator-min-microvolt = <2100000>; |
| 580 | regulator-max-microvolt = <2875000>; |
| 581 | regulator-always-on; |
| 582 | anatop-reg-offset = <0x130>; |
| 583 | anatop-vol-bit-shift = <8>; |
| 584 | anatop-vol-bit-width = <5>; |
| 585 | anatop-min-bit-val = <0>; |
| 586 | anatop-min-voltage = <2100000>; |
| 587 | anatop-max-voltage = <2875000>; |
| 588 | }; |
| 589 | |
| 590 | reg_arm: regulator-vddcore@140 { |
| 591 | compatible = "fsl,anatop-regulator"; |
Fabio Estevam | f78a597 | 2014-06-17 01:07:35 -0300 | [diff] [blame] | 592 | regulator-name = "vddarm"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 593 | regulator-min-microvolt = <725000>; |
| 594 | regulator-max-microvolt = <1450000>; |
| 595 | regulator-always-on; |
| 596 | anatop-reg-offset = <0x140>; |
| 597 | anatop-vol-bit-shift = <0>; |
| 598 | anatop-vol-bit-width = <5>; |
| 599 | anatop-delay-reg-offset = <0x170>; |
| 600 | anatop-delay-bit-shift = <24>; |
| 601 | anatop-delay-bit-width = <2>; |
| 602 | anatop-min-bit-val = <1>; |
| 603 | anatop-min-voltage = <725000>; |
| 604 | anatop-max-voltage = <1450000>; |
| 605 | }; |
| 606 | |
| 607 | reg_pcie: regulator-vddpcie@140 { |
| 608 | compatible = "fsl,anatop-regulator"; |
| 609 | regulator-name = "vddpcie"; |
| 610 | regulator-min-microvolt = <725000>; |
| 611 | regulator-max-microvolt = <1450000>; |
| 612 | anatop-reg-offset = <0x140>; |
| 613 | anatop-vol-bit-shift = <9>; |
| 614 | anatop-vol-bit-width = <5>; |
| 615 | anatop-delay-reg-offset = <0x170>; |
| 616 | anatop-delay-bit-shift = <26>; |
| 617 | anatop-delay-bit-width = <2>; |
| 618 | anatop-min-bit-val = <1>; |
| 619 | anatop-min-voltage = <725000>; |
| 620 | anatop-max-voltage = <1450000>; |
| 621 | }; |
| 622 | |
| 623 | reg_soc: regulator-vddsoc@140 { |
| 624 | compatible = "fsl,anatop-regulator"; |
| 625 | regulator-name = "vddsoc"; |
| 626 | regulator-min-microvolt = <725000>; |
| 627 | regulator-max-microvolt = <1450000>; |
| 628 | regulator-always-on; |
| 629 | anatop-reg-offset = <0x140>; |
| 630 | anatop-vol-bit-shift = <18>; |
| 631 | anatop-vol-bit-width = <5>; |
| 632 | anatop-delay-reg-offset = <0x170>; |
| 633 | anatop-delay-bit-shift = <28>; |
| 634 | anatop-delay-bit-width = <2>; |
| 635 | anatop-min-bit-val = <1>; |
| 636 | anatop-min-voltage = <725000>; |
| 637 | anatop-max-voltage = <1450000>; |
| 638 | }; |
| 639 | }; |
| 640 | |
| 641 | tempmon: tempmon { |
| 642 | compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; |
| 643 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
| 644 | fsl,tempmon = <&anatop>; |
| 645 | fsl,tempmon-data = <&ocotp>; |
| 646 | clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; |
| 647 | }; |
| 648 | |
| 649 | usbphy1: usbphy@020c9000 { |
| 650 | compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; |
| 651 | reg = <0x020c9000 0x1000>; |
| 652 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
| 653 | clocks = <&clks IMX6SX_CLK_USBPHY1>; |
| 654 | fsl,anatop = <&anatop>; |
| 655 | }; |
| 656 | |
| 657 | usbphy2: usbphy@020ca000 { |
| 658 | compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; |
| 659 | reg = <0x020ca000 0x1000>; |
| 660 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| 661 | clocks = <&clks IMX6SX_CLK_USBPHY2>; |
| 662 | fsl,anatop = <&anatop>; |
| 663 | }; |
| 664 | |
| 665 | snvs: snvs@020cc000 { |
Frank Li | 95d739b | 2015-05-27 00:25:59 +0800 | [diff] [blame] | 666 | compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; |
| 667 | reg = <0x020cc000 0x4000>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 668 | |
Frank Li | 95d739b | 2015-05-27 00:25:59 +0800 | [diff] [blame] | 669 | snvs_rtc: snvs-rtc-lp { |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 670 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
Frank Li | 95d739b | 2015-05-27 00:25:59 +0800 | [diff] [blame] | 671 | regmap = <&snvs>; |
| 672 | offset = <0x34>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 673 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 674 | }; |
Robin Gong | 422b067 | 2014-11-12 16:20:37 +0800 | [diff] [blame] | 675 | |
Frank Li | 95d739b | 2015-05-27 00:25:59 +0800 | [diff] [blame] | 676 | snvs_poweroff: snvs-poweroff { |
| 677 | compatible = "syscon-poweroff"; |
| 678 | regmap = <&snvs>; |
| 679 | offset = <0x38>; |
| 680 | mask = <0x60>; |
Robin Gong | 422b067 | 2014-11-12 16:20:37 +0800 | [diff] [blame] | 681 | status = "disabled"; |
| 682 | }; |
Frank Li | 93db055 | 2015-05-27 00:26:02 +0800 | [diff] [blame] | 683 | |
| 684 | snvs_pwrkey: snvs-powerkey { |
| 685 | compatible = "fsl,sec-v4.0-pwrkey"; |
| 686 | regmap = <&snvs>; |
| 687 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| 688 | linux,keycode = <KEY_POWER>; |
Anson Huang | 461aa6d | 2015-08-05 21:57:55 +0800 | [diff] [blame] | 689 | wakeup-source; |
Frank Li | 93db055 | 2015-05-27 00:26:02 +0800 | [diff] [blame] | 690 | }; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 691 | }; |
| 692 | |
| 693 | epit1: epit@020d0000 { |
| 694 | reg = <0x020d0000 0x4000>; |
| 695 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| 696 | }; |
| 697 | |
| 698 | epit2: epit@020d4000 { |
| 699 | reg = <0x020d4000 0x4000>; |
| 700 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
| 701 | }; |
| 702 | |
| 703 | src: src@020d8000 { |
| 704 | compatible = "fsl,imx6sx-src", "fsl,imx51-src"; |
| 705 | reg = <0x020d8000 0x4000>; |
| 706 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, |
| 707 | <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 708 | #reset-cells = <1>; |
| 709 | }; |
| 710 | |
| 711 | gpc: gpc@020dc000 { |
| 712 | compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; |
| 713 | reg = <0x020dc000 0x4000>; |
Marc Zyngier | b923ff6 | 2015-02-23 17:45:18 +0000 | [diff] [blame] | 714 | interrupt-controller; |
| 715 | #interrupt-cells = <3>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 716 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
Marc Zyngier | b923ff6 | 2015-02-23 17:45:18 +0000 | [diff] [blame] | 717 | interrupt-parent = <&intc>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 718 | }; |
| 719 | |
| 720 | iomuxc: iomuxc@020e0000 { |
| 721 | compatible = "fsl,imx6sx-iomuxc"; |
| 722 | reg = <0x020e0000 0x4000>; |
| 723 | }; |
| 724 | |
| 725 | gpr: iomuxc-gpr@020e4000 { |
Anson Huang | 77e0d1c | 2014-06-23 14:04:01 +0800 | [diff] [blame] | 726 | compatible = "fsl,imx6sx-iomuxc-gpr", |
| 727 | "fsl,imx6q-iomuxc-gpr", "syscon"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 728 | reg = <0x020e4000 0x4000>; |
| 729 | }; |
| 730 | |
| 731 | sdma: sdma@020ec000 { |
Shawn Guo | 811e7685 | 2014-07-04 14:30:27 +0800 | [diff] [blame] | 732 | compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 733 | reg = <0x020ec000 0x4000>; |
| 734 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| 735 | clocks = <&clks IMX6SX_CLK_SDMA>, |
| 736 | <&clks IMX6SX_CLK_SDMA>; |
| 737 | clock-names = "ipg", "ahb"; |
| 738 | #dma-cells = <3>; |
Fabio Estevam | aeb8853 | 2014-07-02 11:58:49 -0300 | [diff] [blame] | 739 | /* imx6sx reuses imx6q sdma firmware */ |
| 740 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 741 | }; |
| 742 | }; |
| 743 | |
| 744 | aips2: aips-bus@02100000 { |
| 745 | compatible = "fsl,aips-bus", "simple-bus"; |
| 746 | #address-cells = <1>; |
| 747 | #size-cells = <1>; |
| 748 | reg = <0x02100000 0x100000>; |
| 749 | ranges; |
| 750 | |
Victoria Milhoan | b15e9ea | 2015-08-06 11:42:37 -0700 | [diff] [blame] | 751 | crypto: caam@2100000 { |
| 752 | compatible = "fsl,sec-v4.0"; |
| 753 | fsl,sec-era = <4>; |
| 754 | #address-cells = <1>; |
| 755 | #size-cells = <1>; |
| 756 | reg = <0x2100000 0x10000>; |
| 757 | ranges = <0 0x2100000 0x10000>; |
| 758 | interrupt-parent = <&intc>; |
| 759 | clocks = <&clks IMX6SX_CLK_CAAM_MEM>, |
| 760 | <&clks IMX6SX_CLK_CAAM_ACLK>, |
| 761 | <&clks IMX6SX_CLK_CAAM_IPG>, |
| 762 | <&clks IMX6SX_CLK_EIM_SLOW>; |
| 763 | clock-names = "mem", "aclk", "ipg", "emi_slow"; |
| 764 | |
| 765 | sec_jr0: jr0@1000 { |
| 766 | compatible = "fsl,sec-v4.0-job-ring"; |
| 767 | reg = <0x1000 0x1000>; |
| 768 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| 769 | }; |
| 770 | |
| 771 | sec_jr1: jr1@2000 { |
| 772 | compatible = "fsl,sec-v4.0-job-ring"; |
| 773 | reg = <0x2000 0x1000>; |
| 774 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| 775 | }; |
| 776 | }; |
| 777 | |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 778 | usbotg1: usb@02184000 { |
| 779 | compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; |
| 780 | reg = <0x02184000 0x200>; |
| 781 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
| 782 | clocks = <&clks IMX6SX_CLK_USBOH3>; |
| 783 | fsl,usbphy = <&usbphy1>; |
| 784 | fsl,usbmisc = <&usbmisc 0>; |
| 785 | fsl,anatop = <&anatop>; |
Peter Chen | 9493bf5 | 2015-09-30 10:17:16 +0800 | [diff] [blame] | 786 | ahb-burst-config = <0x0>; |
Peter Chen | 2b1a40e | 2015-09-30 10:17:17 +0800 | [diff] [blame] | 787 | tx-burst-size-dword = <0x10>; |
| 788 | rx-burst-size-dword = <0x10>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 789 | status = "disabled"; |
| 790 | }; |
| 791 | |
| 792 | usbotg2: usb@02184200 { |
| 793 | compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; |
| 794 | reg = <0x02184200 0x200>; |
| 795 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| 796 | clocks = <&clks IMX6SX_CLK_USBOH3>; |
| 797 | fsl,usbphy = <&usbphy2>; |
| 798 | fsl,usbmisc = <&usbmisc 1>; |
Peter Chen | 9493bf5 | 2015-09-30 10:17:16 +0800 | [diff] [blame] | 799 | ahb-burst-config = <0x0>; |
Peter Chen | 2b1a40e | 2015-09-30 10:17:17 +0800 | [diff] [blame] | 800 | tx-burst-size-dword = <0x10>; |
| 801 | rx-burst-size-dword = <0x10>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 802 | status = "disabled"; |
| 803 | }; |
| 804 | |
| 805 | usbh: usb@02184400 { |
| 806 | compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; |
| 807 | reg = <0x02184400 0x200>; |
| 808 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| 809 | clocks = <&clks IMX6SX_CLK_USBOH3>; |
| 810 | fsl,usbmisc = <&usbmisc 2>; |
| 811 | phy_type = "hsic"; |
| 812 | fsl,anatop = <&anatop>; |
Matt Porter | 3ec481e | 2015-02-27 09:06:00 -0500 | [diff] [blame] | 813 | dr_mode = "host"; |
Peter Chen | 9493bf5 | 2015-09-30 10:17:16 +0800 | [diff] [blame] | 814 | ahb-burst-config = <0x0>; |
Peter Chen | 2b1a40e | 2015-09-30 10:17:17 +0800 | [diff] [blame] | 815 | tx-burst-size-dword = <0x10>; |
| 816 | rx-burst-size-dword = <0x10>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 817 | status = "disabled"; |
| 818 | }; |
| 819 | |
| 820 | usbmisc: usbmisc@02184800 { |
| 821 | #index-cells = <1>; |
Fabio Estevam | b29f4fa | 2014-06-23 11:21:04 -0300 | [diff] [blame] | 822 | compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 823 | reg = <0x02184800 0x200>; |
| 824 | clocks = <&clks IMX6SX_CLK_USBOH3>; |
| 825 | }; |
| 826 | |
| 827 | fec1: ethernet@02188000 { |
| 828 | compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; |
| 829 | reg = <0x02188000 0x4000>; |
| 830 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 831 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
| 832 | clocks = <&clks IMX6SX_CLK_ENET>, |
| 833 | <&clks IMX6SX_CLK_ENET_AHB>, |
| 834 | <&clks IMX6SX_CLK_ENET_PTP>, |
| 835 | <&clks IMX6SX_CLK_ENET_REF>, |
| 836 | <&clks IMX6SX_CLK_ENET_PTP>; |
| 837 | clock-names = "ipg", "ahb", "ptp", |
| 838 | "enet_clk_ref", "enet_out"; |
Frank Li | 0afdfe9 | 2014-09-13 05:00:57 +0800 | [diff] [blame] | 839 | fsl,num-tx-queues=<3>; |
| 840 | fsl,num-rx-queues=<3>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 841 | status = "disabled"; |
| 842 | }; |
| 843 | |
| 844 | mlb: mlb@0218c000 { |
| 845 | reg = <0x0218c000 0x4000>; |
| 846 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| 847 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 848 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; |
| 849 | clocks = <&clks IMX6SX_CLK_MLB>; |
| 850 | status = "disabled"; |
| 851 | }; |
| 852 | |
| 853 | usdhc1: usdhc@02190000 { |
| 854 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; |
| 855 | reg = <0x02190000 0x4000>; |
| 856 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| 857 | clocks = <&clks IMX6SX_CLK_USDHC1>, |
| 858 | <&clks IMX6SX_CLK_USDHC1>, |
| 859 | <&clks IMX6SX_CLK_USDHC1>; |
| 860 | clock-names = "ipg", "ahb", "per"; |
| 861 | bus-width = <4>; |
| 862 | status = "disabled"; |
| 863 | }; |
| 864 | |
| 865 | usdhc2: usdhc@02194000 { |
| 866 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; |
| 867 | reg = <0x02194000 0x4000>; |
| 868 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| 869 | clocks = <&clks IMX6SX_CLK_USDHC2>, |
| 870 | <&clks IMX6SX_CLK_USDHC2>, |
| 871 | <&clks IMX6SX_CLK_USDHC2>; |
| 872 | clock-names = "ipg", "ahb", "per"; |
| 873 | bus-width = <4>; |
| 874 | status = "disabled"; |
| 875 | }; |
| 876 | |
| 877 | usdhc3: usdhc@02198000 { |
| 878 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; |
| 879 | reg = <0x02198000 0x4000>; |
| 880 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
| 881 | clocks = <&clks IMX6SX_CLK_USDHC3>, |
| 882 | <&clks IMX6SX_CLK_USDHC3>, |
| 883 | <&clks IMX6SX_CLK_USDHC3>; |
| 884 | clock-names = "ipg", "ahb", "per"; |
| 885 | bus-width = <4>; |
| 886 | status = "disabled"; |
| 887 | }; |
| 888 | |
| 889 | usdhc4: usdhc@0219c000 { |
| 890 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; |
| 891 | reg = <0x0219c000 0x4000>; |
| 892 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| 893 | clocks = <&clks IMX6SX_CLK_USDHC4>, |
| 894 | <&clks IMX6SX_CLK_USDHC4>, |
| 895 | <&clks IMX6SX_CLK_USDHC4>; |
| 896 | clock-names = "ipg", "ahb", "per"; |
| 897 | bus-width = <4>; |
| 898 | status = "disabled"; |
| 899 | }; |
| 900 | |
| 901 | i2c1: i2c@021a0000 { |
| 902 | #address-cells = <1>; |
| 903 | #size-cells = <0>; |
| 904 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; |
| 905 | reg = <0x021a0000 0x4000>; |
| 906 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| 907 | clocks = <&clks IMX6SX_CLK_I2C1>; |
| 908 | status = "disabled"; |
| 909 | }; |
| 910 | |
| 911 | i2c2: i2c@021a4000 { |
| 912 | #address-cells = <1>; |
| 913 | #size-cells = <0>; |
| 914 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; |
| 915 | reg = <0x021a4000 0x4000>; |
| 916 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| 917 | clocks = <&clks IMX6SX_CLK_I2C2>; |
| 918 | status = "disabled"; |
| 919 | }; |
| 920 | |
| 921 | i2c3: i2c@021a8000 { |
| 922 | #address-cells = <1>; |
| 923 | #size-cells = <0>; |
| 924 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; |
| 925 | reg = <0x021a8000 0x4000>; |
| 926 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 927 | clocks = <&clks IMX6SX_CLK_I2C3>; |
| 928 | status = "disabled"; |
| 929 | }; |
| 930 | |
| 931 | mmdc: mmdc@021b0000 { |
| 932 | compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; |
| 933 | reg = <0x021b0000 0x4000>; |
| 934 | }; |
| 935 | |
| 936 | fec2: ethernet@021b4000 { |
Fugang Duan | 9863aba | 2014-09-28 16:40:36 +0800 | [diff] [blame] | 937 | compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 938 | reg = <0x021b4000 0x4000>; |
| 939 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| 940 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| 941 | clocks = <&clks IMX6SX_CLK_ENET>, |
| 942 | <&clks IMX6SX_CLK_ENET_AHB>, |
| 943 | <&clks IMX6SX_CLK_ENET_PTP>, |
| 944 | <&clks IMX6SX_CLK_ENET2_REF_125M>, |
| 945 | <&clks IMX6SX_CLK_ENET_PTP>; |
| 946 | clock-names = "ipg", "ahb", "ptp", |
| 947 | "enet_clk_ref", "enet_out"; |
| 948 | status = "disabled"; |
| 949 | }; |
| 950 | |
| 951 | weim: weim@021b8000 { |
| 952 | compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; |
| 953 | reg = <0x021b8000 0x4000>; |
| 954 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 955 | clocks = <&clks IMX6SX_CLK_EIM_SLOW>; |
| 956 | }; |
| 957 | |
| 958 | ocotp: ocotp@021bc000 { |
| 959 | compatible = "fsl,imx6sx-ocotp", "syscon"; |
| 960 | reg = <0x021bc000 0x4000>; |
| 961 | clocks = <&clks IMX6SX_CLK_OCOTP>; |
| 962 | }; |
| 963 | |
| 964 | sai1: sai@021d4000 { |
| 965 | compatible = "fsl,imx6sx-sai"; |
| 966 | reg = <0x021d4000 0x4000>; |
| 967 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 968 | clocks = <&clks IMX6SX_CLK_SAI1_IPG>, |
| 969 | <&clks IMX6SX_CLK_SAI1>, |
| 970 | <&clks 0>, <&clks 0>; |
| 971 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| 972 | dma-names = "rx", "tx"; |
Fabio Estevam | 78f31b0 | 2016-04-01 20:52:14 -0300 | [diff] [blame^] | 973 | dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 974 | dma-source = <&gpr 0 15 0 16>; |
| 975 | status = "disabled"; |
| 976 | }; |
| 977 | |
| 978 | audmux: audmux@021d8000 { |
| 979 | compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; |
| 980 | reg = <0x021d8000 0x4000>; |
| 981 | status = "disabled"; |
| 982 | }; |
| 983 | |
| 984 | sai2: sai@021dc000 { |
| 985 | compatible = "fsl,imx6sx-sai"; |
| 986 | reg = <0x021dc000 0x4000>; |
| 987 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| 988 | clocks = <&clks IMX6SX_CLK_SAI2_IPG>, |
| 989 | <&clks IMX6SX_CLK_SAI2>, |
| 990 | <&clks 0>, <&clks 0>; |
| 991 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| 992 | dma-names = "rx", "tx"; |
Fabio Estevam | 78f31b0 | 2016-04-01 20:52:14 -0300 | [diff] [blame^] | 993 | dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 994 | dma-source = <&gpr 0 17 0 18>; |
| 995 | status = "disabled"; |
| 996 | }; |
| 997 | |
| 998 | qspi1: qspi@021e0000 { |
| 999 | #address-cells = <1>; |
| 1000 | #size-cells = <0>; |
| 1001 | compatible = "fsl,imx6sx-qspi"; |
| 1002 | reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; |
| 1003 | reg-names = "QuadSPI", "QuadSPI-memory"; |
| 1004 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| 1005 | clocks = <&clks IMX6SX_CLK_QSPI1>, |
| 1006 | <&clks IMX6SX_CLK_QSPI1>; |
| 1007 | clock-names = "qspi_en", "qspi"; |
| 1008 | status = "disabled"; |
| 1009 | }; |
| 1010 | |
| 1011 | qspi2: qspi@021e4000 { |
| 1012 | #address-cells = <1>; |
| 1013 | #size-cells = <0>; |
| 1014 | compatible = "fsl,imx6sx-qspi"; |
| 1015 | reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; |
| 1016 | reg-names = "QuadSPI", "QuadSPI-memory"; |
| 1017 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
| 1018 | clocks = <&clks IMX6SX_CLK_QSPI2>, |
| 1019 | <&clks IMX6SX_CLK_QSPI2>; |
| 1020 | clock-names = "qspi_en", "qspi"; |
| 1021 | status = "disabled"; |
| 1022 | }; |
| 1023 | |
| 1024 | uart2: serial@021e8000 { |
| 1025 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; |
| 1026 | reg = <0x021e8000 0x4000>; |
| 1027 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
| 1028 | clocks = <&clks IMX6SX_CLK_UART_IPG>, |
| 1029 | <&clks IMX6SX_CLK_UART_SERIAL>; |
| 1030 | clock-names = "ipg", "per"; |
| 1031 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
| 1032 | dma-names = "rx", "tx"; |
| 1033 | status = "disabled"; |
| 1034 | }; |
| 1035 | |
| 1036 | uart3: serial@021ec000 { |
| 1037 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; |
| 1038 | reg = <0x021ec000 0x4000>; |
| 1039 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| 1040 | clocks = <&clks IMX6SX_CLK_UART_IPG>, |
| 1041 | <&clks IMX6SX_CLK_UART_SERIAL>; |
| 1042 | clock-names = "ipg", "per"; |
| 1043 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
| 1044 | dma-names = "rx", "tx"; |
| 1045 | status = "disabled"; |
| 1046 | }; |
| 1047 | |
| 1048 | uart4: serial@021f0000 { |
| 1049 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; |
| 1050 | reg = <0x021f0000 0x4000>; |
| 1051 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| 1052 | clocks = <&clks IMX6SX_CLK_UART_IPG>, |
| 1053 | <&clks IMX6SX_CLK_UART_SERIAL>; |
| 1054 | clock-names = "ipg", "per"; |
| 1055 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
| 1056 | dma-names = "rx", "tx"; |
| 1057 | status = "disabled"; |
| 1058 | }; |
| 1059 | |
| 1060 | uart5: serial@021f4000 { |
| 1061 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; |
| 1062 | reg = <0x021f4000 0x4000>; |
| 1063 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| 1064 | clocks = <&clks IMX6SX_CLK_UART_IPG>, |
| 1065 | <&clks IMX6SX_CLK_UART_SERIAL>; |
| 1066 | clock-names = "ipg", "per"; |
| 1067 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
| 1068 | dma-names = "rx", "tx"; |
| 1069 | status = "disabled"; |
| 1070 | }; |
| 1071 | |
| 1072 | i2c4: i2c@021f8000 { |
| 1073 | #address-cells = <1>; |
| 1074 | #size-cells = <0>; |
| 1075 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; |
| 1076 | reg = <0x021f8000 0x4000>; |
| 1077 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| 1078 | clocks = <&clks IMX6SX_CLK_I2C4>; |
| 1079 | status = "disabled"; |
| 1080 | }; |
| 1081 | }; |
| 1082 | |
| 1083 | aips3: aips-bus@02200000 { |
| 1084 | compatible = "fsl,aips-bus", "simple-bus"; |
| 1085 | #address-cells = <1>; |
| 1086 | #size-cells = <1>; |
| 1087 | reg = <0x02200000 0x100000>; |
| 1088 | ranges; |
| 1089 | |
| 1090 | spba-bus@02200000 { |
| 1091 | compatible = "fsl,spba-bus", "simple-bus"; |
| 1092 | #address-cells = <1>; |
| 1093 | #size-cells = <1>; |
| 1094 | reg = <0x02240000 0x40000>; |
| 1095 | ranges; |
| 1096 | |
| 1097 | csi1: csi@02214000 { |
| 1098 | reg = <0x02214000 0x4000>; |
| 1099 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 1100 | clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, |
| 1101 | <&clks IMX6SX_CLK_CSI>, |
| 1102 | <&clks IMX6SX_CLK_DCIC1>; |
| 1103 | clock-names = "disp-axi", "csi_mclk", "dcic"; |
| 1104 | status = "disabled"; |
| 1105 | }; |
| 1106 | |
| 1107 | pxp: pxp@02218000 { |
| 1108 | reg = <0x02218000 0x4000>; |
| 1109 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| 1110 | clocks = <&clks IMX6SX_CLK_PXP_AXI>, |
| 1111 | <&clks IMX6SX_CLK_DISPLAY_AXI>; |
| 1112 | clock-names = "pxp-axi", "disp-axi"; |
| 1113 | status = "disabled"; |
| 1114 | }; |
| 1115 | |
| 1116 | csi2: csi@0221c000 { |
| 1117 | reg = <0x0221c000 0x4000>; |
| 1118 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| 1119 | clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, |
| 1120 | <&clks IMX6SX_CLK_CSI>, |
| 1121 | <&clks IMX6SX_CLK_DCIC2>; |
| 1122 | clock-names = "disp-axi", "csi_mclk", "dcic"; |
| 1123 | status = "disabled"; |
| 1124 | }; |
| 1125 | |
| 1126 | lcdif1: lcdif@02220000 { |
Fabio Estevam | 8c78c40 | 2014-09-02 15:00:43 -0300 | [diff] [blame] | 1127 | compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 1128 | reg = <0x02220000 0x4000>; |
| 1129 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| 1130 | clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, |
| 1131 | <&clks IMX6SX_CLK_LCDIF_APB>, |
| 1132 | <&clks IMX6SX_CLK_DISPLAY_AXI>; |
| 1133 | clock-names = "pix", "axi", "disp_axi"; |
| 1134 | status = "disabled"; |
| 1135 | }; |
| 1136 | |
| 1137 | lcdif2: lcdif@02224000 { |
Fabio Estevam | 8c78c40 | 2014-09-02 15:00:43 -0300 | [diff] [blame] | 1138 | compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 1139 | reg = <0x02224000 0x4000>; |
| 1140 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| 1141 | clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, |
| 1142 | <&clks IMX6SX_CLK_LCDIF_APB>, |
| 1143 | <&clks IMX6SX_CLK_DISPLAY_AXI>; |
| 1144 | clock-names = "pix", "axi", "disp_axi"; |
| 1145 | status = "disabled"; |
| 1146 | }; |
| 1147 | |
| 1148 | vadc: vadc@02228000 { |
| 1149 | reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; |
| 1150 | reg-names = "vadc-vafe", "vadc-vdec"; |
| 1151 | clocks = <&clks IMX6SX_CLK_VADC>, |
| 1152 | <&clks IMX6SX_CLK_CSI>; |
| 1153 | clock-names = "vadc", "csi"; |
| 1154 | status = "disabled"; |
| 1155 | }; |
| 1156 | }; |
| 1157 | |
| 1158 | adc1: adc@02280000 { |
| 1159 | compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; |
| 1160 | reg = <0x02280000 0x4000>; |
| 1161 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| 1162 | clocks = <&clks IMX6SX_CLK_IPG>; |
| 1163 | clock-names = "adc"; |
Fabio Estevam | eb45ff7 | 2015-11-03 14:25:36 -0200 | [diff] [blame] | 1164 | fsl,adck-max-frequency = <30000000>, <40000000>, |
| 1165 | <20000000>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 1166 | status = "disabled"; |
| 1167 | }; |
| 1168 | |
| 1169 | adc2: adc@02284000 { |
| 1170 | compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; |
| 1171 | reg = <0x02284000 0x4000>; |
| 1172 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
| 1173 | clocks = <&clks IMX6SX_CLK_IPG>; |
| 1174 | clock-names = "adc"; |
Fabio Estevam | eb45ff7 | 2015-11-03 14:25:36 -0200 | [diff] [blame] | 1175 | fsl,adck-max-frequency = <30000000>, <40000000>, |
| 1176 | <20000000>; |
Shawn Guo | b1d17f6 | 2014-05-13 20:21:35 +0800 | [diff] [blame] | 1177 | status = "disabled"; |
| 1178 | }; |
| 1179 | |
| 1180 | wdog3: wdog@02288000 { |
| 1181 | compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; |
| 1182 | reg = <0x02288000 0x4000>; |
| 1183 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| 1184 | clocks = <&clks IMX6SX_CLK_DUMMY>; |
| 1185 | status = "disabled"; |
| 1186 | }; |
| 1187 | |
| 1188 | ecspi5: ecspi@0228c000 { |
| 1189 | #address-cells = <1>; |
| 1190 | #size-cells = <0>; |
| 1191 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; |
| 1192 | reg = <0x0228c000 0x4000>; |
| 1193 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; |
| 1194 | clocks = <&clks IMX6SX_CLK_ECSPI5>, |
| 1195 | <&clks IMX6SX_CLK_ECSPI5>; |
| 1196 | clock-names = "ipg", "per"; |
| 1197 | status = "disabled"; |
| 1198 | }; |
| 1199 | |
| 1200 | uart6: serial@022a0000 { |
| 1201 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; |
| 1202 | reg = <0x022a0000 0x4000>; |
| 1203 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| 1204 | clocks = <&clks IMX6SX_CLK_UART_IPG>, |
| 1205 | <&clks IMX6SX_CLK_UART_SERIAL>; |
| 1206 | clock-names = "ipg", "per"; |
| 1207 | dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; |
| 1208 | dma-names = "rx", "tx"; |
| 1209 | status = "disabled"; |
| 1210 | }; |
| 1211 | |
| 1212 | pwm5: pwm@022a4000 { |
| 1213 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 1214 | reg = <0x022a4000 0x4000>; |
| 1215 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 1216 | clocks = <&clks IMX6SX_CLK_PWM5>, |
| 1217 | <&clks IMX6SX_CLK_PWM5>; |
| 1218 | clock-names = "ipg", "per"; |
| 1219 | #pwm-cells = <2>; |
| 1220 | }; |
| 1221 | |
| 1222 | pwm6: pwm@022a8000 { |
| 1223 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 1224 | reg = <0x022a8000 0x4000>; |
| 1225 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| 1226 | clocks = <&clks IMX6SX_CLK_PWM6>, |
| 1227 | <&clks IMX6SX_CLK_PWM6>; |
| 1228 | clock-names = "ipg", "per"; |
| 1229 | #pwm-cells = <2>; |
| 1230 | }; |
| 1231 | |
| 1232 | pwm7: pwm@022ac000 { |
| 1233 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 1234 | reg = <0x022ac000 0x4000>; |
| 1235 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| 1236 | clocks = <&clks IMX6SX_CLK_PWM7>, |
| 1237 | <&clks IMX6SX_CLK_PWM7>; |
| 1238 | clock-names = "ipg", "per"; |
| 1239 | #pwm-cells = <2>; |
| 1240 | }; |
| 1241 | |
| 1242 | pwm8: pwm@0022b0000 { |
| 1243 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; |
| 1244 | reg = <0x0022b0000 0x4000>; |
| 1245 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 1246 | clocks = <&clks IMX6SX_CLK_PWM8>, |
| 1247 | <&clks IMX6SX_CLK_PWM8>; |
| 1248 | clock-names = "ipg", "per"; |
| 1249 | #pwm-cells = <2>; |
| 1250 | }; |
| 1251 | }; |
| 1252 | |
| 1253 | pcie: pcie@0x08000000 { |
| 1254 | compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; |
| 1255 | reg = <0x08ffc000 0x4000>; /* DBI */ |
| 1256 | #address-cells = <3>; |
| 1257 | #size-cells = <2>; |
| 1258 | device_type = "pci"; |
| 1259 | /* configuration space */ |
| 1260 | ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 |
| 1261 | /* downstream I/O */ |
| 1262 | 0x81000000 0 0 0x08f80000 0 0x00010000 |
| 1263 | /* non-prefetchable memory */ |
| 1264 | 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; |
| 1265 | num-lanes = <1>; |
| 1266 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
| 1267 | clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, |
| 1268 | <&clks IMX6SX_CLK_PCIE_AXI>, |
| 1269 | <&clks IMX6SX_CLK_LVDS1_OUT>, |
| 1270 | <&clks IMX6SX_CLK_DISPLAY_AXI>; |
| 1271 | clock-names = "pcie_ref_125m", "pcie_axi", |
| 1272 | "lvds_gate", "display_axi"; |
| 1273 | status = "disabled"; |
| 1274 | }; |
| 1275 | }; |
| 1276 | }; |