Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 2 | |
Suresh Siddha | 61c4628 | 2008-03-10 15:28:04 -0700 | [diff] [blame] | 3 | #include <linux/errno.h> |
| 4 | #include <linux/kernel.h> |
| 5 | #include <linux/mm.h> |
| 6 | #include <linux/smp.h> |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 7 | #include <linux/prctl.h> |
Suresh Siddha | 61c4628 | 2008-03-10 15:28:04 -0700 | [diff] [blame] | 8 | #include <linux/slab.h> |
| 9 | #include <linux/sched.h> |
Peter Zijlstra | 7f424a8 | 2008-04-25 17:39:01 +0200 | [diff] [blame] | 10 | #include <linux/module.h> |
| 11 | #include <linux/pm.h> |
Thomas Gleixner | 162a688 | 2015-04-03 02:01:28 +0200 | [diff] [blame] | 12 | #include <linux/tick.h> |
Amerigo Wang | 9d62dcd | 2009-05-11 22:05:28 -0400 | [diff] [blame] | 13 | #include <linux/random.h> |
Avi Kivity | 7c68af6 | 2009-09-19 09:40:22 +0300 | [diff] [blame] | 14 | #include <linux/user-return-notifier.h> |
Andy Isaacson | 814e2c8 | 2009-12-08 00:29:42 -0800 | [diff] [blame] | 15 | #include <linux/dmi.h> |
| 16 | #include <linux/utsname.h> |
Richard Weinberger | 90e2401 | 2012-03-25 23:00:04 +0200 | [diff] [blame] | 17 | #include <linux/stackprotector.h> |
| 18 | #include <linux/tick.h> |
| 19 | #include <linux/cpuidle.h> |
Arjan van de Ven | 6161352 | 2009-09-17 16:11:28 +0200 | [diff] [blame] | 20 | #include <trace/events/power.h> |
Frederic Weisbecker | 24f1e32c | 2009-09-09 19:22:48 +0200 | [diff] [blame] | 21 | #include <linux/hw_breakpoint.h> |
Borislav Petkov | 93789b3 | 2011-01-20 15:42:52 +0100 | [diff] [blame] | 22 | #include <asm/cpu.h> |
Ivan Vecera | d3ec5ca | 2008-11-11 14:33:44 +0100 | [diff] [blame] | 23 | #include <asm/apic.h> |
Jaswinder Singh Rajput | 2c1b284 | 2009-04-11 00:03:10 +0530 | [diff] [blame] | 24 | #include <asm/syscalls.h> |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 25 | #include <asm/idle.h> |
| 26 | #include <asm/uaccess.h> |
Len Brown | b253149 | 2014-01-15 00:37:34 -0500 | [diff] [blame] | 27 | #include <asm/mwait.h> |
Ingo Molnar | 78f7f1e | 2015-04-24 02:54:44 +0200 | [diff] [blame^] | 28 | #include <asm/fpu/internal.h> |
K.Prasad | 66cb591 | 2009-06-01 23:44:55 +0530 | [diff] [blame] | 29 | #include <asm/debugreg.h> |
Richard Weinberger | 90e2401 | 2012-03-25 23:00:04 +0200 | [diff] [blame] | 30 | #include <asm/nmi.h> |
Andy Lutomirski | 375074c | 2014-10-24 15:58:07 -0700 | [diff] [blame] | 31 | #include <asm/tlbflush.h> |
Richard Weinberger | 90e2401 | 2012-03-25 23:00:04 +0200 | [diff] [blame] | 32 | |
Thomas Gleixner | 4504689 | 2012-05-03 09:03:01 +0000 | [diff] [blame] | 33 | /* |
| 34 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, |
| 35 | * no more per-task TSS's. The TSS size is kept cacheline-aligned |
| 36 | * so they are allowed to end up in the .data..cacheline_aligned |
| 37 | * section. Since TSS's are completely CPU-local, we want them |
| 38 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. |
| 39 | */ |
Andy Lutomirski | d0a0de2 | 2015-03-05 19:19:06 -0800 | [diff] [blame] | 40 | __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { |
| 41 | .x86_tss = { |
Andy Lutomirski | d9e05cc | 2015-03-10 11:05:59 -0700 | [diff] [blame] | 42 | .sp0 = TOP_OF_INIT_STACK, |
Andy Lutomirski | d0a0de2 | 2015-03-05 19:19:06 -0800 | [diff] [blame] | 43 | #ifdef CONFIG_X86_32 |
| 44 | .ss0 = __KERNEL_DS, |
| 45 | .ss1 = __KERNEL_CS, |
| 46 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, |
| 47 | #endif |
| 48 | }, |
| 49 | #ifdef CONFIG_X86_32 |
| 50 | /* |
| 51 | * Note that the .io_bitmap member must be extra-big. This is because |
| 52 | * the CPU will access an additional byte beyond the end of the IO |
| 53 | * permission bitmap. The extra byte must be all 1 bits, and must |
| 54 | * be within the limit. |
| 55 | */ |
| 56 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, |
| 57 | #endif |
| 58 | }; |
Marc Dionne | de71ad2 | 2015-05-04 15:16:44 -0300 | [diff] [blame] | 59 | EXPORT_PER_CPU_SYMBOL(cpu_tss); |
Thomas Gleixner | 4504689 | 2012-05-03 09:03:01 +0000 | [diff] [blame] | 60 | |
Richard Weinberger | 90e2401 | 2012-03-25 23:00:04 +0200 | [diff] [blame] | 61 | #ifdef CONFIG_X86_64 |
| 62 | static DEFINE_PER_CPU(unsigned char, is_idle); |
| 63 | static ATOMIC_NOTIFIER_HEAD(idle_notifier); |
| 64 | |
| 65 | void idle_notifier_register(struct notifier_block *n) |
| 66 | { |
| 67 | atomic_notifier_chain_register(&idle_notifier, n); |
| 68 | } |
| 69 | EXPORT_SYMBOL_GPL(idle_notifier_register); |
| 70 | |
| 71 | void idle_notifier_unregister(struct notifier_block *n) |
| 72 | { |
| 73 | atomic_notifier_chain_unregister(&idle_notifier, n); |
| 74 | } |
| 75 | EXPORT_SYMBOL_GPL(idle_notifier_unregister); |
| 76 | #endif |
Zhao Yakui | c1e3b37 | 2008-06-24 17:58:53 +0800 | [diff] [blame] | 77 | |
Suresh Siddha | 55ccf3f | 2012-05-16 15:03:51 -0700 | [diff] [blame] | 78 | /* |
| 79 | * this gets called so that we can store lazy state into memory and copy the |
| 80 | * current task into the new thread. |
| 81 | */ |
Suresh Siddha | 61c4628 | 2008-03-10 15:28:04 -0700 | [diff] [blame] | 82 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
| 83 | { |
| 84 | *dst = *src; |
Oleg Nesterov | f185350 | 2014-09-02 19:57:23 +0200 | [diff] [blame] | 85 | |
Ingo Molnar | c69e098 | 2015-04-24 02:07:15 +0200 | [diff] [blame] | 86 | return fpu__copy(&dst->thread.fpu, &src->thread.fpu); |
Suresh Siddha | 61c4628 | 2008-03-10 15:28:04 -0700 | [diff] [blame] | 87 | } |
| 88 | |
Thomas Gleixner | 38e7c57 | 2012-05-05 15:05:42 +0000 | [diff] [blame] | 89 | void arch_release_task_struct(struct task_struct *tsk) |
Suresh Siddha | 61c4628 | 2008-03-10 15:28:04 -0700 | [diff] [blame] | 90 | { |
Ingo Molnar | 11ad192 | 2015-04-22 11:44:46 +0200 | [diff] [blame] | 91 | fpstate_free(&tsk->thread.fpu); |
Suresh Siddha | 61c4628 | 2008-03-10 15:28:04 -0700 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | void arch_task_cache_init(void) |
| 95 | { |
Ingo Molnar | 8ffb53a | 2015-04-22 15:41:56 +0200 | [diff] [blame] | 96 | fpstate_cache_init(); |
Suresh Siddha | 61c4628 | 2008-03-10 15:28:04 -0700 | [diff] [blame] | 97 | } |
Peter Zijlstra | 7f424a8 | 2008-04-25 17:39:01 +0200 | [diff] [blame] | 98 | |
Thomas Gleixner | 00dba56 | 2008-06-09 18:35:28 +0200 | [diff] [blame] | 99 | /* |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 100 | * Free current thread data structures etc.. |
| 101 | */ |
| 102 | void exit_thread(void) |
| 103 | { |
| 104 | struct task_struct *me = current; |
| 105 | struct thread_struct *t = &me->thread; |
Thomas Gleixner | 250981e | 2009-03-16 13:07:21 +0100 | [diff] [blame] | 106 | unsigned long *bp = t->io_bitmap_ptr; |
Ingo Molnar | ca6787b | 2015-04-23 12:33:50 +0200 | [diff] [blame] | 107 | struct fpu *fpu = &t->fpu; |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 108 | |
Thomas Gleixner | 250981e | 2009-03-16 13:07:21 +0100 | [diff] [blame] | 109 | if (bp) { |
Andy Lutomirski | 24933b8 | 2015-03-05 19:19:05 -0800 | [diff] [blame] | 110 | struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu()); |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 111 | |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 112 | t->io_bitmap_ptr = NULL; |
| 113 | clear_thread_flag(TIF_IO_BITMAP); |
| 114 | /* |
| 115 | * Careful, clear this in the TSS too: |
| 116 | */ |
| 117 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); |
| 118 | t->io_bitmap_max = 0; |
| 119 | put_cpu(); |
Thomas Gleixner | 250981e | 2009-03-16 13:07:21 +0100 | [diff] [blame] | 120 | kfree(bp); |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 121 | } |
Suresh Siddha | 1dcc8d7 | 2012-05-16 15:03:54 -0700 | [diff] [blame] | 122 | |
Ingo Molnar | ca6787b | 2015-04-23 12:33:50 +0200 | [diff] [blame] | 123 | drop_fpu(fpu); |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | void flush_thread(void) |
| 127 | { |
| 128 | struct task_struct *tsk = current; |
| 129 | |
Frederic Weisbecker | 24f1e32c | 2009-09-09 19:22:48 +0200 | [diff] [blame] | 130 | flush_ptrace_hw_breakpoint(tsk); |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 131 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
Oleg Nesterov | 110d7f7 | 2015-01-19 19:52:12 +0100 | [diff] [blame] | 132 | |
Ingo Molnar | 2e8a310 | 2015-04-24 02:28:23 +0200 | [diff] [blame] | 133 | fpu__clear(tsk); |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 134 | } |
| 135 | |
| 136 | static void hard_disable_TSC(void) |
| 137 | { |
Andy Lutomirski | 375074c | 2014-10-24 15:58:07 -0700 | [diff] [blame] | 138 | cr4_set_bits(X86_CR4_TSD); |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | void disable_TSC(void) |
| 142 | { |
| 143 | preempt_disable(); |
| 144 | if (!test_and_set_thread_flag(TIF_NOTSC)) |
| 145 | /* |
| 146 | * Must flip the CPU state synchronously with |
| 147 | * TIF_NOTSC in the current running context. |
| 148 | */ |
| 149 | hard_disable_TSC(); |
| 150 | preempt_enable(); |
| 151 | } |
| 152 | |
| 153 | static void hard_enable_TSC(void) |
| 154 | { |
Andy Lutomirski | 375074c | 2014-10-24 15:58:07 -0700 | [diff] [blame] | 155 | cr4_clear_bits(X86_CR4_TSD); |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 156 | } |
| 157 | |
| 158 | static void enable_TSC(void) |
| 159 | { |
| 160 | preempt_disable(); |
| 161 | if (test_and_clear_thread_flag(TIF_NOTSC)) |
| 162 | /* |
| 163 | * Must flip the CPU state synchronously with |
| 164 | * TIF_NOTSC in the current running context. |
| 165 | */ |
| 166 | hard_enable_TSC(); |
| 167 | preempt_enable(); |
| 168 | } |
| 169 | |
| 170 | int get_tsc_mode(unsigned long adr) |
| 171 | { |
| 172 | unsigned int val; |
| 173 | |
| 174 | if (test_thread_flag(TIF_NOTSC)) |
| 175 | val = PR_TSC_SIGSEGV; |
| 176 | else |
| 177 | val = PR_TSC_ENABLE; |
| 178 | |
| 179 | return put_user(val, (unsigned int __user *)adr); |
| 180 | } |
| 181 | |
| 182 | int set_tsc_mode(unsigned int val) |
| 183 | { |
| 184 | if (val == PR_TSC_SIGSEGV) |
| 185 | disable_TSC(); |
| 186 | else if (val == PR_TSC_ENABLE) |
| 187 | enable_TSC(); |
| 188 | else |
| 189 | return -EINVAL; |
| 190 | |
| 191 | return 0; |
| 192 | } |
| 193 | |
| 194 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, |
| 195 | struct tss_struct *tss) |
| 196 | { |
| 197 | struct thread_struct *prev, *next; |
| 198 | |
| 199 | prev = &prev_p->thread; |
| 200 | next = &next_p->thread; |
| 201 | |
Peter Zijlstra | ea8e61b | 2010-03-25 14:51:51 +0100 | [diff] [blame] | 202 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
| 203 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { |
| 204 | unsigned long debugctl = get_debugctlmsr(); |
| 205 | |
| 206 | debugctl &= ~DEBUGCTLMSR_BTF; |
| 207 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) |
| 208 | debugctl |= DEBUGCTLMSR_BTF; |
| 209 | |
| 210 | update_debugctlmsr(debugctl); |
| 211 | } |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 212 | |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 213 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
| 214 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { |
| 215 | /* prev and next are different */ |
| 216 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) |
| 217 | hard_disable_TSC(); |
| 218 | else |
| 219 | hard_enable_TSC(); |
| 220 | } |
| 221 | |
| 222 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { |
| 223 | /* |
| 224 | * Copy the relevant range of the IO bitmap. |
| 225 | * Normally this is 128 bytes or less: |
| 226 | */ |
| 227 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, |
| 228 | max(prev->io_bitmap_max, next->io_bitmap_max)); |
| 229 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { |
| 230 | /* |
| 231 | * Clear any possible leftover bits: |
| 232 | */ |
| 233 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); |
| 234 | } |
Avi Kivity | 7c68af6 | 2009-09-19 09:40:22 +0300 | [diff] [blame] | 235 | propagate_user_return_notify(prev_p, next_p); |
Jeremy Fitzhardinge | 389d1fb | 2009-02-27 13:25:28 -0800 | [diff] [blame] | 236 | } |
| 237 | |
Brian Gerst | df59e7b | 2009-12-09 12:34:44 -0500 | [diff] [blame] | 238 | /* |
Thomas Gleixner | 00dba56 | 2008-06-09 18:35:28 +0200 | [diff] [blame] | 239 | * Idle related variables and functions |
| 240 | */ |
Thomas Renninger | d189604 | 2010-11-03 17:06:14 +0100 | [diff] [blame] | 241 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
Thomas Gleixner | 00dba56 | 2008-06-09 18:35:28 +0200 | [diff] [blame] | 242 | EXPORT_SYMBOL(boot_option_idle_override); |
| 243 | |
Len Brown | a476bda | 2013-02-09 21:45:03 -0500 | [diff] [blame] | 244 | static void (*x86_idle)(void); |
Thomas Gleixner | 00dba56 | 2008-06-09 18:35:28 +0200 | [diff] [blame] | 245 | |
Richard Weinberger | 90e2401 | 2012-03-25 23:00:04 +0200 | [diff] [blame] | 246 | #ifndef CONFIG_SMP |
| 247 | static inline void play_dead(void) |
| 248 | { |
| 249 | BUG(); |
| 250 | } |
| 251 | #endif |
| 252 | |
| 253 | #ifdef CONFIG_X86_64 |
| 254 | void enter_idle(void) |
| 255 | { |
Alex Shi | c6ae41e | 2012-05-11 15:35:27 +0800 | [diff] [blame] | 256 | this_cpu_write(is_idle, 1); |
Richard Weinberger | 90e2401 | 2012-03-25 23:00:04 +0200 | [diff] [blame] | 257 | atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); |
| 258 | } |
| 259 | |
| 260 | static void __exit_idle(void) |
| 261 | { |
| 262 | if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) |
| 263 | return; |
| 264 | atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); |
| 265 | } |
| 266 | |
| 267 | /* Called from interrupts to signify idle end */ |
| 268 | void exit_idle(void) |
| 269 | { |
| 270 | /* idle loop has pid 0 */ |
| 271 | if (current->pid) |
| 272 | return; |
| 273 | __exit_idle(); |
| 274 | } |
| 275 | #endif |
| 276 | |
Thomas Gleixner | 7d1a941 | 2013-03-21 22:50:03 +0100 | [diff] [blame] | 277 | void arch_cpu_idle_enter(void) |
| 278 | { |
| 279 | local_touch_nmi(); |
| 280 | enter_idle(); |
| 281 | } |
Richard Weinberger | 90e2401 | 2012-03-25 23:00:04 +0200 | [diff] [blame] | 282 | |
Thomas Gleixner | 7d1a941 | 2013-03-21 22:50:03 +0100 | [diff] [blame] | 283 | void arch_cpu_idle_exit(void) |
| 284 | { |
| 285 | __exit_idle(); |
| 286 | } |
Richard Weinberger | 90e2401 | 2012-03-25 23:00:04 +0200 | [diff] [blame] | 287 | |
Thomas Gleixner | 7d1a941 | 2013-03-21 22:50:03 +0100 | [diff] [blame] | 288 | void arch_cpu_idle_dead(void) |
| 289 | { |
| 290 | play_dead(); |
Richard Weinberger | 90e2401 | 2012-03-25 23:00:04 +0200 | [diff] [blame] | 291 | } |
| 292 | |
Thomas Gleixner | 00dba56 | 2008-06-09 18:35:28 +0200 | [diff] [blame] | 293 | /* |
Thomas Gleixner | 7d1a941 | 2013-03-21 22:50:03 +0100 | [diff] [blame] | 294 | * Called from the generic idle code. |
| 295 | */ |
| 296 | void arch_cpu_idle(void) |
| 297 | { |
Nicolas Pitre | 16f8b05 | 2014-01-29 12:45:12 -0500 | [diff] [blame] | 298 | x86_idle(); |
Thomas Gleixner | 7d1a941 | 2013-03-21 22:50:03 +0100 | [diff] [blame] | 299 | } |
| 300 | |
| 301 | /* |
| 302 | * We use this if we don't have any better idle routine.. |
Thomas Gleixner | 00dba56 | 2008-06-09 18:35:28 +0200 | [diff] [blame] | 303 | */ |
| 304 | void default_idle(void) |
| 305 | { |
Daniel Lezcano | 4d0e42c | 2012-10-25 18:13:11 +0200 | [diff] [blame] | 306 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
Thomas Gleixner | 7d1a941 | 2013-03-21 22:50:03 +0100 | [diff] [blame] | 307 | safe_halt(); |
Daniel Lezcano | 4d0e42c | 2012-10-25 18:13:11 +0200 | [diff] [blame] | 308 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
Thomas Gleixner | 00dba56 | 2008-06-09 18:35:28 +0200 | [diff] [blame] | 309 | } |
Andy Whitcroft | 60b8b1d | 2011-06-14 12:45:10 -0700 | [diff] [blame] | 310 | #ifdef CONFIG_APM_MODULE |
Thomas Gleixner | 00dba56 | 2008-06-09 18:35:28 +0200 | [diff] [blame] | 311 | EXPORT_SYMBOL(default_idle); |
| 312 | #endif |
| 313 | |
Len Brown | 6a377dd | 2013-02-09 23:08:07 -0500 | [diff] [blame] | 314 | #ifdef CONFIG_XEN |
| 315 | bool xen_set_default_idle(void) |
Konrad Rzeszutek Wilk | e5fd47b | 2011-11-21 18:02:02 -0500 | [diff] [blame] | 316 | { |
Len Brown | a476bda | 2013-02-09 21:45:03 -0500 | [diff] [blame] | 317 | bool ret = !!x86_idle; |
Konrad Rzeszutek Wilk | e5fd47b | 2011-11-21 18:02:02 -0500 | [diff] [blame] | 318 | |
Len Brown | a476bda | 2013-02-09 21:45:03 -0500 | [diff] [blame] | 319 | x86_idle = default_idle; |
Konrad Rzeszutek Wilk | e5fd47b | 2011-11-21 18:02:02 -0500 | [diff] [blame] | 320 | |
| 321 | return ret; |
| 322 | } |
Len Brown | 6a377dd | 2013-02-09 23:08:07 -0500 | [diff] [blame] | 323 | #endif |
Ivan Vecera | d3ec5ca | 2008-11-11 14:33:44 +0100 | [diff] [blame] | 324 | void stop_this_cpu(void *dummy) |
| 325 | { |
| 326 | local_irq_disable(); |
| 327 | /* |
| 328 | * Remove this CPU: |
| 329 | */ |
Rusty Russell | 4f06289 | 2009-03-13 14:49:54 +1030 | [diff] [blame] | 330 | set_cpu_online(smp_processor_id(), false); |
Ivan Vecera | d3ec5ca | 2008-11-11 14:33:44 +0100 | [diff] [blame] | 331 | disable_local_APIC(); |
| 332 | |
Len Brown | 27be457 | 2013-02-10 02:28:46 -0500 | [diff] [blame] | 333 | for (;;) |
| 334 | halt(); |
Peter Zijlstra | 7f424a8 | 2008-04-25 17:39:01 +0200 | [diff] [blame] | 335 | } |
| 336 | |
Len Brown | 02c68a0 | 2011-04-01 16:59:53 -0400 | [diff] [blame] | 337 | bool amd_e400_c1e_detected; |
| 338 | EXPORT_SYMBOL(amd_e400_c1e_detected); |
Thomas Gleixner | aa276e1 | 2008-06-09 19:15:00 +0200 | [diff] [blame] | 339 | |
Len Brown | 02c68a0 | 2011-04-01 16:59:53 -0400 | [diff] [blame] | 340 | static cpumask_var_t amd_e400_c1e_mask; |
Thomas Gleixner | 4faac97 | 2008-09-22 18:54:29 +0200 | [diff] [blame] | 341 | |
Len Brown | 02c68a0 | 2011-04-01 16:59:53 -0400 | [diff] [blame] | 342 | void amd_e400_remove_cpu(int cpu) |
Thomas Gleixner | 4faac97 | 2008-09-22 18:54:29 +0200 | [diff] [blame] | 343 | { |
Len Brown | 02c68a0 | 2011-04-01 16:59:53 -0400 | [diff] [blame] | 344 | if (amd_e400_c1e_mask != NULL) |
| 345 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); |
Thomas Gleixner | 4faac97 | 2008-09-22 18:54:29 +0200 | [diff] [blame] | 346 | } |
| 347 | |
Thomas Gleixner | aa276e1 | 2008-06-09 19:15:00 +0200 | [diff] [blame] | 348 | /* |
Len Brown | 02c68a0 | 2011-04-01 16:59:53 -0400 | [diff] [blame] | 349 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
Thomas Gleixner | aa276e1 | 2008-06-09 19:15:00 +0200 | [diff] [blame] | 350 | * pending message MSR. If we detect C1E, then we handle it the same |
| 351 | * way as C3 power states (local apic timer and TSC stop) |
| 352 | */ |
Len Brown | 02c68a0 | 2011-04-01 16:59:53 -0400 | [diff] [blame] | 353 | static void amd_e400_idle(void) |
Thomas Gleixner | aa276e1 | 2008-06-09 19:15:00 +0200 | [diff] [blame] | 354 | { |
Len Brown | 02c68a0 | 2011-04-01 16:59:53 -0400 | [diff] [blame] | 355 | if (!amd_e400_c1e_detected) { |
Thomas Gleixner | aa276e1 | 2008-06-09 19:15:00 +0200 | [diff] [blame] | 356 | u32 lo, hi; |
| 357 | |
| 358 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); |
Michal Schmidt | e8c534e | 2010-07-27 18:53:35 +0200 | [diff] [blame] | 359 | |
Thomas Gleixner | aa276e1 | 2008-06-09 19:15:00 +0200 | [diff] [blame] | 360 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
Len Brown | 02c68a0 | 2011-04-01 16:59:53 -0400 | [diff] [blame] | 361 | amd_e400_c1e_detected = true; |
Venki Pallipadi | 40fb171 | 2008-11-17 16:11:37 -0800 | [diff] [blame] | 362 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
Andreas Herrmann | 09bfeea | 2008-09-18 21:12:10 +0200 | [diff] [blame] | 363 | mark_tsc_unstable("TSC halt in AMD C1E"); |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 364 | pr_info("System has AMD C1E enabled\n"); |
Thomas Gleixner | aa276e1 | 2008-06-09 19:15:00 +0200 | [diff] [blame] | 365 | } |
| 366 | } |
| 367 | |
Len Brown | 02c68a0 | 2011-04-01 16:59:53 -0400 | [diff] [blame] | 368 | if (amd_e400_c1e_detected) { |
Thomas Gleixner | aa276e1 | 2008-06-09 19:15:00 +0200 | [diff] [blame] | 369 | int cpu = smp_processor_id(); |
| 370 | |
Len Brown | 02c68a0 | 2011-04-01 16:59:53 -0400 | [diff] [blame] | 371 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
| 372 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); |
Thomas Gleixner | 162a688 | 2015-04-03 02:01:28 +0200 | [diff] [blame] | 373 | /* Force broadcast so ACPI can not interfere. */ |
| 374 | tick_broadcast_force(); |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 375 | pr_info("Switch to broadcast mode on CPU%d\n", cpu); |
Thomas Gleixner | aa276e1 | 2008-06-09 19:15:00 +0200 | [diff] [blame] | 376 | } |
Thomas Gleixner | 435c350 | 2015-04-03 02:05:53 +0200 | [diff] [blame] | 377 | tick_broadcast_enter(); |
Thomas Gleixner | 0beefa2 | 2008-06-17 09:12:03 +0200 | [diff] [blame] | 378 | |
Thomas Gleixner | aa276e1 | 2008-06-09 19:15:00 +0200 | [diff] [blame] | 379 | default_idle(); |
Thomas Gleixner | 0beefa2 | 2008-06-17 09:12:03 +0200 | [diff] [blame] | 380 | |
| 381 | /* |
| 382 | * The switch back from broadcast mode needs to be |
| 383 | * called with interrupts disabled. |
| 384 | */ |
Peter Zijlstra | ea81174 | 2013-09-11 12:43:13 +0200 | [diff] [blame] | 385 | local_irq_disable(); |
Thomas Gleixner | 435c350 | 2015-04-03 02:05:53 +0200 | [diff] [blame] | 386 | tick_broadcast_exit(); |
Peter Zijlstra | ea81174 | 2013-09-11 12:43:13 +0200 | [diff] [blame] | 387 | local_irq_enable(); |
Thomas Gleixner | aa276e1 | 2008-06-09 19:15:00 +0200 | [diff] [blame] | 388 | } else |
| 389 | default_idle(); |
| 390 | } |
| 391 | |
Len Brown | b253149 | 2014-01-15 00:37:34 -0500 | [diff] [blame] | 392 | /* |
| 393 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. |
| 394 | * We can't rely on cpuidle installing MWAIT, because it will not load |
| 395 | * on systems that support only C1 -- so the boot default must be MWAIT. |
| 396 | * |
| 397 | * Some AMD machines are the opposite, they depend on using HALT. |
| 398 | * |
| 399 | * So for default C1, which is used during boot until cpuidle loads, |
| 400 | * use MWAIT-C1 on Intel HW that has it, else use HALT. |
| 401 | */ |
| 402 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) |
| 403 | { |
| 404 | if (c->x86_vendor != X86_VENDOR_INTEL) |
| 405 | return 0; |
| 406 | |
| 407 | if (!cpu_has(c, X86_FEATURE_MWAIT)) |
| 408 | return 0; |
| 409 | |
| 410 | return 1; |
| 411 | } |
| 412 | |
| 413 | /* |
| 414 | * MONITOR/MWAIT with no hints, used for default default C1 state. |
| 415 | * This invokes MWAIT with interrutps enabled and no flags, |
| 416 | * which is backwards compatible with the original MWAIT implementation. |
| 417 | */ |
| 418 | |
| 419 | static void mwait_idle(void) |
| 420 | { |
Mike Galbraith | f8e617f | 2014-01-18 17:14:44 +0100 | [diff] [blame] | 421 | if (!current_set_polling_and_test()) { |
| 422 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { |
| 423 | smp_mb(); /* quirk */ |
Len Brown | b253149 | 2014-01-15 00:37:34 -0500 | [diff] [blame] | 424 | clflush((void *)¤t_thread_info()->flags); |
Mike Galbraith | f8e617f | 2014-01-18 17:14:44 +0100 | [diff] [blame] | 425 | smp_mb(); /* quirk */ |
| 426 | } |
Len Brown | b253149 | 2014-01-15 00:37:34 -0500 | [diff] [blame] | 427 | |
| 428 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
Len Brown | b253149 | 2014-01-15 00:37:34 -0500 | [diff] [blame] | 429 | if (!need_resched()) |
| 430 | __sti_mwait(0, 0); |
| 431 | else |
| 432 | local_irq_enable(); |
Mike Galbraith | f8e617f | 2014-01-18 17:14:44 +0100 | [diff] [blame] | 433 | } else { |
Len Brown | b253149 | 2014-01-15 00:37:34 -0500 | [diff] [blame] | 434 | local_irq_enable(); |
Mike Galbraith | f8e617f | 2014-01-18 17:14:44 +0100 | [diff] [blame] | 435 | } |
| 436 | __current_clr_polling(); |
Len Brown | b253149 | 2014-01-15 00:37:34 -0500 | [diff] [blame] | 437 | } |
| 438 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 439 | void select_idle_routine(const struct cpuinfo_x86 *c) |
Peter Zijlstra | 7f424a8 | 2008-04-25 17:39:01 +0200 | [diff] [blame] | 440 | { |
Ingo Molnar | 3e5095d | 2009-01-27 17:07:08 +0100 | [diff] [blame] | 441 | #ifdef CONFIG_SMP |
Thomas Gleixner | 7d1a941 | 2013-03-21 22:50:03 +0100 | [diff] [blame] | 442 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 443 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
Peter Zijlstra | 7f424a8 | 2008-04-25 17:39:01 +0200 | [diff] [blame] | 444 | #endif |
Thomas Gleixner | 7d1a941 | 2013-03-21 22:50:03 +0100 | [diff] [blame] | 445 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
Thomas Gleixner | 6ddd2a2 | 2008-06-09 16:59:53 +0200 | [diff] [blame] | 446 | return; |
| 447 | |
Borislav Petkov | 7d7dc11 | 2013-03-20 15:07:28 +0100 | [diff] [blame] | 448 | if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) { |
Hans Rosenfeld | 9d8888c | 2010-07-28 19:09:31 +0200 | [diff] [blame] | 449 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 450 | pr_info("using AMD E400 aware idle routine\n"); |
Len Brown | a476bda | 2013-02-09 21:45:03 -0500 | [diff] [blame] | 451 | x86_idle = amd_e400_idle; |
Len Brown | b253149 | 2014-01-15 00:37:34 -0500 | [diff] [blame] | 452 | } else if (prefer_mwait_c1_over_halt(c)) { |
| 453 | pr_info("using mwait in idle threads\n"); |
| 454 | x86_idle = mwait_idle; |
Thomas Gleixner | 6ddd2a2 | 2008-06-09 16:59:53 +0200 | [diff] [blame] | 455 | } else |
Len Brown | a476bda | 2013-02-09 21:45:03 -0500 | [diff] [blame] | 456 | x86_idle = default_idle; |
Peter Zijlstra | 7f424a8 | 2008-04-25 17:39:01 +0200 | [diff] [blame] | 457 | } |
| 458 | |
Len Brown | 02c68a0 | 2011-04-01 16:59:53 -0400 | [diff] [blame] | 459 | void __init init_amd_e400_c1e_mask(void) |
Rusty Russell | 30e1e6d | 2009-03-17 14:50:34 +1030 | [diff] [blame] | 460 | { |
Len Brown | 02c68a0 | 2011-04-01 16:59:53 -0400 | [diff] [blame] | 461 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
Len Brown | a476bda | 2013-02-09 21:45:03 -0500 | [diff] [blame] | 462 | if (x86_idle == amd_e400_idle) |
Len Brown | 02c68a0 | 2011-04-01 16:59:53 -0400 | [diff] [blame] | 463 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); |
Rusty Russell | 30e1e6d | 2009-03-17 14:50:34 +1030 | [diff] [blame] | 464 | } |
| 465 | |
Peter Zijlstra | 7f424a8 | 2008-04-25 17:39:01 +0200 | [diff] [blame] | 466 | static int __init idle_setup(char *str) |
| 467 | { |
Cyrill Gorcunov | ab6bc3e | 2008-07-05 15:53:36 +0400 | [diff] [blame] | 468 | if (!str) |
| 469 | return -EINVAL; |
| 470 | |
Peter Zijlstra | 7f424a8 | 2008-04-25 17:39:01 +0200 | [diff] [blame] | 471 | if (!strcmp(str, "poll")) { |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 472 | pr_info("using polling idle threads\n"); |
Thomas Renninger | d189604 | 2010-11-03 17:06:14 +0100 | [diff] [blame] | 473 | boot_option_idle_override = IDLE_POLL; |
Thomas Gleixner | 7d1a941 | 2013-03-21 22:50:03 +0100 | [diff] [blame] | 474 | cpu_idle_poll_ctrl(true); |
Thomas Renninger | d189604 | 2010-11-03 17:06:14 +0100 | [diff] [blame] | 475 | } else if (!strcmp(str, "halt")) { |
Zhao Yakui | c1e3b37 | 2008-06-24 17:58:53 +0800 | [diff] [blame] | 476 | /* |
| 477 | * When the boot option of idle=halt is added, halt is |
| 478 | * forced to be used for CPU idle. In such case CPU C2/C3 |
| 479 | * won't be used again. |
| 480 | * To continue to load the CPU idle driver, don't touch |
| 481 | * the boot_option_idle_override. |
| 482 | */ |
Len Brown | a476bda | 2013-02-09 21:45:03 -0500 | [diff] [blame] | 483 | x86_idle = default_idle; |
Thomas Renninger | d189604 | 2010-11-03 17:06:14 +0100 | [diff] [blame] | 484 | boot_option_idle_override = IDLE_HALT; |
Zhao Yakui | da5e09a | 2008-06-24 18:01:09 +0800 | [diff] [blame] | 485 | } else if (!strcmp(str, "nomwait")) { |
| 486 | /* |
| 487 | * If the boot option of "idle=nomwait" is added, |
| 488 | * it means that mwait will be disabled for CPU C2/C3 |
| 489 | * states. In such case it won't touch the variable |
| 490 | * of boot_option_idle_override. |
| 491 | */ |
Thomas Renninger | d189604 | 2010-11-03 17:06:14 +0100 | [diff] [blame] | 492 | boot_option_idle_override = IDLE_NOMWAIT; |
Zhao Yakui | c1e3b37 | 2008-06-24 17:58:53 +0800 | [diff] [blame] | 493 | } else |
Peter Zijlstra | 7f424a8 | 2008-04-25 17:39:01 +0200 | [diff] [blame] | 494 | return -1; |
| 495 | |
Peter Zijlstra | 7f424a8 | 2008-04-25 17:39:01 +0200 | [diff] [blame] | 496 | return 0; |
| 497 | } |
| 498 | early_param("idle", idle_setup); |
| 499 | |
Amerigo Wang | 9d62dcd | 2009-05-11 22:05:28 -0400 | [diff] [blame] | 500 | unsigned long arch_align_stack(unsigned long sp) |
| 501 | { |
| 502 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) |
| 503 | sp -= get_random_int() % 8192; |
| 504 | return sp & ~0xf; |
| 505 | } |
| 506 | |
| 507 | unsigned long arch_randomize_brk(struct mm_struct *mm) |
| 508 | { |
| 509 | unsigned long range_end = mm->brk + 0x02000000; |
| 510 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; |
| 511 | } |
| 512 | |