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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
Fabian Godehardtb6e49132009-06-11 14:53:18 +01009 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31#define SUPPORT_SYSRQ
32#endif
33
34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/init.h>
37#include <linux/console.h>
38#include <linux/sysrq.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010039#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <linux/tty.h>
41#include <linux/tty_flip.h>
42#include <linux/serial_core.h>
43#include <linux/serial.h>
Sascha Hauer38a41fd2008-07-05 10:02:46 +020044#include <linux/clk.h>
Fabian Godehardtb6e49132009-06-11 14:53:18 +010045#include <linux/delay.h>
Oskar Schirmer534fca02009-06-11 14:52:23 +010046#include <linux/rational.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090047#include <linux/slab.h>
Shawn Guo22698aa2011-06-25 02:04:34 +080048#include <linux/of.h>
49#include <linux/of_device.h>
Sachin Kamate32a9f82013-01-07 10:25:03 +053050#include <linux/io.h>
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080051#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#include <asm/irq.h>
Arnd Bergmann82906b12012-08-24 15:14:29 +020054#include <linux/platform_data/serial-imx.h>
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080055#include <linux/platform_data/dma-imx.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070056
Sascha Hauerff4bfb22007-04-26 08:26:13 +010057/* Register definitions */
58#define URXD0 0x0 /* Receiver Register */
59#define URTX0 0x40 /* Transmitter Register */
60#define UCR1 0x80 /* Control Register 1 */
61#define UCR2 0x84 /* Control Register 2 */
62#define UCR3 0x88 /* Control Register 3 */
63#define UCR4 0x8c /* Control Register 4 */
64#define UFCR 0x90 /* FIFO Control Register */
65#define USR1 0x94 /* Status Register 1 */
66#define USR2 0x98 /* Status Register 2 */
67#define UESC 0x9c /* Escape Character Register */
68#define UTIM 0xa0 /* Escape Timer Register */
69#define UBIR 0xa4 /* BRM Incremental Register */
70#define UBMR 0xa8 /* BRM Modulator Register */
71#define UBRC 0xac /* Baud Rate Count Register */
Shawn Guofe6b5402011-06-25 02:04:33 +080072#define IMX21_ONEMS 0xb0 /* One Millisecond register */
73#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
Sascha Hauerff4bfb22007-04-26 08:26:13 +010075
76/* UART Control Register Bit Fields.*/
Jiada Wang55d86932014-12-09 18:11:22 +090077#define URXD_DUMMY_READ (1<<16)
Sachin Kamat82313e62013-01-07 10:25:02 +053078#define URXD_CHARRDY (1<<15)
79#define URXD_ERR (1<<14)
80#define URXD_OVRRUN (1<<13)
81#define URXD_FRMERR (1<<12)
82#define URXD_BRK (1<<11)
83#define URXD_PRERR (1<<10)
Dirk Behme26c47412014-09-03 12:33:53 +010084#define URXD_RX_DATA (0xFF<<0)
Sachin Kamat82313e62013-01-07 10:25:02 +053085#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
86#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
87#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
88#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080089#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
Sachin Kamat82313e62013-01-07 10:25:02 +053090#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
91#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
92#define UCR1_IREN (1<<7) /* Infrared interface enable */
93#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
94#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
95#define UCR1_SNDBRK (1<<4) /* Send break */
96#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
97#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080098#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
Sachin Kamat82313e62013-01-07 10:25:02 +053099#define UCR1_DOZE (1<<1) /* Doze */
100#define UCR1_UARTEN (1<<0) /* UART enabled */
101#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
102#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
103#define UCR2_CTSC (1<<13) /* CTS pin control */
104#define UCR2_CTS (1<<12) /* Clear to send */
105#define UCR2_ESCEN (1<<11) /* Escape enable */
106#define UCR2_PREN (1<<8) /* Parity enable */
107#define UCR2_PROE (1<<7) /* Parity odd/even */
108#define UCR2_STPB (1<<6) /* Stop */
109#define UCR2_WS (1<<5) /* Word size */
110#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
111#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
112#define UCR2_TXEN (1<<2) /* Transmitter enabled */
113#define UCR2_RXEN (1<<1) /* Receiver enabled */
114#define UCR2_SRST (1<<0) /* SW reset */
115#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
116#define UCR3_PARERREN (1<<12) /* Parity enable */
117#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
118#define UCR3_DSR (1<<10) /* Data set ready */
119#define UCR3_DCD (1<<9) /* Data carrier detect */
120#define UCR3_RI (1<<8) /* Ring indicator */
Fabio Estevamb38cb7d2014-05-14 15:55:03 -0300121#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
Sachin Kamat82313e62013-01-07 10:25:02 +0530122#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
123#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
124#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
125#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
126#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
127#define UCR3_BPEN (1<<0) /* Preset registers enable */
128#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
129#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
130#define UCR4_INVR (1<<9) /* Inverted infrared reception */
131#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
132#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
133#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800134#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
Sachin Kamat82313e62013-01-07 10:25:02 +0530135#define UCR4_IRSC (1<<5) /* IR special case */
136#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
137#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
138#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
139#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
140#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
141#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
142#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
143#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
144#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
145#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
146#define USR1_RTSS (1<<14) /* RTS pin status */
147#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
148#define USR1_RTSD (1<<12) /* RTS delta */
149#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
150#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
151#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
152#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
153#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
154#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
155#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
156#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
157#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
158#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
159#define USR2_IDLE (1<<12) /* Idle condition */
160#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
161#define USR2_WAKE (1<<7) /* Wake */
162#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
163#define USR2_TXDC (1<<3) /* Transmitter complete */
164#define USR2_BRCD (1<<2) /* Break condition */
165#define USR2_ORE (1<<1) /* Overrun error */
166#define USR2_RDR (1<<0) /* Recv data ready */
167#define UTS_FRCPERR (1<<13) /* Force parity error */
168#define UTS_LOOP (1<<12) /* Loop tx and rx */
169#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
170#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
171#define UTS_TXFULL (1<<4) /* TxFIFO full */
172#define UTS_RXFULL (1<<3) /* RxFIFO full */
173#define UTS_SOFTRST (1<<0) /* Software reset */
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100174
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175/* We've been assigned a range on the "Low-density serial ports" major */
Sachin Kamat82313e62013-01-07 10:25:02 +0530176#define SERIAL_IMX_MAJOR 207
177#define MINOR_START 16
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200178#define DEV_NAME "ttymxc"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 * This determines how often we check the modem status signals
182 * for any change. They generally aren't connected to an IRQ
183 * so we have to poll them. We also check immediately before
184 * filling the TX fifo incase CTS has been dropped.
185 */
186#define MCTRL_TIMEOUT (250*HZ/1000)
187
188#define DRIVER_NAME "IMX-uart"
189
Sascha Hauerdbff4e92008-07-05 10:02:45 +0200190#define UART_NR 8
191
Shawn Guofe6b5402011-06-25 02:04:33 +0800192/* i.mx21 type uart runs on all i.mx except i.mx1 */
193enum imx_uart_type {
194 IMX1_UART,
195 IMX21_UART,
Huang Shijiea496e622013-07-08 17:14:17 +0800196 IMX6Q_UART,
Shawn Guofe6b5402011-06-25 02:04:33 +0800197};
198
199/* device type dependent stuff */
200struct imx_uart_data {
201 unsigned uts_reg;
202 enum imx_uart_type devtype;
203};
204
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205struct imx_port {
206 struct uart_port port;
207 struct timer_list timer;
208 unsigned int old_status;
Sachin Kamat82313e62013-01-07 10:25:02 +0530209 int txirq, rxirq, rtsirq;
Daniel Glöckner26bbb3f2009-06-11 14:36:29 +0100210 unsigned int have_rtscts:1;
Huang Shijie20ff2fe2013-05-30 14:07:12 +0800211 unsigned int dte_mode:1;
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100212 unsigned int use_irda:1;
213 unsigned int irda_inv_rx:1;
214 unsigned int irda_inv_tx:1;
215 unsigned short trcv_delay; /* transceiver delay */
Sascha Hauer3a9465f2012-03-07 09:31:43 +0100216 struct clk *clk_ipg;
217 struct clk *clk_per;
Uwe Kleine-König7d0b0662012-05-21 21:57:39 +0200218 const struct imx_uart_data *devdata;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800219
220 /* DMA fields */
221 unsigned int dma_is_inited:1;
222 unsigned int dma_is_enabled:1;
223 unsigned int dma_is_rxing:1;
224 unsigned int dma_is_txing:1;
225 struct dma_chan *dma_chan_rx, *dma_chan_tx;
226 struct scatterlist rx_sgl, tx_sgl[2];
227 void *rx_buf;
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800228 unsigned int tx_bytes;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800229 unsigned int dma_tx_nents;
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -0700230 wait_queue_head_t dma_wait;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231};
232
Dirk Behme0ad5a812011-12-22 09:57:52 +0100233struct imx_port_ucrs {
234 unsigned int ucr1;
235 unsigned int ucr2;
236 unsigned int ucr3;
237};
238
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100239#ifdef CONFIG_IRDA
240#define USE_IRDA(sport) ((sport)->use_irda)
241#else
242#define USE_IRDA(sport) (0)
243#endif
244
Shawn Guofe6b5402011-06-25 02:04:33 +0800245static struct imx_uart_data imx_uart_devdata[] = {
246 [IMX1_UART] = {
247 .uts_reg = IMX1_UTS,
248 .devtype = IMX1_UART,
249 },
250 [IMX21_UART] = {
251 .uts_reg = IMX21_UTS,
252 .devtype = IMX21_UART,
253 },
Huang Shijiea496e622013-07-08 17:14:17 +0800254 [IMX6Q_UART] = {
255 .uts_reg = IMX21_UTS,
256 .devtype = IMX6Q_UART,
257 },
Shawn Guofe6b5402011-06-25 02:04:33 +0800258};
259
260static struct platform_device_id imx_uart_devtype[] = {
261 {
262 .name = "imx1-uart",
263 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
264 }, {
265 .name = "imx21-uart",
266 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
267 }, {
Huang Shijiea496e622013-07-08 17:14:17 +0800268 .name = "imx6q-uart",
269 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
270 }, {
Shawn Guofe6b5402011-06-25 02:04:33 +0800271 /* sentinel */
272 }
273};
274MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
275
Shawn Guo22698aa2011-06-25 02:04:34 +0800276static struct of_device_id imx_uart_dt_ids[] = {
Huang Shijiea496e622013-07-08 17:14:17 +0800277 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
Shawn Guo22698aa2011-06-25 02:04:34 +0800278 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
279 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
280 { /* sentinel */ }
281};
282MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
283
Shawn Guofe6b5402011-06-25 02:04:33 +0800284static inline unsigned uts_reg(struct imx_port *sport)
285{
286 return sport->devdata->uts_reg;
287}
288
289static inline int is_imx1_uart(struct imx_port *sport)
290{
291 return sport->devdata->devtype == IMX1_UART;
292}
293
294static inline int is_imx21_uart(struct imx_port *sport)
295{
296 return sport->devdata->devtype == IMX21_UART;
297}
298
Huang Shijiea496e622013-07-08 17:14:17 +0800299static inline int is_imx6q_uart(struct imx_port *sport)
300{
301 return sport->devdata->devtype == IMX6Q_UART;
302}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303/*
fabio.estevam@freescale.com44a75412013-02-06 19:00:02 -0200304 * Save and restore functions for UCR1, UCR2 and UCR3 registers
305 */
Fabio Estevam93d94b32014-11-12 15:55:07 -0200306#if defined(CONFIG_SERIAL_IMX_CONSOLE)
fabio.estevam@freescale.com44a75412013-02-06 19:00:02 -0200307static void imx_port_ucrs_save(struct uart_port *port,
308 struct imx_port_ucrs *ucr)
309{
310 /* save control registers */
311 ucr->ucr1 = readl(port->membase + UCR1);
312 ucr->ucr2 = readl(port->membase + UCR2);
313 ucr->ucr3 = readl(port->membase + UCR3);
314}
315
316static void imx_port_ucrs_restore(struct uart_port *port,
317 struct imx_port_ucrs *ucr)
318{
319 /* restore control registers */
320 writel(ucr->ucr1, port->membase + UCR1);
321 writel(ucr->ucr2, port->membase + UCR2);
322 writel(ucr->ucr3, port->membase + UCR3);
323}
Fabio Estevame8bfa762013-06-05 00:58:46 -0300324#endif
fabio.estevam@freescale.com44a75412013-02-06 19:00:02 -0200325
326/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327 * Handle any change of modem status signal since we were last called.
328 */
329static void imx_mctrl_check(struct imx_port *sport)
330{
331 unsigned int status, changed;
332
333 status = sport->port.ops->get_mctrl(&sport->port);
334 changed = status ^ sport->old_status;
335
336 if (changed == 0)
337 return;
338
339 sport->old_status = status;
340
341 if (changed & TIOCM_RI)
342 sport->port.icount.rng++;
343 if (changed & TIOCM_DSR)
344 sport->port.icount.dsr++;
345 if (changed & TIOCM_CAR)
346 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
347 if (changed & TIOCM_CTS)
348 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
349
Alan Coxbdc04e32009-09-19 13:13:31 -0700350 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351}
352
353/*
354 * This is our per-port timeout handler, for checking the
355 * modem status signals.
356 */
357static void imx_timeout(unsigned long data)
358{
359 struct imx_port *sport = (struct imx_port *)data;
360 unsigned long flags;
361
Alan Coxebd2c8f2009-09-19 13:13:28 -0700362 if (sport->port.state) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363 spin_lock_irqsave(&sport->port.lock, flags);
364 imx_mctrl_check(sport);
365 spin_unlock_irqrestore(&sport->port.lock, flags);
366
367 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
368 }
369}
370
371/*
372 * interrupts disabled on entry
373 */
Russell Kingb129a8c2005-08-31 10:12:14 +0100374static void imx_stop_tx(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375{
376 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100377 unsigned long temp;
378
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100379 if (USE_IRDA(sport)) {
380 /* half duplex - wait for end of transmission */
381 int n = 256;
382 while ((--n > 0) &&
383 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
384 udelay(5);
385 barrier();
386 }
387 /*
388 * irda transceiver - wait a bit more to avoid
389 * cutoff, hardware dependent
390 */
391 udelay(sport->trcv_delay);
392
393 /*
394 * half duplex - reactivate receive mode,
395 * flush receive pipe echo crap
396 */
397 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
398 temp = readl(sport->port.membase + UCR1);
399 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
400 writel(temp, sport->port.membase + UCR1);
401
402 temp = readl(sport->port.membase + UCR4);
403 temp &= ~(UCR4_TCEN);
404 writel(temp, sport->port.membase + UCR4);
405
406 while (readl(sport->port.membase + URXD0) &
407 URXD_CHARRDY)
408 barrier();
409
410 temp = readl(sport->port.membase + UCR1);
411 temp |= UCR1_RRDYEN;
412 writel(temp, sport->port.membase + UCR1);
413
414 temp = readl(sport->port.membase + UCR4);
415 temp |= UCR4_DREN;
416 writel(temp, sport->port.membase + UCR4);
417 }
418 return;
419 }
420
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -0700421 /*
422 * We are maybe in the SMP context, so if the DMA TX thread is running
423 * on other cpu, we have to wait for it to finish.
424 */
425 if (sport->dma_is_enabled && sport->dma_is_txing)
426 return;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800427
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100428 temp = readl(sport->port.membase + UCR1);
429 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430}
431
432/*
433 * interrupts disabled on entry
434 */
435static void imx_stop_rx(struct uart_port *port)
436{
437 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100438 unsigned long temp;
439
Huang Shijie45564a62014-09-19 15:33:12 +0800440 if (sport->dma_is_enabled && sport->dma_is_rxing) {
441 if (sport->port.suspended) {
442 dmaengine_terminate_all(sport->dma_chan_rx);
443 sport->dma_is_rxing = 0;
444 } else {
445 return;
446 }
447 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800448
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100449 temp = readl(sport->port.membase + UCR2);
Sachin Kamat82313e62013-01-07 10:25:02 +0530450 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
Huang Shijie85878392014-05-23 12:32:54 +0800451
452 /* disable the `Receiver Ready Interrrupt` */
453 temp = readl(sport->port.membase + UCR1);
454 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455}
456
457/*
458 * Set the modem control timer to fire immediately.
459 */
460static void imx_enable_ms(struct uart_port *port)
461{
462 struct imx_port *sport = (struct imx_port *)port;
463
464 mod_timer(&sport->timer, jiffies);
465}
466
467static inline void imx_transmit_buffer(struct imx_port *sport)
468{
Alan Coxebd2c8f2009-09-19 13:13:28 -0700469 struct circ_buf *xmit = &sport->port.state->xmit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470
Peter Hurley5e42e9a2014-09-02 17:39:12 -0400471 if (sport->port.x_char) {
472 /* Send next char */
473 writel(sport->port.x_char, sport->port.membase + URTX0);
474 return;
475 }
476
477 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
478 imx_stop_tx(&sport->port);
479 return;
480 }
481
Volker Ernst4e4e6602010-10-13 11:03:57 +0200482 while (!uart_circ_empty(xmit) &&
Peter Hurley5e42e9a2014-09-02 17:39:12 -0400483 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484 /* send xmit->buf[xmit->tail]
485 * out the port here */
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100486 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100487 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488 sport->port.icount.tx++;
Sascha Hauer8c0b2542007-02-05 16:10:16 -0800489 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490
Fabian Godehardt977757312009-06-11 14:37:19 +0100491 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
492 uart_write_wakeup(&sport->port);
493
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494 if (uart_circ_empty(xmit))
Russell Kingb129a8c2005-08-31 10:12:14 +0100495 imx_stop_tx(&sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496}
497
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800498static void dma_tx_callback(void *data)
499{
500 struct imx_port *sport = data;
501 struct scatterlist *sgl = &sport->tx_sgl[0];
502 struct circ_buf *xmit = &sport->port.state->xmit;
503 unsigned long flags;
504
505 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
506
507 sport->dma_is_txing = 0;
508
509 /* update the stat */
510 spin_lock_irqsave(&sport->port.lock, flags);
511 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
512 sport->port.icount.tx += sport->tx_bytes;
513 spin_unlock_irqrestore(&sport->port.lock, flags);
514
515 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
516
Huang Shijie2ad28e32014-01-22 16:23:37 +0800517 uart_write_wakeup(&sport->port);
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -0700518
519 if (waitqueue_active(&sport->dma_wait)) {
520 wake_up(&sport->dma_wait);
521 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
522 return;
523 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800524}
525
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800526static void imx_dma_tx(struct imx_port *sport)
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800527{
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800528 struct circ_buf *xmit = &sport->port.state->xmit;
529 struct scatterlist *sgl = sport->tx_sgl;
530 struct dma_async_tx_descriptor *desc;
531 struct dma_chan *chan = sport->dma_chan_tx;
532 struct device *dev = sport->port.dev;
533 enum dma_status status;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800534 int ret;
535
Huang Shijief0ef8832013-10-11 18:31:01 +0800536 status = dmaengine_tx_status(chan, (dma_cookie_t)0, NULL);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800537 if (DMA_IN_PROGRESS == status)
538 return;
539
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800540 sport->tx_bytes = uart_circ_chars_pending(xmit);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800541
Dirk Behme7942f852014-12-09 18:11:25 +0900542 if (xmit->tail < xmit->head) {
543 sport->dma_tx_nents = 1;
544 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
545 } else {
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800546 sport->dma_tx_nents = 2;
547 sg_init_table(sgl, 2);
548 sg_set_buf(sgl, xmit->buf + xmit->tail,
549 UART_XMIT_SIZE - xmit->tail);
550 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800551 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800552
553 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
554 if (ret == 0) {
555 dev_err(dev, "DMA mapping error for TX.\n");
556 return;
557 }
558 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
559 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
560 if (!desc) {
561 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
562 return;
563 }
564 desc->callback = dma_tx_callback;
565 desc->callback_param = sport;
566
567 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
568 uart_circ_chars_pending(xmit));
569 /* fire it */
570 sport->dma_is_txing = 1;
571 dmaengine_submit(desc);
572 dma_async_issue_pending(chan);
573 return;
574}
575
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576/*
577 * interrupts disabled on entry
578 */
Russell Kingb129a8c2005-08-31 10:12:14 +0100579static void imx_start_tx(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580{
581 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100582 unsigned long temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100584 if (USE_IRDA(sport)) {
585 /* half duplex in IrDA mode; have to disable receive mode */
586 temp = readl(sport->port.membase + UCR4);
587 temp &= ~(UCR4_DREN);
588 writel(temp, sport->port.membase + UCR4);
589
590 temp = readl(sport->port.membase + UCR1);
591 temp &= ~(UCR1_RRDYEN);
592 writel(temp, sport->port.membase + UCR1);
593 }
Alexander Steinf1f836e2013-05-14 17:06:07 +0200594 /* Clear any pending ORE flag before enabling interrupt */
595 temp = readl(sport->port.membase + USR2);
596 writel(temp | USR2_ORE, sport->port.membase + USR2);
597
598 temp = readl(sport->port.membase + UCR4);
599 temp |= UCR4_OREN;
600 writel(temp, sport->port.membase + UCR4);
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100601
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800602 if (!sport->dma_is_enabled) {
603 temp = readl(sport->port.membase + UCR1);
604 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
605 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100607 if (USE_IRDA(sport)) {
608 temp = readl(sport->port.membase + UCR1);
609 temp |= UCR1_TRDYEN;
610 writel(temp, sport->port.membase + UCR1);
611
612 temp = readl(sport->port.membase + UCR4);
613 temp |= UCR4_TCEN;
614 writel(temp, sport->port.membase + UCR4);
615 }
616
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800617 if (sport->dma_is_enabled) {
Peter Hurley5e42e9a2014-09-02 17:39:12 -0400618 /* FIXME: port->x_char must be transmitted if != 0 */
619 if (!uart_circ_empty(&port->state->xmit) &&
620 !uart_tx_stopped(port))
621 imx_dma_tx(sport);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800622 return;
623 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624}
625
David Howells7d12e782006-10-05 14:55:46 +0100626static irqreturn_t imx_rtsint(int irq, void *dev_id)
Sascha Hauerceca6292005-10-12 19:58:08 +0100627{
Jeff Garzik15aafa22008-02-06 01:36:20 -0800628 struct imx_port *sport = dev_id;
Uwe Kleine-König5680e942011-04-11 10:59:09 +0200629 unsigned int val;
Sascha Hauerceca6292005-10-12 19:58:08 +0100630 unsigned long flags;
631
632 spin_lock_irqsave(&sport->port.lock, flags);
633
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100634 writel(USR1_RTSD, sport->port.membase + USR1);
Uwe Kleine-König5680e942011-04-11 10:59:09 +0200635 val = readl(sport->port.membase + USR1) & USR1_RTSS;
Sascha Hauerceca6292005-10-12 19:58:08 +0100636 uart_handle_cts_change(&sport->port, !!val);
Alan Coxbdc04e32009-09-19 13:13:31 -0700637 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
Sascha Hauerceca6292005-10-12 19:58:08 +0100638
639 spin_unlock_irqrestore(&sport->port.lock, flags);
640 return IRQ_HANDLED;
641}
642
David Howells7d12e782006-10-05 14:55:46 +0100643static irqreturn_t imx_txint(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644{
Jeff Garzik15aafa22008-02-06 01:36:20 -0800645 struct imx_port *sport = dev_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646 unsigned long flags;
647
Sachin Kamat82313e62013-01-07 10:25:02 +0530648 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649 imx_transmit_buffer(sport);
Sachin Kamat82313e62013-01-07 10:25:02 +0530650 spin_unlock_irqrestore(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651 return IRQ_HANDLED;
652}
653
David Howells7d12e782006-10-05 14:55:46 +0100654static irqreturn_t imx_rxint(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655{
656 struct imx_port *sport = dev_id;
Sachin Kamat82313e62013-01-07 10:25:02 +0530657 unsigned int rx, flg, ignored = 0;
Jiri Slaby92a19f92013-01-03 15:53:03 +0100658 struct tty_port *port = &sport->port.state->port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100659 unsigned long flags, temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660
Sachin Kamat82313e62013-01-07 10:25:02 +0530661 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662
Sascha Hauer0d3c3932008-04-17 08:43:14 +0100663 while (readl(sport->port.membase + USR2) & USR2_RDR) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664 flg = TTY_NORMAL;
665 sport->port.icount.rx++;
666
Sascha Hauer0d3c3932008-04-17 08:43:14 +0100667 rx = readl(sport->port.membase + URXD0);
668
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100669 temp = readl(sport->port.membase + USR2);
Sascha Hauer864eeed2008-04-17 08:39:22 +0100670 if (temp & USR2_BRCD) {
Andy Green94d32f92010-02-01 13:28:54 +0100671 writel(USR2_BRCD, sport->port.membase + USR2);
Sascha Hauer864eeed2008-04-17 08:39:22 +0100672 if (uart_handle_break(&sport->port))
673 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700674 }
675
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100676 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
Sascha Hauer864eeed2008-04-17 08:39:22 +0100677 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678
Hui Wang019dc9e2011-08-24 17:41:47 +0800679 if (unlikely(rx & URXD_ERR)) {
680 if (rx & URXD_BRK)
681 sport->port.icount.brk++;
682 else if (rx & URXD_PRERR)
Sascha Hauer864eeed2008-04-17 08:39:22 +0100683 sport->port.icount.parity++;
684 else if (rx & URXD_FRMERR)
685 sport->port.icount.frame++;
686 if (rx & URXD_OVRRUN)
687 sport->port.icount.overrun++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688
Sascha Hauer864eeed2008-04-17 08:39:22 +0100689 if (rx & sport->port.ignore_status_mask) {
690 if (++ignored > 100)
691 goto out;
692 continue;
693 }
694
695 rx &= sport->port.read_status_mask;
696
Hui Wang019dc9e2011-08-24 17:41:47 +0800697 if (rx & URXD_BRK)
698 flg = TTY_BREAK;
699 else if (rx & URXD_PRERR)
Sascha Hauer864eeed2008-04-17 08:39:22 +0100700 flg = TTY_PARITY;
701 else if (rx & URXD_FRMERR)
702 flg = TTY_FRAME;
703 if (rx & URXD_OVRRUN)
704 flg = TTY_OVERRUN;
705
706#ifdef SUPPORT_SYSRQ
707 sport->port.sysrq = 0;
708#endif
709 }
710
Jiada Wang55d86932014-12-09 18:11:22 +0900711 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
712 goto out;
713
Jiri Slaby92a19f92013-01-03 15:53:03 +0100714 tty_insert_flip_char(port, rx, flg);
Sascha Hauer864eeed2008-04-17 08:39:22 +0100715 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716
717out:
Sachin Kamat82313e62013-01-07 10:25:02 +0530718 spin_unlock_irqrestore(&sport->port.lock, flags);
Jiri Slaby2e124b42013-01-03 15:53:06 +0100719 tty_flip_buffer_push(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720 return IRQ_HANDLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721}
722
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800723static int start_rx_dma(struct imx_port *sport);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800724/*
725 * If the RXFIFO is filled with some data, and then we
726 * arise a DMA operation to receive them.
727 */
728static void imx_dma_rxint(struct imx_port *sport)
729{
730 unsigned long temp;
Jiada Wang73631812014-12-09 18:11:23 +0900731 unsigned long flags;
732
733 spin_lock_irqsave(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800734
735 temp = readl(sport->port.membase + USR2);
736 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
737 sport->dma_is_rxing = 1;
738
739 /* disable the `Recerver Ready Interrrupt` */
740 temp = readl(sport->port.membase + UCR1);
741 temp &= ~(UCR1_RRDYEN);
742 writel(temp, sport->port.membase + UCR1);
743
744 /* tell the DMA to receive the data. */
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800745 start_rx_dma(sport);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800746 }
Jiada Wang73631812014-12-09 18:11:23 +0900747
748 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800749}
750
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200751static irqreturn_t imx_int(int irq, void *dev_id)
752{
753 struct imx_port *sport = dev_id;
754 unsigned int sts;
Alexander Steinf1f836e2013-05-14 17:06:07 +0200755 unsigned int sts2;
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200756
757 sts = readl(sport->port.membase + USR1);
758
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800759 if (sts & USR1_RRDY) {
760 if (sport->dma_is_enabled)
761 imx_dma_rxint(sport);
762 else
763 imx_rxint(irq, dev_id);
764 }
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200765
766 if (sts & USR1_TRDY &&
767 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
768 imx_txint(irq, dev_id);
769
Marc Kleine-Budde9fbe6042008-07-28 21:26:01 +0200770 if (sts & USR1_RTSD)
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200771 imx_rtsint(irq, dev_id);
772
Fabio Estevamdb1a9b52011-12-13 01:23:48 -0200773 if (sts & USR1_AWAKE)
774 writel(USR1_AWAKE, sport->port.membase + USR1);
775
Alexander Steinf1f836e2013-05-14 17:06:07 +0200776 sts2 = readl(sport->port.membase + USR2);
777 if (sts2 & USR2_ORE) {
778 dev_err(sport->port.dev, "Rx FIFO overrun\n");
779 sport->port.icount.overrun++;
780 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
781 }
782
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200783 return IRQ_HANDLED;
784}
785
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786/*
787 * Return TIOCSER_TEMT when transmitter is not busy.
788 */
789static unsigned int imx_tx_empty(struct uart_port *port)
790{
791 struct imx_port *sport = (struct imx_port *)port;
Huang Shijie1ce43e52013-10-11 18:30:59 +0800792 unsigned int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793
Huang Shijie1ce43e52013-10-11 18:30:59 +0800794 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
795
796 /* If the TX DMA is working, return 0. */
797 if (sport->dma_is_enabled && sport->dma_is_txing)
798 ret = 0;
799
800 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801}
802
Sascha Hauer0f302dc2005-08-31 21:48:47 +0100803/*
804 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
805 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700806static unsigned int imx_get_mctrl(struct uart_port *port)
807{
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100808 struct imx_port *sport = (struct imx_port *)port;
809 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
Sascha Hauer0f302dc2005-08-31 21:48:47 +0100810
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100811 if (readl(sport->port.membase + USR1) & USR1_RTSS)
812 tmp |= TIOCM_CTS;
Sascha Hauer0f302dc2005-08-31 21:48:47 +0100813
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100814 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
815 tmp |= TIOCM_RTS;
Sascha Hauer0f302dc2005-08-31 21:48:47 +0100816
Huang Shijie6b471a92013-11-29 17:29:24 +0800817 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
818 tmp |= TIOCM_LOOP;
819
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100820 return tmp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700821}
822
823static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
824{
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100825 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100826 unsigned long temp;
827
Fugang Duanbb2f8612014-09-19 15:26:40 +0800828 temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC);
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100829 if (mctrl & TIOCM_RTS)
Fugang Duanbb2f8612014-09-19 15:26:40 +0800830 temp |= UCR2_CTS | UCR2_CTSC;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100831
832 writel(temp, sport->port.membase + UCR2);
Huang Shijie6b471a92013-11-29 17:29:24 +0800833
834 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
835 if (mctrl & TIOCM_LOOP)
836 temp |= UTS_LOOP;
837 writel(temp, sport->port.membase + uts_reg(sport));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838}
839
840/*
841 * Interrupts always disabled.
842 */
843static void imx_break_ctl(struct uart_port *port, int break_state)
844{
845 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100846 unsigned long flags, temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847
848 spin_lock_irqsave(&sport->port.lock, flags);
849
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100850 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
851
Sachin Kamat82313e62013-01-07 10:25:02 +0530852 if (break_state != 0)
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100853 temp |= UCR1_SNDBRK;
854
855 writel(temp, sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856
857 spin_unlock_irqrestore(&sport->port.lock, flags);
858}
859
860#define TXTL 2 /* reset default */
861#define RXTL 1 /* reset default */
862
Sascha Hauer587897f2005-04-29 22:46:40 +0100863static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
864{
865 unsigned int val;
Sascha Hauer587897f2005-04-29 22:46:40 +0100866
Dirk Behme7be06702012-08-31 10:02:47 +0200867 /* set receiver / transmitter trigger level */
868 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
869 val |= TXTL << UFCR_TXTL_SHF | RXTL;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100870 writel(val, sport->port.membase + UFCR);
Sascha Hauer587897f2005-04-29 22:46:40 +0100871 return 0;
872}
873
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800874#define RX_BUF_SIZE (PAGE_SIZE)
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800875static void imx_rx_dma_done(struct imx_port *sport)
876{
877 unsigned long temp;
Jiada Wang73631812014-12-09 18:11:23 +0900878 unsigned long flags;
879
880 spin_lock_irqsave(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800881
882 /* Enable this interrupt when the RXFIFO is empty. */
883 temp = readl(sport->port.membase + UCR1);
884 temp |= UCR1_RRDYEN;
885 writel(temp, sport->port.membase + UCR1);
886
887 sport->dma_is_rxing = 0;
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -0700888
889 /* Is the shutdown waiting for us? */
890 if (waitqueue_active(&sport->dma_wait))
891 wake_up(&sport->dma_wait);
Jiada Wang73631812014-12-09 18:11:23 +0900892
893 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800894}
895
896/*
897 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
898 * [1] the RX DMA buffer is full.
899 * [2] the Aging timer expires(wait for 8 bytes long)
900 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
901 *
902 * The [2] is trigger when a character was been sitting in the FIFO
903 * meanwhile [3] can wait for 32 bytes long when the RX line is
904 * on IDLE state and RxFIFO is empty.
905 */
906static void dma_rx_callback(void *data)
907{
908 struct imx_port *sport = data;
909 struct dma_chan *chan = sport->dma_chan_rx;
910 struct scatterlist *sgl = &sport->rx_sgl;
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800911 struct tty_port *port = &sport->port.state->port;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800912 struct dma_tx_state state;
913 enum dma_status status;
914 unsigned int count;
915
916 /* unmap it first */
917 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
918
Huang Shijief0ef8832013-10-11 18:31:01 +0800919 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800920 count = RX_BUF_SIZE - state.residue;
921 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
922
923 if (count) {
Jiada Wang55d86932014-12-09 18:11:22 +0900924 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ))
925 tty_insert_flip_string(port, sport->rx_buf, count);
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800926 tty_flip_buffer_push(port);
927
928 start_rx_dma(sport);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800929 } else
930 imx_rx_dma_done(sport);
931}
932
933static int start_rx_dma(struct imx_port *sport)
934{
935 struct scatterlist *sgl = &sport->rx_sgl;
936 struct dma_chan *chan = sport->dma_chan_rx;
937 struct device *dev = sport->port.dev;
938 struct dma_async_tx_descriptor *desc;
939 int ret;
940
941 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
942 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
943 if (ret == 0) {
944 dev_err(dev, "DMA mapping error for RX.\n");
945 return -EINVAL;
946 }
947 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
948 DMA_PREP_INTERRUPT);
949 if (!desc) {
950 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
951 return -EINVAL;
952 }
953 desc->callback = dma_rx_callback;
954 desc->callback_param = sport;
955
956 dev_dbg(dev, "RX: prepare for the DMA.\n");
957 dmaengine_submit(desc);
958 dma_async_issue_pending(chan);
959 return 0;
960}
961
962static void imx_uart_dma_exit(struct imx_port *sport)
963{
964 if (sport->dma_chan_rx) {
965 dma_release_channel(sport->dma_chan_rx);
966 sport->dma_chan_rx = NULL;
967
968 kfree(sport->rx_buf);
969 sport->rx_buf = NULL;
970 }
971
972 if (sport->dma_chan_tx) {
973 dma_release_channel(sport->dma_chan_tx);
974 sport->dma_chan_tx = NULL;
975 }
976
977 sport->dma_is_inited = 0;
978}
979
980static int imx_uart_dma_init(struct imx_port *sport)
981{
Huang Shijieb09c74a2013-08-29 16:29:25 +0800982 struct dma_slave_config slave_config = {};
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800983 struct device *dev = sport->port.dev;
984 int ret;
985
986 /* Prepare for RX : */
987 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
988 if (!sport->dma_chan_rx) {
989 dev_dbg(dev, "cannot get the DMA channel.\n");
990 ret = -EINVAL;
991 goto err;
992 }
993
994 slave_config.direction = DMA_DEV_TO_MEM;
995 slave_config.src_addr = sport->port.mapbase + URXD0;
996 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
997 slave_config.src_maxburst = RXTL;
998 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
999 if (ret) {
1000 dev_err(dev, "error in RX dma configuration.\n");
1001 goto err;
1002 }
1003
1004 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1005 if (!sport->rx_buf) {
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001006 ret = -ENOMEM;
1007 goto err;
1008 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001009
1010 /* Prepare for TX : */
1011 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1012 if (!sport->dma_chan_tx) {
1013 dev_err(dev, "cannot get the TX DMA channel!\n");
1014 ret = -EINVAL;
1015 goto err;
1016 }
1017
1018 slave_config.direction = DMA_MEM_TO_DEV;
1019 slave_config.dst_addr = sport->port.mapbase + URTX0;
1020 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1021 slave_config.dst_maxburst = TXTL;
1022 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1023 if (ret) {
1024 dev_err(dev, "error in TX dma configuration.");
1025 goto err;
1026 }
1027
1028 sport->dma_is_inited = 1;
1029
1030 return 0;
1031err:
1032 imx_uart_dma_exit(sport);
1033 return ret;
1034}
1035
1036static void imx_enable_dma(struct imx_port *sport)
1037{
1038 unsigned long temp;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001039
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -07001040 init_waitqueue_head(&sport->dma_wait);
1041
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001042 /* set UCR1 */
1043 temp = readl(sport->port.membase + UCR1);
1044 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1045 /* wait for 32 idle frames for IDDMA interrupt */
1046 UCR1_ICD_REG(3);
1047 writel(temp, sport->port.membase + UCR1);
1048
1049 /* set UCR4 */
1050 temp = readl(sport->port.membase + UCR4);
1051 temp |= UCR4_IDDMAEN;
1052 writel(temp, sport->port.membase + UCR4);
1053
1054 sport->dma_is_enabled = 1;
1055}
1056
1057static void imx_disable_dma(struct imx_port *sport)
1058{
1059 unsigned long temp;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001060
1061 /* clear UCR1 */
1062 temp = readl(sport->port.membase + UCR1);
1063 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1064 writel(temp, sport->port.membase + UCR1);
1065
1066 /* clear UCR2 */
1067 temp = readl(sport->port.membase + UCR2);
1068 temp &= ~(UCR2_CTSC | UCR2_CTS);
1069 writel(temp, sport->port.membase + UCR2);
1070
1071 /* clear UCR4 */
1072 temp = readl(sport->port.membase + UCR4);
1073 temp &= ~UCR4_IDDMAEN;
1074 writel(temp, sport->port.membase + UCR4);
1075
1076 sport->dma_is_enabled = 0;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001077}
1078
Valentin Longchamp1c5250d2010-05-05 11:47:07 +02001079/* half the RX buffer size */
1080#define CTSTL 16
1081
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082static int imx_startup(struct uart_port *port)
1083{
1084 struct imx_port *sport = (struct imx_port *)port;
Huang Shijie772f8992014-05-21 08:56:28 +08001085 int retval, i;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001086 unsigned long flags, temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087
Huang Shijie1cf93e02013-06-28 13:39:42 +08001088 retval = clk_prepare_enable(sport->clk_per);
1089 if (retval)
Fabio Estevamcb0f0a52014-10-27 14:49:38 -02001090 return retval;
Huang Shijie1cf93e02013-06-28 13:39:42 +08001091 retval = clk_prepare_enable(sport->clk_ipg);
1092 if (retval) {
1093 clk_disable_unprepare(sport->clk_per);
Fabio Estevamcb0f0a52014-10-27 14:49:38 -02001094 return retval;
Huang Shijie0c375502013-06-09 10:01:19 +08001095 }
Huang Shijie28eb4272013-06-04 09:59:33 +08001096
Sascha Hauer587897f2005-04-29 22:46:40 +01001097 imx_setup_ufcr(sport, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098
1099 /* disable the DREN bit (Data Ready interrupt enable) before
1100 * requesting IRQs
1101 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001102 temp = readl(sport->port.membase + UCR4);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001103
1104 if (USE_IRDA(sport))
1105 temp |= UCR4_IRSC;
1106
Valentin Longchamp1c5250d2010-05-05 11:47:07 +02001107 /* set the trigger level for CTS */
Sachin Kamat82313e62013-01-07 10:25:02 +05301108 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1109 temp |= CTSTL << UCR4_CTSTL_SHF;
Valentin Longchamp1c5250d2010-05-05 11:47:07 +02001110
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001111 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001112
Huang Shijie772f8992014-05-21 08:56:28 +08001113 /* Reset fifo's and state machines */
1114 i = 100;
1115
1116 temp = readl(sport->port.membase + UCR2);
1117 temp &= ~UCR2_SRST;
1118 writel(temp, sport->port.membase + UCR2);
1119
1120 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1121 udelay(1);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001122
Xinyu Chen9ec18822012-08-27 09:36:51 +02001123 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124 /*
1125 * Finally, clear and enable interrupts
1126 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001127 writel(USR1_RTSD, sport->port.membase + USR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001128
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001129 temp = readl(sport->port.membase + UCR1);
Sascha Hauer789d5252008-04-17 08:44:47 +01001130 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001131
1132 if (USE_IRDA(sport)) {
1133 temp |= UCR1_IREN;
1134 temp &= ~(UCR1_RTSDEN);
1135 }
1136
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001137 writel(temp, sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001138
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001139 temp = readl(sport->port.membase + UCR2);
1140 temp |= (UCR2_RXEN | UCR2_TXEN);
Lucas Stachbff09b02013-05-30 15:47:04 +02001141 if (!sport->have_rtscts)
1142 temp |= UCR2_IRTS;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001143 writel(temp, sport->port.membase + UCR2);
1144
Huang Shijiea496e622013-07-08 17:14:17 +08001145 if (!is_imx1_uart(sport)) {
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001146 temp = readl(sport->port.membase + UCR3);
Fabio Estevamb38cb7d2014-05-14 15:55:03 -03001147 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001148 writel(temp, sport->port.membase + UCR3);
1149 }
Marc Kleine-Budde44118052008-07-28 12:10:34 +02001150
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001151 if (USE_IRDA(sport)) {
1152 temp = readl(sport->port.membase + UCR4);
1153 if (sport->irda_inv_rx)
1154 temp |= UCR4_INVR;
1155 else
1156 temp &= ~(UCR4_INVR);
1157 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1158
1159 temp = readl(sport->port.membase + UCR3);
1160 if (sport->irda_inv_tx)
1161 temp |= UCR3_INVT;
1162 else
1163 temp &= ~(UCR3_INVT);
1164 writel(temp, sport->port.membase + UCR3);
1165 }
1166
Linus Torvalds1da177e2005-04-16 15:20:36 -07001167 /*
1168 * Enable modem status interrupts
1169 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001170 imx_enable_ms(&sport->port);
Sachin Kamat82313e62013-01-07 10:25:02 +05301171 spin_unlock_irqrestore(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001172
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001173 if (USE_IRDA(sport)) {
1174 struct imxuart_platform_data *pdata;
Jingoo Han574de552013-07-30 17:06:57 +09001175 pdata = dev_get_platdata(sport->port.dev);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001176 sport->irda_inv_rx = pdata->irda_inv_rx;
1177 sport->irda_inv_tx = pdata->irda_inv_tx;
1178 sport->trcv_delay = pdata->transceiver_delay;
1179 if (pdata->irda_enable)
1180 pdata->irda_enable(1);
1181 }
1182
Linus Torvalds1da177e2005-04-16 15:20:36 -07001183 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001184}
1185
1186static void imx_shutdown(struct uart_port *port)
1187{
1188 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001189 unsigned long temp;
Xinyu Chen9ec18822012-08-27 09:36:51 +02001190 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001191
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001192 if (sport->dma_is_enabled) {
Huang Shijiea4688bc2014-09-19 15:42:57 +08001193 int ret;
1194
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -07001195 /* We have to wait for the DMA to finish. */
Huang Shijiea4688bc2014-09-19 15:42:57 +08001196 ret = wait_event_interruptible(sport->dma_wait,
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -07001197 !sport->dma_is_rxing && !sport->dma_is_txing);
Huang Shijiea4688bc2014-09-19 15:42:57 +08001198 if (ret != 0) {
1199 sport->dma_is_rxing = 0;
1200 sport->dma_is_txing = 0;
1201 dmaengine_terminate_all(sport->dma_chan_tx);
1202 dmaengine_terminate_all(sport->dma_chan_rx);
1203 }
Jiada Wang73631812014-12-09 18:11:23 +09001204 spin_lock_irqsave(&sport->port.lock, flags);
Huang Shijiea4688bc2014-09-19 15:42:57 +08001205 imx_stop_tx(port);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001206 imx_stop_rx(port);
1207 imx_disable_dma(sport);
Jiada Wang73631812014-12-09 18:11:23 +09001208 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001209 imx_uart_dma_exit(sport);
1210 }
1211
Xinyu Chen9ec18822012-08-27 09:36:51 +02001212 spin_lock_irqsave(&sport->port.lock, flags);
Fabian Godehardt2e146392009-06-11 14:38:38 +01001213 temp = readl(sport->port.membase + UCR2);
1214 temp &= ~(UCR2_TXEN);
1215 writel(temp, sport->port.membase + UCR2);
Xinyu Chen9ec18822012-08-27 09:36:51 +02001216 spin_unlock_irqrestore(&sport->port.lock, flags);
Fabian Godehardt2e146392009-06-11 14:38:38 +01001217
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001218 if (USE_IRDA(sport)) {
1219 struct imxuart_platform_data *pdata;
Jingoo Han574de552013-07-30 17:06:57 +09001220 pdata = dev_get_platdata(sport->port.dev);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001221 if (pdata->irda_enable)
1222 pdata->irda_enable(0);
1223 }
1224
Linus Torvalds1da177e2005-04-16 15:20:36 -07001225 /*
1226 * Stop our timer.
1227 */
1228 del_timer_sync(&sport->timer);
1229
1230 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001231 * Disable all interrupts, port and break condition.
1232 */
1233
Xinyu Chen9ec18822012-08-27 09:36:51 +02001234 spin_lock_irqsave(&sport->port.lock, flags);
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001235 temp = readl(sport->port.membase + UCR1);
1236 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001237 if (USE_IRDA(sport))
1238 temp &= ~(UCR1_IREN);
1239
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001240 writel(temp, sport->port.membase + UCR1);
Xinyu Chen9ec18822012-08-27 09:36:51 +02001241 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijie28eb4272013-06-04 09:59:33 +08001242
Huang Shijie1cf93e02013-06-28 13:39:42 +08001243 clk_disable_unprepare(sport->clk_per);
1244 clk_disable_unprepare(sport->clk_ipg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245}
1246
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001247static void imx_flush_buffer(struct uart_port *port)
1248{
1249 struct imx_port *sport = (struct imx_port *)port;
1250
1251 if (sport->dma_is_enabled) {
1252 sport->tx_bytes = 0;
1253 dmaengine_terminate_all(sport->dma_chan_tx);
1254 }
1255}
1256
Linus Torvalds1da177e2005-04-16 15:20:36 -07001257static void
Alan Cox606d0992006-12-08 02:38:45 -08001258imx_set_termios(struct uart_port *port, struct ktermios *termios,
1259 struct ktermios *old)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001260{
1261 struct imx_port *sport = (struct imx_port *)port;
1262 unsigned long flags;
1263 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1264 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
Oskar Schirmer534fca02009-06-11 14:52:23 +01001265 unsigned int div, ufcr;
1266 unsigned long num, denom;
Oskar Schirmerd7f8d432009-06-11 14:55:22 +01001267 uint64_t tdiv64;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001268
1269 /*
1270 * If we don't support modem control lines, don't allow
1271 * these to be set.
1272 */
1273 if (0) {
1274 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1275 termios->c_cflag |= CLOCAL;
1276 }
1277
1278 /*
1279 * We only support CS7 and CS8.
1280 */
1281 while ((termios->c_cflag & CSIZE) != CS7 &&
1282 (termios->c_cflag & CSIZE) != CS8) {
1283 termios->c_cflag &= ~CSIZE;
1284 termios->c_cflag |= old_csize;
1285 old_csize = CS8;
1286 }
1287
1288 if ((termios->c_cflag & CSIZE) == CS8)
1289 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1290 else
1291 ucr2 = UCR2_SRST | UCR2_IRTS;
1292
1293 if (termios->c_cflag & CRTSCTS) {
Sachin Kamat82313e62013-01-07 10:25:02 +05301294 if (sport->have_rtscts) {
Sascha Hauer5b802342006-05-04 14:07:42 +01001295 ucr2 &= ~UCR2_IRTS;
1296 ucr2 |= UCR2_CTSC;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001297
1298 /* Can we enable the DMA support? */
1299 if (is_imx6q_uart(sport) && !uart_console(port)
1300 && !sport->dma_is_inited)
1301 imx_uart_dma_init(sport);
Sascha Hauer5b802342006-05-04 14:07:42 +01001302 } else {
1303 termios->c_cflag &= ~CRTSCTS;
1304 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001305 }
1306
1307 if (termios->c_cflag & CSTOPB)
1308 ucr2 |= UCR2_STPB;
1309 if (termios->c_cflag & PARENB) {
1310 ucr2 |= UCR2_PREN;
Matt Reimer3261e362006-01-13 20:51:44 +00001311 if (termios->c_cflag & PARODD)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001312 ucr2 |= UCR2_PROE;
1313 }
1314
Eric Miao995234d2011-12-23 05:39:27 +08001315 del_timer_sync(&sport->timer);
1316
Linus Torvalds1da177e2005-04-16 15:20:36 -07001317 /*
1318 * Ask the core to calculate the divisor for us.
1319 */
Sascha Hauer036bb152008-07-05 10:02:44 +02001320 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001321 quot = uart_get_divisor(port, baud);
1322
1323 spin_lock_irqsave(&sport->port.lock, flags);
1324
1325 sport->port.read_status_mask = 0;
1326 if (termios->c_iflag & INPCK)
1327 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1328 if (termios->c_iflag & (BRKINT | PARMRK))
1329 sport->port.read_status_mask |= URXD_BRK;
1330
1331 /*
1332 * Characters to ignore
1333 */
1334 sport->port.ignore_status_mask = 0;
1335 if (termios->c_iflag & IGNPAR)
1336 sport->port.ignore_status_mask |= URXD_PRERR;
1337 if (termios->c_iflag & IGNBRK) {
1338 sport->port.ignore_status_mask |= URXD_BRK;
1339 /*
1340 * If we're ignoring parity and break indicators,
1341 * ignore overruns too (for real raw support).
1342 */
1343 if (termios->c_iflag & IGNPAR)
1344 sport->port.ignore_status_mask |= URXD_OVRRUN;
1345 }
1346
Jiada Wang55d86932014-12-09 18:11:22 +09001347 if ((termios->c_cflag & CREAD) == 0)
1348 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1349
Linus Torvalds1da177e2005-04-16 15:20:36 -07001350 /*
1351 * Update the per-port timeout.
1352 */
1353 uart_update_timeout(port, termios->c_cflag, baud);
1354
1355 /*
1356 * disable interrupts and drain transmitter
1357 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001358 old_ucr1 = readl(sport->port.membase + UCR1);
1359 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1360 sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001361
Sachin Kamat82313e62013-01-07 10:25:02 +05301362 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001363 barrier();
1364
1365 /* then, disable everything */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001366 old_txrxen = readl(sport->port.membase + UCR2);
Sachin Kamat82313e62013-01-07 10:25:02 +05301367 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001368 sport->port.membase + UCR2);
1369 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001371 if (USE_IRDA(sport)) {
1372 /*
1373 * use maximum available submodule frequency to
1374 * avoid missing short pulses due to low sampling rate
1375 */
Sascha Hauer036bb152008-07-05 10:02:44 +02001376 div = 1;
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001377 } else {
Hubert Feurstein09bd00f2013-07-18 18:52:49 +02001378 /* custom-baudrate handling */
1379 div = sport->port.uartclk / (baud * 16);
1380 if (baud == 38400 && quot != div)
1381 baud = sport->port.uartclk / (quot * 16);
1382
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001383 div = sport->port.uartclk / (baud * 16);
1384 if (div > 7)
1385 div = 7;
1386 if (!div)
1387 div = 1;
1388 }
Sascha Hauer036bb152008-07-05 10:02:44 +02001389
Oskar Schirmer534fca02009-06-11 14:52:23 +01001390 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1391 1 << 16, 1 << 16, &num, &denom);
Sascha Hauer036bb152008-07-05 10:02:44 +02001392
Alan Coxeab4f5a2010-06-01 22:52:52 +02001393 tdiv64 = sport->port.uartclk;
1394 tdiv64 *= num;
1395 do_div(tdiv64, denom * 16 * div);
1396 tty_termios_encode_baud_rate(termios,
Sascha Hauer1a2c4b32009-06-16 17:02:15 +01001397 (speed_t)tdiv64, (speed_t)tdiv64);
Oskar Schirmerd7f8d432009-06-11 14:55:22 +01001398
Oskar Schirmer534fca02009-06-11 14:52:23 +01001399 num -= 1;
1400 denom -= 1;
Sascha Hauer036bb152008-07-05 10:02:44 +02001401
1402 ufcr = readl(sport->port.membase + UFCR);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001403 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
Huang Shijie20ff2fe2013-05-30 14:07:12 +08001404 if (sport->dte_mode)
1405 ufcr |= UFCR_DCEDTE;
Sascha Hauer036bb152008-07-05 10:02:44 +02001406 writel(ufcr, sport->port.membase + UFCR);
1407
Oskar Schirmer534fca02009-06-11 14:52:23 +01001408 writel(num, sport->port.membase + UBIR);
1409 writel(denom, sport->port.membase + UBMR);
1410
Huang Shijiea496e622013-07-08 17:14:17 +08001411 if (!is_imx1_uart(sport))
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001412 writel(sport->port.uartclk / div / 1000,
Shawn Guofe6b5402011-06-25 02:04:33 +08001413 sport->port.membase + IMX21_ONEMS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001414
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001415 writel(old_ucr1, sport->port.membase + UCR1);
1416
1417 /* set the parity, stop bits and data size */
1418 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001419
1420 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1421 imx_enable_ms(&sport->port);
1422
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001423 if (sport->dma_is_inited && !sport->dma_is_enabled)
1424 imx_enable_dma(sport);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001425 spin_unlock_irqrestore(&sport->port.lock, flags);
1426}
1427
1428static const char *imx_type(struct uart_port *port)
1429{
1430 struct imx_port *sport = (struct imx_port *)port;
1431
1432 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1433}
1434
1435/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001436 * Configure/autoconfigure the port.
1437 */
1438static void imx_config_port(struct uart_port *port, int flags)
1439{
1440 struct imx_port *sport = (struct imx_port *)port;
1441
Alexander Shiyanda82f992014-02-22 16:01:33 +04001442 if (flags & UART_CONFIG_TYPE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001443 sport->port.type = PORT_IMX;
1444}
1445
1446/*
1447 * Verify the new serial_struct (for TIOCSSERIAL).
1448 * The only change we allow are to the flags and type, and
1449 * even then only between PORT_IMX and PORT_UNKNOWN
1450 */
1451static int
1452imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1453{
1454 struct imx_port *sport = (struct imx_port *)port;
1455 int ret = 0;
1456
1457 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1458 ret = -EINVAL;
1459 if (sport->port.irq != ser->irq)
1460 ret = -EINVAL;
1461 if (ser->io_type != UPIO_MEM)
1462 ret = -EINVAL;
1463 if (sport->port.uartclk / 16 != ser->baud_base)
1464 ret = -EINVAL;
Olof Johanssona50c44c2013-09-11 21:27:53 -07001465 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466 ret = -EINVAL;
1467 if (sport->port.iobase != ser->port)
1468 ret = -EINVAL;
1469 if (ser->hub6 != 0)
1470 ret = -EINVAL;
1471 return ret;
1472}
1473
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001474#if defined(CONFIG_CONSOLE_POLL)
Daniel Thompson6b8bdad2014-10-28 09:28:08 +01001475
1476static int imx_poll_init(struct uart_port *port)
1477{
1478 struct imx_port *sport = (struct imx_port *)port;
1479 unsigned long flags;
1480 unsigned long temp;
1481 int retval;
1482
1483 retval = clk_prepare_enable(sport->clk_ipg);
1484 if (retval)
1485 return retval;
1486 retval = clk_prepare_enable(sport->clk_per);
1487 if (retval)
1488 clk_disable_unprepare(sport->clk_ipg);
1489
1490 imx_setup_ufcr(sport, 0);
1491
1492 spin_lock_irqsave(&sport->port.lock, flags);
1493
1494 temp = readl(sport->port.membase + UCR1);
1495 if (is_imx1_uart(sport))
1496 temp |= IMX1_UCR1_UARTCLKEN;
1497 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1498 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1499 writel(temp, sport->port.membase + UCR1);
1500
1501 temp = readl(sport->port.membase + UCR2);
1502 temp |= UCR2_RXEN;
1503 writel(temp, sport->port.membase + UCR2);
1504
1505 spin_unlock_irqrestore(&sport->port.lock, flags);
1506
1507 return 0;
1508}
1509
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001510static int imx_poll_get_char(struct uart_port *port)
1511{
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001512 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
Dirk Behme26c47412014-09-03 12:33:53 +01001513 return NO_POLL_CHAR;
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001514
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001515 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001516}
1517
1518static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1519{
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001520 unsigned int status;
1521
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001522 /* drain */
1523 do {
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001524 status = readl_relaxed(port->membase + USR1);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001525 } while (~status & USR1_TRDY);
1526
1527 /* write */
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001528 writel_relaxed(c, port->membase + URTX0);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001529
1530 /* flush */
1531 do {
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001532 status = readl_relaxed(port->membase + USR2);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001533 } while (~status & USR2_TXDC);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001534}
1535#endif
1536
Linus Torvalds1da177e2005-04-16 15:20:36 -07001537static struct uart_ops imx_pops = {
1538 .tx_empty = imx_tx_empty,
1539 .set_mctrl = imx_set_mctrl,
1540 .get_mctrl = imx_get_mctrl,
1541 .stop_tx = imx_stop_tx,
1542 .start_tx = imx_start_tx,
1543 .stop_rx = imx_stop_rx,
1544 .enable_ms = imx_enable_ms,
1545 .break_ctl = imx_break_ctl,
1546 .startup = imx_startup,
1547 .shutdown = imx_shutdown,
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001548 .flush_buffer = imx_flush_buffer,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001549 .set_termios = imx_set_termios,
1550 .type = imx_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551 .config_port = imx_config_port,
1552 .verify_port = imx_verify_port,
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001553#if defined(CONFIG_CONSOLE_POLL)
Daniel Thompson6b8bdad2014-10-28 09:28:08 +01001554 .poll_init = imx_poll_init,
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001555 .poll_get_char = imx_poll_get_char,
1556 .poll_put_char = imx_poll_put_char,
1557#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001558};
1559
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001560static struct imx_port *imx_ports[UART_NR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001561
1562#ifdef CONFIG_SERIAL_IMX_CONSOLE
Russell Kingd3587882006-03-20 20:00:09 +00001563static void imx_console_putchar(struct uart_port *port, int ch)
1564{
1565 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001566
Shawn Guofe6b5402011-06-25 02:04:33 +08001567 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
Russell Kingd3587882006-03-20 20:00:09 +00001568 barrier();
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001569
1570 writel(ch, sport->port.membase + URTX0);
Russell Kingd3587882006-03-20 20:00:09 +00001571}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001572
1573/*
1574 * Interrupts are disabled on entering
1575 */
1576static void
1577imx_console_write(struct console *co, const char *s, unsigned int count)
1578{
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001579 struct imx_port *sport = imx_ports[co->index];
Dirk Behme0ad5a812011-12-22 09:57:52 +01001580 struct imx_port_ucrs old_ucr;
1581 unsigned int ucr1;
Shawn Guof30e8262013-02-18 13:15:36 +08001582 unsigned long flags = 0;
Thomas Gleixner677fe552013-02-14 21:01:06 +01001583 int locked = 1;
Huang Shijie1cf93e02013-06-28 13:39:42 +08001584 int retval;
1585
1586 retval = clk_enable(sport->clk_per);
1587 if (retval)
1588 return;
1589 retval = clk_enable(sport->clk_ipg);
1590 if (retval) {
1591 clk_disable(sport->clk_per);
1592 return;
1593 }
Xinyu Chen9ec18822012-08-27 09:36:51 +02001594
Thomas Gleixner677fe552013-02-14 21:01:06 +01001595 if (sport->port.sysrq)
1596 locked = 0;
1597 else if (oops_in_progress)
1598 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1599 else
1600 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001601
1602 /*
Dirk Behme0ad5a812011-12-22 09:57:52 +01001603 * First, save UCR1/2/3 and then disable interrupts
Linus Torvalds1da177e2005-04-16 15:20:36 -07001604 */
Dirk Behme0ad5a812011-12-22 09:57:52 +01001605 imx_port_ucrs_save(&sport->port, &old_ucr);
1606 ucr1 = old_ucr.ucr1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001607
Shawn Guofe6b5402011-06-25 02:04:33 +08001608 if (is_imx1_uart(sport))
1609 ucr1 |= IMX1_UCR1_UARTCLKEN;
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001610 ucr1 |= UCR1_UARTEN;
1611 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1612
1613 writel(ucr1, sport->port.membase + UCR1);
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001614
Dirk Behme0ad5a812011-12-22 09:57:52 +01001615 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001616
Russell Kingd3587882006-03-20 20:00:09 +00001617 uart_console_write(&sport->port, s, count, imx_console_putchar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001618
1619 /*
1620 * Finally, wait for transmitter to become empty
Dirk Behme0ad5a812011-12-22 09:57:52 +01001621 * and restore UCR1/2/3
Linus Torvalds1da177e2005-04-16 15:20:36 -07001622 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001623 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001624
Dirk Behme0ad5a812011-12-22 09:57:52 +01001625 imx_port_ucrs_restore(&sport->port, &old_ucr);
Xinyu Chen9ec18822012-08-27 09:36:51 +02001626
Thomas Gleixner677fe552013-02-14 21:01:06 +01001627 if (locked)
1628 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijie1cf93e02013-06-28 13:39:42 +08001629
1630 clk_disable(sport->clk_ipg);
1631 clk_disable(sport->clk_per);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001632}
1633
1634/*
1635 * If the port was already initialised (eg, by a boot loader),
1636 * try to determine the current setup.
1637 */
1638static void __init
1639imx_console_get_options(struct imx_port *sport, int *baud,
1640 int *parity, int *bits)
1641{
Sascha Hauer587897f2005-04-29 22:46:40 +01001642
Roel Kluin2e2eb502009-12-09 12:31:36 -08001643 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001644 /* ok, the port was enabled */
Sachin Kamat82313e62013-01-07 10:25:02 +05301645 unsigned int ucr2, ubir, ubmr, uartclk;
Sascha Hauer587897f2005-04-29 22:46:40 +01001646 unsigned int baud_raw;
1647 unsigned int ucfr_rfdiv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001648
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001649 ucr2 = readl(sport->port.membase + UCR2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001650
1651 *parity = 'n';
1652 if (ucr2 & UCR2_PREN) {
1653 if (ucr2 & UCR2_PROE)
1654 *parity = 'o';
1655 else
1656 *parity = 'e';
1657 }
1658
1659 if (ucr2 & UCR2_WS)
1660 *bits = 8;
1661 else
1662 *bits = 7;
1663
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001664 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1665 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001666
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001667 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
Sascha Hauer587897f2005-04-29 22:46:40 +01001668 if (ucfr_rfdiv == 6)
1669 ucfr_rfdiv = 7;
1670 else
1671 ucfr_rfdiv = 6 - ucfr_rfdiv;
1672
Sascha Hauer3a9465f2012-03-07 09:31:43 +01001673 uartclk = clk_get_rate(sport->clk_per);
Sascha Hauer587897f2005-04-29 22:46:40 +01001674 uartclk /= ucfr_rfdiv;
1675
1676 { /*
1677 * The next code provides exact computation of
1678 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1679 * without need of float support or long long division,
1680 * which would be required to prevent 32bit arithmetic overflow
1681 */
1682 unsigned int mul = ubir + 1;
1683 unsigned int div = 16 * (ubmr + 1);
1684 unsigned int rem = uartclk % div;
1685
1686 baud_raw = (uartclk / div) * mul;
1687 baud_raw += (rem * mul + div / 2) / div;
1688 *baud = (baud_raw + 50) / 100 * 100;
1689 }
1690
Sachin Kamat82313e62013-01-07 10:25:02 +05301691 if (*baud != baud_raw)
Sachin Kamat50bbdba2013-01-07 10:25:05 +05301692 pr_info("Console IMX rounded baud rate from %d to %d\n",
Sascha Hauer587897f2005-04-29 22:46:40 +01001693 baud_raw, *baud);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001694 }
1695}
1696
1697static int __init
1698imx_console_setup(struct console *co, char *options)
1699{
1700 struct imx_port *sport;
1701 int baud = 9600;
1702 int bits = 8;
1703 int parity = 'n';
1704 int flow = 'n';
Huang Shijie1cf93e02013-06-28 13:39:42 +08001705 int retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001706
1707 /*
1708 * Check whether an invalid uart number has been specified, and
1709 * if so, search for the first available port that does have
1710 * console support.
1711 */
1712 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1713 co->index = 0;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001714 sport = imx_ports[co->index];
Sachin Kamat82313e62013-01-07 10:25:02 +05301715 if (sport == NULL)
Eric Lammertse76afc42009-05-19 20:53:20 -04001716 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001717
Huang Shijie1cf93e02013-06-28 13:39:42 +08001718 /* For setting the registers, we only need to enable the ipg clock. */
1719 retval = clk_prepare_enable(sport->clk_ipg);
1720 if (retval)
1721 goto error_console;
1722
Linus Torvalds1da177e2005-04-16 15:20:36 -07001723 if (options)
1724 uart_parse_options(options, &baud, &parity, &bits, &flow);
1725 else
1726 imx_console_get_options(sport, &baud, &parity, &bits);
1727
Sascha Hauer587897f2005-04-29 22:46:40 +01001728 imx_setup_ufcr(sport, 0);
1729
Huang Shijie1cf93e02013-06-28 13:39:42 +08001730 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1731
1732 clk_disable(sport->clk_ipg);
1733 if (retval) {
1734 clk_unprepare(sport->clk_ipg);
1735 goto error_console;
1736 }
1737
1738 retval = clk_prepare(sport->clk_per);
1739 if (retval)
1740 clk_disable_unprepare(sport->clk_ipg);
1741
1742error_console:
1743 return retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001744}
1745
Vincent Sanders9f4426d2005-10-01 22:56:34 +01001746static struct uart_driver imx_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001747static struct console imx_console = {
Sascha Hauere3d13ff2008-07-05 10:02:48 +02001748 .name = DEV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001749 .write = imx_console_write,
1750 .device = uart_console_device,
1751 .setup = imx_console_setup,
1752 .flags = CON_PRINTBUFFER,
1753 .index = -1,
1754 .data = &imx_reg,
1755};
1756
Linus Torvalds1da177e2005-04-16 15:20:36 -07001757#define IMX_CONSOLE &imx_console
1758#else
1759#define IMX_CONSOLE NULL
1760#endif
1761
1762static struct uart_driver imx_reg = {
1763 .owner = THIS_MODULE,
1764 .driver_name = DRIVER_NAME,
Sascha Hauere3d13ff2008-07-05 10:02:48 +02001765 .dev_name = DEV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001766 .major = SERIAL_IMX_MAJOR,
1767 .minor = MINOR_START,
1768 .nr = ARRAY_SIZE(imx_ports),
1769 .cons = IMX_CONSOLE,
1770};
1771
Russell King3ae5eae2005-11-09 22:32:44 +00001772static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001773{
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01001774 struct imx_port *sport = platform_get_drvdata(dev);
Fabio Estevamdb1a9b52011-12-13 01:23:48 -02001775 unsigned int val;
1776
1777 /* enable wakeup from i.MX UART */
1778 val = readl(sport->port.membase + UCR3);
1779 val |= UCR3_AWAKEN;
1780 writel(val, sport->port.membase + UCR3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001781
Richard Zhao034dc4d2012-09-18 16:14:59 +08001782 uart_suspend_port(&imx_reg, &sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001783
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01001784 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001785}
1786
Russell King3ae5eae2005-11-09 22:32:44 +00001787static int serial_imx_resume(struct platform_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001788{
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01001789 struct imx_port *sport = platform_get_drvdata(dev);
Fabio Estevamdb1a9b52011-12-13 01:23:48 -02001790 unsigned int val;
1791
1792 /* disable wakeup from i.MX UART */
1793 val = readl(sport->port.membase + UCR3);
1794 val &= ~UCR3_AWAKEN;
1795 writel(val, sport->port.membase + UCR3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001796
Richard Zhao034dc4d2012-09-18 16:14:59 +08001797 uart_resume_port(&imx_reg, &sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001798
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01001799 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001800}
1801
Shawn Guo22698aa2011-06-25 02:04:34 +08001802#ifdef CONFIG_OF
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001803/*
1804 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1805 * could successfully get all information from dt or a negative errno.
1806 */
Shawn Guo22698aa2011-06-25 02:04:34 +08001807static int serial_imx_probe_dt(struct imx_port *sport,
1808 struct platform_device *pdev)
1809{
1810 struct device_node *np = pdev->dev.of_node;
1811 const struct of_device_id *of_id =
1812 of_match_device(imx_uart_dt_ids, &pdev->dev);
Shawn Guoff059672011-09-22 14:48:13 +08001813 int ret;
Shawn Guo22698aa2011-06-25 02:04:34 +08001814
1815 if (!np)
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001816 /* no device tree device */
1817 return 1;
Shawn Guo22698aa2011-06-25 02:04:34 +08001818
Shawn Guoff059672011-09-22 14:48:13 +08001819 ret = of_alias_get_id(np, "serial");
1820 if (ret < 0) {
1821 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
Uwe Kleine-Königa197a192011-12-14 21:26:51 +01001822 return ret;
Shawn Guoff059672011-09-22 14:48:13 +08001823 }
1824 sport->port.line = ret;
Shawn Guo22698aa2011-06-25 02:04:34 +08001825
1826 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1827 sport->have_rtscts = 1;
1828
1829 if (of_get_property(np, "fsl,irda-mode", NULL))
1830 sport->use_irda = 1;
1831
Huang Shijie20ff2fe2013-05-30 14:07:12 +08001832 if (of_get_property(np, "fsl,dte-mode", NULL))
1833 sport->dte_mode = 1;
1834
Shawn Guo22698aa2011-06-25 02:04:34 +08001835 sport->devdata = of_id->data;
1836
1837 return 0;
1838}
1839#else
1840static inline int serial_imx_probe_dt(struct imx_port *sport,
1841 struct platform_device *pdev)
1842{
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001843 return 1;
Shawn Guo22698aa2011-06-25 02:04:34 +08001844}
1845#endif
1846
1847static void serial_imx_probe_pdata(struct imx_port *sport,
1848 struct platform_device *pdev)
1849{
Jingoo Han574de552013-07-30 17:06:57 +09001850 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
Shawn Guo22698aa2011-06-25 02:04:34 +08001851
1852 sport->port.line = pdev->id;
1853 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1854
1855 if (!pdata)
1856 return;
1857
1858 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1859 sport->have_rtscts = 1;
1860
1861 if (pdata->flags & IMXUART_IRDA)
1862 sport->use_irda = 1;
1863}
1864
Sascha Hauer2582d8c2008-07-05 10:02:45 +02001865static int serial_imx_probe(struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001866{
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001867 struct imx_port *sport;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001868 void __iomem *base;
1869 int ret = 0;
1870 struct resource *res;
Sascha Hauer5b802342006-05-04 14:07:42 +01001871
Sachin Kamat42d34192013-01-07 10:25:06 +05301872 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001873 if (!sport)
1874 return -ENOMEM;
1875
Shawn Guo22698aa2011-06-25 02:04:34 +08001876 ret = serial_imx_probe_dt(sport, pdev);
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001877 if (ret > 0)
Shawn Guo22698aa2011-06-25 02:04:34 +08001878 serial_imx_probe_pdata(sport, pdev);
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001879 else if (ret < 0)
Sachin Kamat42d34192013-01-07 10:25:06 +05301880 return ret;
Shawn Guo22698aa2011-06-25 02:04:34 +08001881
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001882 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Alexander Shiyanda82f992014-02-22 16:01:33 +04001883 base = devm_ioremap_resource(&pdev->dev, res);
1884 if (IS_ERR(base))
1885 return PTR_ERR(base);
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001886
1887 sport->port.dev = &pdev->dev;
1888 sport->port.mapbase = res->start;
1889 sport->port.membase = base;
1890 sport->port.type = PORT_IMX,
1891 sport->port.iotype = UPIO_MEM;
1892 sport->port.irq = platform_get_irq(pdev, 0);
1893 sport->rxirq = platform_get_irq(pdev, 0);
1894 sport->txirq = platform_get_irq(pdev, 1);
1895 sport->rtsirq = platform_get_irq(pdev, 2);
1896 sport->port.fifosize = 32;
1897 sport->port.ops = &imx_pops;
1898 sport->port.flags = UPF_BOOT_AUTOCONF;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001899 init_timer(&sport->timer);
1900 sport->timer.function = imx_timeout;
1901 sport->timer.data = (unsigned long)sport;
Sascha Hauer38a41fd2008-07-05 10:02:46 +02001902
Sascha Hauer3a9465f2012-03-07 09:31:43 +01001903 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1904 if (IS_ERR(sport->clk_ipg)) {
1905 ret = PTR_ERR(sport->clk_ipg);
Uwe Kleine-König833462e2012-08-20 09:57:04 +02001906 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
Sachin Kamat42d34192013-01-07 10:25:06 +05301907 return ret;
Sascha Hauer38a41fd2008-07-05 10:02:46 +02001908 }
Sascha Hauer38a41fd2008-07-05 10:02:46 +02001909
Sascha Hauer3a9465f2012-03-07 09:31:43 +01001910 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1911 if (IS_ERR(sport->clk_per)) {
1912 ret = PTR_ERR(sport->clk_per);
Uwe Kleine-König833462e2012-08-20 09:57:04 +02001913 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
Sachin Kamat42d34192013-01-07 10:25:06 +05301914 return ret;
Sascha Hauer3a9465f2012-03-07 09:31:43 +01001915 }
1916
Sascha Hauer3a9465f2012-03-07 09:31:43 +01001917 sport->port.uartclk = clk_get_rate(sport->clk_per);
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001918
Fabio Estevamc0d1c6b2014-10-27 14:49:37 -02001919 /*
1920 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1921 * chips only have one interrupt.
1922 */
1923 if (sport->txirq > 0) {
1924 ret = devm_request_irq(&pdev->dev, sport->rxirq, imx_rxint, 0,
1925 dev_name(&pdev->dev), sport);
1926 if (ret)
1927 return ret;
1928
1929 ret = devm_request_irq(&pdev->dev, sport->txirq, imx_txint, 0,
1930 dev_name(&pdev->dev), sport);
1931 if (ret)
1932 return ret;
1933
1934 /* do not use RTS IRQ on IrDA */
1935 if (!USE_IRDA(sport)) {
1936 ret = devm_request_irq(&pdev->dev, sport->rtsirq,
1937 imx_rtsint, 0,
1938 dev_name(&pdev->dev), sport);
1939 if (ret)
1940 return ret;
1941 }
1942 } else {
1943 ret = devm_request_irq(&pdev->dev, sport->port.irq, imx_int, 0,
1944 dev_name(&pdev->dev), sport);
1945 if (ret)
1946 return ret;
1947 }
1948
Shawn Guo22698aa2011-06-25 02:04:34 +08001949 imx_ports[sport->port.line] = sport;
Sascha Hauer5b802342006-05-04 14:07:42 +01001950
Richard Zhao0a86a862012-09-18 16:14:58 +08001951 platform_set_drvdata(pdev, sport);
Sascha Hauer2582d8c2008-07-05 10:02:45 +02001952
Alexander Shiyan45af7802014-02-22 16:01:35 +04001953 return uart_add_one_port(&imx_reg, &sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001954}
1955
Sascha Hauer2582d8c2008-07-05 10:02:45 +02001956static int serial_imx_remove(struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001957{
Sascha Hauer2582d8c2008-07-05 10:02:45 +02001958 struct imx_port *sport = platform_get_drvdata(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001959
Alexander Shiyan45af7802014-02-22 16:01:35 +04001960 return uart_remove_one_port(&imx_reg, &sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001961}
1962
Russell King3ae5eae2005-11-09 22:32:44 +00001963static struct platform_driver serial_imx_driver = {
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01001964 .probe = serial_imx_probe,
1965 .remove = serial_imx_remove,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001966
1967 .suspend = serial_imx_suspend,
1968 .resume = serial_imx_resume,
Shawn Guofe6b5402011-06-25 02:04:33 +08001969 .id_table = imx_uart_devtype,
Russell King3ae5eae2005-11-09 22:32:44 +00001970 .driver = {
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01001971 .name = "imx-uart",
Shawn Guo22698aa2011-06-25 02:04:34 +08001972 .of_match_table = imx_uart_dt_ids,
Russell King3ae5eae2005-11-09 22:32:44 +00001973 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001974};
1975
1976static int __init imx_serial_init(void)
1977{
Fabio Estevamf0fd1b72014-10-27 14:49:40 -02001978 int ret = uart_register_driver(&imx_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001979
Linus Torvalds1da177e2005-04-16 15:20:36 -07001980 if (ret)
1981 return ret;
1982
Russell King3ae5eae2005-11-09 22:32:44 +00001983 ret = platform_driver_register(&serial_imx_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001984 if (ret != 0)
1985 uart_unregister_driver(&imx_reg);
1986
Uwe Kleine-Königf2278242011-11-22 14:22:55 +01001987 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001988}
1989
1990static void __exit imx_serial_exit(void)
1991{
Russell Kingc889b892005-11-21 17:05:21 +00001992 platform_driver_unregister(&serial_imx_driver);
Sascha Hauer4b300c32007-07-17 13:35:46 +01001993 uart_unregister_driver(&imx_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001994}
1995
1996module_init(imx_serial_init);
1997module_exit(imx_serial_exit);
1998
1999MODULE_AUTHOR("Sascha Hauer");
2000MODULE_DESCRIPTION("IMX generic serial port driver");
2001MODULE_LICENSE("GPL");
Kay Sieverse169c132008-04-15 14:34:35 -07002002MODULE_ALIAS("platform:imx-uart");