blob: d3577871be28ddc3897d835a59f5f83fbc6b3c0f [file] [log] [blame]
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Stephen Hemminger793b8832005-09-14 16:06:14 -070018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070026#include <linux/config.h>
Stephen Hemminger793b8832005-09-14 16:06:14 -070027#include <linux/crc32.h>
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070028#include <linux/kernel.h>
29#include <linux/version.h>
30#include <linux/module.h>
31#include <linux/netdevice.h>
Andrew Mortond0bbccf2005-11-10 15:29:27 -080032#include <linux/dma-mapping.h>
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070033#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/in.h>
39#include <linux/delay.h>
Stephen Hemminger91c86df2005-12-09 11:34:57 -080040#include <linux/workqueue.h>
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -070041#include <linux/if_vlan.h>
Stephen Hemmingerd70cd512005-12-09 11:35:09 -080042#include <linux/prefetch.h>
shemminger@osdl.orgef743d32005-11-30 11:45:12 -080043#include <linux/mii.h>
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070044
45#include <asm/irq.h>
46
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -070047#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070051#include "sky2.h"
52
53#define DRV_NAME "sky2"
Stephen Hemmingerc9b84dc2006-05-17 14:37:07 -070054#define DRV_VERSION "1.4"
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070055#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
62 */
63
shemminger@osdl.org13210ce2005-11-30 11:45:14 -080064#define RX_LE_SIZE 512
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070065#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
shemminger@osdl.orgbea86102005-10-26 12:16:10 -070066#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
shemminger@osdl.org13210ce2005-11-30 11:45:14 -080067#define RX_DEF_PENDING RX_MAX_PENDING
Stephen Hemminger82788c72006-01-17 13:43:10 -080068#define RX_SKB_ALIGN 8
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070069
Stephen Hemminger793b8832005-09-14 16:06:14 -070070#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
Stephen Hemmingerb19666d2006-03-07 11:06:36 -080073#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
Stephen Hemminger793b8832005-09-14 16:06:14 -070074
75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070076#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
Stephen Hemmingercb5d9542006-05-08 15:11:29 -070082#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070084static const u32 default_msg =
Stephen Hemminger793b8832005-09-14 16:06:14 -070085 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
Stephen Hemminger3be92a72006-01-17 13:43:17 -080087 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070088
Stephen Hemminger793b8832005-09-14 16:06:14 -070089static int debug = -1; /* defaults above */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -070090module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
Stephen Hemmingerbdb5c582005-12-09 11:34:55 -080093static int copybreak __read_mostly = 256;
94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -080097static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
Stephen Hemminger01bd7562006-05-08 15:11:30 -0700101static int idle_timeout = 100;
102module_param(idle_timeout, int, 0);
103MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700105static const struct pci_device_id sky2_id_table[] = {
Stephen Hemminger793b8832005-09-14 16:06:14 -0700106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
Stephen Hemminger2d2a3872006-05-17 14:37:04 -0700108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -0800119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -0800123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700124 { 0 }
125};
Stephen Hemminger793b8832005-09-14 16:06:14 -0700126
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700127MODULE_DEVICE_TABLE(pci, sky2_id_table);
128
129/* Avoid conditionals by using array */
130static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
131static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
Stephen Hemmingerf4ea4312006-05-09 14:46:54 -0700132static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700133
Stephen Hemminger92f965e2005-12-09 11:34:53 -0800134/* This driver supports yukon2 chipset only */
135static const char *yukon2_name[] = {
136 "XL", /* 0xb3 */
137 "EC Ultra", /* 0xb4 */
138 "UNKNOWN", /* 0xb5 */
139 "EC", /* 0xb6 */
140 "FE", /* 0xb7 */
Stephen Hemminger793b8832005-09-14 16:06:14 -0700141};
142
Stephen Hemminger793b8832005-09-14 16:06:14 -0700143/* Access to external PHY */
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800144static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700145{
146 int i;
147
148 gma_write16(hw, port, GM_SMI_DATA, val);
149 gma_write16(hw, port, GM_SMI_CTRL,
150 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
151
152 for (i = 0; i < PHY_RETRIES; i++) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700153 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800154 return 0;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700155 udelay(1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700156 }
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800157
Stephen Hemminger793b8832005-09-14 16:06:14 -0700158 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800159 return -ETIMEDOUT;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700160}
161
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800162static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700163{
164 int i;
165
Stephen Hemminger793b8832005-09-14 16:06:14 -0700166 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700167 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
168
169 for (i = 0; i < PHY_RETRIES; i++) {
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800170 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
171 *val = gma_read16(hw, port, GM_SMI_DATA);
172 return 0;
173 }
174
Stephen Hemminger793b8832005-09-14 16:06:14 -0700175 udelay(1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700176 }
177
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800178 return -ETIMEDOUT;
179}
180
181static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
182{
183 u16 v;
184
185 if (__gm_phy_read(hw, port, reg, &v) != 0)
186 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
187 return v;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700188}
189
Stephen Hemminger2ccc99b2006-06-13 17:17:27 +0900190static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700191{
192 u16 power_control;
193 u32 reg1;
194 int vaux;
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700195
196 pr_debug("sky2_set_power_state %d\n", state);
197 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
198
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800199 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
Stephen Hemminger08c06d82006-01-30 11:37:54 -0800200 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700201 (power_control & PCI_PM_CAP_PME_D3cold);
202
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800203 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700204
205 power_control |= PCI_PM_CTRL_PME_STATUS;
206 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
207
208 switch (state) {
209 case PCI_D0:
210 /* switch power to VCC (WA for VAUX problem) */
211 sky2_write8(hw, B0_POWER_CTRL,
212 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
213
214 /* disable Core Clock Division, */
215 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
216
217 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
218 /* enable bits are inverted */
219 sky2_write8(hw, B2_Y2_CLK_GATE,
220 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
221 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
222 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
223 else
224 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
225
226 /* Turn off phy power saving */
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800227 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700228 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
229
shemminger@osdl.orgd571b692005-10-26 12:16:09 -0700230 /* looks like this XL is back asswards .. */
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
232 reg1 |= PCI_Y2_PHY1_COMA;
233 if (hw->ports > 1)
234 reg1 |= PCI_Y2_PHY2_COMA;
235 }
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800236
237 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
Stephen Hemminger86a31a72006-05-17 14:37:05 -0700238 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800239 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
240 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800241 reg1 &= P_ASPM_CONTROL_MSK;
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800242 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
243 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800244 }
245
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800246 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800247
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700248 break;
249
250 case PCI_D3hot:
251 case PCI_D3cold:
252 /* Turn on phy power saving */
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800253 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700254 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
255 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
256 else
257 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800258 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700259
260 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
261 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
262 else
263 /* enable bits are inverted */
264 sky2_write8(hw, B2_Y2_CLK_GATE,
265 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
266 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
267 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
268
269 /* switch power to VAUX */
270 if (vaux && state != PCI_D3cold)
271 sky2_write8(hw, B0_POWER_CTRL,
272 (PC_VAUX_ENA | PC_VCC_ENA |
273 PC_VAUX_ON | PC_VCC_OFF));
274 break;
275 default:
276 printk(KERN_ERR PFX "Unknown power state %d\n", state);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700277 }
278
Stephen Hemminger56a645c2006-02-22 11:45:02 -0800279 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700280 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -0700281}
282
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700283static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
284{
285 u16 reg;
286
287 /* disable all GMAC IRQ's */
288 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
289 /* disable PHY IRQs */
290 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700291
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
296
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
300}
301
302static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
303{
304 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700305 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700306
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700307 if (sky2->autoneg == AUTONEG_ENABLE &&
Stephen Hemminger86a31a72006-05-17 14:37:05 -0700308 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700309 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
310
311 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
Stephen Hemminger793b8832005-09-14 16:06:14 -0700312 PHY_M_EC_MAC_S_MSK);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700313 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
314
315 if (hw->chip_id == CHIP_ID_YUKON_EC)
316 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
317 else
318 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
319
320 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
321 }
322
323 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
324 if (hw->copper) {
325 if (hw->chip_id == CHIP_ID_YUKON_FE) {
326 /* enable automatic crossover */
327 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
328 } else {
329 /* disable energy detect */
330 ctrl &= ~PHY_M_PC_EN_DET_MSK;
331
332 /* enable automatic crossover */
333 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
334
335 if (sky2->autoneg == AUTONEG_ENABLE &&
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700336 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700337 ctrl &= ~PHY_M_PC_DSC_MSK;
338 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
339 }
340 }
341 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
342 } else {
343 /* workaround for deviation #4.88 (CRC errors) */
344 /* disable Automatic Crossover */
345
346 ctrl &= ~PHY_M_PC_MDIX_MSK;
347 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
348
349 if (hw->chip_id == CHIP_ID_YUKON_XL) {
350 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
351 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
353 ctrl &= ~PHY_M_MAC_MD_MSK;
354 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
355 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
356
357 /* select page 1 to access Fiber registers */
358 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
359 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700360 }
361
362 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
363 if (sky2->autoneg == AUTONEG_DISABLE)
364 ctrl &= ~PHY_CT_ANE;
365 else
366 ctrl |= PHY_CT_ANE;
367
368 ctrl |= PHY_CT_RESET;
369 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
370
371 ctrl = 0;
372 ct1000 = 0;
373 adv = PHY_AN_CSMA;
374
375 if (sky2->autoneg == AUTONEG_ENABLE) {
376 if (hw->copper) {
377 if (sky2->advertising & ADVERTISED_1000baseT_Full)
378 ct1000 |= PHY_M_1000C_AFD;
379 if (sky2->advertising & ADVERTISED_1000baseT_Half)
380 ct1000 |= PHY_M_1000C_AHD;
381 if (sky2->advertising & ADVERTISED_100baseT_Full)
382 adv |= PHY_M_AN_100_FD;
383 if (sky2->advertising & ADVERTISED_100baseT_Half)
384 adv |= PHY_M_AN_100_HD;
385 if (sky2->advertising & ADVERTISED_10baseT_Full)
386 adv |= PHY_M_AN_10_FD;
387 if (sky2->advertising & ADVERTISED_10baseT_Half)
388 adv |= PHY_M_AN_10_HD;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700389 } else /* special defines for FIBER (88E1011S only) */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700390 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
391
392 /* Set Flow-control capabilities */
393 if (sky2->tx_pause && sky2->rx_pause)
Stephen Hemminger793b8832005-09-14 16:06:14 -0700394 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700395 else if (sky2->rx_pause && !sky2->tx_pause)
Stephen Hemminger793b8832005-09-14 16:06:14 -0700396 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700397 else if (!sky2->rx_pause && sky2->tx_pause)
398 adv |= PHY_AN_PAUSE_ASYM; /* local */
399
400 /* Restart Auto-negotiation */
401 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
402 } else {
403 /* forced speed/duplex settings */
404 ct1000 = PHY_M_1000C_MSE;
405
406 if (sky2->duplex == DUPLEX_FULL)
407 ctrl |= PHY_CT_DUP_MD;
408
409 switch (sky2->speed) {
410 case SPEED_1000:
411 ctrl |= PHY_CT_SP1000;
412 break;
413 case SPEED_100:
414 ctrl |= PHY_CT_SP100;
415 break;
416 }
417
418 ctrl |= PHY_CT_RESET;
419 }
420
421 if (hw->chip_id != CHIP_ID_YUKON_FE)
422 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
423
424 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
425 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
426
427 /* Setup Phy LED's */
428 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
429 ledover = 0;
430
431 switch (hw->chip_id) {
432 case CHIP_ID_YUKON_FE:
433 /* on 88E3082 these bits are at 11..9 (shifted left) */
434 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
435
436 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
437
438 /* delete ACT LED control bits */
439 ctrl &= ~PHY_M_FELP_LED1_MSK;
440 /* change ACT LED control to blink mode */
441 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
442 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
443 break;
444
445 case CHIP_ID_YUKON_XL:
Stephen Hemminger793b8832005-09-14 16:06:14 -0700446 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700447
448 /* select page 3 to access LED control register */
449 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
450
451 /* set LED Function Control register */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700452 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
453 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
454 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
455 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
456 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700457
458 /* set Polarity Control register */
459 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
Stephen Hemminger793b8832005-09-14 16:06:14 -0700460 (PHY_M_POLC_LS1_P_MIX(4) |
461 PHY_M_POLC_IS0_P_MIX(4) |
462 PHY_M_POLC_LOS_CTRL(2) |
463 PHY_M_POLC_INIT_CTRL(2) |
464 PHY_M_POLC_STA1_CTRL(2) |
465 PHY_M_POLC_STA0_CTRL(2)));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700466
467 /* restore page register */
Stephen Hemminger793b8832005-09-14 16:06:14 -0700468 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700469 break;
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700470 case CHIP_ID_YUKON_EC_U:
471 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
472
473 /* select page 3 to access LED control register */
474 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
475
476 /* set LED Function Control register */
477 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
478 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
479 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
480 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
481 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
482
483 /* set Blink Rate in LED Timer Control Register */
484 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
485 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
486 /* restore page register */
487 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
488 break;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700489
490 default:
491 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
492 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
493 /* turn off the Rx LED (LED_RX) */
494 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
495 }
496
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700497 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800498 /* apply fixes in PHY AFE */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700499 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
500 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
501
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800502 /* increase differential signal amplitude in 10BASE-T */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700503 gm_phy_write(hw, port, 0x18, 0xaa99);
504 gm_phy_write(hw, port, 0x17, 0x2011);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700505
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800506 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700507 gm_phy_write(hw, port, 0x18, 0xa204);
508 gm_phy_write(hw, port, 0x17, 0x2002);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800509
510 /* set page register to 0 */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700511 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800512 } else {
513 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
514
515 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
516 /* turn on 100 Mbps LED (LED_LINK100) */
517 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
518 }
519
520 if (ledover)
521 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
522
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700523 }
shemminger@osdl.orgd571b692005-10-26 12:16:09 -0700524 /* Enable phy interrupt on auto-negotiation complete (or link up) */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700525 if (sky2->autoneg == AUTONEG_ENABLE)
526 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
527 else
528 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
529}
530
Stephen Hemminger1b537562005-12-20 15:08:07 -0800531/* Force a renegotiation */
532static void sky2_phy_reinit(struct sky2_port *sky2)
533{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800534 spin_lock_bh(&sky2->phy_lock);
Stephen Hemminger1b537562005-12-20 15:08:07 -0800535 sky2_phy_init(sky2->hw, sky2->port);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800536 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemminger1b537562005-12-20 15:08:07 -0800537}
538
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700539static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
540{
541 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
542 u16 reg;
543 int i;
544 const u8 *addr = hw->dev[port]->dev_addr;
545
shemminger@osdl.org42eeea02005-11-30 11:45:13 -0800546 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
547 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700548
549 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
550
Stephen Hemminger793b8832005-09-14 16:06:14 -0700551 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700552 /* WA DEV_472 -- looks like crossed wires on port 2 */
553 /* clear GMAC 1 Control reset */
554 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
555 do {
556 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
557 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
558 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
559 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
560 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
561 }
562
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700563 if (sky2->autoneg == AUTONEG_DISABLE) {
564 reg = gma_read16(hw, port, GM_GP_CTRL);
565 reg |= GM_GPCR_AU_ALL_DIS;
566 gma_write16(hw, port, GM_GP_CTRL, reg);
567 gma_read16(hw, port, GM_GP_CTRL);
568
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700569 switch (sky2->speed) {
570 case SPEED_1000:
Stephen Hemminger6f4c56b2006-02-10 15:58:59 -0800571 reg &= ~GM_GPCR_SPEED_100;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700572 reg |= GM_GPCR_SPEED_1000;
Stephen Hemminger6f4c56b2006-02-10 15:58:59 -0800573 break;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700574 case SPEED_100:
Stephen Hemminger6f4c56b2006-02-10 15:58:59 -0800575 reg &= ~GM_GPCR_SPEED_1000;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700576 reg |= GM_GPCR_SPEED_100;
Stephen Hemminger6f4c56b2006-02-10 15:58:59 -0800577 break;
578 case SPEED_10:
579 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
580 break;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700581 }
582
583 if (sky2->duplex == DUPLEX_FULL)
584 reg |= GM_GPCR_DUP_FULL;
Stephen Hemmingered6d32c2006-05-08 15:11:33 -0700585
586 /* turn off pause in 10/100mbps half duplex */
587 else if (sky2->speed != SPEED_1000 &&
588 hw->chip_id != CHIP_ID_YUKON_EC_U)
589 sky2->tx_pause = sky2->rx_pause = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700590 } else
591 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
592
593 if (!sky2->tx_pause && !sky2->rx_pause) {
594 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700595 reg |=
596 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
597 } else if (sky2->tx_pause && !sky2->rx_pause) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700598 /* disable Rx flow-control */
599 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
600 }
601
602 gma_write16(hw, port, GM_GP_CTRL, reg);
603
Stephen Hemminger793b8832005-09-14 16:06:14 -0700604 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700605
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800606 spin_lock_bh(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700607 sky2_phy_init(hw, port);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800608 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700609
610 /* MIB clear */
611 reg = gma_read16(hw, port, GM_PHY_ADDR);
612 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
613
Stephen Hemminger43f2f102006-04-05 17:47:15 -0700614 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
615 gma_read16(hw, port, i);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700616 gma_write16(hw, port, GM_PHY_ADDR, reg);
617
618 /* transmit control */
619 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
620
621 /* receive control reg: unicast + multicast + no FCS */
622 gma_write16(hw, port, GM_RX_CTRL,
Stephen Hemminger793b8832005-09-14 16:06:14 -0700623 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700624
625 /* transmit flow control */
626 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
627
628 /* transmit parameter */
629 gma_write16(hw, port, GM_TX_PARAM,
630 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
631 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
632 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
633 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
634
635 /* serial mode register */
636 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700637 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700638
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700639 if (hw->dev[port]->mtu > ETH_DATA_LEN)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700640 reg |= GM_SMOD_JUMBO_ENA;
641
642 gma_write16(hw, port, GM_SERIAL_MODE, reg);
643
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700644 /* virtual address for data */
645 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
646
Stephen Hemminger793b8832005-09-14 16:06:14 -0700647 /* physical address: used for pause frames */
648 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
649
650 /* ignore counter overflows */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700651 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
652 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
653 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
654
655 /* Configure Rx MAC FIFO */
656 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
Stephen Hemminger70f1be42006-03-07 11:06:37 -0800657 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
658 GMF_OPER_ON | GMF_RX_F_FL_ON);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700659
shemminger@osdl.orgd571b692005-10-26 12:16:09 -0700660 /* Flush Rx MAC FIFO on any flow control or error */
shemminger@osdl.org42eeea02005-11-30 11:45:13 -0800661 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700662
Stephen Hemminger793b8832005-09-14 16:06:14 -0700663 /* Set threshold to 0xa (64 bytes)
664 * ASF disabled so no need to do WA dev #4.30
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700665 */
666 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
667
668 /* Configure Tx MAC FIFO */
669 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
670 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -0800671
672 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
673 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
674 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
675 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
676 /* set Tx GMAC FIFO Almost Empty Threshold */
677 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
678 /* Disable Store & Forward mode for TX */
679 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
680 }
681 }
682
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700683}
684
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800685/* Assign Ram Buffer allocation.
686 * start and end are in units of 4k bytes
687 * ram registers are in units of 64bit words
688 */
689static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700690{
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800691 u32 start, end;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700692
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800693 start = startk * 4096/8;
694 end = (endk * 4096/8) - 1;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700695
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700696 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
697 sky2_write32(hw, RB_ADDR(q, RB_START), start);
698 sky2_write32(hw, RB_ADDR(q, RB_END), end);
699 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
700 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
701
702 if (q == Q_R1 || q == Q_R2) {
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800703 u32 space = (endk - startk) * 4096/8;
704 u32 tp = space - space/4;
Stephen Hemminger793b8832005-09-14 16:06:14 -0700705
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800706 /* On receive queue's set the thresholds
707 * give receiver priority when > 3/4 full
708 * send pause when down to 2K
709 */
710 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
711 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700712
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -0800713 tp = space - 2048/8;
714 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
715 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700716 } else {
717 /* Enable store & forward on Tx queue's because
718 * Tx FIFO is only 1K on Yukon
719 */
720 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
721 }
722
723 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700724 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700725}
726
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700727/* Setup Bus Memory Interface */
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -0800728static void sky2_qset(struct sky2_hw *hw, u16 q)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700729{
730 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
731 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
732 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -0800733 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700734}
735
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700736/* Setup prefetch unit registers. This is the interface between
737 * hardware and driver list elements
738 */
Stephen Hemminger8cc048e2005-12-09 11:35:07 -0800739static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700740 u64 addr, u32 last)
741{
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700742 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
743 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
744 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
745 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
746 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
747 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700748
749 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700750}
751
Stephen Hemminger793b8832005-09-14 16:06:14 -0700752static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
753{
754 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
755
Stephen Hemmingercb5d9542006-05-08 15:11:29 -0700756 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700757 return le;
758}
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700759
Stephen Hemminger290d4de2006-03-20 15:48:15 -0800760/* Update chip's next pointer */
761static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700762{
Stephen Hemminger762c2de2006-01-17 13:43:14 -0800763 wmb();
Stephen Hemminger290d4de2006-03-20 15:48:15 -0800764 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
Stephen Hemminger762c2de2006-01-17 13:43:14 -0800765 mmiowb();
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700766}
767
Stephen Hemminger793b8832005-09-14 16:06:14 -0700768
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700769static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
770{
771 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
Stephen Hemmingercb5d9542006-05-08 15:11:29 -0700772 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700773 return le;
774}
775
shemminger@osdl.orga018e332005-11-30 11:45:16 -0800776/* Return high part of DMA address (could be 32 or 64 bit) */
777static inline u32 high32(dma_addr_t a)
778{
Stephen Hemmingera0361192006-01-17 13:43:16 -0800779 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
shemminger@osdl.orga018e332005-11-30 11:45:16 -0800780}
781
Stephen Hemminger793b8832005-09-14 16:06:14 -0700782/* Build description to hardware about buffer */
Stephen Hemminger28bd1812006-01-17 13:43:19 -0800783static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700784{
785 struct sky2_rx_le *le;
Stephen Hemminger734d1862005-12-09 11:35:00 -0800786 u32 hi = high32(map);
787 u16 len = sky2->rx_bufsize;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700788
Stephen Hemminger793b8832005-09-14 16:06:14 -0700789 if (sky2->rx_addr64 != hi) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700790 le = sky2_next_rx(sky2);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700791 le->addr = cpu_to_le32(hi);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700792 le->ctrl = 0;
793 le->opcode = OP_ADDR64 | HW_OWNER;
Stephen Hemminger734d1862005-12-09 11:35:00 -0800794 sky2->rx_addr64 = high32(map + len);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700795 }
Stephen Hemminger793b8832005-09-14 16:06:14 -0700796
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700797 le = sky2_next_rx(sky2);
Stephen Hemminger734d1862005-12-09 11:35:00 -0800798 le->addr = cpu_to_le32((u32) map);
799 le->length = cpu_to_le16(len);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700800 le->ctrl = 0;
801 le->opcode = OP_PACKET | HW_OWNER;
802}
803
Stephen Hemminger793b8832005-09-14 16:06:14 -0700804
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700805/* Tell chip where to start receive checksum.
806 * Actually has two checksums, but set both same to avoid possible byte
807 * order problems.
808 */
Stephen Hemminger793b8832005-09-14 16:06:14 -0700809static void rx_set_checksum(struct sky2_port *sky2)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700810{
811 struct sky2_rx_le *le;
812
Stephen Hemminger793b8832005-09-14 16:06:14 -0700813 le = sky2_next_rx(sky2);
814 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
815 le->ctrl = 0;
816 le->opcode = OP_TCPSTART | HW_OWNER;
817
Stephen Hemminger793b8832005-09-14 16:06:14 -0700818 sky2_write32(sky2->hw,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700819 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
820 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
821
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700822}
823
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700824/*
825 * The RX Stop command will not work for Yukon-2 if the BMU does not
826 * reach the end of packet and since we can't make sure that we have
827 * incoming data, we must reset the BMU while it is not doing a DMA
828 * transfer. Since it is possible that the RX path is still active,
829 * the RX RAM buffer will be stopped first, so any possible incoming
830 * data will not trigger a DMA. After the RAM buffer is stopped, the
831 * BMU is polled until any DMA in progress is ended and only then it
832 * will be reset.
833 */
834static void sky2_rx_stop(struct sky2_port *sky2)
835{
836 struct sky2_hw *hw = sky2->hw;
837 unsigned rxq = rxqaddr[sky2->port];
838 int i;
839
840 /* disable the RAM Buffer receive queue */
841 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
842
843 for (i = 0; i < 0xffff; i++)
844 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
845 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
846 goto stopped;
847
848 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
849 sky2->netdev->name);
850stopped:
851 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
852
853 /* reset the Rx prefetch unit */
854 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
855}
Stephen Hemminger793b8832005-09-14 16:06:14 -0700856
shemminger@osdl.orgd571b692005-10-26 12:16:09 -0700857/* Clean out receive buffer area, assumes receiver hardware stopped */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700858static void sky2_rx_clean(struct sky2_port *sky2)
859{
860 unsigned i;
861
862 memset(sky2->rx_le, 0, RX_LE_BYTES);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700863 for (i = 0; i < sky2->rx_pending; i++) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700864 struct ring_info *re = sky2->rx_ring + i;
865
866 if (re->skb) {
Stephen Hemminger793b8832005-09-14 16:06:14 -0700867 pci_unmap_single(sky2->hw->pdev,
Stephen Hemminger734d1862005-12-09 11:35:00 -0800868 re->mapaddr, sky2->rx_bufsize,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700869 PCI_DMA_FROMDEVICE);
870 kfree_skb(re->skb);
871 re->skb = NULL;
872 }
873 }
874}
875
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800876/* Basic MII support */
877static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
878{
879 struct mii_ioctl_data *data = if_mii(ifr);
880 struct sky2_port *sky2 = netdev_priv(dev);
881 struct sky2_hw *hw = sky2->hw;
882 int err = -EOPNOTSUPP;
883
884 if (!netif_running(dev))
885 return -ENODEV; /* Phy still in reset */
886
Stephen Hemmingerd89e1342006-03-20 15:48:20 -0800887 switch (cmd) {
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800888 case SIOCGMIIPHY:
889 data->phy_id = PHY_ADDR_MARV;
890
891 /* fallthru */
892 case SIOCGMIIREG: {
893 u16 val = 0;
Stephen Hemminger91c86df2005-12-09 11:34:57 -0800894
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800895 spin_lock_bh(&sky2->phy_lock);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800896 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800897 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemminger91c86df2005-12-09 11:34:57 -0800898
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800899 data->val_out = val;
900 break;
901 }
902
903 case SIOCSMIIREG:
904 if (!capable(CAP_NET_ADMIN))
905 return -EPERM;
906
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800907 spin_lock_bh(&sky2->phy_lock);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800908 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
909 data->val_in);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -0800910 spin_unlock_bh(&sky2->phy_lock);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -0800911 break;
912 }
913 return err;
914}
915
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700916#ifdef SKY2_VLAN_TAG_USED
917static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
918{
919 struct sky2_port *sky2 = netdev_priv(dev);
920 struct sky2_hw *hw = sky2->hw;
921 u16 port = sky2->port;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700922
Stephen Hemminger302d1252006-01-17 13:43:20 -0800923 spin_lock_bh(&sky2->tx_lock);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700924
925 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
926 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
927 sky2->vlgrp = grp;
928
Stephen Hemminger302d1252006-01-17 13:43:20 -0800929 spin_unlock_bh(&sky2->tx_lock);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700930}
931
932static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
933{
934 struct sky2_port *sky2 = netdev_priv(dev);
935 struct sky2_hw *hw = sky2->hw;
936 u16 port = sky2->port;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700937
Stephen Hemminger302d1252006-01-17 13:43:20 -0800938 spin_lock_bh(&sky2->tx_lock);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700939
940 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
941 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
942 if (sky2->vlgrp)
943 sky2->vlgrp->vlan_devices[vid] = NULL;
944
Stephen Hemminger302d1252006-01-17 13:43:20 -0800945 spin_unlock_bh(&sky2->tx_lock);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -0700946}
947#endif
948
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700949/*
Stephen Hemminger82788c72006-01-17 13:43:10 -0800950 * It appears the hardware has a bug in the FIFO logic that
951 * cause it to hang if the FIFO gets overrun and the receive buffer
952 * is not aligned. ALso alloc_skb() won't align properly if slab
953 * debugging is enabled.
954 */
955static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
956{
957 struct sk_buff *skb;
958
959 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
960 if (likely(skb)) {
961 unsigned long p = (unsigned long) skb->data;
Stephen Hemminger4a15d562006-04-25 10:58:52 -0700962 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
Stephen Hemminger82788c72006-01-17 13:43:10 -0800963 }
964
965 return skb;
966}
967
968/*
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700969 * Allocate and setup receiver buffer pool.
970 * In case of 64 bit dma, there are 2X as many list elements
971 * available as ring entries
972 * and need to reserve one list element so we don't wrap around.
973 */
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700974static int sky2_rx_start(struct sky2_port *sky2)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700975{
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700976 struct sky2_hw *hw = sky2->hw;
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700977 unsigned rxq = rxqaddr[sky2->port];
978 int i;
Stephen Hemmingera1433ac2006-05-22 12:03:42 -0700979 unsigned thresh;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700980
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700981 sky2->rx_put = sky2->rx_next = 0;
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -0800982 sky2_qset(hw, rxq);
Stephen Hemminger977bdf02006-02-22 11:44:58 -0800983
984 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
985 /* MAC Rx RAM Read is controlled by hardware */
986 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
987 }
988
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700989 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
990
991 rx_set_checksum(sky2);
Stephen Hemminger793b8832005-09-14 16:06:14 -0700992 for (i = 0; i < sky2->rx_pending; i++) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700993 struct ring_info *re = sky2->rx_ring + i;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700994
Stephen Hemminger82788c72006-01-17 13:43:10 -0800995 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -0700996 if (!re->skb)
997 goto nomem;
998
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -0700999 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
Stephen Hemminger734d1862005-12-09 11:35:00 -08001000 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1001 sky2_rx_add(sky2, re->mapaddr);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001002 }
1003
Stephen Hemmingera1433ac2006-05-22 12:03:42 -07001004
1005 /*
1006 * The receiver hangs if it receives frames larger than the
1007 * packet buffer. As a workaround, truncate oversize frames, but
1008 * the register is limited to 9 bits, so if you do frames > 2052
1009 * you better get the MTU right!
1010 */
1011 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
1012 if (thresh > 0x1ff)
1013 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1014 else {
1015 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1016 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1017 }
1018
Stephen Hemminger70f1be42006-03-07 11:06:37 -08001019
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001020 /* Tell chip about available buffers */
1021 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001022 return 0;
1023nomem:
1024 sky2_rx_clean(sky2);
1025 return -ENOMEM;
1026}
1027
1028/* Bring up network interface. */
1029static int sky2_up(struct net_device *dev)
1030{
1031 struct sky2_port *sky2 = netdev_priv(dev);
1032 struct sky2_hw *hw = sky2->hw;
1033 unsigned port = sky2->port;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001034 u32 ramsize, rxspace, imask;
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001035 int cap, err = -ENOMEM;
Stephen Hemminger843a46f2006-05-11 15:07:28 -07001036 struct net_device *otherdev = hw->dev[sky2->port^1];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001037
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001038 /*
1039 * On dual port PCI-X card, there is an problem where status
1040 * can be received out of order due to split transactions
Stephen Hemminger843a46f2006-05-11 15:07:28 -07001041 */
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001042 if (otherdev && netif_running(otherdev) &&
1043 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1044 struct sky2_port *osky2 = netdev_priv(otherdev);
1045 u16 cmd;
Stephen Hemminger843a46f2006-05-11 15:07:28 -07001046
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07001047 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1048 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1049 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1050
1051 sky2->rx_csum = 0;
1052 osky2->rx_csum = 0;
1053 }
1054
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001055 if (netif_msg_ifup(sky2))
1056 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1057
1058 /* must be power of 2 */
1059 sky2->tx_le = pci_alloc_consistent(hw->pdev,
Stephen Hemminger793b8832005-09-14 16:06:14 -07001060 TX_RING_SIZE *
1061 sizeof(struct sky2_tx_le),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001062 &sky2->tx_le_map);
1063 if (!sky2->tx_le)
1064 goto err_out;
1065
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001066 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001067 GFP_KERNEL);
1068 if (!sky2->tx_ring)
1069 goto err_out;
1070 sky2->tx_prod = sky2->tx_cons = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001071
1072 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1073 &sky2->rx_le_map);
1074 if (!sky2->rx_le)
1075 goto err_out;
1076 memset(sky2->rx_le, 0, RX_LE_BYTES);
1077
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001078 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001079 GFP_KERNEL);
1080 if (!sky2->rx_ring)
1081 goto err_out;
1082
1083 sky2_mac_init(hw, port);
1084
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -08001085 /* Determine available ram buffer space (in 4K blocks).
1086 * Note: not sure about the FE setting below yet
1087 */
1088 if (hw->chip_id == CHIP_ID_YUKON_FE)
1089 ramsize = 4;
1090 else
1091 ramsize = sky2_read8(hw, B2_E_0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001092
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -08001093 /* Give transmitter one third (rounded up) */
1094 rxspace = ramsize - (ramsize + 2) / 3;
1095
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001096 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
Stephen Hemminger1c28f6b2006-01-17 13:43:13 -08001097 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001098
Stephen Hemminger793b8832005-09-14 16:06:14 -07001099 /* Make sure SyncQ is disabled */
1100 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1101 RB_RST_SET);
1102
shemminger@osdl.orgaf4ed7e2005-11-30 11:45:21 -08001103 sky2_qset(hw, txqaddr[port]);
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08001104
Stephen Hemminger977bdf02006-02-22 11:44:58 -08001105 /* Set almost empty threshold */
1106 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1107 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08001108
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001109 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1110 TX_RING_SIZE - 1);
1111
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001112 err = sky2_rx_start(sky2);
1113 if (err)
1114 goto err_out;
1115
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001116 /* Enable interrupts from phy/mac for port */
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001117 imask = sky2_read32(hw, B0_IMSK);
Stephen Hemmingerf4ea4312006-05-09 14:46:54 -07001118 imask |= portirq_msk[port];
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001119 sky2_write32(hw, B0_IMSK, imask);
1120
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001121 return 0;
1122
1123err_out:
Stephen Hemminger1b537562005-12-20 15:08:07 -08001124 if (sky2->rx_le) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001125 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1126 sky2->rx_le, sky2->rx_le_map);
Stephen Hemminger1b537562005-12-20 15:08:07 -08001127 sky2->rx_le = NULL;
1128 }
1129 if (sky2->tx_le) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001130 pci_free_consistent(hw->pdev,
1131 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1132 sky2->tx_le, sky2->tx_le_map);
Stephen Hemminger1b537562005-12-20 15:08:07 -08001133 sky2->tx_le = NULL;
1134 }
1135 kfree(sky2->tx_ring);
1136 kfree(sky2->rx_ring);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001137
Stephen Hemminger1b537562005-12-20 15:08:07 -08001138 sky2->tx_ring = NULL;
1139 sky2->rx_ring = NULL;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001140 return err;
1141}
1142
Stephen Hemminger793b8832005-09-14 16:06:14 -07001143/* Modular subtraction in ring */
1144static inline int tx_dist(unsigned tail, unsigned head)
1145{
Stephen Hemmingercb5d9542006-05-08 15:11:29 -07001146 return (head - tail) & (TX_RING_SIZE - 1);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001147}
1148
1149/* Number of list elements available for next tx */
1150static inline int tx_avail(const struct sky2_port *sky2)
1151{
1152 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1153}
1154
1155/* Estimate of number of transmit list elements required */
Stephen Hemminger28bd1812006-01-17 13:43:19 -08001156static unsigned tx_le_req(const struct sk_buff *skb)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001157{
1158 unsigned count;
1159
1160 count = sizeof(dma_addr_t) / sizeof(u32);
1161 count += skb_shinfo(skb)->nr_frags * count;
1162
Herbert Xu79671682006-06-22 02:40:14 -07001163 if (skb_shinfo(skb)->gso_size)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001164 ++count;
1165
Stephen Hemminger0e3ff6a2005-12-09 11:35:02 -08001166 if (skb->ip_summed == CHECKSUM_HW)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001167 ++count;
1168
1169 return count;
1170}
1171
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001172/*
Stephen Hemminger793b8832005-09-14 16:06:14 -07001173 * Put one packet in ring for transmit.
1174 * A single packet can generate multiple list elements, and
1175 * the number of ring elements will probably be less than the number
1176 * of list elements used.
Stephen Hemmingerf2e46562005-12-09 11:34:58 -08001177 *
1178 * No BH disabling for tx_lock here (like tg3)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001179 */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001180static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1181{
1182 struct sky2_port *sky2 = netdev_priv(dev);
1183 struct sky2_hw *hw = sky2->hw;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001184 struct sky2_tx_le *le = NULL;
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001185 struct tx_ring_info *re;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001186 unsigned i, len;
Stephen Hemmingerb19666d2006-03-07 11:06:36 -08001187 int avail;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001188 dma_addr_t mapping;
1189 u32 addr64;
1190 u16 mss;
1191 u8 ctrl;
1192
Stephen Hemminger302d1252006-01-17 13:43:20 -08001193 /* No BH disabling for tx_lock here. We are running in BH disabled
1194 * context and TX reclaim runs via poll inside of a software
1195 * interrupt, and no related locks in IRQ processing.
1196 */
Stephen Hemmingerf2e46562005-12-09 11:34:58 -08001197 if (!spin_trylock(&sky2->tx_lock))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001198 return NETDEV_TX_LOCKED;
1199
Stephen Hemminger793b8832005-09-14 16:06:14 -07001200 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
Stephen Hemminger8c463ef2005-12-09 11:35:08 -08001201 /* There is a known but harmless race with lockless tx
1202 * and netif_stop_queue.
1203 */
1204 if (!netif_queue_stopped(dev)) {
1205 netif_stop_queue(dev);
Stephen Hemminger3be92a72006-01-17 13:43:17 -08001206 if (net_ratelimit())
1207 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1208 dev->name);
Stephen Hemminger8c463ef2005-12-09 11:35:08 -08001209 }
Stephen Hemmingerf2e46562005-12-09 11:34:58 -08001210 spin_unlock(&sky2->tx_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001211
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001212 return NETDEV_TX_BUSY;
1213 }
1214
Stephen Hemminger793b8832005-09-14 16:06:14 -07001215 if (unlikely(netif_msg_tx_queued(sky2)))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001216 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1217 dev->name, sky2->tx_prod, skb->len);
1218
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001219 len = skb_headlen(skb);
1220 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
shemminger@osdl.orga018e332005-11-30 11:45:16 -08001221 addr64 = high32(mapping);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001222
1223 re = sky2->tx_ring + sky2->tx_prod;
1224
shemminger@osdl.orga018e332005-11-30 11:45:16 -08001225 /* Send high bits if changed or crosses boundary */
1226 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07001227 le = get_tx_le(sky2);
1228 le->tx.addr = cpu_to_le32(addr64);
1229 le->ctrl = 0;
1230 le->opcode = OP_ADDR64 | HW_OWNER;
shemminger@osdl.orga018e332005-11-30 11:45:16 -08001231 sky2->tx_addr64 = high32(mapping + len);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001232 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001233
1234 /* Check for TCP Segmentation Offload */
Herbert Xu79671682006-06-22 02:40:14 -07001235 mss = skb_shinfo(skb)->gso_size;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001236 if (mss != 0) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001237 /* just drop the packet if non-linear expansion fails */
1238 if (skb_header_cloned(skb) &&
1239 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
Stephen Hemminger15240072006-03-23 08:51:38 -08001240 dev_kfree_skb(skb);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001241 goto out_unlock;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001242 }
1243
1244 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1245 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1246 mss += ETH_HLEN;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001247 }
1248
Stephen Hemminger793b8832005-09-14 16:06:14 -07001249 if (mss != sky2->tx_last_mss) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001250 le = get_tx_le(sky2);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001251 le->tx.tso.size = cpu_to_le16(mss);
1252 le->tx.tso.rsvd = 0;
1253 le->opcode = OP_LRGLEN | HW_OWNER;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001254 le->ctrl = 0;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001255 sky2->tx_last_mss = mss;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001256 }
1257
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001258 ctrl = 0;
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001259#ifdef SKY2_VLAN_TAG_USED
1260 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1261 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1262 if (!le) {
1263 le = get_tx_le(sky2);
1264 le->tx.addr = 0;
1265 le->opcode = OP_VLAN|HW_OWNER;
1266 le->ctrl = 0;
1267 } else
1268 le->opcode |= OP_VLAN;
1269 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1270 ctrl |= INS_VLAN;
1271 }
1272#endif
1273
1274 /* Handle TCP checksum offload */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001275 if (skb->ip_summed == CHECKSUM_HW) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07001276 u16 hdr = skb->h.raw - skb->data;
1277 u16 offset = hdr + skb->csum;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001278
1279 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1280 if (skb->nh.iph->protocol == IPPROTO_UDP)
1281 ctrl |= UDPTCP;
1282
1283 le = get_tx_le(sky2);
1284 le->tx.csum.start = cpu_to_le16(hdr);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001285 le->tx.csum.offset = cpu_to_le16(offset);
1286 le->length = 0; /* initial checksum value */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001287 le->ctrl = 1; /* one packet */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001288 le->opcode = OP_TCPLISW | HW_OWNER;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001289 }
1290
1291 le = get_tx_le(sky2);
1292 le->tx.addr = cpu_to_le32((u32) mapping);
1293 le->length = cpu_to_le16(len);
1294 le->ctrl = ctrl;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001295 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001296
Stephen Hemminger793b8832005-09-14 16:06:14 -07001297 /* Record the transmit mapping info */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001298 re->skb = skb;
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001299 pci_unmap_addr_set(re, mapaddr, mapping);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001300
1301 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1302 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001303 struct tx_ring_info *fre;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001304
1305 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1306 frag->size, PCI_DMA_TODEVICE);
Stephen Hemmingera0361192006-01-17 13:43:16 -08001307 addr64 = high32(mapping);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001308 if (addr64 != sky2->tx_addr64) {
1309 le = get_tx_le(sky2);
1310 le->tx.addr = cpu_to_le32(addr64);
1311 le->ctrl = 0;
1312 le->opcode = OP_ADDR64 | HW_OWNER;
1313 sky2->tx_addr64 = addr64;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001314 }
1315
1316 le = get_tx_le(sky2);
1317 le->tx.addr = cpu_to_le32((u32) mapping);
1318 le->length = cpu_to_le16(frag->size);
1319 le->ctrl = ctrl;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001320 le->opcode = OP_BUFFER | HW_OWNER;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001321
Stephen Hemminger793b8832005-09-14 16:06:14 -07001322 fre = sky2->tx_ring
Stephen Hemmingercb5d9542006-05-08 15:11:29 -07001323 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001324 pci_unmap_addr_set(fre, mapaddr, mapping);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001325 }
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001326
Stephen Hemminger793b8832005-09-14 16:06:14 -07001327 re->idx = sky2->tx_prod;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001328 le->ctrl |= EOP;
1329
Stephen Hemmingerb19666d2006-03-07 11:06:36 -08001330 avail = tx_avail(sky2);
1331 if (mss != 0 || avail < TX_MIN_PENDING) {
1332 le->ctrl |= FRC_STAT;
1333 if (avail <= MAX_SKB_TX_LE)
1334 netif_stop_queue(dev);
1335 }
1336
Stephen Hemminger290d4de2006-03-20 15:48:15 -08001337 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001338
Stephen Hemminger793b8832005-09-14 16:06:14 -07001339out_unlock:
Stephen Hemmingerf2e46562005-12-09 11:34:58 -08001340 spin_unlock(&sky2->tx_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001341
1342 dev->trans_start = jiffies;
1343 return NETDEV_TX_OK;
1344}
1345
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001346/*
Stephen Hemminger793b8832005-09-14 16:06:14 -07001347 * Free ring elements from starting at tx_cons until "done"
1348 *
1349 * NB: the hardware will tell us about partial completion of multi-part
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001350 * buffers; these are deferred until completion.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001351 */
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001352static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001353{
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001354 struct net_device *dev = sky2->netdev;
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001355 struct pci_dev *pdev = sky2->hw->pdev;
1356 u16 nxt, put;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001357 unsigned i;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001358
Stephen Hemminger0e3ff6a2005-12-09 11:35:02 -08001359 BUG_ON(done >= TX_RING_SIZE);
shemminger@osdl.org22247952005-11-30 11:45:19 -08001360
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001361 if (unlikely(netif_msg_tx_done(sky2)))
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001362 printk(KERN_DEBUG "%s: tx done, up to %u\n",
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001363 dev->name, done);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001364
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001365 for (put = sky2->tx_cons; put != done; put = nxt) {
1366 struct tx_ring_info *re = sky2->tx_ring + put;
1367 struct sk_buff *skb = re->skb;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001368
Stephen Hemmingerd89e1342006-03-20 15:48:20 -08001369 nxt = re->idx;
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001370 BUG_ON(nxt >= TX_RING_SIZE);
Stephen Hemmingerd70cd512005-12-09 11:35:09 -08001371 prefetch(sky2->tx_ring + nxt);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001372
Stephen Hemminger793b8832005-09-14 16:06:14 -07001373 /* Check for partial status */
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001374 if (tx_dist(put, done) < tx_dist(put, nxt))
1375 break;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001376
Stephen Hemminger793b8832005-09-14 16:06:14 -07001377 skb = re->skb;
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001378 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
Stephen Hemminger734d1862005-12-09 11:35:00 -08001379 skb_headlen(skb), PCI_DMA_TODEVICE);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001380
Stephen Hemminger793b8832005-09-14 16:06:14 -07001381 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
Stephen Hemminger6cdbbdf2005-12-09 11:35:01 -08001382 struct tx_ring_info *fre;
Stephen Hemmingercb5d9542006-05-08 15:11:29 -07001383 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001384 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
Stephen Hemmingerd89e1342006-03-20 15:48:20 -08001385 skb_shinfo(skb)->frags[i].size,
Stephen Hemminger734d1862005-12-09 11:35:00 -08001386 PCI_DMA_TODEVICE);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001387 }
1388
Stephen Hemminger15240072006-03-23 08:51:38 -08001389 dev_kfree_skb(skb);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001390 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07001391
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001392 sky2->tx_cons = put;
Stephen Hemminger8f246642006-03-20 15:48:21 -08001393 if (tx_avail(sky2) > MAX_SKB_TX_LE)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001394 netif_wake_queue(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001395}
1396
1397/* Cleanup all untransmitted buffers, assume transmitter not running */
Stephen Hemminger13b97b72005-12-09 11:35:03 -08001398static void sky2_tx_clean(struct sky2_port *sky2)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001399{
Stephen Hemminger302d1252006-01-17 13:43:20 -08001400 spin_lock_bh(&sky2->tx_lock);
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001401 sky2_tx_complete(sky2, sky2->tx_prod);
Stephen Hemminger302d1252006-01-17 13:43:20 -08001402 spin_unlock_bh(&sky2->tx_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001403}
1404
1405/* Network shutdown */
1406static int sky2_down(struct net_device *dev)
1407{
1408 struct sky2_port *sky2 = netdev_priv(dev);
1409 struct sky2_hw *hw = sky2->hw;
1410 unsigned port = sky2->port;
1411 u16 ctrl;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001412 u32 imask;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001413
Stephen Hemminger1b537562005-12-20 15:08:07 -08001414 /* Never really got started! */
1415 if (!sky2->tx_le)
1416 return 0;
1417
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001418 if (netif_msg_ifdown(sky2))
1419 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1420
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001421 /* Stop more packets from being queued */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001422 netif_stop_queue(dev);
1423
Stephen Hemminger793b8832005-09-14 16:06:14 -07001424 sky2_phy_reset(hw, port);
1425
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001426 /* Stop transmitter */
1427 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1428 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1429
1430 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
Stephen Hemminger793b8832005-09-14 16:06:14 -07001431 RB_RST_SET | RB_DIS_OP_MD);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001432
1433 ctrl = gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001434 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001435 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1436
1437 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1438
1439 /* Workaround shared GMAC reset */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001440 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1441 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001442 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1443
1444 /* Disable Force Sync bit and Enable Alloc bit */
1445 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1446 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1447
1448 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1449 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1450 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1451
1452 /* Reset the PCI FIFO of the async Tx queue */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001453 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1454 BMU_RST_SET | BMU_FIFO_RST);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001455
1456 /* Reset the Tx prefetch units */
1457 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1458 PREF_UNIT_RST_SET);
1459
1460 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1461
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001462 sky2_rx_stop(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001463
1464 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1465 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1466
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001467 /* Disable port IRQ */
1468 imask = sky2_read32(hw, B0_IMSK);
Stephen Hemmingerf4ea4312006-05-09 14:46:54 -07001469 imask &= ~portirq_msk[port];
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001470 sky2_write32(hw, B0_IMSK, imask);
1471
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001472 /* turn off LED's */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001473 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1474
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001475 synchronize_irq(hw->pdev->irq);
1476
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001477 sky2_tx_clean(sky2);
1478 sky2_rx_clean(sky2);
1479
1480 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1481 sky2->rx_le, sky2->rx_le_map);
1482 kfree(sky2->rx_ring);
1483
1484 pci_free_consistent(hw->pdev,
1485 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1486 sky2->tx_le, sky2->tx_le_map);
1487 kfree(sky2->tx_ring);
1488
Stephen Hemminger1b537562005-12-20 15:08:07 -08001489 sky2->tx_le = NULL;
1490 sky2->rx_le = NULL;
1491
1492 sky2->rx_ring = NULL;
1493 sky2->tx_ring = NULL;
1494
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001495 return 0;
1496}
1497
1498static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1499{
Stephen Hemminger793b8832005-09-14 16:06:14 -07001500 if (!hw->copper)
1501 return SPEED_1000;
1502
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001503 if (hw->chip_id == CHIP_ID_YUKON_FE)
1504 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1505
1506 switch (aux & PHY_M_PS_SPEED_MSK) {
1507 case PHY_M_PS_SPEED_1000:
1508 return SPEED_1000;
1509 case PHY_M_PS_SPEED_100:
1510 return SPEED_100;
1511 default:
1512 return SPEED_10;
1513 }
1514}
1515
1516static void sky2_link_up(struct sky2_port *sky2)
1517{
1518 struct sky2_hw *hw = sky2->hw;
1519 unsigned port = sky2->port;
1520 u16 reg;
1521
1522 /* Enable Transmit FIFO Underrun */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001523 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001524
1525 reg = gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemminger6f4c56b2006-02-10 15:58:59 -08001526 if (sky2->autoneg == AUTONEG_DISABLE) {
1527 reg |= GM_GPCR_AU_ALL_DIS;
1528
1529 /* Is write/read necessary? Copied from sky2_mac_init */
1530 gma_write16(hw, port, GM_GP_CTRL, reg);
1531 gma_read16(hw, port, GM_GP_CTRL);
1532
1533 switch (sky2->speed) {
1534 case SPEED_1000:
1535 reg &= ~GM_GPCR_SPEED_100;
1536 reg |= GM_GPCR_SPEED_1000;
1537 break;
1538 case SPEED_100:
1539 reg &= ~GM_GPCR_SPEED_1000;
1540 reg |= GM_GPCR_SPEED_100;
1541 break;
1542 case SPEED_10:
1543 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1544 break;
1545 }
1546 } else
1547 reg &= ~GM_GPCR_AU_ALL_DIS;
1548
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001549 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1550 reg |= GM_GPCR_DUP_FULL;
1551
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001552 /* enable Rx/Tx */
1553 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1554 gma_write16(hw, port, GM_GP_CTRL, reg);
1555 gma_read16(hw, port, GM_GP_CTRL);
1556
1557 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1558
1559 netif_carrier_on(sky2->netdev);
1560 netif_wake_queue(sky2->netdev);
1561
1562 /* Turn on link LED */
Stephen Hemminger793b8832005-09-14 16:06:14 -07001563 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001564 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1565
Stephen Hemmingered6d32c2006-05-08 15:11:33 -07001566 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07001567 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
Stephen Hemmingered6d32c2006-05-08 15:11:33 -07001568 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1569
1570 switch(sky2->speed) {
1571 case SPEED_10:
1572 led |= PHY_M_LEDC_INIT_CTRL(7);
1573 break;
1574
1575 case SPEED_100:
1576 led |= PHY_M_LEDC_STA1_CTRL(7);
1577 break;
1578
1579 case SPEED_1000:
1580 led |= PHY_M_LEDC_STA0_CTRL(7);
1581 break;
1582 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07001583
1584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
Stephen Hemmingered6d32c2006-05-08 15:11:33 -07001585 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1587 }
1588
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001589 if (netif_msg_link(sky2))
1590 printk(KERN_INFO PFX
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001591 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001592 sky2->netdev->name, sky2->speed,
1593 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1594 (sky2->tx_pause && sky2->rx_pause) ? "both" :
Stephen Hemminger793b8832005-09-14 16:06:14 -07001595 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001596}
1597
1598static void sky2_link_down(struct sky2_port *sky2)
1599{
1600 struct sky2_hw *hw = sky2->hw;
1601 unsigned port = sky2->port;
1602 u16 reg;
1603
1604 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1605
1606 reg = gma_read16(hw, port, GM_GP_CTRL);
1607 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1608 gma_write16(hw, port, GM_GP_CTRL, reg);
1609 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1610
1611 if (sky2->rx_pause && !sky2->tx_pause) {
1612 /* restore Asymmetric Pause bit */
1613 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
Stephen Hemminger793b8832005-09-14 16:06:14 -07001614 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1615 | PHY_M_AN_ASP);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001616 }
1617
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001618 netif_carrier_off(sky2->netdev);
1619 netif_stop_queue(sky2->netdev);
1620
1621 /* Turn on link LED */
1622 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1623
1624 if (netif_msg_link(sky2))
1625 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1626 sky2_phy_init(hw, port);
1627}
1628
Stephen Hemminger793b8832005-09-14 16:06:14 -07001629static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1630{
1631 struct sky2_hw *hw = sky2->hw;
1632 unsigned port = sky2->port;
1633 u16 lpa;
1634
1635 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1636
1637 if (lpa & PHY_M_AN_RF) {
1638 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1639 return -1;
1640 }
1641
1642 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1643 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1644 printk(KERN_ERR PFX "%s: master/slave fault",
1645 sky2->netdev->name);
1646 return -1;
1647 }
1648
1649 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1650 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1651 sky2->netdev->name);
1652 return -1;
1653 }
1654
1655 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1656
1657 sky2->speed = sky2_phy_speed(hw, aux);
1658
1659 /* Pause bits are offset (9..8) */
Stephen Hemmingered6d32c2006-05-08 15:11:33 -07001660 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001661 aux >>= 6;
1662
1663 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1664 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1665
1666 if ((sky2->tx_pause || sky2->rx_pause)
1667 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1668 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1669 else
1670 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1671
1672 return 0;
1673}
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001674
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001675/* Interrupt from PHY */
1676static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001677{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001678 struct net_device *dev = hw->dev[port];
1679 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001680 u16 istatus, phystat;
1681
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001682 spin_lock(&sky2->phy_lock);
1683 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1684 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1685
1686 if (!netif_running(dev))
1687 goto out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001688
1689 if (netif_msg_intr(sky2))
1690 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1691 sky2->netdev->name, istatus, phystat);
1692
1693 if (istatus & PHY_M_IS_AN_COMPL) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07001694 if (sky2_autoneg_done(sky2, phystat) == 0)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001695 sky2_link_up(sky2);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001696 goto out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001697 }
1698
Stephen Hemminger793b8832005-09-14 16:06:14 -07001699 if (istatus & PHY_M_IS_LSP_CHANGE)
1700 sky2->speed = sky2_phy_speed(hw, phystat);
1701
1702 if (istatus & PHY_M_IS_DUP_CHANGE)
1703 sky2->duplex =
1704 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1705
1706 if (istatus & PHY_M_IS_LST_CHANGE) {
1707 if (phystat & PHY_M_PS_LINK_UP)
1708 sky2_link_up(sky2);
1709 else
1710 sky2_link_down(sky2);
1711 }
1712out:
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001713 spin_unlock(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001714}
1715
Stephen Hemminger302d1252006-01-17 13:43:20 -08001716
1717/* Transmit timeout is only called if we are running, carries is up
1718 * and tx queue is full (stopped).
1719 */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001720static void sky2_tx_timeout(struct net_device *dev)
1721{
1722 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger8cc048e2005-12-09 11:35:07 -08001723 struct sky2_hw *hw = sky2->hw;
1724 unsigned txq = txqaddr[sky2->port];
Stephen Hemminger8f246642006-03-20 15:48:21 -08001725 u16 report, done;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001726
1727 if (netif_msg_timer(sky2))
1728 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1729
Stephen Hemminger8f246642006-03-20 15:48:21 -08001730 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1731 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001732
Stephen Hemminger8f246642006-03-20 15:48:21 -08001733 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1734 dev->name,
1735 sky2->tx_cons, sky2->tx_prod, report, done);
Stephen Hemminger8cc048e2005-12-09 11:35:07 -08001736
Stephen Hemminger8f246642006-03-20 15:48:21 -08001737 if (report != done) {
1738 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1739
1740 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1741 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1742 } else if (report != sky2->tx_cons) {
1743 printk(KERN_INFO PFX "status report lost?\n");
1744
1745 spin_lock_bh(&sky2->tx_lock);
1746 sky2_tx_complete(sky2, report);
1747 spin_unlock_bh(&sky2->tx_lock);
1748 } else {
1749 printk(KERN_INFO PFX "hardware hung? flushing\n");
1750
1751 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1752 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1753
1754 sky2_tx_clean(sky2);
1755
1756 sky2_qset(hw, txq);
1757 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1758 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001759}
1760
Stephen Hemminger734d1862005-12-09 11:35:00 -08001761
Stephen Hemminger70f1be42006-03-07 11:06:37 -08001762/* Want receive buffer size to be multiple of 64 bits
1763 * and incl room for vlan and truncation
1764 */
Stephen Hemminger734d1862005-12-09 11:35:00 -08001765static inline unsigned sky2_buf_size(int mtu)
1766{
Stephen Hemminger4a15d562006-04-25 10:58:52 -07001767 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
Stephen Hemminger734d1862005-12-09 11:35:00 -08001768}
1769
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001770static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1771{
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001772 struct sky2_port *sky2 = netdev_priv(dev);
1773 struct sky2_hw *hw = sky2->hw;
1774 int err;
1775 u16 ctl, mode;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001776 u32 imask;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001777
1778 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1779 return -EINVAL;
1780
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08001781 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1782 return -EINVAL;
1783
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001784 if (!netif_running(dev)) {
1785 dev->mtu = new_mtu;
1786 return 0;
1787 }
1788
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001789 imask = sky2_read32(hw, B0_IMSK);
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001790 sky2_write32(hw, B0_IMSK, 0);
1791
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001792 dev->trans_start = jiffies; /* prevent tx timeout */
1793 netif_stop_queue(dev);
1794 netif_poll_disable(hw->dev[0]);
1795
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001796 synchronize_irq(hw->pdev->irq);
1797
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001798 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1799 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1800 sky2_rx_stop(sky2);
1801 sky2_rx_clean(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001802
1803 dev->mtu = new_mtu;
Stephen Hemminger734d1862005-12-09 11:35:00 -08001804 sky2->rx_bufsize = sky2_buf_size(new_mtu);
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001805 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1806 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001807
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001808 if (dev->mtu > ETH_DATA_LEN)
1809 mode |= GM_SMOD_JUMBO_ENA;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001810
shemminger@osdl.org6b1a3ae2005-09-27 15:02:55 -07001811 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1812
1813 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1814
1815 err = sky2_rx_start(sky2);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001816 sky2_write32(hw, B0_IMSK, imask);
shemminger@osdl.org018d1c62005-11-30 11:45:18 -08001817
Stephen Hemminger1b537562005-12-20 15:08:07 -08001818 if (err)
1819 dev_close(dev);
1820 else {
1821 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1822
1823 netif_poll_enable(hw->dev[0]);
1824 netif_wake_queue(dev);
1825 }
1826
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001827 return err;
1828}
1829
1830/*
1831 * Receive one packet.
1832 * For small packets or errors, just reuse existing skb.
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07001833 * For larger packets, get new buffer.
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001834 */
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001835static struct sk_buff *sky2_receive(struct sky2_port *sky2,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001836 u16 length, u32 status)
1837{
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001838 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001839 struct sk_buff *skb = NULL;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001840
1841 if (unlikely(netif_msg_rx_status(sky2)))
1842 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001843 sky2->netdev->name, sky2->rx_next, status, length);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001844
Stephen Hemminger793b8832005-09-14 16:06:14 -07001845 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
Stephen Hemmingerd70cd512005-12-09 11:35:09 -08001846 prefetch(sky2->rx_ring + sky2->rx_next);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001847
shemminger@osdl.org42eeea02005-11-30 11:45:13 -08001848 if (status & GMR_FS_ANY_ERR)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001849 goto error;
1850
shemminger@osdl.org42eeea02005-11-30 11:45:13 -08001851 if (!(status & GMR_FS_RX_OK))
1852 goto resubmit;
1853
Stephen Hemminger70f1be42006-03-07 11:06:37 -08001854 if (length > sky2->netdev->mtu + ETH_HLEN)
Stephen Hemminger6e15b712005-12-20 15:08:09 -08001855 goto oversize;
1856
Stephen Hemmingerbdb5c582005-12-09 11:34:55 -08001857 if (length < copybreak) {
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001858 skb = alloc_skb(length + 2, GFP_ATOMIC);
1859 if (!skb)
Stephen Hemminger793b8832005-09-14 16:06:14 -07001860 goto resubmit;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001861
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001862 skb_reserve(skb, 2);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001863 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1864 length, PCI_DMA_FROMDEVICE);
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001865 memcpy(skb->data, re->skb->data, length);
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001866 skb->ip_summed = re->skb->ip_summed;
1867 skb->csum = re->skb->csum;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001868 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1869 length, PCI_DMA_FROMDEVICE);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001870 } else {
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001871 struct sk_buff *nskb;
1872
Stephen Hemminger82788c72006-01-17 13:43:10 -08001873 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001874 if (!nskb)
1875 goto resubmit;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001876
Stephen Hemminger793b8832005-09-14 16:06:14 -07001877 skb = re->skb;
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001878 re->skb = nskb;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001879 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
Stephen Hemminger734d1862005-12-09 11:35:00 -08001880 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001881 prefetch(skb->data);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001882
Stephen Hemminger793b8832005-09-14 16:06:14 -07001883 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
Stephen Hemminger734d1862005-12-09 11:35:00 -08001884 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001885 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001886
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001887 skb_put(skb, length);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001888resubmit:
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001889 re->skb->ip_summed = CHECKSUM_NONE;
Stephen Hemminger734d1862005-12-09 11:35:00 -08001890 sky2_rx_add(sky2, re->mapaddr);
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001891
shemminger@osdl.orgbea86102005-10-26 12:16:10 -07001892 /* Tell receiver about new buffers. */
Stephen Hemminger290d4de2006-03-20 15:48:15 -08001893 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
shemminger@osdl.orgbea86102005-10-26 12:16:10 -07001894
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001895 return skb;
1896
Stephen Hemminger6e15b712005-12-20 15:08:09 -08001897oversize:
1898 ++sky2->net_stats.rx_over_errors;
1899 goto resubmit;
1900
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001901error:
Stephen Hemminger6e15b712005-12-20 15:08:09 -08001902 ++sky2->net_stats.rx_errors;
1903
Stephen Hemminger3be92a72006-01-17 13:43:17 -08001904 if (netif_msg_rx_err(sky2) && net_ratelimit())
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001905 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1906 sky2->netdev->name, status, length);
Stephen Hemminger793b8832005-09-14 16:06:14 -07001907
1908 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001909 sky2->net_stats.rx_length_errors++;
1910 if (status & GMR_FS_FRAGMENT)
1911 sky2->net_stats.rx_frame_errors++;
1912 if (status & GMR_FS_CRC_ERR)
1913 sky2->net_stats.rx_crc_errors++;
Stephen Hemminger793b8832005-09-14 16:06:14 -07001914 if (status & GMR_FS_RX_FF_OV)
1915 sky2->net_stats.rx_fifo_errors++;
Stephen Hemminger79e57d32005-09-19 15:42:33 -07001916
Stephen Hemminger793b8832005-09-14 16:06:14 -07001917 goto resubmit;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001918}
1919
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001920/* Transmit complete */
1921static inline void sky2_tx_done(struct net_device *dev, u16 last)
Stephen Hemminger13b97b72005-12-09 11:35:03 -08001922{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001923 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger302d1252006-01-17 13:43:20 -08001924
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001925 if (netif_running(dev)) {
1926 spin_lock(&sky2->tx_lock);
1927 sky2_tx_complete(sky2, last);
1928 spin_unlock(&sky2->tx_lock);
shemminger@osdl.org22247952005-11-30 11:45:19 -08001929 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001930}
1931
Stephen Hemminger86fba632006-05-17 14:37:06 -07001932/* Is status ring empty or is there more to do? */
1933static inline int sky2_more_work(const struct sky2_hw *hw)
1934{
1935 return (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX));
1936}
1937
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001938/* Process status response ring */
1939static int sky2_status_intr(struct sky2_hw *hw, int to_do)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001940{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001941 int work_done = 0;
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07001942 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001943
Stephen Hemmingeraf2a58a2005-12-09 11:35:04 -08001944 rmb();
shemminger@osdl.orgbea86102005-10-26 12:16:10 -07001945
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07001946 while (hw->st_idx != hwidx) {
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08001947 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1948 struct net_device *dev;
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001949 struct sky2_port *sky2;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001950 struct sk_buff *skb;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001951 u32 status;
1952 u16 length;
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001953
Stephen Hemmingercb5d9542006-05-08 15:11:29 -07001954 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
shemminger@osdl.orgbea86102005-10-26 12:16:10 -07001955
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07001956 BUG_ON(le->link >= 2);
1957 dev = hw->dev[le->link];
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08001958
1959 sky2 = netdev_priv(dev);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08001960 length = le->length;
1961 status = le->status;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001962
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07001963 switch (le->opcode & ~HW_OWNER) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001964 case OP_RXSTAT:
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001965 skb = sky2_receive(sky2, length, status);
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001966 if (!skb)
1967 break;
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08001968
1969 skb->dev = dev;
1970 skb->protocol = eth_type_trans(skb, dev);
1971 dev->last_rx = jiffies;
1972
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001973#ifdef SKY2_VLAN_TAG_USED
1974 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1975 vlan_hwaccel_receive_skb(skb,
1976 sky2->vlgrp,
1977 be16_to_cpu(sky2->rx_tag));
1978 } else
1979#endif
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001980 netif_receive_skb(skb);
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08001981
1982 if (++work_done >= to_do)
1983 goto exit_loop;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001984 break;
1985
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07001986#ifdef SKY2_VLAN_TAG_USED
1987 case OP_RXVLAN:
1988 sky2->rx_tag = length;
1989 break;
1990
1991 case OP_RXCHKSVLAN:
1992 sky2->rx_tag = length;
1993 /* fall through */
1994#endif
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001995 case OP_RXCHKS:
shemminger@osdl.orgd11c13e2005-09-27 15:02:56 -07001996 skb = sky2->rx_ring[sky2->rx_next].skb;
1997 skb->ip_summed = CHECKSUM_HW;
1998 skb->csum = le16_to_cpu(status);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07001999 break;
2000
2001 case OP_TXINDEXLE:
Stephen Hemminger13b97b72005-12-09 11:35:03 -08002002 /* TX index reports status for both ports */
Stephen Hemmingerf55925d2006-05-08 15:11:28 -07002003 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2004 sky2_tx_done(hw->dev[0], status & 0xfff);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002005 if (hw->dev[1])
2006 sky2_tx_done(hw->dev[1],
2007 ((status >> 24) & 0xff)
2008 | (u16)(length & 0xf) << 8);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002009 break;
2010
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002011 default:
2012 if (net_ratelimit())
Stephen Hemminger793b8832005-09-14 16:06:14 -07002013 printk(KERN_WARNING PFX
Stephen Hemmingere71ebd72006-05-08 15:11:31 -07002014 "unknown status opcode 0x%x\n", le->opcode);
2015 goto exit_loop;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002016 }
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002017 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002018
shemminger@osdl.org13210ce2005-11-30 11:45:14 -08002019exit_loop:
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002020 return work_done;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002021}
2022
2023static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2024{
2025 struct net_device *dev = hw->dev[port];
2026
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002027 if (net_ratelimit())
2028 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2029 dev->name, status);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002030
2031 if (status & Y2_IS_PAR_RD1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002032 if (net_ratelimit())
2033 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2034 dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002035 /* Clear IRQ */
2036 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2037 }
2038
2039 if (status & Y2_IS_PAR_WR1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002040 if (net_ratelimit())
2041 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2042 dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002043
2044 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2045 }
2046
2047 if (status & Y2_IS_PAR_MAC1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002048 if (net_ratelimit())
2049 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002050 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2051 }
2052
2053 if (status & Y2_IS_PAR_RX1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002054 if (net_ratelimit())
2055 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002056 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2057 }
2058
2059 if (status & Y2_IS_TCP_TXA1) {
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002060 if (net_ratelimit())
2061 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2062 dev->name);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002063 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2064 }
2065}
2066
2067static void sky2_hw_intr(struct sky2_hw *hw)
2068{
2069 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2070
Stephen Hemminger793b8832005-09-14 16:06:14 -07002071 if (status & Y2_IS_TIST_OV)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002072 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002073
2074 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002075 u16 pci_err;
2076
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002077 pci_err = sky2_pci_read16(hw, PCI_STATUS);
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002078 if (net_ratelimit())
2079 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2080 pci_name(hw->pdev), pci_err);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002081
2082 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002083 sky2_pci_write16(hw, PCI_STATUS,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002084 pci_err | PCI_STATUS_ERROR_BITS);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002085 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2086 }
2087
2088 if (status & Y2_IS_PCI_EXP) {
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07002089 /* PCI-Express uncorrectable Error occurred */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002090 u32 pex_err;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002091
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002092 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002093
Stephen Hemminger3be92a72006-01-17 13:43:17 -08002094 if (net_ratelimit())
2095 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2096 pci_name(hw->pdev), pex_err);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002097
2098 /* clear the interrupt */
2099 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002100 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002101 0xffffffffUL);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002102 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2103
2104 if (pex_err & PEX_FATAL_ERRORS) {
2105 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2106 hwmsk &= ~Y2_IS_PCI_EXP;
2107 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2108 }
2109 }
2110
2111 if (status & Y2_HWE_L1_MASK)
2112 sky2_hw_error(hw, 0, status);
2113 status >>= 8;
2114 if (status & Y2_HWE_L1_MASK)
2115 sky2_hw_error(hw, 1, status);
2116}
2117
2118static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2119{
2120 struct net_device *dev = hw->dev[port];
2121 struct sky2_port *sky2 = netdev_priv(dev);
2122 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2123
2124 if (netif_msg_intr(sky2))
2125 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2126 dev->name, status);
2127
2128 if (status & GM_IS_RX_FF_OR) {
2129 ++sky2->net_stats.rx_fifo_errors;
2130 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2131 }
2132
2133 if (status & GM_IS_TX_FF_UR) {
2134 ++sky2->net_stats.tx_fifo_errors;
2135 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2136 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002137}
2138
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002139/* This should never happen it is a fatal situation */
2140static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2141 const char *rxtx, u32 mask)
2142{
2143 struct net_device *dev = hw->dev[port];
2144 struct sky2_port *sky2 = netdev_priv(dev);
2145 u32 imask;
2146
2147 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2148 dev ? dev->name : "<not registered>", rxtx);
2149
2150 imask = sky2_read32(hw, B0_IMSK);
2151 imask &= ~mask;
2152 sky2_write32(hw, B0_IMSK, imask);
2153
2154 if (dev) {
2155 spin_lock(&sky2->phy_lock);
2156 sky2_link_down(sky2);
2157 spin_unlock(&sky2->phy_lock);
2158 }
2159}
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002160
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002161/* If idle then force a fake soft NAPI poll once a second
2162 * to work around cases where sharing an edge triggered interrupt.
2163 */
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09002164static inline void sky2_idle_start(struct sky2_hw *hw)
2165{
2166 if (idle_timeout > 0)
2167 mod_timer(&hw->idle_timer,
2168 jiffies + msecs_to_jiffies(idle_timeout));
2169}
2170
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002171static void sky2_idle(unsigned long arg)
2172{
Stephen Hemminger01bd7562006-05-08 15:11:30 -07002173 struct sky2_hw *hw = (struct sky2_hw *) arg;
2174 struct net_device *dev = hw->dev[0];
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002175
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002176 if (__netif_rx_schedule_prep(dev))
2177 __netif_rx_schedule(dev);
Stephen Hemminger01bd7562006-05-08 15:11:30 -07002178
2179 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07002180}
2181
2182
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002183static int sky2_poll(struct net_device *dev0, int *budget)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002184{
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002185 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2186 int work_limit = min(dev0->quota, *budget);
2187 int work_done = 0;
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08002188 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002189
Linus Torvaldsd374c1c2006-06-12 12:53:27 -07002190 if (!~status)
Stephen Hemminger26ec43f2006-06-13 17:17:29 +09002191 goto out;
Linus Torvaldsd374c1c2006-06-12 12:53:27 -07002192
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002193 if (status & Y2_IS_HW_ERR)
2194 sky2_hw_intr(hw);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002195
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002196 if (status & Y2_IS_IRQ_PHY1)
2197 sky2_phy_intr(hw, 0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002198
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002199 if (status & Y2_IS_IRQ_PHY2)
2200 sky2_phy_intr(hw, 1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002201
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002202 if (status & Y2_IS_IRQ_MAC1)
2203 sky2_mac_intr(hw, 0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002204
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002205 if (status & Y2_IS_IRQ_MAC2)
2206 sky2_mac_intr(hw, 1);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002207
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002208 if (status & Y2_IS_CHK_RX1)
2209 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002210
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002211 if (status & Y2_IS_CHK_RX2)
2212 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002213
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002214 if (status & Y2_IS_CHK_TXA1)
2215 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
Stephen Hemmingerd2579242006-03-20 15:48:22 -08002216
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002217 if (status & Y2_IS_CHK_TXA2)
2218 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002219
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002220 work_done = sky2_status_intr(hw, work_limit);
2221 *budget -= work_done;
2222 dev0->quota -= work_done;
2223
Stephen Hemminger86fba632006-05-17 14:37:06 -07002224 if (status & Y2_IS_STAT_BMU)
2225 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2226
2227 if (sky2_more_work(hw))
Stephen Hemminger1e5f1282006-05-08 15:11:27 -07002228 return 1;
Stephen Hemminger26ec43f2006-06-13 17:17:29 +09002229out:
Stephen Hemmingerd3240312006-05-08 15:11:26 -07002230 netif_rx_complete(dev0);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002231
Stephen Hemminger86fba632006-05-17 14:37:06 -07002232 sky2_read32(hw, B0_Y2_SP_LISR);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002233 return 0;
2234}
2235
2236static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2237{
2238 struct sky2_hw *hw = dev_id;
2239 struct net_device *dev0 = hw->dev[0];
2240 u32 status;
2241
2242 /* Reading this mask interrupts as side effect */
2243 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2244 if (status == 0 || status == ~0)
2245 return IRQ_NONE;
2246
2247 prefetch(&hw->st_le[hw->st_idx]);
2248 if (likely(__netif_rx_schedule_prep(dev0)))
2249 __netif_rx_schedule(dev0);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002250
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002251 return IRQ_HANDLED;
2252}
2253
2254#ifdef CONFIG_NET_POLL_CONTROLLER
2255static void sky2_netpoll(struct net_device *dev)
2256{
2257 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger88d11362006-06-16 12:10:46 -07002258 struct net_device *dev0 = sky2->hw->dev[0];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002259
Stephen Hemminger88d11362006-06-16 12:10:46 -07002260 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2261 __netif_rx_schedule(dev0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002262}
2263#endif
2264
2265/* Chip internal frequency for clock calculations */
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002266static inline u32 sky2_mhz(const struct sky2_hw *hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002267{
Stephen Hemminger793b8832005-09-14 16:06:14 -07002268 switch (hw->chip_id) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002269 case CHIP_ID_YUKON_EC:
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08002270 case CHIP_ID_YUKON_EC_U:
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002271 return 125; /* 125 Mhz */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002272 case CHIP_ID_YUKON_FE:
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002273 return 100; /* 100 Mhz */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002274 default: /* YUKON_XL */
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002275 return 156; /* 156 Mhz */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002276 }
2277}
2278
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002279static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2280{
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002281 return sky2_mhz(hw) * us;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002282}
2283
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002284static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2285{
2286 return clk / sky2_mhz(hw);
2287}
2288
2289
Stephen Hemminger98712e52006-04-25 10:58:53 -07002290static int __devinit sky2_reset(struct sky2_hw *hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002291{
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002292 u16 status;
2293 u8 t8, pmd_type;
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002294 int i;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002295
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002296 sky2_write8(hw, B0_CTST, CS_RST_CLR);
Stephen Hemminger08c06d82006-01-30 11:37:54 -08002297
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002298 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2299 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2300 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2301 pci_name(hw->pdev), hw->chip_id);
2302 return -EOPNOTSUPP;
2303 }
2304
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002305 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2306
2307 /* This rev is really old, and requires untested workarounds */
2308 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2309 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2310 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2311 hw->chip_id, hw->chip_rev);
2312 return -EOPNOTSUPP;
2313 }
2314
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002315 /* disable ASF */
2316 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2317 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2318 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2319 }
2320
2321 /* do a SW reset */
2322 sky2_write8(hw, B0_CTST, CS_RST_SET);
2323 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2324
2325 /* clear PCI errors, if any */
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002326 status = sky2_pci_read16(hw, PCI_STATUS);
Stephen Hemminger2d42d212006-01-30 11:37:55 -08002327
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002328 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002329 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2330
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002331
2332 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2333
2334 /* clear any PEX errors */
Stephen Hemmingerd89e1342006-03-20 15:48:20 -08002335 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
Stephen Hemminger56a645c2006-02-22 11:45:02 -08002336 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2337
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002338
2339 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2340 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2341
2342 hw->ports = 1;
2343 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2344 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2345 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2346 ++hw->ports;
2347 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002348
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07002349 sky2_set_power_state(hw, PCI_D0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002350
2351 for (i = 0; i < hw->ports; i++) {
2352 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2353 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2354 }
2355
2356 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2357
Stephen Hemminger793b8832005-09-14 16:06:14 -07002358 /* Clear I2C IRQ noise */
2359 sky2_write32(hw, B2_I2C_IRQ, 1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002360
2361 /* turn off hardware timer (unused) */
2362 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2363 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002364
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002365 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2366
Stephen Hemminger69634ee2005-12-09 11:35:06 -08002367 /* Turn off descriptor polling */
2368 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002369
2370 /* Turn off receive timestamp */
2371 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002372 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002373
2374 /* enable the Tx Arbiters */
2375 for (i = 0; i < hw->ports; i++)
2376 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2377
2378 /* Initialize ram interface */
2379 for (i = 0; i < hw->ports; i++) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002380 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002381
2382 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2383 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2384 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2385 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2386 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2387 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2388 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2389 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2390 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2391 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2392 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2393 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2394 }
2395
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002396 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2397
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002398 for (i = 0; i < hw->ports; i++)
2399 sky2_phy_reset(hw, i);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002400
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002401 memset(hw->st_le, 0, STATUS_LE_BYTES);
2402 hw->st_idx = 0;
2403
2404 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2405 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2406
2407 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002408 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002409
2410 /* Set the list last index */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002411 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002412
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002413 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2414 sky2_write8(hw, STAT_FIFO_WM, 16);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002415
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002416 /* set Status-FIFO ISR watermark */
2417 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2418 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2419 else
2420 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002421
Stephen Hemminger290d4de2006-03-20 15:48:15 -08002422 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
Stephen Hemminger77b3d6a2006-03-20 15:48:18 -08002423 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2424 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002425
Stephen Hemminger793b8832005-09-14 16:06:14 -07002426 /* enable status unit */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002427 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2428
2429 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2430 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2431 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2432
2433 return 0;
2434}
2435
Stephen Hemminger28bd1812006-01-17 13:43:19 -08002436static u32 sky2_supported_modes(const struct sky2_hw *hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002437{
2438 u32 modes;
2439 if (hw->copper) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002440 modes = SUPPORTED_10baseT_Half
2441 | SUPPORTED_10baseT_Full
2442 | SUPPORTED_100baseT_Half
2443 | SUPPORTED_100baseT_Full
2444 | SUPPORTED_Autoneg | SUPPORTED_TP;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002445
2446 if (hw->chip_id != CHIP_ID_YUKON_FE)
2447 modes |= SUPPORTED_1000baseT_Half
Stephen Hemminger793b8832005-09-14 16:06:14 -07002448 | SUPPORTED_1000baseT_Full;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002449 } else
2450 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
Stephen Hemminger793b8832005-09-14 16:06:14 -07002451 | SUPPORTED_Autoneg;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002452 return modes;
2453}
2454
Stephen Hemminger793b8832005-09-14 16:06:14 -07002455static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002456{
2457 struct sky2_port *sky2 = netdev_priv(dev);
2458 struct sky2_hw *hw = sky2->hw;
2459
2460 ecmd->transceiver = XCVR_INTERNAL;
2461 ecmd->supported = sky2_supported_modes(hw);
2462 ecmd->phy_address = PHY_ADDR_MARV;
2463 if (hw->copper) {
2464 ecmd->supported = SUPPORTED_10baseT_Half
Stephen Hemminger793b8832005-09-14 16:06:14 -07002465 | SUPPORTED_10baseT_Full
2466 | SUPPORTED_100baseT_Half
2467 | SUPPORTED_100baseT_Full
2468 | SUPPORTED_1000baseT_Half
2469 | SUPPORTED_1000baseT_Full
2470 | SUPPORTED_Autoneg | SUPPORTED_TP;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002471 ecmd->port = PORT_TP;
2472 } else
2473 ecmd->port = PORT_FIBRE;
2474
2475 ecmd->advertising = sky2->advertising;
2476 ecmd->autoneg = sky2->autoneg;
2477 ecmd->speed = sky2->speed;
2478 ecmd->duplex = sky2->duplex;
2479 return 0;
2480}
2481
2482static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2483{
2484 struct sky2_port *sky2 = netdev_priv(dev);
2485 const struct sky2_hw *hw = sky2->hw;
2486 u32 supported = sky2_supported_modes(hw);
2487
2488 if (ecmd->autoneg == AUTONEG_ENABLE) {
2489 ecmd->advertising = supported;
2490 sky2->duplex = -1;
2491 sky2->speed = -1;
2492 } else {
2493 u32 setting;
2494
Stephen Hemminger793b8832005-09-14 16:06:14 -07002495 switch (ecmd->speed) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002496 case SPEED_1000:
2497 if (ecmd->duplex == DUPLEX_FULL)
2498 setting = SUPPORTED_1000baseT_Full;
2499 else if (ecmd->duplex == DUPLEX_HALF)
2500 setting = SUPPORTED_1000baseT_Half;
2501 else
2502 return -EINVAL;
2503 break;
2504 case SPEED_100:
2505 if (ecmd->duplex == DUPLEX_FULL)
2506 setting = SUPPORTED_100baseT_Full;
2507 else if (ecmd->duplex == DUPLEX_HALF)
2508 setting = SUPPORTED_100baseT_Half;
2509 else
2510 return -EINVAL;
2511 break;
2512
2513 case SPEED_10:
2514 if (ecmd->duplex == DUPLEX_FULL)
2515 setting = SUPPORTED_10baseT_Full;
2516 else if (ecmd->duplex == DUPLEX_HALF)
2517 setting = SUPPORTED_10baseT_Half;
2518 else
2519 return -EINVAL;
2520 break;
2521 default:
2522 return -EINVAL;
2523 }
2524
2525 if ((setting & supported) == 0)
2526 return -EINVAL;
2527
2528 sky2->speed = ecmd->speed;
2529 sky2->duplex = ecmd->duplex;
2530 }
2531
2532 sky2->autoneg = ecmd->autoneg;
2533 sky2->advertising = ecmd->advertising;
2534
Stephen Hemminger1b537562005-12-20 15:08:07 -08002535 if (netif_running(dev))
2536 sky2_phy_reinit(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002537
2538 return 0;
2539}
2540
2541static void sky2_get_drvinfo(struct net_device *dev,
2542 struct ethtool_drvinfo *info)
2543{
2544 struct sky2_port *sky2 = netdev_priv(dev);
2545
2546 strcpy(info->driver, DRV_NAME);
2547 strcpy(info->version, DRV_VERSION);
2548 strcpy(info->fw_version, "N/A");
2549 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2550}
2551
2552static const struct sky2_stat {
Stephen Hemminger793b8832005-09-14 16:06:14 -07002553 char name[ETH_GSTRING_LEN];
2554 u16 offset;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002555} sky2_stats[] = {
2556 { "tx_bytes", GM_TXO_OK_HI },
2557 { "rx_bytes", GM_RXO_OK_HI },
2558 { "tx_broadcast", GM_TXF_BC_OK },
2559 { "rx_broadcast", GM_RXF_BC_OK },
2560 { "tx_multicast", GM_TXF_MC_OK },
2561 { "rx_multicast", GM_RXF_MC_OK },
2562 { "tx_unicast", GM_TXF_UC_OK },
2563 { "rx_unicast", GM_RXF_UC_OK },
2564 { "tx_mac_pause", GM_TXF_MPAUSE },
2565 { "rx_mac_pause", GM_RXF_MPAUSE },
Stephen Hemmingereadfa7d2006-03-22 10:38:45 -08002566 { "collisions", GM_TXF_COL },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002567 { "late_collision",GM_TXF_LAT_COL },
2568 { "aborted", GM_TXF_ABO_COL },
Stephen Hemmingereadfa7d2006-03-22 10:38:45 -08002569 { "single_collisions", GM_TXF_SNG_COL },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002570 { "multi_collisions", GM_TXF_MUL_COL },
Stephen Hemmingereadfa7d2006-03-22 10:38:45 -08002571
Stephen Hemmingerd2604542006-03-23 08:51:36 -08002572 { "rx_short", GM_RXF_SHT },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002573 { "rx_runt", GM_RXE_FRAG },
Stephen Hemmingereadfa7d2006-03-22 10:38:45 -08002574 { "rx_64_byte_packets", GM_RXF_64B },
2575 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2576 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2577 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2578 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2579 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2580 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002581 { "rx_too_long", GM_RXF_LNG_ERR },
Stephen Hemmingereadfa7d2006-03-22 10:38:45 -08002582 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2583 { "rx_jabber", GM_RXF_JAB_PKT },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002584 { "rx_fcs_error", GM_RXF_FCS_ERR },
Stephen Hemmingereadfa7d2006-03-22 10:38:45 -08002585
2586 { "tx_64_byte_packets", GM_TXF_64B },
2587 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2588 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2589 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2590 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2591 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2592 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2593 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002594};
2595
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002596static u32 sky2_get_rx_csum(struct net_device *dev)
2597{
2598 struct sky2_port *sky2 = netdev_priv(dev);
2599
2600 return sky2->rx_csum;
2601}
2602
2603static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2604{
2605 struct sky2_port *sky2 = netdev_priv(dev);
2606
2607 sky2->rx_csum = data;
Stephen Hemminger793b8832005-09-14 16:06:14 -07002608
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002609 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2610 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2611
2612 return 0;
2613}
2614
2615static u32 sky2_get_msglevel(struct net_device *netdev)
2616{
2617 struct sky2_port *sky2 = netdev_priv(netdev);
2618 return sky2->msg_enable;
2619}
2620
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07002621static int sky2_nway_reset(struct net_device *dev)
2622{
2623 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07002624
2625 if (sky2->autoneg != AUTONEG_ENABLE)
2626 return -EINVAL;
2627
Stephen Hemminger1b537562005-12-20 15:08:07 -08002628 sky2_phy_reinit(sky2);
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07002629
2630 return 0;
2631}
2632
Stephen Hemminger793b8832005-09-14 16:06:14 -07002633static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002634{
2635 struct sky2_hw *hw = sky2->hw;
2636 unsigned port = sky2->port;
2637 int i;
2638
2639 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
Stephen Hemminger793b8832005-09-14 16:06:14 -07002640 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002641 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
Stephen Hemminger793b8832005-09-14 16:06:14 -07002642 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002643
Stephen Hemminger793b8832005-09-14 16:06:14 -07002644 for (i = 2; i < count; i++)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002645 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2646}
2647
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002648static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2649{
2650 struct sky2_port *sky2 = netdev_priv(netdev);
2651 sky2->msg_enable = value;
2652}
2653
2654static int sky2_get_stats_count(struct net_device *dev)
2655{
2656 return ARRAY_SIZE(sky2_stats);
2657}
2658
2659static void sky2_get_ethtool_stats(struct net_device *dev,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002660 struct ethtool_stats *stats, u64 * data)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002661{
2662 struct sky2_port *sky2 = netdev_priv(dev);
2663
Stephen Hemminger793b8832005-09-14 16:06:14 -07002664 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002665}
2666
Stephen Hemminger793b8832005-09-14 16:06:14 -07002667static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002668{
2669 int i;
2670
2671 switch (stringset) {
2672 case ETH_SS_STATS:
2673 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2674 memcpy(data + i * ETH_GSTRING_LEN,
2675 sky2_stats[i].name, ETH_GSTRING_LEN);
2676 break;
2677 }
2678}
2679
2680/* Use hardware MIB variables for critical path statistics and
2681 * transmit feedback not reported at interrupt.
2682 * Other errors are accounted for in interrupt handler.
2683 */
2684static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2685{
2686 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002687 u64 data[13];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002688
Stephen Hemminger793b8832005-09-14 16:06:14 -07002689 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002690
2691 sky2->net_stats.tx_bytes = data[0];
2692 sky2->net_stats.rx_bytes = data[1];
2693 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2694 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
Stephen Hemminger050ff182006-03-23 08:51:37 -08002695 sky2->net_stats.multicast = data[3] + data[5];
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002696 sky2->net_stats.collisions = data[10];
2697 sky2->net_stats.tx_aborted_errors = data[12];
2698
2699 return &sky2->net_stats;
2700}
2701
2702static int sky2_set_mac_address(struct net_device *dev, void *p)
2703{
2704 struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08002705 struct sky2_hw *hw = sky2->hw;
2706 unsigned port = sky2->port;
2707 const struct sockaddr *addr = p;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002708
2709 if (!is_valid_ether_addr(addr->sa_data))
2710 return -EADDRNOTAVAIL;
2711
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002712 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08002713 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002714 dev->dev_addr, ETH_ALEN);
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08002715 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002716 dev->dev_addr, ETH_ALEN);
Stephen Hemminger1b537562005-12-20 15:08:07 -08002717
Stephen Hemmingera8ab1ec2006-01-30 11:37:57 -08002718 /* virtual address for data */
2719 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2720
2721 /* physical address: used for pause frames */
2722 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
Stephen Hemminger1b537562005-12-20 15:08:07 -08002723
2724 return 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002725}
2726
2727static void sky2_set_multicast(struct net_device *dev)
2728{
2729 struct sky2_port *sky2 = netdev_priv(dev);
2730 struct sky2_hw *hw = sky2->hw;
2731 unsigned port = sky2->port;
2732 struct dev_mc_list *list = dev->mc_list;
2733 u16 reg;
2734 u8 filter[8];
2735
2736 memset(filter, 0, sizeof(filter));
2737
2738 reg = gma_read16(hw, port, GM_RX_CTRL);
2739 reg |= GM_RXCR_UCF_ENA;
2740
shemminger@osdl.orgd571b692005-10-26 12:16:09 -07002741 if (dev->flags & IFF_PROMISC) /* promiscuous */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002742 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002743 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002744 memset(filter, 0xff, sizeof(filter));
Stephen Hemminger793b8832005-09-14 16:06:14 -07002745 else if (dev->mc_count == 0) /* no multicast */
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002746 reg &= ~GM_RXCR_MCF_ENA;
2747 else {
2748 int i;
2749 reg |= GM_RXCR_MCF_ENA;
2750
2751 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2752 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
Stephen Hemminger793b8832005-09-14 16:06:14 -07002753 filter[bit / 8] |= 1 << (bit % 8);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002754 }
2755 }
2756
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002757 gma_write16(hw, port, GM_MC_ADDR_H1,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002758 (u16) filter[0] | ((u16) filter[1] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002759 gma_write16(hw, port, GM_MC_ADDR_H2,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002760 (u16) filter[2] | ((u16) filter[3] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002761 gma_write16(hw, port, GM_MC_ADDR_H3,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002762 (u16) filter[4] | ((u16) filter[5] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002763 gma_write16(hw, port, GM_MC_ADDR_H4,
Stephen Hemminger793b8832005-09-14 16:06:14 -07002764 (u16) filter[6] | ((u16) filter[7] << 8));
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002765
2766 gma_write16(hw, port, GM_RX_CTRL, reg);
2767}
2768
2769/* Can have one global because blinking is controlled by
2770 * ethtool and that is always under RTNL mutex
2771 */
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002772static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002773{
Stephen Hemminger793b8832005-09-14 16:06:14 -07002774 u16 pg;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002775
Stephen Hemminger793b8832005-09-14 16:06:14 -07002776 switch (hw->chip_id) {
2777 case CHIP_ID_YUKON_XL:
2778 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2779 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2780 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2781 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2782 PHY_M_LEDC_INIT_CTRL(7) |
2783 PHY_M_LEDC_STA1_CTRL(7) |
2784 PHY_M_LEDC_STA0_CTRL(7))
2785 : 0);
2786
2787 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2788 break;
2789
2790 default:
2791 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2792 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2793 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2794 PHY_M_LED_MO_10(MO_LED_ON) |
2795 PHY_M_LED_MO_100(MO_LED_ON) |
2796 PHY_M_LED_MO_1000(MO_LED_ON) |
2797 PHY_M_LED_MO_RX(MO_LED_ON)
2798 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2799 PHY_M_LED_MO_10(MO_LED_OFF) |
2800 PHY_M_LED_MO_100(MO_LED_OFF) |
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002801 PHY_M_LED_MO_1000(MO_LED_OFF) |
2802 PHY_M_LED_MO_RX(MO_LED_OFF));
2803
Stephen Hemminger793b8832005-09-14 16:06:14 -07002804 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002805}
2806
2807/* blink LED's for finding board */
2808static int sky2_phys_id(struct net_device *dev, u32 data)
2809{
2810 struct sky2_port *sky2 = netdev_priv(dev);
2811 struct sky2_hw *hw = sky2->hw;
2812 unsigned port = sky2->port;
Stephen Hemminger793b8832005-09-14 16:06:14 -07002813 u16 ledctrl, ledover = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002814 long ms;
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002815 int interrupted;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002816 int onoff = 1;
2817
Stephen Hemminger793b8832005-09-14 16:06:14 -07002818 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002819 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2820 else
2821 ms = data * 1000;
2822
2823 /* save initial values */
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002824 spin_lock_bh(&sky2->phy_lock);
Stephen Hemminger793b8832005-09-14 16:06:14 -07002825 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2826 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2827 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2828 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2829 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2830 } else {
2831 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2832 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2833 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002834
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002835 interrupted = 0;
2836 while (!interrupted && ms > 0) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002837 sky2_led(hw, port, onoff);
2838 onoff = !onoff;
2839
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002840 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002841 interrupted = msleep_interruptible(250);
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002842 spin_lock_bh(&sky2->phy_lock);
Stephen Hemminger91c86df2005-12-09 11:34:57 -08002843
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002844 ms -= 250;
2845 }
2846
2847 /* resume regularly scheduled programming */
Stephen Hemminger793b8832005-09-14 16:06:14 -07002848 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2849 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2850 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2851 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2852 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2853 } else {
2854 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2855 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2856 }
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08002857 spin_unlock_bh(&sky2->phy_lock);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002858
2859 return 0;
2860}
2861
2862static void sky2_get_pauseparam(struct net_device *dev,
2863 struct ethtool_pauseparam *ecmd)
2864{
2865 struct sky2_port *sky2 = netdev_priv(dev);
2866
2867 ecmd->tx_pause = sky2->tx_pause;
2868 ecmd->rx_pause = sky2->rx_pause;
2869 ecmd->autoneg = sky2->autoneg;
2870}
2871
2872static int sky2_set_pauseparam(struct net_device *dev,
2873 struct ethtool_pauseparam *ecmd)
2874{
2875 struct sky2_port *sky2 = netdev_priv(dev);
2876 int err = 0;
2877
2878 sky2->autoneg = ecmd->autoneg;
2879 sky2->tx_pause = ecmd->tx_pause != 0;
2880 sky2->rx_pause = ecmd->rx_pause != 0;
2881
Stephen Hemminger1b537562005-12-20 15:08:07 -08002882 sky2_phy_reinit(sky2);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07002883
2884 return err;
2885}
2886
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002887static int sky2_get_coalesce(struct net_device *dev,
2888 struct ethtool_coalesce *ecmd)
2889{
2890 struct sky2_port *sky2 = netdev_priv(dev);
2891 struct sky2_hw *hw = sky2->hw;
2892
2893 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2894 ecmd->tx_coalesce_usecs = 0;
2895 else {
2896 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2897 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2898 }
2899 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2900
2901 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2902 ecmd->rx_coalesce_usecs = 0;
2903 else {
2904 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2905 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2906 }
2907 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2908
2909 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2910 ecmd->rx_coalesce_usecs_irq = 0;
2911 else {
2912 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2913 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2914 }
2915
2916 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2917
2918 return 0;
2919}
2920
2921/* Note: this affect both ports */
2922static int sky2_set_coalesce(struct net_device *dev,
2923 struct ethtool_coalesce *ecmd)
2924{
2925 struct sky2_port *sky2 = netdev_priv(dev);
2926 struct sky2_hw *hw = sky2->hw;
Stephen Hemminger77b3d6a2006-03-20 15:48:18 -08002927 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002928
Stephen Hemminger77b3d6a2006-03-20 15:48:18 -08002929 if (ecmd->tx_coalesce_usecs > tmax ||
2930 ecmd->rx_coalesce_usecs > tmax ||
2931 ecmd->rx_coalesce_usecs_irq > tmax)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002932 return -EINVAL;
2933
Stephen Hemmingerff81fbb2006-02-22 11:44:59 -08002934 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002935 return -EINVAL;
Stephen Hemmingerff81fbb2006-02-22 11:44:59 -08002936 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002937 return -EINVAL;
Stephen Hemmingerff81fbb2006-02-22 11:44:59 -08002938 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002939 return -EINVAL;
2940
2941 if (ecmd->tx_coalesce_usecs == 0)
2942 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2943 else {
2944 sky2_write32(hw, STAT_TX_TIMER_INI,
2945 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2946 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2947 }
2948 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2949
2950 if (ecmd->rx_coalesce_usecs == 0)
2951 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2952 else {
2953 sky2_write32(hw, STAT_LEV_TIMER_INI,
2954 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2955 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2956 }
2957 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2958
2959 if (ecmd->rx_coalesce_usecs_irq == 0)
2960 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2961 else {
Stephen Hemmingerd28d4872006-01-30 11:37:56 -08002962 sky2_write32(hw, STAT_ISR_TIMER_INI,
Stephen Hemmingerfb173582005-12-09 11:34:56 -08002963 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2964 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2965 }
2966 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2967 return 0;
2968}
2969
Stephen Hemminger793b8832005-09-14 16:06:14 -07002970static void sky2_get_ringparam(struct net_device *dev,
2971 struct ethtool_ringparam *ering)
2972{
2973 struct sky2_port *sky2 = netdev_priv(dev);
2974
2975 ering->rx_max_pending = RX_MAX_PENDING;
2976 ering->rx_mini_max_pending = 0;
2977 ering->rx_jumbo_max_pending = 0;
2978 ering->tx_max_pending = TX_RING_SIZE - 1;
2979
2980 ering->rx_pending = sky2->rx_pending;
2981 ering->rx_mini_pending = 0;
2982 ering->rx_jumbo_pending = 0;
2983 ering->tx_pending = sky2->tx_pending;
2984}
2985
2986static int sky2_set_ringparam(struct net_device *dev,
2987 struct ethtool_ringparam *ering)
2988{
2989 struct sky2_port *sky2 = netdev_priv(dev);
2990 int err = 0;
2991
2992 if (ering->rx_pending > RX_MAX_PENDING ||
2993 ering->rx_pending < 8 ||
2994 ering->tx_pending < MAX_SKB_TX_LE ||
2995 ering->tx_pending > TX_RING_SIZE - 1)
2996 return -EINVAL;
2997
2998 if (netif_running(dev))
2999 sky2_down(dev);
3000
3001 sky2->rx_pending = ering->rx_pending;
3002 sky2->tx_pending = ering->tx_pending;
3003
Stephen Hemminger1b537562005-12-20 15:08:07 -08003004 if (netif_running(dev)) {
Stephen Hemminger793b8832005-09-14 16:06:14 -07003005 err = sky2_up(dev);
Stephen Hemminger1b537562005-12-20 15:08:07 -08003006 if (err)
3007 dev_close(dev);
Stephen Hemminger6ed995b2005-12-20 15:08:08 -08003008 else
3009 sky2_set_multicast(dev);
Stephen Hemminger1b537562005-12-20 15:08:07 -08003010 }
Stephen Hemminger793b8832005-09-14 16:06:14 -07003011
3012 return err;
3013}
3014
Stephen Hemminger793b8832005-09-14 16:06:14 -07003015static int sky2_get_regs_len(struct net_device *dev)
3016{
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003017 return 0x4000;
Stephen Hemminger793b8832005-09-14 16:06:14 -07003018}
3019
3020/*
3021 * Returns copy of control register region
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003022 * Note: access to the RAM address register set will cause timeouts.
Stephen Hemminger793b8832005-09-14 16:06:14 -07003023 */
3024static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3025 void *p)
3026{
3027 const struct sky2_port *sky2 = netdev_priv(dev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003028 const void __iomem *io = sky2->hw->regs;
Stephen Hemminger793b8832005-09-14 16:06:14 -07003029
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003030 BUG_ON(regs->len < B3_RI_WTO_R1);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003031 regs->version = 1;
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003032 memset(p, 0, regs->len);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003033
Stephen Hemminger6e4cbb32005-09-19 15:47:57 -07003034 memcpy_fromio(p, io, B3_RAM_ADDR);
3035
3036 memcpy_fromio(p + B3_RI_WTO_R1,
3037 io + B3_RI_WTO_R1,
3038 regs->len - B3_RI_WTO_R1);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003039}
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003040
3041static struct ethtool_ops sky2_ethtool_ops = {
Stephen Hemminger793b8832005-09-14 16:06:14 -07003042 .get_settings = sky2_get_settings,
3043 .set_settings = sky2_set_settings,
3044 .get_drvinfo = sky2_get_drvinfo,
3045 .get_msglevel = sky2_get_msglevel,
3046 .set_msglevel = sky2_set_msglevel,
Stephen Hemminger9a7ae0a2005-09-27 15:28:42 -07003047 .nway_reset = sky2_nway_reset,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003048 .get_regs_len = sky2_get_regs_len,
3049 .get_regs = sky2_get_regs,
3050 .get_link = ethtool_op_get_link,
3051 .get_sg = ethtool_op_get_sg,
3052 .set_sg = ethtool_op_set_sg,
3053 .get_tx_csum = ethtool_op_get_tx_csum,
3054 .set_tx_csum = ethtool_op_set_tx_csum,
3055 .get_tso = ethtool_op_get_tso,
3056 .set_tso = ethtool_op_set_tso,
3057 .get_rx_csum = sky2_get_rx_csum,
3058 .set_rx_csum = sky2_set_rx_csum,
3059 .get_strings = sky2_get_strings,
Stephen Hemmingerfb173582005-12-09 11:34:56 -08003060 .get_coalesce = sky2_get_coalesce,
3061 .set_coalesce = sky2_set_coalesce,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003062 .get_ringparam = sky2_get_ringparam,
3063 .set_ringparam = sky2_set_ringparam,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003064 .get_pauseparam = sky2_get_pauseparam,
3065 .set_pauseparam = sky2_set_pauseparam,
Stephen Hemminger793b8832005-09-14 16:06:14 -07003066 .phys_id = sky2_phys_id,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003067 .get_stats_count = sky2_get_stats_count,
3068 .get_ethtool_stats = sky2_get_ethtool_stats,
Stephen Hemminger2995bfb2005-09-28 10:01:03 -07003069 .get_perm_addr = ethtool_op_get_perm_addr,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003070};
3071
3072/* Initialize network device */
3073static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3074 unsigned port, int highmem)
3075{
3076 struct sky2_port *sky2;
3077 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3078
3079 if (!dev) {
3080 printk(KERN_ERR "sky2 etherdev alloc failed");
3081 return NULL;
3082 }
3083
3084 SET_MODULE_OWNER(dev);
3085 SET_NETDEV_DEV(dev, &hw->pdev->dev);
shemminger@osdl.orgef743d32005-11-30 11:45:12 -08003086 dev->irq = hw->pdev->irq;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003087 dev->open = sky2_up;
3088 dev->stop = sky2_down;
shemminger@osdl.orgef743d32005-11-30 11:45:12 -08003089 dev->do_ioctl = sky2_ioctl;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003090 dev->hard_start_xmit = sky2_xmit_frame;
3091 dev->get_stats = sky2_get_stats;
3092 dev->set_multicast_list = sky2_set_multicast;
3093 dev->set_mac_address = sky2_set_mac_address;
3094 dev->change_mtu = sky2_change_mtu;
3095 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3096 dev->tx_timeout = sky2_tx_timeout;
3097 dev->watchdog_timeo = TX_WATCHDOG;
3098 if (port == 0)
3099 dev->poll = sky2_poll;
3100 dev->weight = NAPI_WEIGHT;
3101#ifdef CONFIG_NET_POLL_CONTROLLER
3102 dev->poll_controller = sky2_netpoll;
3103#endif
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003104
3105 sky2 = netdev_priv(dev);
3106 sky2->netdev = dev;
3107 sky2->hw = hw;
3108 sky2->msg_enable = netif_msg_init(debug, default_msg);
3109
3110 spin_lock_init(&sky2->tx_lock);
3111 /* Auto speed and flow control */
3112 sky2->autoneg = AUTONEG_ENABLE;
Stephen Hemminger585b56012005-12-09 11:35:10 -08003113 sky2->tx_pause = 1;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003114 sky2->rx_pause = 1;
3115 sky2->duplex = -1;
3116 sky2->speed = -1;
3117 sky2->advertising = sky2_supported_modes(hw);
Stephen Hemmingeree7abb02006-05-18 11:16:21 -07003118 sky2->rx_csum = 1;
Stephen Hemminger75d070c2005-12-09 11:35:11 -08003119
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08003120 spin_lock_init(&sky2->phy_lock);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003121 sky2->tx_pending = TX_DEF_PENDING;
Stephen Hemminger290d4de2006-03-20 15:48:15 -08003122 sky2->rx_pending = RX_DEF_PENDING;
Stephen Hemminger734d1862005-12-09 11:35:00 -08003123 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003124
3125 hw->dev[port] = dev;
3126
3127 sky2->port = port;
3128
shemminger@osdl.org5a5b1ea2005-11-30 11:45:15 -08003129 dev->features |= NETIF_F_LLTX;
3130 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3131 dev->features |= NETIF_F_TSO;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003132 if (highmem)
3133 dev->features |= NETIF_F_HIGHDMA;
Stephen Hemminger793b8832005-09-14 16:06:14 -07003134 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003135
shemminger@osdl.orgd1f13702005-09-27 15:02:57 -07003136#ifdef SKY2_VLAN_TAG_USED
3137 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3138 dev->vlan_rx_register = sky2_vlan_rx_register;
3139 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3140#endif
3141
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003142 /* read the mac address */
Stephen Hemminger793b8832005-09-14 16:06:14 -07003143 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
Stephen Hemminger2995bfb2005-09-28 10:01:03 -07003144 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003145
3146 /* device is off until link detection */
3147 netif_carrier_off(dev);
3148 netif_stop_queue(dev);
3149
3150 return dev;
3151}
3152
Stephen Hemminger28bd1812006-01-17 13:43:19 -08003153static void __devinit sky2_show_addr(struct net_device *dev)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003154{
3155 const struct sky2_port *sky2 = netdev_priv(dev);
3156
3157 if (netif_msg_probe(sky2))
3158 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3159 dev->name,
3160 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3161 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3162}
3163
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003164/* Handle software interrupt used during MSI test */
3165static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3166 struct pt_regs *regs)
3167{
3168 struct sky2_hw *hw = dev_id;
3169 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3170
3171 if (status == 0)
3172 return IRQ_NONE;
3173
3174 if (status & Y2_IS_IRQ_SW) {
3175 hw->msi_detected = 1;
3176 wake_up(&hw->msi_wait);
3177 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3178 }
3179 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3180
3181 return IRQ_HANDLED;
3182}
3183
3184/* Test interrupt path by forcing a a software IRQ */
3185static int __devinit sky2_test_msi(struct sky2_hw *hw)
3186{
3187 struct pci_dev *pdev = hw->pdev;
3188 int err;
3189
3190 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3191
3192 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3193 if (err) {
3194 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3195 pci_name(pdev), pdev->irq);
3196 return err;
3197 }
3198
3199 init_waitqueue_head (&hw->msi_wait);
3200
3201 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3202 wmb();
3203
3204 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3205
3206 if (!hw->msi_detected) {
3207 /* MSI test failed, go back to INTx mode */
3208 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3209 "switching to INTx mode. Please report this failure to "
3210 "the PCI maintainer and include system chipset information.\n",
3211 pci_name(pdev));
3212
3213 err = -EOPNOTSUPP;
3214 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3215 }
3216
3217 sky2_write32(hw, B0_IMSK, 0);
3218
3219 free_irq(pdev->irq, hw);
3220
3221 return err;
3222}
3223
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003224static int __devinit sky2_probe(struct pci_dev *pdev,
3225 const struct pci_device_id *ent)
3226{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003227 struct net_device *dev, *dev1 = NULL;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003228 struct sky2_hw *hw;
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003229 int err, pm_cap, using_dac = 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003230
Stephen Hemminger793b8832005-09-14 16:06:14 -07003231 err = pci_enable_device(pdev);
3232 if (err) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003233 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3234 pci_name(pdev));
3235 goto err_out;
3236 }
3237
Stephen Hemminger793b8832005-09-14 16:06:14 -07003238 err = pci_request_regions(pdev, DRV_NAME);
3239 if (err) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003240 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3241 pci_name(pdev));
Stephen Hemminger793b8832005-09-14 16:06:14 -07003242 goto err_out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003243 }
3244
3245 pci_set_master(pdev);
3246
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003247 /* Find power-management capability. */
3248 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3249 if (pm_cap == 0) {
3250 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3251 "aborting.\n");
3252 err = -EIO;
3253 goto err_out_free_regions;
3254 }
3255
Stephen Hemmingerd1f3d4d2006-01-17 13:43:11 -08003256 if (sizeof(dma_addr_t) > sizeof(u32) &&
3257 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3258 using_dac = 1;
3259 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3260 if (err < 0) {
3261 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3262 "for consistent allocations\n", pci_name(pdev));
3263 goto err_out_free_regions;
3264 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003265
Stephen Hemmingerd1f3d4d2006-01-17 13:43:11 -08003266 } else {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003267 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3268 if (err) {
3269 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3270 pci_name(pdev));
3271 goto err_out_free_regions;
3272 }
3273 }
Stephen Hemmingerd1f3d4d2006-01-17 13:43:11 -08003274
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003275 err = -ENOMEM;
Stephen Hemminger6aad85d2006-01-17 13:43:18 -08003276 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003277 if (!hw) {
3278 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3279 pci_name(pdev));
3280 goto err_out_free_regions;
3281 }
3282
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003283 hw->pdev = pdev;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003284
3285 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3286 if (!hw->regs) {
3287 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3288 pci_name(pdev));
3289 goto err_out_free_hw;
3290 }
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003291 hw->pm_cap = pm_cap;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003292
Stephen Hemminger56a645c2006-02-22 11:45:02 -08003293#ifdef __BIG_ENDIAN
3294 /* byte swap descriptors in hardware */
3295 {
3296 u32 reg;
3297
3298 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3299 reg |= PCI_REV_DESC;
3300 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3301 }
3302#endif
3303
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003304 /* ring for status responses */
3305 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3306 &hw->st_dma);
3307 if (!hw->st_le)
3308 goto err_out_iounmap;
3309
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003310 err = sky2_reset(hw);
3311 if (err)
Stephen Hemminger793b8832005-09-14 16:06:14 -07003312 goto err_out_iounmap;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003313
shemminger@osdl.org5f4f9dc2005-11-30 11:45:23 -08003314 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3315 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
Stephen Hemminger92f965e2005-12-09 11:34:53 -08003316 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
Stephen Hemminger793b8832005-09-14 16:06:14 -07003317 hw->chip_id, hw->chip_rev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003318
Stephen Hemminger793b8832005-09-14 16:06:14 -07003319 dev = sky2_init_netdev(hw, 0, using_dac);
3320 if (!dev)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003321 goto err_out_free_pci;
3322
Stephen Hemminger793b8832005-09-14 16:06:14 -07003323 err = register_netdev(dev);
3324 if (err) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003325 printk(KERN_ERR PFX "%s: cannot register net device\n",
3326 pci_name(pdev));
3327 goto err_out_free_netdev;
3328 }
3329
3330 sky2_show_addr(dev);
3331
3332 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3333 if (register_netdev(dev1) == 0)
3334 sky2_show_addr(dev1);
3335 else {
3336 /* Failure to register second port need not be fatal */
Stephen Hemminger793b8832005-09-14 16:06:14 -07003337 printk(KERN_WARNING PFX
3338 "register of second port failed\n");
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003339 hw->dev[1] = NULL;
3340 free_netdev(dev1);
3341 }
3342 }
3343
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003344 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3345 err = sky2_test_msi(hw);
3346 if (err == -EOPNOTSUPP)
3347 pci_disable_msi(pdev);
3348 else if (err)
3349 goto err_out_unregister;
3350 }
3351
3352 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003353 if (err) {
3354 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3355 pci_name(pdev), pdev->irq);
3356 goto err_out_unregister;
3357 }
3358
Stephen Hemmingere07b1aa2006-03-20 15:48:17 -08003359 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003360
Stephen Hemminger01bd7562006-05-08 15:11:30 -07003361 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003362 sky2_idle_start(hw);
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07003363
Stephen Hemminger793b8832005-09-14 16:06:14 -07003364 pci_set_drvdata(pdev, hw);
3365
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003366 return 0;
3367
Stephen Hemminger793b8832005-09-14 16:06:14 -07003368err_out_unregister:
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003369 pci_disable_msi(pdev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003370 if (dev1) {
3371 unregister_netdev(dev1);
3372 free_netdev(dev1);
3373 }
3374 unregister_netdev(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003375err_out_free_netdev:
3376 free_netdev(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003377err_out_free_pci:
Stephen Hemminger793b8832005-09-14 16:06:14 -07003378 sky2_write8(hw, B0_CTST, CS_RST_SET);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003379 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3380err_out_iounmap:
3381 iounmap(hw->regs);
3382err_out_free_hw:
3383 kfree(hw);
3384err_out_free_regions:
3385 pci_release_regions(pdev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003386 pci_disable_device(pdev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003387err_out:
3388 return err;
3389}
3390
3391static void __devexit sky2_remove(struct pci_dev *pdev)
3392{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003393 struct sky2_hw *hw = pci_get_drvdata(pdev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003394 struct net_device *dev0, *dev1;
3395
Stephen Hemminger793b8832005-09-14 16:06:14 -07003396 if (!hw)
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003397 return;
3398
Stephen Hemmingerd27ed382006-04-25 10:58:51 -07003399 del_timer_sync(&hw->idle_timer);
3400
3401 sky2_write32(hw, B0_IMSK, 0);
Stephen Hemminger72cb8522006-05-08 15:11:32 -07003402 synchronize_irq(hw->pdev->irq);
3403
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003404 dev0 = hw->dev[0];
Stephen Hemminger793b8832005-09-14 16:06:14 -07003405 dev1 = hw->dev[1];
3406 if (dev1)
3407 unregister_netdev(dev1);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003408 unregister_netdev(dev0);
3409
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003410 sky2_set_power_state(hw, PCI_D3hot);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003411 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003412 sky2_write8(hw, B0_CTST, CS_RST_SET);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003413 sky2_read8(hw, B0_CTST);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003414
3415 free_irq(pdev->irq, hw);
Stephen Hemmingerfb2690a2006-03-20 15:48:19 -08003416 pci_disable_msi(pdev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003417 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003418 pci_release_regions(pdev);
3419 pci_disable_device(pdev);
Stephen Hemminger793b8832005-09-14 16:06:14 -07003420
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003421 if (dev1)
3422 free_netdev(dev1);
3423 free_netdev(dev0);
3424 iounmap(hw->regs);
3425 kfree(hw);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003426
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003427 pci_set_drvdata(pdev, NULL);
3428}
3429
3430#ifdef CONFIG_PM
3431static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3432{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003433 struct sky2_hw *hw = pci_get_drvdata(pdev);
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003434 int i;
Stephen Hemminger2ccc99b2006-06-13 17:17:27 +09003435 pci_power_t pstate = pci_choose_state(pdev, state);
3436
3437 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3438 return -EINVAL;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003439
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003440 del_timer_sync(&hw->idle_timer);
3441
Stephen Hemmingerf05267e2006-06-13 17:17:28 +09003442 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003443 struct net_device *dev = hw->dev[i];
3444
3445 if (dev) {
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003446 if (!netif_running(dev))
3447 continue;
3448
3449 sky2_down(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003450 netif_device_detach(dev);
Stephen Hemminger88d11362006-06-16 12:10:46 -07003451 netif_poll_disable(dev);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003452 }
3453 }
3454
Stephen Hemminger8ab8fca2006-06-13 17:17:30 +09003455 sky2_write32(hw, B0_IMSK, 0);
Linus Torvaldsd374c1c2006-06-12 12:53:27 -07003456 pci_save_state(pdev);
Stephen Hemminger2ccc99b2006-06-13 17:17:27 +09003457 sky2_set_power_state(hw, pstate);
3458 return 0;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003459}
3460
3461static int sky2_resume(struct pci_dev *pdev)
3462{
Stephen Hemminger793b8832005-09-14 16:06:14 -07003463 struct sky2_hw *hw = pci_get_drvdata(pdev);
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003464 int i, err;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003465
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003466 pci_restore_state(pdev);
3467 pci_enable_wake(pdev, PCI_D0, 0);
Stephen Hemminger2ccc99b2006-06-13 17:17:27 +09003468 sky2_set_power_state(hw, PCI_D0);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003469
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003470 err = sky2_reset(hw);
3471 if (err)
3472 goto out;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003473
Stephen Hemminger8ab8fca2006-06-13 17:17:30 +09003474 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3475
Stephen Hemmingerf05267e2006-06-13 17:17:28 +09003476 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003477 struct net_device *dev = hw->dev[i];
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003478 if (dev && netif_running(dev)) {
3479 netif_device_attach(dev);
Stephen Hemminger88d11362006-06-16 12:10:46 -07003480 netif_poll_enable(dev);
3481
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003482 err = sky2_up(dev);
3483 if (err) {
3484 printk(KERN_ERR PFX "%s: could not up: %d\n",
3485 dev->name, err);
3486 dev_close(dev);
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003487 goto out;
shemminger@osdl.org5afa0a92005-09-27 15:03:00 -07003488 }
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003489 }
3490 }
Stephen Hemmingereb35cf62006-06-13 17:17:31 +09003491
3492 sky2_idle_start(hw);
Stephen Hemminger08c06d82006-01-30 11:37:54 -08003493out:
3494 return err;
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003495}
3496#endif
3497
3498static struct pci_driver sky2_driver = {
Stephen Hemminger793b8832005-09-14 16:06:14 -07003499 .name = DRV_NAME,
3500 .id_table = sky2_id_table,
3501 .probe = sky2_probe,
3502 .remove = __devexit_p(sky2_remove),
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003503#ifdef CONFIG_PM
Stephen Hemminger793b8832005-09-14 16:06:14 -07003504 .suspend = sky2_suspend,
3505 .resume = sky2_resume,
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003506#endif
3507};
3508
3509static int __init sky2_init_module(void)
3510{
shemminger@osdl.org50241c42005-11-30 11:45:22 -08003511 return pci_register_driver(&sky2_driver);
Stephen Hemmingercd28ab62005-08-16 16:36:49 -07003512}
3513
3514static void __exit sky2_cleanup_module(void)
3515{
3516 pci_unregister_driver(&sky2_driver);
3517}
3518
3519module_init(sky2_init_module);
3520module_exit(sky2_cleanup_module);
3521
3522MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3523MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3524MODULE_LICENSE("GPL");
shemminger@osdl.org5f4f9dc2005-11-30 11:45:23 -08003525MODULE_VERSION(DRV_VERSION);