Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Keith Packard <keithp@keithp.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 30 | #include <linux/export.h> |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 31 | #include <linux/notifier.h> |
| 32 | #include <linux/reboot.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/drmP.h> |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 34 | #include <drm/drm_atomic_helper.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 35 | #include <drm/drm_crtc.h> |
| 36 | #include <drm/drm_crtc_helper.h> |
| 37 | #include <drm/drm_edid.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 38 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 39 | #include <drm/i915_drm.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 40 | #include "i915_drv.h" |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 41 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 42 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
| 43 | |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 44 | /* Compliance test status bits */ |
| 45 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 |
| 46 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 47 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 48 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 49 | |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 50 | struct dp_link_dpll { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 51 | int clock; |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 52 | struct dpll dpll; |
| 53 | }; |
| 54 | |
| 55 | static const struct dp_link_dpll gen4_dpll[] = { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 56 | { 162000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 57 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 58 | { 270000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 59 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
| 60 | }; |
| 61 | |
| 62 | static const struct dp_link_dpll pch_dpll[] = { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 63 | { 162000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 64 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 65 | { 270000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 66 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
| 67 | }; |
| 68 | |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 69 | static const struct dp_link_dpll vlv_dpll[] = { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 70 | { 162000, |
Chon Ming Lee | 58f6e63 | 2013-09-25 15:47:51 +0800 | [diff] [blame] | 71 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 72 | { 270000, |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 73 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
| 74 | }; |
| 75 | |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 76 | /* |
| 77 | * CHV supports eDP 1.4 that have more link rates. |
| 78 | * Below only provides the fixed rate but exclude variable rate. |
| 79 | */ |
| 80 | static const struct dp_link_dpll chv_dpll[] = { |
| 81 | /* |
| 82 | * CHV requires to program fractional division for m2. |
| 83 | * m2 is stored in fixed point format using formula below |
| 84 | * (m2_int << 22) | m2_fraction |
| 85 | */ |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 86 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 87 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 88 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 89 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 90 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 91 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
| 92 | }; |
Sonika Jindal | 637a9c6 | 2015-05-07 09:52:08 +0530 | [diff] [blame] | 93 | |
Sonika Jindal | 64987fc | 2015-05-26 17:50:13 +0530 | [diff] [blame] | 94 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
| 95 | 324000, 432000, 540000 }; |
Sonika Jindal | 637a9c6 | 2015-05-07 09:52:08 +0530 | [diff] [blame] | 96 | static const int skl_rates[] = { 162000, 216000, 270000, |
Ville Syrjälä | f4896f1 | 2015-03-12 17:10:27 +0200 | [diff] [blame] | 97 | 324000, 432000, 540000 }; |
| 98 | static const int default_rates[] = { 162000, 270000, 540000 }; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 99 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 100 | /** |
| 101 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
| 102 | * @intel_dp: DP struct |
| 103 | * |
| 104 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
| 105 | * will return true, and false otherwise. |
| 106 | */ |
| 107 | static bool is_edp(struct intel_dp *intel_dp) |
| 108 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 109 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 110 | |
| 111 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 112 | } |
| 113 | |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 114 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 115 | { |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 116 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 117 | |
| 118 | return intel_dig_port->base.base.dev; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 119 | } |
| 120 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 121 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
| 122 | { |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 123 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 124 | } |
| 125 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 126 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
Ville Syrjälä | 1e0560e | 2014-08-19 13:24:25 +0300 | [diff] [blame] | 127 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 128 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 129 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 130 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
| 131 | enum pipe pipe); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 132 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 133 | static unsigned int intel_dp_unused_lane_mask(int lane_count) |
| 134 | { |
| 135 | return ~((1 << lane_count) - 1) & 0xf; |
| 136 | } |
| 137 | |
Ville Syrjälä | ed4e9c1 | 2015-03-12 17:10:36 +0200 | [diff] [blame] | 138 | static int |
| 139 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 140 | { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 141 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 142 | |
| 143 | switch (max_link_bw) { |
| 144 | case DP_LINK_BW_1_62: |
| 145 | case DP_LINK_BW_2_7: |
Ville Syrjälä | 1db10e2 | 2015-03-12 17:10:32 +0200 | [diff] [blame] | 146 | case DP_LINK_BW_5_4: |
Imre Deak | d4eead5 | 2013-07-09 17:05:26 +0300 | [diff] [blame] | 147 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 148 | default: |
Imre Deak | d4eead5 | 2013-07-09 17:05:26 +0300 | [diff] [blame] | 149 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
| 150 | max_link_bw); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 151 | max_link_bw = DP_LINK_BW_1_62; |
| 152 | break; |
| 153 | } |
| 154 | return max_link_bw; |
| 155 | } |
| 156 | |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 157 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
| 158 | { |
| 159 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 160 | u8 source_max, sink_max; |
| 161 | |
Ville Syrjälä | ccb1a83 | 2015-12-08 19:59:38 +0200 | [diff] [blame] | 162 | source_max = intel_dig_port->max_lanes; |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 163 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
| 164 | |
| 165 | return min(source_max, sink_max); |
| 166 | } |
| 167 | |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 168 | /* |
| 169 | * The units on the numbers in the next two are... bizarre. Examples will |
| 170 | * make it clearer; this one parallels an example in the eDP spec. |
| 171 | * |
| 172 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
| 173 | * |
| 174 | * 270000 * 1 * 8 / 10 == 216000 |
| 175 | * |
| 176 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
| 177 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
| 178 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
| 179 | * 119000. At 18bpp that's 2142000 kilobits per second. |
| 180 | * |
| 181 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
| 182 | * get the result in decakilobits instead of kilobits. |
| 183 | */ |
| 184 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 185 | static int |
Keith Packard | c898261 | 2012-01-25 08:16:25 -0800 | [diff] [blame] | 186 | intel_dp_link_required(int pixel_clock, int bpp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 187 | { |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 188 | return (pixel_clock * bpp + 9) / 10; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 189 | } |
| 190 | |
| 191 | static int |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 192 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
| 193 | { |
| 194 | return (max_link_clock * max_lanes * 8) / 10; |
| 195 | } |
| 196 | |
Damien Lespiau | c19de8e | 2013-11-28 15:29:18 +0000 | [diff] [blame] | 197 | static enum drm_mode_status |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 198 | intel_dp_mode_valid(struct drm_connector *connector, |
| 199 | struct drm_display_mode *mode) |
| 200 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 201 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 202 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 203 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 204 | int target_clock = mode->clock; |
| 205 | int max_rate, mode_rate, max_lanes, max_link_clock; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 206 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 207 | if (is_edp(intel_dp) && fixed_mode) { |
| 208 | if (mode->hdisplay > fixed_mode->hdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 209 | return MODE_PANEL; |
| 210 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 211 | if (mode->vdisplay > fixed_mode->vdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 212 | return MODE_PANEL; |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 213 | |
| 214 | target_clock = fixed_mode->clock; |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 215 | } |
| 216 | |
Ville Syrjälä | 50fec21 | 2015-03-12 17:10:34 +0200 | [diff] [blame] | 217 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 218 | max_lanes = intel_dp_max_lane_count(intel_dp); |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 219 | |
| 220 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
| 221 | mode_rate = intel_dp_link_required(target_clock, 18); |
| 222 | |
| 223 | if (mode_rate > max_rate) |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 224 | return MODE_CLOCK_HIGH; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 225 | |
| 226 | if (mode->clock < 10000) |
| 227 | return MODE_CLOCK_LOW; |
| 228 | |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 229 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 230 | return MODE_H_ILLEGAL; |
| 231 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 232 | return MODE_OK; |
| 233 | } |
| 234 | |
Rodrigo Vivi | a4f1289 | 2014-11-14 08:52:27 -0800 | [diff] [blame] | 235 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 236 | { |
| 237 | int i; |
| 238 | uint32_t v = 0; |
| 239 | |
| 240 | if (src_bytes > 4) |
| 241 | src_bytes = 4; |
| 242 | for (i = 0; i < src_bytes; i++) |
| 243 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
| 244 | return v; |
| 245 | } |
| 246 | |
Damien Lespiau | c2af70e | 2015-02-10 19:32:23 +0000 | [diff] [blame] | 247 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 248 | { |
| 249 | int i; |
| 250 | if (dst_bytes > 4) |
| 251 | dst_bytes = 4; |
| 252 | for (i = 0; i < dst_bytes; i++) |
| 253 | dst[i] = src >> ((3-i) * 8); |
| 254 | } |
| 255 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 256 | static void |
| 257 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 258 | struct intel_dp *intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 259 | static void |
| 260 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 261 | struct intel_dp *intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 262 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 263 | static void pps_lock(struct intel_dp *intel_dp) |
| 264 | { |
| 265 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 266 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 267 | struct drm_device *dev = encoder->base.dev; |
| 268 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 269 | enum intel_display_power_domain power_domain; |
| 270 | |
| 271 | /* |
| 272 | * See vlv_power_sequencer_reset() why we need |
| 273 | * a power domain reference here. |
| 274 | */ |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 275 | power_domain = intel_display_port_aux_power_domain(encoder); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 276 | intel_display_power_get(dev_priv, power_domain); |
| 277 | |
| 278 | mutex_lock(&dev_priv->pps_mutex); |
| 279 | } |
| 280 | |
| 281 | static void pps_unlock(struct intel_dp *intel_dp) |
| 282 | { |
| 283 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 284 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 285 | struct drm_device *dev = encoder->base.dev; |
| 286 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 287 | enum intel_display_power_domain power_domain; |
| 288 | |
| 289 | mutex_unlock(&dev_priv->pps_mutex); |
| 290 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 291 | power_domain = intel_display_port_aux_power_domain(encoder); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 292 | intel_display_power_put(dev_priv, power_domain); |
| 293 | } |
| 294 | |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 295 | static void |
| 296 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
| 297 | { |
| 298 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 299 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 300 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 301 | enum pipe pipe = intel_dp->pps_pipe; |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 302 | bool pll_enabled, release_cl_override = false; |
| 303 | enum dpio_phy phy = DPIO_PHY(pipe); |
| 304 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 305 | uint32_t DP; |
| 306 | |
| 307 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, |
| 308 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", |
| 309 | pipe_name(pipe), port_name(intel_dig_port->port))) |
| 310 | return; |
| 311 | |
| 312 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", |
| 313 | pipe_name(pipe), port_name(intel_dig_port->port)); |
| 314 | |
| 315 | /* Preserve the BIOS-computed detected bit. This is |
| 316 | * supposed to be read-only. |
| 317 | */ |
| 318 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
| 319 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
| 320 | DP |= DP_PORT_WIDTH(1); |
| 321 | DP |= DP_LINK_TRAIN_PAT_1; |
| 322 | |
| 323 | if (IS_CHERRYVIEW(dev)) |
| 324 | DP |= DP_PIPE_SELECT_CHV(pipe); |
| 325 | else if (pipe == PIPE_B) |
| 326 | DP |= DP_PIPEB_SELECT; |
| 327 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 328 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
| 329 | |
| 330 | /* |
| 331 | * The DPLL for the pipe must be enabled for this to work. |
| 332 | * So enable temporarily it if it's not already enabled. |
| 333 | */ |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 334 | if (!pll_enabled) { |
| 335 | release_cl_override = IS_CHERRYVIEW(dev) && |
| 336 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
| 337 | |
Tvrtko Ursulin | 3f36b93 | 2016-01-19 15:25:17 +0000 | [diff] [blame] | 338 | if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
| 339 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
| 340 | DRM_ERROR("Failed to force on pll for pipe %c!\n", |
| 341 | pipe_name(pipe)); |
| 342 | return; |
| 343 | } |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 344 | } |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 345 | |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 346 | /* |
| 347 | * Similar magic as in intel_dp_enable_port(). |
| 348 | * We _must_ do this port enable + disable trick |
| 349 | * to make this power seqeuencer lock onto the port. |
| 350 | * Otherwise even VDD force bit won't work. |
| 351 | */ |
| 352 | I915_WRITE(intel_dp->output_reg, DP); |
| 353 | POSTING_READ(intel_dp->output_reg); |
| 354 | |
| 355 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); |
| 356 | POSTING_READ(intel_dp->output_reg); |
| 357 | |
| 358 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
| 359 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 360 | |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 361 | if (!pll_enabled) { |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 362 | vlv_force_pll_off(dev, pipe); |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 363 | |
| 364 | if (release_cl_override) |
| 365 | chv_phy_powergate_ch(dev_priv, phy, ch, false); |
| 366 | } |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 367 | } |
| 368 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 369 | static enum pipe |
| 370 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
| 371 | { |
| 372 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 373 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 374 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 375 | struct intel_encoder *encoder; |
| 376 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 377 | enum pipe pipe; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 378 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 379 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 380 | |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 381 | /* We should never land here with regular DP ports */ |
| 382 | WARN_ON(!is_edp(intel_dp)); |
| 383 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 384 | if (intel_dp->pps_pipe != INVALID_PIPE) |
| 385 | return intel_dp->pps_pipe; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 386 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 387 | /* |
| 388 | * We don't have power sequencer currently. |
| 389 | * Pick one that's not used by other ports. |
| 390 | */ |
Jani Nikula | 19c8054 | 2015-12-16 12:48:16 +0200 | [diff] [blame] | 391 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 392 | struct intel_dp *tmp; |
| 393 | |
| 394 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 395 | continue; |
| 396 | |
| 397 | tmp = enc_to_intel_dp(&encoder->base); |
| 398 | |
| 399 | if (tmp->pps_pipe != INVALID_PIPE) |
| 400 | pipes &= ~(1 << tmp->pps_pipe); |
| 401 | } |
| 402 | |
| 403 | /* |
| 404 | * Didn't find one. This should not happen since there |
| 405 | * are two power sequencers and up to two eDP ports. |
| 406 | */ |
| 407 | if (WARN_ON(pipes == 0)) |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 408 | pipe = PIPE_A; |
| 409 | else |
| 410 | pipe = ffs(pipes) - 1; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 411 | |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 412 | vlv_steal_power_sequencer(dev, pipe); |
| 413 | intel_dp->pps_pipe = pipe; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 414 | |
| 415 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", |
| 416 | pipe_name(intel_dp->pps_pipe), |
| 417 | port_name(intel_dig_port->port)); |
| 418 | |
| 419 | /* init power sequencer on this pipe and port */ |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 420 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 421 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 422 | |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 423 | /* |
| 424 | * Even vdd force doesn't work until we've made |
| 425 | * the power sequencer lock in on the port. |
| 426 | */ |
| 427 | vlv_power_sequencer_kick(intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 428 | |
| 429 | return intel_dp->pps_pipe; |
| 430 | } |
| 431 | |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 432 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
| 433 | enum pipe pipe); |
| 434 | |
| 435 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, |
| 436 | enum pipe pipe) |
| 437 | { |
| 438 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; |
| 439 | } |
| 440 | |
| 441 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, |
| 442 | enum pipe pipe) |
| 443 | { |
| 444 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
| 445 | } |
| 446 | |
| 447 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, |
| 448 | enum pipe pipe) |
| 449 | { |
| 450 | return true; |
| 451 | } |
| 452 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 453 | static enum pipe |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 454 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
| 455 | enum port port, |
| 456 | vlv_pipe_check pipe_check) |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 457 | { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 458 | enum pipe pipe; |
| 459 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 460 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
| 461 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
| 462 | PANEL_PORT_SELECT_MASK; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 463 | |
| 464 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) |
| 465 | continue; |
| 466 | |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 467 | if (!pipe_check(dev_priv, pipe)) |
| 468 | continue; |
| 469 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 470 | return pipe; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 471 | } |
| 472 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 473 | return INVALID_PIPE; |
| 474 | } |
| 475 | |
| 476 | static void |
| 477 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
| 478 | { |
| 479 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 480 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 481 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 482 | enum port port = intel_dig_port->port; |
| 483 | |
| 484 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 485 | |
| 486 | /* try to find a pipe with this port selected */ |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 487 | /* first pick one where the panel is on */ |
| 488 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 489 | vlv_pipe_has_pp_on); |
| 490 | /* didn't find one? pick one where vdd is on */ |
| 491 | if (intel_dp->pps_pipe == INVALID_PIPE) |
| 492 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 493 | vlv_pipe_has_vdd_on); |
| 494 | /* didn't find one? pick one with just the correct port */ |
| 495 | if (intel_dp->pps_pipe == INVALID_PIPE) |
| 496 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 497 | vlv_pipe_any); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 498 | |
| 499 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
| 500 | if (intel_dp->pps_pipe == INVALID_PIPE) { |
| 501 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", |
| 502 | port_name(port)); |
| 503 | return; |
| 504 | } |
| 505 | |
| 506 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
| 507 | port_name(port), pipe_name(intel_dp->pps_pipe)); |
| 508 | |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 509 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 510 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 511 | } |
| 512 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 513 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
| 514 | { |
| 515 | struct drm_device *dev = dev_priv->dev; |
| 516 | struct intel_encoder *encoder; |
| 517 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 518 | if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))) |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 519 | return; |
| 520 | |
| 521 | /* |
| 522 | * We can't grab pps_mutex here due to deadlock with power_domain |
| 523 | * mutex when power_domain functions are called while holding pps_mutex. |
| 524 | * That also means that in order to use pps_pipe the code needs to |
| 525 | * hold both a power domain reference and pps_mutex, and the power domain |
| 526 | * reference get/put must be done while _not_ holding pps_mutex. |
| 527 | * pps_{lock,unlock}() do these steps in the correct order, so one |
| 528 | * should use them always. |
| 529 | */ |
| 530 | |
Jani Nikula | 19c8054 | 2015-12-16 12:48:16 +0200 | [diff] [blame] | 531 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 532 | struct intel_dp *intel_dp; |
| 533 | |
| 534 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 535 | continue; |
| 536 | |
| 537 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 538 | intel_dp->pps_pipe = INVALID_PIPE; |
| 539 | } |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 540 | } |
| 541 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 542 | static i915_reg_t |
| 543 | _pp_ctrl_reg(struct intel_dp *intel_dp) |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 544 | { |
| 545 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 546 | |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 547 | if (IS_BROXTON(dev)) |
| 548 | return BXT_PP_CONTROL(0); |
| 549 | else if (HAS_PCH_SPLIT(dev)) |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 550 | return PCH_PP_CONTROL; |
| 551 | else |
| 552 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
| 553 | } |
| 554 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 555 | static i915_reg_t |
| 556 | _pp_stat_reg(struct intel_dp *intel_dp) |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 557 | { |
| 558 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 559 | |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 560 | if (IS_BROXTON(dev)) |
| 561 | return BXT_PP_STATUS(0); |
| 562 | else if (HAS_PCH_SPLIT(dev)) |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 563 | return PCH_PP_STATUS; |
| 564 | else |
| 565 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
| 566 | } |
| 567 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 568 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
| 569 | This function only applicable when panel PM state is not to be tracked */ |
| 570 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
| 571 | void *unused) |
| 572 | { |
| 573 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), |
| 574 | edp_notifier); |
| 575 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 576 | struct drm_i915_private *dev_priv = dev->dev_private; |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 577 | |
| 578 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
| 579 | return 0; |
| 580 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 581 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 582 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 583 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 584 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 585 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 586 | u32 pp_div; |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 587 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 588 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
| 589 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
| 590 | pp_div = I915_READ(pp_div_reg); |
| 591 | pp_div &= PP_REFERENCE_DIVIDER_MASK; |
| 592 | |
| 593 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
| 594 | I915_WRITE(pp_div_reg, pp_div | 0x1F); |
| 595 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
| 596 | msleep(intel_dp->panel_power_cycle_delay); |
| 597 | } |
| 598 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 599 | pps_unlock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 600 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 601 | return 0; |
| 602 | } |
| 603 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 604 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 605 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 606 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 607 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 608 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 609 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 610 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 611 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
Ville Syrjälä | 9a42356 | 2014-10-16 21:29:48 +0300 | [diff] [blame] | 612 | intel_dp->pps_pipe == INVALID_PIPE) |
| 613 | return false; |
| 614 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 615 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 616 | } |
| 617 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 618 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 619 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 620 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 621 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 622 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 623 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 624 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 625 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
Ville Syrjälä | 9a42356 | 2014-10-16 21:29:48 +0300 | [diff] [blame] | 626 | intel_dp->pps_pipe == INVALID_PIPE) |
| 627 | return false; |
| 628 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 629 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 630 | } |
| 631 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 632 | static void |
| 633 | intel_dp_check_edp(struct intel_dp *intel_dp) |
| 634 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 635 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 636 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 637 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 638 | if (!is_edp(intel_dp)) |
| 639 | return; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 640 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 641 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 642 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
| 643 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 644 | I915_READ(_pp_stat_reg(intel_dp)), |
| 645 | I915_READ(_pp_ctrl_reg(intel_dp))); |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 646 | } |
| 647 | } |
| 648 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 649 | static uint32_t |
| 650 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
| 651 | { |
| 652 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 653 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 654 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 655 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 656 | uint32_t status; |
| 657 | bool done; |
| 658 | |
Daniel Vetter | ef04f00 | 2012-12-01 21:03:59 +0100 | [diff] [blame] | 659 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 660 | if (has_aux_irq) |
Paulo Zanoni | b18ac46 | 2013-02-18 19:00:24 -0300 | [diff] [blame] | 661 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
Imre Deak | 3598706 | 2013-05-21 20:03:20 +0300 | [diff] [blame] | 662 | msecs_to_jiffies_timeout(10)); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 663 | else |
| 664 | done = wait_for_atomic(C, 10) == 0; |
| 665 | if (!done) |
| 666 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
| 667 | has_aux_irq); |
| 668 | #undef C |
| 669 | |
| 670 | return status; |
| 671 | } |
| 672 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 673 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 674 | { |
| 675 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 676 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 677 | |
| 678 | /* |
| 679 | * The clock divider is based off the hrawclk, and would like to run at |
| 680 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
| 681 | */ |
Ville Syrjälä | fce18c4 | 2015-11-30 16:23:46 +0200 | [diff] [blame] | 682 | return index ? 0 : DIV_ROUND_CLOSEST(intel_hrawclk(dev), 2); |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 683 | } |
| 684 | |
| 685 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 686 | { |
| 687 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 688 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Ville Syrjälä | 469d4b2 | 2015-03-31 14:11:59 +0300 | [diff] [blame] | 689 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 690 | |
| 691 | if (index) |
| 692 | return 0; |
| 693 | |
| 694 | if (intel_dig_port->port == PORT_A) { |
Ville Syrjälä | fce18c4 | 2015-11-30 16:23:46 +0200 | [diff] [blame] | 695 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
Ville Syrjälä | 05024da | 2015-06-03 15:45:08 +0300 | [diff] [blame] | 696 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 697 | } else { |
Ville Syrjälä | fce18c4 | 2015-11-30 16:23:46 +0200 | [diff] [blame] | 698 | return DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2); |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 699 | } |
| 700 | } |
| 701 | |
| 702 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 703 | { |
| 704 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 705 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 706 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 707 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 708 | if (intel_dig_port->port == PORT_A) { |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 709 | if (index) |
| 710 | return 0; |
Ville Syrjälä | 05024da | 2015-06-03 15:45:08 +0300 | [diff] [blame] | 711 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
Ville Syrjälä | 56f5f70 | 2015-11-30 16:23:44 +0200 | [diff] [blame] | 712 | } else if (HAS_PCH_LPT_H(dev_priv)) { |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 713 | /* Workaround for non-ULT HSW */ |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 714 | switch (index) { |
| 715 | case 0: return 63; |
| 716 | case 1: return 72; |
| 717 | default: return 0; |
| 718 | } |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 719 | } else { |
Ville Syrjälä | fce18c4 | 2015-11-30 16:23:46 +0200 | [diff] [blame] | 720 | return index ? 0 : DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2); |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 721 | } |
| 722 | } |
| 723 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 724 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 725 | { |
| 726 | return index ? 0 : 100; |
| 727 | } |
| 728 | |
Damien Lespiau | b6b5e38 | 2014-01-20 16:00:59 +0000 | [diff] [blame] | 729 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 730 | { |
| 731 | /* |
| 732 | * SKL doesn't need us to program the AUX clock divider (Hardware will |
| 733 | * derive the clock from CDCLK automatically). We still implement the |
| 734 | * get_aux_clock_divider vfunc to plug-in into the existing code. |
| 735 | */ |
| 736 | return index ? 0 : 1; |
| 737 | } |
| 738 | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 739 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 740 | bool has_aux_irq, |
| 741 | int send_bytes, |
| 742 | uint32_t aux_clock_divider) |
| 743 | { |
| 744 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 745 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 746 | uint32_t precharge, timeout; |
| 747 | |
| 748 | if (IS_GEN6(dev)) |
| 749 | precharge = 3; |
| 750 | else |
| 751 | precharge = 5; |
| 752 | |
Ville Syrjälä | f3c6a3a | 2015-11-11 20:34:10 +0200 | [diff] [blame] | 753 | if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 754 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
| 755 | else |
| 756 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
| 757 | |
| 758 | return DP_AUX_CH_CTL_SEND_BUSY | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 759 | DP_AUX_CH_CTL_DONE | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 760 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 761 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 762 | timeout | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 763 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 764 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 765 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 766 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 767 | } |
| 768 | |
Damien Lespiau | b9ca5fa | 2014-01-20 16:01:00 +0000 | [diff] [blame] | 769 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 770 | bool has_aux_irq, |
| 771 | int send_bytes, |
| 772 | uint32_t unused) |
| 773 | { |
| 774 | return DP_AUX_CH_CTL_SEND_BUSY | |
| 775 | DP_AUX_CH_CTL_DONE | |
| 776 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
| 777 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 778 | DP_AUX_CH_CTL_TIME_OUT_1600us | |
| 779 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
| 780 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 781 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
| 782 | } |
| 783 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 784 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 785 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
Daniel Vetter | bd9f74a | 2014-10-02 09:45:35 +0200 | [diff] [blame] | 786 | const uint8_t *send, int send_bytes, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 787 | uint8_t *recv, int recv_size) |
| 788 | { |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 789 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 790 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 791 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 792 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 793 | uint32_t aux_clock_divider; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 794 | int i, ret, recv_bytes; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 795 | uint32_t status; |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 796 | int try, clock = 0; |
Daniel Vetter | 4e6b788 | 2014-02-07 16:33:20 +0100 | [diff] [blame] | 797 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
Jani Nikula | 884f19e | 2014-03-14 16:51:14 +0200 | [diff] [blame] | 798 | bool vdd; |
| 799 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 800 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 801 | |
Ville Syrjälä | 72c3500 | 2014-08-18 22:16:00 +0300 | [diff] [blame] | 802 | /* |
| 803 | * We will be called with VDD already enabled for dpcd/edid/oui reads. |
| 804 | * In such cases we want to leave VDD enabled and it's up to upper layers |
| 805 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
| 806 | * ourselves. |
| 807 | */ |
Ville Syrjälä | 1e0560e | 2014-08-19 13:24:25 +0300 | [diff] [blame] | 808 | vdd = edp_panel_vdd_on(intel_dp); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 809 | |
| 810 | /* dp aux is extremely sensitive to irq latency, hence request the |
| 811 | * lowest possible wakeup latency and so prevent the cpu from going into |
| 812 | * deep sleep states. |
| 813 | */ |
| 814 | pm_qos_update_request(&dev_priv->pm_qos, 0); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 815 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 816 | intel_dp_check_edp(intel_dp); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 817 | |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 818 | /* Try to wait for any previous AUX channel activity */ |
| 819 | for (try = 0; try < 3; try++) { |
Daniel Vetter | ef04f00 | 2012-12-01 21:03:59 +0100 | [diff] [blame] | 820 | status = I915_READ_NOTRACE(ch_ctl); |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 821 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 822 | break; |
| 823 | msleep(1); |
| 824 | } |
| 825 | |
| 826 | if (try == 3) { |
Mika Kuoppala | 02196c7 | 2015-08-06 16:48:58 +0300 | [diff] [blame] | 827 | static u32 last_status = -1; |
| 828 | const u32 status = I915_READ(ch_ctl); |
| 829 | |
| 830 | if (status != last_status) { |
| 831 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
| 832 | status); |
| 833 | last_status = status; |
| 834 | } |
| 835 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 836 | ret = -EBUSY; |
| 837 | goto out; |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 838 | } |
| 839 | |
Paulo Zanoni | 46a5ae9 | 2013-09-17 11:14:10 -0300 | [diff] [blame] | 840 | /* Only 5 data registers! */ |
| 841 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
| 842 | ret = -E2BIG; |
| 843 | goto out; |
| 844 | } |
| 845 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 846 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
Damien Lespiau | 153b110 | 2014-01-21 13:37:15 +0000 | [diff] [blame] | 847 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
| 848 | has_aux_irq, |
| 849 | send_bytes, |
| 850 | aux_clock_divider); |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 851 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 852 | /* Must try at least 3 times according to DP spec */ |
| 853 | for (try = 0; try < 5; try++) { |
| 854 | /* Load the send data into the aux channel data registers */ |
| 855 | for (i = 0; i < send_bytes; i += 4) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 856 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
Rodrigo Vivi | a4f1289 | 2014-11-14 08:52:27 -0800 | [diff] [blame] | 857 | intel_dp_pack_aux(send + i, |
| 858 | send_bytes - i)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 859 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 860 | /* Send the command and wait for it to complete */ |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 861 | I915_WRITE(ch_ctl, send_ctl); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 862 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 863 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 864 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 865 | /* Clear done status and any errors */ |
| 866 | I915_WRITE(ch_ctl, |
| 867 | status | |
| 868 | DP_AUX_CH_CTL_DONE | |
| 869 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 870 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
Adam Jackson | d7e96fe | 2011-07-26 15:39:46 -0400 | [diff] [blame] | 871 | |
Todd Previte | 74ebf29 | 2015-04-15 08:38:41 -0700 | [diff] [blame] | 872 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 873 | continue; |
Todd Previte | 74ebf29 | 2015-04-15 08:38:41 -0700 | [diff] [blame] | 874 | |
| 875 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
| 876 | * 400us delay required for errors and timeouts |
| 877 | * Timeout errors from the HW already meet this |
| 878 | * requirement so skip to next iteration |
| 879 | */ |
| 880 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
| 881 | usleep_range(400, 500); |
| 882 | continue; |
| 883 | } |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 884 | if (status & DP_AUX_CH_CTL_DONE) |
Jim Bride | e058c94 | 2015-05-27 10:21:48 -0700 | [diff] [blame] | 885 | goto done; |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 886 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 887 | } |
| 888 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 889 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 890 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 891 | ret = -EBUSY; |
| 892 | goto out; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 893 | } |
| 894 | |
Jim Bride | e058c94 | 2015-05-27 10:21:48 -0700 | [diff] [blame] | 895 | done: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 896 | /* Check for timeout or receive error. |
| 897 | * Timeouts occur when the sink is not connected |
| 898 | */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 899 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 900 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 901 | ret = -EIO; |
| 902 | goto out; |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 903 | } |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 904 | |
| 905 | /* Timeouts occur when the device isn't connected, so they're |
| 906 | * "normal" -- don't fill the kernel log with these */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 907 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 908 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 909 | ret = -ETIMEDOUT; |
| 910 | goto out; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 911 | } |
| 912 | |
| 913 | /* Unload any bytes sent back from the other side */ |
| 914 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
| 915 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
Rodrigo Vivi | 14e0188 | 2015-12-10 11:12:27 -0800 | [diff] [blame] | 916 | |
| 917 | /* |
| 918 | * By BSpec: "Message sizes of 0 or >20 are not allowed." |
| 919 | * We have no idea of what happened so we return -EBUSY so |
| 920 | * drm layer takes care for the necessary retries. |
| 921 | */ |
| 922 | if (recv_bytes == 0 || recv_bytes > 20) { |
| 923 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", |
| 924 | recv_bytes); |
| 925 | /* |
| 926 | * FIXME: This patch was created on top of a series that |
| 927 | * organize the retries at drm level. There EBUSY should |
| 928 | * also take care for 1ms wait before retrying. |
| 929 | * That aux retries re-org is still needed and after that is |
| 930 | * merged we remove this sleep from here. |
| 931 | */ |
| 932 | usleep_range(1000, 1500); |
| 933 | ret = -EBUSY; |
| 934 | goto out; |
| 935 | } |
| 936 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 937 | if (recv_bytes > recv_size) |
| 938 | recv_bytes = recv_size; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 939 | |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 940 | for (i = 0; i < recv_bytes; i += 4) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 941 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
Rodrigo Vivi | a4f1289 | 2014-11-14 08:52:27 -0800 | [diff] [blame] | 942 | recv + i, recv_bytes - i); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 943 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 944 | ret = recv_bytes; |
| 945 | out: |
| 946 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
| 947 | |
Jani Nikula | 884f19e | 2014-03-14 16:51:14 +0200 | [diff] [blame] | 948 | if (vdd) |
| 949 | edp_panel_vdd_off(intel_dp, false); |
| 950 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 951 | pps_unlock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 952 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 953 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 954 | } |
| 955 | |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 956 | #define BARE_ADDRESS_SIZE 3 |
| 957 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 958 | static ssize_t |
| 959 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 960 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 961 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
| 962 | uint8_t txbuf[20], rxbuf[20]; |
| 963 | size_t txsize, rxsize; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 964 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 965 | |
Ville Syrjälä | d2d9cbb | 2015-03-19 11:44:06 +0200 | [diff] [blame] | 966 | txbuf[0] = (msg->request << 4) | |
| 967 | ((msg->address >> 16) & 0xf); |
| 968 | txbuf[1] = (msg->address >> 8) & 0xff; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 969 | txbuf[2] = msg->address & 0xff; |
| 970 | txbuf[3] = msg->size - 1; |
Paulo Zanoni | 46a5ae9 | 2013-09-17 11:14:10 -0300 | [diff] [blame] | 971 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 972 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
| 973 | case DP_AUX_NATIVE_WRITE: |
| 974 | case DP_AUX_I2C_WRITE: |
Ville Syrjälä | c1e74122 | 2015-08-27 17:23:27 +0300 | [diff] [blame] | 975 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 976 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
Jani Nikula | a1ddefd | 2015-03-17 17:18:54 +0200 | [diff] [blame] | 977 | rxsize = 2; /* 0 or 1 data bytes */ |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 978 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 979 | if (WARN_ON(txsize > 20)) |
| 980 | return -E2BIG; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 981 | |
Imre Deak | d81a67c | 2016-01-29 14:52:26 +0200 | [diff] [blame] | 982 | if (msg->buffer) |
| 983 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
| 984 | else |
| 985 | WARN_ON(msg->size); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 986 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 987 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
| 988 | if (ret > 0) { |
| 989 | msg->reply = rxbuf[0] >> 4; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 990 | |
Jani Nikula | a1ddefd | 2015-03-17 17:18:54 +0200 | [diff] [blame] | 991 | if (ret > 1) { |
| 992 | /* Number of bytes written in a short write. */ |
| 993 | ret = clamp_t(int, rxbuf[1], 0, msg->size); |
| 994 | } else { |
| 995 | /* Return payload size. */ |
| 996 | ret = msg->size; |
| 997 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 998 | } |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 999 | break; |
| 1000 | |
| 1001 | case DP_AUX_NATIVE_READ: |
| 1002 | case DP_AUX_I2C_READ: |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 1003 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1004 | rxsize = msg->size + 1; |
| 1005 | |
| 1006 | if (WARN_ON(rxsize > 20)) |
| 1007 | return -E2BIG; |
| 1008 | |
| 1009 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
| 1010 | if (ret > 0) { |
| 1011 | msg->reply = rxbuf[0] >> 4; |
| 1012 | /* |
| 1013 | * Assume happy day, and copy the data. The caller is |
| 1014 | * expected to check msg->reply before touching it. |
| 1015 | * |
| 1016 | * Return payload size. |
| 1017 | */ |
| 1018 | ret--; |
| 1019 | memcpy(msg->buffer, rxbuf + 1, ret); |
| 1020 | } |
| 1021 | break; |
| 1022 | |
| 1023 | default: |
| 1024 | ret = -EINVAL; |
| 1025 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1026 | } |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 1027 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1028 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1029 | } |
| 1030 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1031 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1032 | enum port port) |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1033 | { |
| 1034 | switch (port) { |
| 1035 | case PORT_B: |
| 1036 | case PORT_C: |
| 1037 | case PORT_D: |
| 1038 | return DP_AUX_CH_CTL(port); |
| 1039 | default: |
| 1040 | MISSING_CASE(port); |
| 1041 | return DP_AUX_CH_CTL(PORT_B); |
| 1042 | } |
| 1043 | } |
| 1044 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1045 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1046 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1047 | { |
| 1048 | switch (port) { |
| 1049 | case PORT_B: |
| 1050 | case PORT_C: |
| 1051 | case PORT_D: |
| 1052 | return DP_AUX_CH_DATA(port, index); |
| 1053 | default: |
| 1054 | MISSING_CASE(port); |
| 1055 | return DP_AUX_CH_DATA(PORT_B, index); |
| 1056 | } |
| 1057 | } |
| 1058 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1059 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1060 | enum port port) |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1061 | { |
| 1062 | switch (port) { |
| 1063 | case PORT_A: |
| 1064 | return DP_AUX_CH_CTL(port); |
| 1065 | case PORT_B: |
| 1066 | case PORT_C: |
| 1067 | case PORT_D: |
| 1068 | return PCH_DP_AUX_CH_CTL(port); |
| 1069 | default: |
| 1070 | MISSING_CASE(port); |
| 1071 | return DP_AUX_CH_CTL(PORT_A); |
| 1072 | } |
| 1073 | } |
| 1074 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1075 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1076 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1077 | { |
| 1078 | switch (port) { |
| 1079 | case PORT_A: |
| 1080 | return DP_AUX_CH_DATA(port, index); |
| 1081 | case PORT_B: |
| 1082 | case PORT_C: |
| 1083 | case PORT_D: |
| 1084 | return PCH_DP_AUX_CH_DATA(port, index); |
| 1085 | default: |
| 1086 | MISSING_CASE(port); |
| 1087 | return DP_AUX_CH_DATA(PORT_A, index); |
| 1088 | } |
| 1089 | } |
| 1090 | |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1091 | /* |
| 1092 | * On SKL we don't have Aux for port E so we rely |
| 1093 | * on VBT to set a proper alternate aux channel. |
| 1094 | */ |
| 1095 | static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv) |
| 1096 | { |
| 1097 | const struct ddi_vbt_port_info *info = |
| 1098 | &dev_priv->vbt.ddi_port_info[PORT_E]; |
| 1099 | |
| 1100 | switch (info->alternate_aux_channel) { |
| 1101 | case DP_AUX_A: |
| 1102 | return PORT_A; |
| 1103 | case DP_AUX_B: |
| 1104 | return PORT_B; |
| 1105 | case DP_AUX_C: |
| 1106 | return PORT_C; |
| 1107 | case DP_AUX_D: |
| 1108 | return PORT_D; |
| 1109 | default: |
| 1110 | MISSING_CASE(info->alternate_aux_channel); |
| 1111 | return PORT_A; |
| 1112 | } |
| 1113 | } |
| 1114 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1115 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1116 | enum port port) |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1117 | { |
| 1118 | if (port == PORT_E) |
| 1119 | port = skl_porte_aux_port(dev_priv); |
| 1120 | |
| 1121 | switch (port) { |
| 1122 | case PORT_A: |
| 1123 | case PORT_B: |
| 1124 | case PORT_C: |
| 1125 | case PORT_D: |
| 1126 | return DP_AUX_CH_CTL(port); |
| 1127 | default: |
| 1128 | MISSING_CASE(port); |
| 1129 | return DP_AUX_CH_CTL(PORT_A); |
| 1130 | } |
| 1131 | } |
| 1132 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1133 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1134 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1135 | { |
| 1136 | if (port == PORT_E) |
| 1137 | port = skl_porte_aux_port(dev_priv); |
| 1138 | |
| 1139 | switch (port) { |
| 1140 | case PORT_A: |
| 1141 | case PORT_B: |
| 1142 | case PORT_C: |
| 1143 | case PORT_D: |
| 1144 | return DP_AUX_CH_DATA(port, index); |
| 1145 | default: |
| 1146 | MISSING_CASE(port); |
| 1147 | return DP_AUX_CH_DATA(PORT_A, index); |
| 1148 | } |
| 1149 | } |
| 1150 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1151 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1152 | enum port port) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1153 | { |
| 1154 | if (INTEL_INFO(dev_priv)->gen >= 9) |
| 1155 | return skl_aux_ctl_reg(dev_priv, port); |
| 1156 | else if (HAS_PCH_SPLIT(dev_priv)) |
| 1157 | return ilk_aux_ctl_reg(dev_priv, port); |
| 1158 | else |
| 1159 | return g4x_aux_ctl_reg(dev_priv, port); |
| 1160 | } |
| 1161 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1162 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1163 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1164 | { |
| 1165 | if (INTEL_INFO(dev_priv)->gen >= 9) |
| 1166 | return skl_aux_data_reg(dev_priv, port, index); |
| 1167 | else if (HAS_PCH_SPLIT(dev_priv)) |
| 1168 | return ilk_aux_data_reg(dev_priv, port, index); |
| 1169 | else |
| 1170 | return g4x_aux_data_reg(dev_priv, port, index); |
| 1171 | } |
| 1172 | |
| 1173 | static void intel_aux_reg_init(struct intel_dp *intel_dp) |
| 1174 | { |
| 1175 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
| 1176 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1177 | int i; |
| 1178 | |
| 1179 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); |
| 1180 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) |
| 1181 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); |
| 1182 | } |
| 1183 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1184 | static void |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1185 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
| 1186 | { |
| 1187 | drm_dp_aux_unregister(&intel_dp->aux); |
| 1188 | kfree(intel_dp->aux.name); |
| 1189 | } |
| 1190 | |
| 1191 | static int |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1192 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1193 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1194 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jani Nikula | 33ad662 | 2014-03-14 16:51:16 +0200 | [diff] [blame] | 1195 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1196 | enum port port = intel_dig_port->port; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 1197 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1198 | |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1199 | intel_aux_reg_init(intel_dp); |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 1200 | |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1201 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
| 1202 | if (!intel_dp->aux.name) |
| 1203 | return -ENOMEM; |
| 1204 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1205 | intel_dp->aux.dev = dev->dev; |
| 1206 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 1207 | |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1208 | DRM_DEBUG_KMS("registering %s bus for %s\n", |
| 1209 | intel_dp->aux.name, |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 1210 | connector->base.kdev->kobj.name); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1211 | |
Dave Airlie | 4f71d0c | 2014-06-04 16:02:28 +1000 | [diff] [blame] | 1212 | ret = drm_dp_aux_register(&intel_dp->aux); |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 1213 | if (ret < 0) { |
Dave Airlie | 4f71d0c | 2014-06-04 16:02:28 +1000 | [diff] [blame] | 1214 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1215 | intel_dp->aux.name, ret); |
| 1216 | kfree(intel_dp->aux.name); |
| 1217 | return ret; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 1218 | } |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 1219 | |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 1220 | ret = sysfs_create_link(&connector->base.kdev->kobj, |
| 1221 | &intel_dp->aux.ddc.dev.kobj, |
| 1222 | intel_dp->aux.ddc.dev.kobj.name); |
| 1223 | if (ret < 0) { |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1224 | DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", |
| 1225 | intel_dp->aux.name, ret); |
| 1226 | intel_dp_aux_fini(intel_dp); |
| 1227 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1228 | } |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1229 | |
| 1230 | return 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1231 | } |
| 1232 | |
Imre Deak | 80f65de | 2014-02-11 17:12:49 +0200 | [diff] [blame] | 1233 | static void |
| 1234 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
| 1235 | { |
| 1236 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
| 1237 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 1238 | if (!intel_connector->mst_port) |
| 1239 | sysfs_remove_link(&intel_connector->base.kdev->kobj, |
| 1240 | intel_dp->aux.ddc.dev.kobj.name); |
Imre Deak | 80f65de | 2014-02-11 17:12:49 +0200 | [diff] [blame] | 1241 | intel_connector_unregister(intel_connector); |
| 1242 | } |
| 1243 | |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1244 | static void |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1245 | skl_edp_set_pll_config(struct intel_crtc_state *pipe_config) |
Damien Lespiau | 5416d87 | 2014-11-14 17:24:33 +0000 | [diff] [blame] | 1246 | { |
| 1247 | u32 ctrl1; |
| 1248 | |
Ander Conselvan de Oliveira | dd3cd74 | 2015-05-15 13:34:29 +0300 | [diff] [blame] | 1249 | memset(&pipe_config->dpll_hw_state, 0, |
| 1250 | sizeof(pipe_config->dpll_hw_state)); |
| 1251 | |
Damien Lespiau | 5416d87 | 2014-11-14 17:24:33 +0000 | [diff] [blame] | 1252 | pipe_config->ddi_pll_sel = SKL_DPLL0; |
| 1253 | pipe_config->dpll_hw_state.cfgcr1 = 0; |
| 1254 | pipe_config->dpll_hw_state.cfgcr2 = 0; |
| 1255 | |
| 1256 | ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0); |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1257 | switch (pipe_config->port_clock / 2) { |
Sonika Jindal | c3346ef | 2015-02-21 11:12:13 +0530 | [diff] [blame] | 1258 | case 81000: |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 1259 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, |
Damien Lespiau | 5416d87 | 2014-11-14 17:24:33 +0000 | [diff] [blame] | 1260 | SKL_DPLL0); |
| 1261 | break; |
Sonika Jindal | c3346ef | 2015-02-21 11:12:13 +0530 | [diff] [blame] | 1262 | case 135000: |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 1263 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, |
Damien Lespiau | 5416d87 | 2014-11-14 17:24:33 +0000 | [diff] [blame] | 1264 | SKL_DPLL0); |
| 1265 | break; |
Sonika Jindal | c3346ef | 2015-02-21 11:12:13 +0530 | [diff] [blame] | 1266 | case 270000: |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 1267 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, |
Damien Lespiau | 5416d87 | 2014-11-14 17:24:33 +0000 | [diff] [blame] | 1268 | SKL_DPLL0); |
| 1269 | break; |
Sonika Jindal | c3346ef | 2015-02-21 11:12:13 +0530 | [diff] [blame] | 1270 | case 162000: |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 1271 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, |
Sonika Jindal | c3346ef | 2015-02-21 11:12:13 +0530 | [diff] [blame] | 1272 | SKL_DPLL0); |
| 1273 | break; |
| 1274 | /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which |
| 1275 | results in CDCLK change. Need to handle the change of CDCLK by |
| 1276 | disabling pipes and re-enabling them */ |
| 1277 | case 108000: |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 1278 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
Sonika Jindal | c3346ef | 2015-02-21 11:12:13 +0530 | [diff] [blame] | 1279 | SKL_DPLL0); |
| 1280 | break; |
| 1281 | case 216000: |
Damien Lespiau | 71cd842 | 2015-04-30 16:39:17 +0100 | [diff] [blame] | 1282 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, |
Sonika Jindal | c3346ef | 2015-02-21 11:12:13 +0530 | [diff] [blame] | 1283 | SKL_DPLL0); |
| 1284 | break; |
| 1285 | |
Damien Lespiau | 5416d87 | 2014-11-14 17:24:33 +0000 | [diff] [blame] | 1286 | } |
| 1287 | pipe_config->dpll_hw_state.ctrl1 = ctrl1; |
| 1288 | } |
| 1289 | |
Ander Conselvan de Oliveira | 6fa2d19 | 2015-08-31 11:23:28 +0300 | [diff] [blame] | 1290 | void |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1291 | hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config) |
Daniel Vetter | 0e50338 | 2014-07-04 11:26:04 -0300 | [diff] [blame] | 1292 | { |
Ander Conselvan de Oliveira | ee46f3c7 | 2015-06-30 16:10:38 +0300 | [diff] [blame] | 1293 | memset(&pipe_config->dpll_hw_state, 0, |
| 1294 | sizeof(pipe_config->dpll_hw_state)); |
| 1295 | |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1296 | switch (pipe_config->port_clock / 2) { |
| 1297 | case 81000: |
Daniel Vetter | 0e50338 | 2014-07-04 11:26:04 -0300 | [diff] [blame] | 1298 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; |
| 1299 | break; |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1300 | case 135000: |
Daniel Vetter | 0e50338 | 2014-07-04 11:26:04 -0300 | [diff] [blame] | 1301 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; |
| 1302 | break; |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1303 | case 270000: |
Daniel Vetter | 0e50338 | 2014-07-04 11:26:04 -0300 | [diff] [blame] | 1304 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; |
| 1305 | break; |
| 1306 | } |
| 1307 | } |
| 1308 | |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1309 | static int |
Ville Syrjälä | 12f6a2e | 2015-03-12 17:10:30 +0200 | [diff] [blame] | 1310 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1311 | { |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1312 | if (intel_dp->num_sink_rates) { |
| 1313 | *sink_rates = intel_dp->sink_rates; |
| 1314 | return intel_dp->num_sink_rates; |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1315 | } |
Ville Syrjälä | 12f6a2e | 2015-03-12 17:10:30 +0200 | [diff] [blame] | 1316 | |
| 1317 | *sink_rates = default_rates; |
| 1318 | |
| 1319 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1320 | } |
| 1321 | |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1322 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1323 | { |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1324 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1325 | struct drm_device *dev = dig_port->base.base.dev; |
| 1326 | |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1327 | /* WaDisableHBR2:skl */ |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 1328 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1329 | return false; |
| 1330 | |
| 1331 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || |
| 1332 | (INTEL_INFO(dev)->gen >= 9)) |
| 1333 | return true; |
| 1334 | else |
| 1335 | return false; |
| 1336 | } |
| 1337 | |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1338 | static int |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1339 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1340 | { |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1341 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1342 | struct drm_device *dev = dig_port->base.base.dev; |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1343 | int size; |
| 1344 | |
Sonika Jindal | 64987fc | 2015-05-26 17:50:13 +0530 | [diff] [blame] | 1345 | if (IS_BROXTON(dev)) { |
| 1346 | *source_rates = bxt_rates; |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1347 | size = ARRAY_SIZE(bxt_rates); |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 1348 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
Sonika Jindal | 637a9c6 | 2015-05-07 09:52:08 +0530 | [diff] [blame] | 1349 | *source_rates = skl_rates; |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1350 | size = ARRAY_SIZE(skl_rates); |
| 1351 | } else { |
| 1352 | *source_rates = default_rates; |
| 1353 | size = ARRAY_SIZE(default_rates); |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1354 | } |
Ville Syrjälä | 636280b | 2015-03-12 17:10:29 +0200 | [diff] [blame] | 1355 | |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1356 | /* This depends on the fact that 5.4 is last value in the array */ |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1357 | if (!intel_dp_source_supports_hbr2(intel_dp)) |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1358 | size--; |
Ville Syrjälä | 636280b | 2015-03-12 17:10:29 +0200 | [diff] [blame] | 1359 | |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1360 | return size; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1361 | } |
| 1362 | |
Daniel Vetter | 0e50338 | 2014-07-04 11:26:04 -0300 | [diff] [blame] | 1363 | static void |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1364 | intel_dp_set_clock(struct intel_encoder *encoder, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1365 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1366 | { |
| 1367 | struct drm_device *dev = encoder->base.dev; |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1368 | const struct dp_link_dpll *divisor = NULL; |
| 1369 | int i, count = 0; |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1370 | |
| 1371 | if (IS_G4X(dev)) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1372 | divisor = gen4_dpll; |
| 1373 | count = ARRAY_SIZE(gen4_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1374 | } else if (HAS_PCH_SPLIT(dev)) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1375 | divisor = pch_dpll; |
| 1376 | count = ARRAY_SIZE(pch_dpll); |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 1377 | } else if (IS_CHERRYVIEW(dev)) { |
| 1378 | divisor = chv_dpll; |
| 1379 | count = ARRAY_SIZE(chv_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1380 | } else if (IS_VALLEYVIEW(dev)) { |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 1381 | divisor = vlv_dpll; |
| 1382 | count = ARRAY_SIZE(vlv_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1383 | } |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1384 | |
| 1385 | if (divisor && count) { |
| 1386 | for (i = 0; i < count; i++) { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1387 | if (pipe_config->port_clock == divisor[i].clock) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1388 | pipe_config->dpll = divisor[i].dpll; |
| 1389 | pipe_config->clock_set = true; |
| 1390 | break; |
| 1391 | } |
| 1392 | } |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1393 | } |
| 1394 | } |
| 1395 | |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1396 | static int intersect_rates(const int *source_rates, int source_len, |
| 1397 | const int *sink_rates, int sink_len, |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1398 | int *common_rates) |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1399 | { |
| 1400 | int i = 0, j = 0, k = 0; |
| 1401 | |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1402 | while (i < source_len && j < sink_len) { |
| 1403 | if (source_rates[i] == sink_rates[j]) { |
Ville Syrjälä | e6bda3e | 2015-03-12 17:10:37 +0200 | [diff] [blame] | 1404 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
| 1405 | return k; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1406 | common_rates[k] = source_rates[i]; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1407 | ++k; |
| 1408 | ++i; |
| 1409 | ++j; |
| 1410 | } else if (source_rates[i] < sink_rates[j]) { |
| 1411 | ++i; |
| 1412 | } else { |
| 1413 | ++j; |
| 1414 | } |
| 1415 | } |
| 1416 | return k; |
| 1417 | } |
| 1418 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1419 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
| 1420 | int *common_rates) |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1421 | { |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1422 | const int *source_rates, *sink_rates; |
| 1423 | int source_len, sink_len; |
| 1424 | |
| 1425 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1426 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1427 | |
| 1428 | return intersect_rates(source_rates, source_len, |
| 1429 | sink_rates, sink_len, |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1430 | common_rates); |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1431 | } |
| 1432 | |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1433 | static void snprintf_int_array(char *str, size_t len, |
| 1434 | const int *array, int nelem) |
| 1435 | { |
| 1436 | int i; |
| 1437 | |
| 1438 | str[0] = '\0'; |
| 1439 | |
| 1440 | for (i = 0; i < nelem; i++) { |
Jani Nikula | b2f505b | 2015-05-18 16:01:45 +0300 | [diff] [blame] | 1441 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1442 | if (r >= len) |
| 1443 | return; |
| 1444 | str += r; |
| 1445 | len -= r; |
| 1446 | } |
| 1447 | } |
| 1448 | |
| 1449 | static void intel_dp_print_rates(struct intel_dp *intel_dp) |
| 1450 | { |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1451 | const int *source_rates, *sink_rates; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1452 | int source_len, sink_len, common_len; |
| 1453 | int common_rates[DP_MAX_SUPPORTED_RATES]; |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1454 | char str[128]; /* FIXME: too big for stack? */ |
| 1455 | |
| 1456 | if ((drm_debug & DRM_UT_KMS) == 0) |
| 1457 | return; |
| 1458 | |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1459 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1460 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
| 1461 | DRM_DEBUG_KMS("source rates: %s\n", str); |
| 1462 | |
| 1463 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
| 1464 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); |
| 1465 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
| 1466 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1467 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
| 1468 | snprintf_int_array(str, sizeof(str), common_rates, common_len); |
| 1469 | DRM_DEBUG_KMS("common rates: %s\n", str); |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1470 | } |
| 1471 | |
Ville Syrjälä | f4896f1 | 2015-03-12 17:10:27 +0200 | [diff] [blame] | 1472 | static int rate_to_index(int find, const int *rates) |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1473 | { |
| 1474 | int i = 0; |
| 1475 | |
| 1476 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) |
| 1477 | if (find == rates[i]) |
| 1478 | break; |
| 1479 | |
| 1480 | return i; |
| 1481 | } |
| 1482 | |
Ville Syrjälä | 50fec21 | 2015-03-12 17:10:34 +0200 | [diff] [blame] | 1483 | int |
| 1484 | intel_dp_max_link_rate(struct intel_dp *intel_dp) |
| 1485 | { |
| 1486 | int rates[DP_MAX_SUPPORTED_RATES] = {}; |
| 1487 | int len; |
| 1488 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1489 | len = intel_dp_common_rates(intel_dp, rates); |
Ville Syrjälä | 50fec21 | 2015-03-12 17:10:34 +0200 | [diff] [blame] | 1490 | if (WARN_ON(len <= 0)) |
| 1491 | return 162000; |
| 1492 | |
| 1493 | return rates[rate_to_index(0, rates) - 1]; |
| 1494 | } |
| 1495 | |
Ville Syrjälä | ed4e9c1 | 2015-03-12 17:10:36 +0200 | [diff] [blame] | 1496 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
| 1497 | { |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1498 | return rate_to_index(rate, intel_dp->sink_rates); |
Ville Syrjälä | ed4e9c1 | 2015-03-12 17:10:36 +0200 | [diff] [blame] | 1499 | } |
| 1500 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 1501 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
| 1502 | uint8_t *link_bw, uint8_t *rate_select) |
Ville Syrjälä | 04a60f9 | 2015-07-06 15:10:06 +0300 | [diff] [blame] | 1503 | { |
| 1504 | if (intel_dp->num_sink_rates) { |
| 1505 | *link_bw = 0; |
| 1506 | *rate_select = |
| 1507 | intel_dp_rate_select(intel_dp, port_clock); |
| 1508 | } else { |
| 1509 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); |
| 1510 | *rate_select = 0; |
| 1511 | } |
| 1512 | } |
| 1513 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 1514 | bool |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1515 | intel_dp_compute_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 1516 | struct intel_crtc_state *pipe_config) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1517 | { |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1518 | struct drm_device *dev = encoder->base.dev; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1519 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 1520 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1521 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1522 | enum port port = dp_to_dig_port(intel_dp)->port; |
Ander Conselvan de Oliveira | 84556d5 | 2015-03-20 16:18:10 +0200 | [diff] [blame] | 1523 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 1524 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1525 | int lane_count, clock; |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1526 | int min_lane_count = 1; |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 1527 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 1528 | /* Conveniently, the link BW constants become indices with a shift...*/ |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1529 | int min_clock = 0; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1530 | int max_clock; |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 1531 | int bpp, mode_rate; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 1532 | int link_avail, link_clock; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1533 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
| 1534 | int common_len; |
Ville Syrjälä | 04a60f9 | 2015-07-06 15:10:06 +0300 | [diff] [blame] | 1535 | uint8_t link_bw, rate_select; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1536 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1537 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1538 | |
| 1539 | /* No common link rates between source and sink */ |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1540 | WARN_ON(common_len <= 0); |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1541 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1542 | max_clock = common_len - 1; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1543 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1544 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1545 | pipe_config->has_pch_encoder = true; |
| 1546 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 1547 | pipe_config->has_dp_encoder = true; |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 1548 | pipe_config->has_drrs = false; |
Jani Nikula | 9fcb170 | 2015-05-05 16:32:12 +0300 | [diff] [blame] | 1549 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1550 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 1551 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
| 1552 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
| 1553 | adjusted_mode); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 1554 | |
| 1555 | if (INTEL_INFO(dev)->gen >= 9) { |
| 1556 | int ret; |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 1557 | ret = skl_update_scaler_crtc(pipe_config); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 1558 | if (ret) |
| 1559 | return ret; |
| 1560 | } |
| 1561 | |
Matt Roper | b5667627 | 2015-11-04 09:05:27 -0800 | [diff] [blame] | 1562 | if (HAS_GMCH_DISPLAY(dev)) |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 1563 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
| 1564 | intel_connector->panel.fitting_mode); |
| 1565 | else |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 1566 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
| 1567 | intel_connector->panel.fitting_mode); |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 1568 | } |
| 1569 | |
Daniel Vetter | cb1793c | 2012-06-04 18:39:21 +0200 | [diff] [blame] | 1570 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 1571 | return false; |
| 1572 | |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 1573 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1574 | "max bw %d pixel clock %iKHz\n", |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1575 | max_lane_count, common_rates[max_clock], |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1576 | adjusted_mode->crtc_clock); |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 1577 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1578 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
| 1579 | * bpc in between. */ |
Daniel Vetter | 3e7ca98 | 2013-06-01 19:45:56 +0200 | [diff] [blame] | 1580 | bpp = pipe_config->pipe_bpp; |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1581 | if (is_edp(intel_dp)) { |
Thulasimani,Sivakumar | 22ce562 | 2015-07-31 11:05:27 +0530 | [diff] [blame] | 1582 | |
| 1583 | /* Get bpp from vbt only for panels that dont have bpp in edid */ |
| 1584 | if (intel_connector->base.display_info.bpc == 0 && |
| 1585 | (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) { |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1586 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
| 1587 | dev_priv->vbt.edp_bpp); |
| 1588 | bpp = dev_priv->vbt.edp_bpp; |
| 1589 | } |
| 1590 | |
Jani Nikula | 344c5bb | 2014-09-09 11:25:13 +0300 | [diff] [blame] | 1591 | /* |
| 1592 | * Use the maximum clock and number of lanes the eDP panel |
| 1593 | * advertizes being capable of. The panels are generally |
| 1594 | * designed to support only a single clock and lane |
| 1595 | * configuration, and typically these values correspond to the |
| 1596 | * native resolution of the panel. |
| 1597 | */ |
| 1598 | min_lane_count = max_lane_count; |
| 1599 | min_clock = max_clock; |
Imre Deak | 7984211 | 2013-07-18 17:44:13 +0300 | [diff] [blame] | 1600 | } |
Daniel Vetter | 657445f | 2013-05-04 10:09:18 +0200 | [diff] [blame] | 1601 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1602 | for (; bpp >= 6*3; bpp -= 2*3) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1603 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
| 1604 | bpp); |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 1605 | |
Dave Airlie | c693099 | 2014-07-14 11:04:39 +1000 | [diff] [blame] | 1606 | for (clock = min_clock; clock <= max_clock; clock++) { |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1607 | for (lane_count = min_lane_count; |
| 1608 | lane_count <= max_lane_count; |
| 1609 | lane_count <<= 1) { |
| 1610 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1611 | link_clock = common_rates[clock]; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1612 | link_avail = intel_dp_max_data_rate(link_clock, |
| 1613 | lane_count); |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 1614 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1615 | if (mode_rate <= link_avail) { |
| 1616 | goto found; |
| 1617 | } |
| 1618 | } |
| 1619 | } |
| 1620 | } |
| 1621 | |
| 1622 | return false; |
| 1623 | |
| 1624 | found: |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 1625 | if (intel_dp->color_range_auto) { |
| 1626 | /* |
| 1627 | * See: |
| 1628 | * CEA-861-E - 5.1 Default Encoding Parameters |
| 1629 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
| 1630 | */ |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 1631 | pipe_config->limited_color_range = |
| 1632 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; |
| 1633 | } else { |
| 1634 | pipe_config->limited_color_range = |
| 1635 | intel_dp->limited_color_range; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 1636 | } |
| 1637 | |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 1638 | pipe_config->lane_count = lane_count; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1639 | |
Daniel Vetter | 657445f | 2013-05-04 10:09:18 +0200 | [diff] [blame] | 1640 | pipe_config->pipe_bpp = bpp; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1641 | pipe_config->port_clock = common_rates[clock]; |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 1642 | |
Ville Syrjälä | 04a60f9 | 2015-07-06 15:10:06 +0300 | [diff] [blame] | 1643 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
| 1644 | &link_bw, &rate_select); |
| 1645 | |
| 1646 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", |
| 1647 | link_bw, rate_select, pipe_config->lane_count, |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 1648 | pipe_config->port_clock, bpp); |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1649 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
| 1650 | mode_rate, link_avail); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1651 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 1652 | intel_link_compute_m_n(bpp, lane_count, |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1653 | adjusted_mode->crtc_clock, |
| 1654 | pipe_config->port_clock, |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 1655 | &pipe_config->dp_m_n); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1656 | |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 1657 | if (intel_connector->panel.downclock_mode != NULL && |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 1658 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 1659 | pipe_config->has_drrs = true; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 1660 | intel_link_compute_m_n(bpp, lane_count, |
| 1661 | intel_connector->panel.downclock_mode->clock, |
| 1662 | pipe_config->port_clock, |
| 1663 | &pipe_config->dp_m2_n2); |
| 1664 | } |
| 1665 | |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 1666 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp)) |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1667 | skl_edp_set_pll_config(pipe_config); |
Satheeshakrishna M | 977bb38 | 2014-08-22 09:49:12 +0530 | [diff] [blame] | 1668 | else if (IS_BROXTON(dev)) |
| 1669 | /* handled in ddi */; |
Damien Lespiau | 5416d87 | 2014-11-14 17:24:33 +0000 | [diff] [blame] | 1670 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1671 | hsw_dp_set_ddi_pll_sel(pipe_config); |
Daniel Vetter | 0e50338 | 2014-07-04 11:26:04 -0300 | [diff] [blame] | 1672 | else |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1673 | intel_dp_set_clock(encoder, pipe_config); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1674 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1675 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1676 | } |
| 1677 | |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 1678 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
| 1679 | const struct intel_crtc_state *pipe_config) |
| 1680 | { |
| 1681 | intel_dp->link_rate = pipe_config->port_clock; |
| 1682 | intel_dp->lane_count = pipe_config->lane_count; |
| 1683 | } |
| 1684 | |
Daniel Vetter | 8ac33ed | 2014-04-24 23:54:54 +0200 | [diff] [blame] | 1685 | static void intel_dp_prepare(struct intel_encoder *encoder) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1686 | { |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1687 | struct drm_device *dev = encoder->base.dev; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1688 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1689 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1690 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1691 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 1692 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1693 | |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 1694 | intel_dp_set_link_params(intel_dp, crtc->config); |
| 1695 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1696 | /* |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1697 | * There are four kinds of DP registers: |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1698 | * |
| 1699 | * IBX PCH |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1700 | * SNB CPU |
| 1701 | * IVB CPU |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1702 | * CPT PCH |
| 1703 | * |
| 1704 | * IBX PCH and CPU are the same for almost everything, |
| 1705 | * except that the CPU DP PLL is configured in this |
| 1706 | * register |
| 1707 | * |
| 1708 | * CPT PCH is quite different, having many bits moved |
| 1709 | * to the TRANS_DP_CTL register instead. That |
| 1710 | * configuration happens (oddly) in ironlake_pch_enable |
| 1711 | */ |
Adam Jackson | 9c9e792 | 2010-04-05 17:57:59 -0400 | [diff] [blame] | 1712 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1713 | /* Preserve the BIOS-computed detected bit. This is |
| 1714 | * supposed to be read-only. |
| 1715 | */ |
| 1716 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1717 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1718 | /* Handle DP bits in common between all three register formats */ |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1719 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 1720 | intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1721 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1722 | /* Split out the IBX/CPU vs CPT settings */ |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1723 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1724 | if (IS_GEN7(dev) && port == PORT_A) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1725 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1726 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 1727 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1728 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 1729 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
| 1730 | |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 1731 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1732 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 1733 | |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 1734 | intel_dp->DP |= crtc->pipe << 29; |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1735 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
Ville Syrjälä | e3ef447 | 2015-05-05 17:17:31 +0300 | [diff] [blame] | 1736 | u32 trans_dp; |
| 1737 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1738 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
Ville Syrjälä | e3ef447 | 2015-05-05 17:17:31 +0300 | [diff] [blame] | 1739 | |
| 1740 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
| 1741 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 1742 | trans_dp |= TRANS_DP_ENH_FRAMING; |
| 1743 | else |
| 1744 | trans_dp &= ~TRANS_DP_ENH_FRAMING; |
| 1745 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1746 | } else { |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 1747 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 1748 | !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range) |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 1749 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1750 | |
| 1751 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1752 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 1753 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1754 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 1755 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
| 1756 | |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 1757 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1758 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 1759 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1760 | if (IS_CHERRYVIEW(dev)) |
Chon Ming Lee | 44f37d1 | 2014-04-09 13:28:21 +0300 | [diff] [blame] | 1761 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1762 | else if (crtc->pipe == PIPE_B) |
| 1763 | intel_dp->DP |= DP_PIPEB_SELECT; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1764 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1765 | } |
| 1766 | |
Paulo Zanoni | ffd6749d | 2013-12-19 14:29:42 -0200 | [diff] [blame] | 1767 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
| 1768 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1769 | |
Paulo Zanoni | 1a5ef5b | 2013-12-19 14:29:43 -0200 | [diff] [blame] | 1770 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
| 1771 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1772 | |
Paulo Zanoni | ffd6749d | 2013-12-19 14:29:42 -0200 | [diff] [blame] | 1773 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
| 1774 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1775 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1776 | static void wait_panel_status(struct intel_dp *intel_dp, |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1777 | u32 mask, |
| 1778 | u32 value) |
| 1779 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1780 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1781 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1782 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1783 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1784 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1785 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1786 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1787 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1788 | |
| 1789 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1790 | mask, value, |
| 1791 | I915_READ(pp_stat_reg), |
| 1792 | I915_READ(pp_ctrl_reg)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1793 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1794 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1795 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1796 | I915_READ(pp_stat_reg), |
| 1797 | I915_READ(pp_ctrl_reg)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1798 | } |
Chris Wilson | 54c136d | 2013-12-02 09:57:16 +0000 | [diff] [blame] | 1799 | |
| 1800 | DRM_DEBUG_KMS("Wait complete\n"); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1801 | } |
| 1802 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1803 | static void wait_panel_on(struct intel_dp *intel_dp) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1804 | { |
| 1805 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1806 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1807 | } |
| 1808 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1809 | static void wait_panel_off(struct intel_dp *intel_dp) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1810 | { |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1811 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1812 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1813 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1814 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1815 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1816 | { |
| 1817 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1818 | |
| 1819 | /* When we disable the VDD override bit last we have to do the manual |
| 1820 | * wait. */ |
| 1821 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, |
| 1822 | intel_dp->panel_power_cycle_delay); |
| 1823 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1824 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1825 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1826 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1827 | static void wait_backlight_on(struct intel_dp *intel_dp) |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1828 | { |
| 1829 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
| 1830 | intel_dp->backlight_on_delay); |
| 1831 | } |
| 1832 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1833 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1834 | { |
| 1835 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
| 1836 | intel_dp->backlight_off_delay); |
| 1837 | } |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1838 | |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1839 | /* Read the current pp_control value, unlocking the register if it |
| 1840 | * is locked |
| 1841 | */ |
| 1842 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1843 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1844 | { |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1845 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1846 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1847 | u32 control; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1848 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1849 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1850 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1851 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 1852 | if (!IS_BROXTON(dev)) { |
| 1853 | control &= ~PANEL_UNLOCK_MASK; |
| 1854 | control |= PANEL_UNLOCK_REGS; |
| 1855 | } |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1856 | return control; |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1857 | } |
| 1858 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 1859 | /* |
| 1860 | * Must be paired with edp_panel_vdd_off(). |
| 1861 | * Must hold pps_mutex around the whole on/off sequence. |
| 1862 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| 1863 | */ |
Ville Syrjälä | 1e0560e | 2014-08-19 13:24:25 +0300 | [diff] [blame] | 1864 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1865 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1866 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1867 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1868 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1869 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1870 | enum intel_display_power_domain power_domain; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1871 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1872 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1873 | bool need_to_disable = !intel_dp->want_panel_vdd; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1874 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1875 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1876 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1877 | if (!is_edp(intel_dp)) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1878 | return false; |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1879 | |
Egbert Eich | 2c623c1 | 2014-11-25 12:54:57 +0100 | [diff] [blame] | 1880 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1881 | intel_dp->want_panel_vdd = true; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1882 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1883 | if (edp_have_panel_vdd(intel_dp)) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1884 | return need_to_disable; |
Paulo Zanoni | b0665d5 | 2013-10-30 19:50:27 -0200 | [diff] [blame] | 1885 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 1886 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1887 | intel_display_power_get(dev_priv, power_domain); |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 1888 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1889 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
| 1890 | port_name(intel_dig_port->port)); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1891 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1892 | if (!edp_have_panel_power(intel_dp)) |
| 1893 | wait_panel_power_cycle(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1894 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1895 | pp = ironlake_get_pp_control(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1896 | pp |= EDP_FORCE_VDD; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1897 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1898 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1899 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1900 | |
| 1901 | I915_WRITE(pp_ctrl_reg, pp); |
| 1902 | POSTING_READ(pp_ctrl_reg); |
| 1903 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1904 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1905 | /* |
| 1906 | * If the panel wasn't on, delay before accessing aux channel |
| 1907 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1908 | if (!edp_have_panel_power(intel_dp)) { |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1909 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
| 1910 | port_name(intel_dig_port->port)); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1911 | msleep(intel_dp->panel_power_up_delay); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1912 | } |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1913 | |
| 1914 | return need_to_disable; |
| 1915 | } |
| 1916 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 1917 | /* |
| 1918 | * Must be paired with intel_edp_panel_vdd_off() or |
| 1919 | * intel_edp_panel_off(). |
| 1920 | * Nested calls to these functions are not allowed since |
| 1921 | * we drop the lock. Caller must use some higher level |
| 1922 | * locking to prevent nested calls from other threads. |
| 1923 | */ |
Daniel Vetter | b80d6c7 | 2014-03-19 15:54:37 +0100 | [diff] [blame] | 1924 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1925 | { |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1926 | bool vdd; |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1927 | |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1928 | if (!is_edp(intel_dp)) |
| 1929 | return; |
| 1930 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1931 | pps_lock(intel_dp); |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1932 | vdd = edp_panel_vdd_on(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1933 | pps_unlock(intel_dp); |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1934 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1935 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1936 | port_name(dp_to_dig_port(intel_dp)->port)); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1937 | } |
| 1938 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1939 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1940 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1941 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1942 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1943 | struct intel_digital_port *intel_dig_port = |
| 1944 | dp_to_dig_port(intel_dp); |
| 1945 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 1946 | enum intel_display_power_domain power_domain; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1947 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1948 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1949 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1950 | lockdep_assert_held(&dev_priv->pps_mutex); |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1951 | |
Ville Syrjälä | 15e899a | 2014-08-18 22:16:02 +0300 | [diff] [blame] | 1952 | WARN_ON(intel_dp->want_panel_vdd); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1953 | |
Ville Syrjälä | 15e899a | 2014-08-18 22:16:02 +0300 | [diff] [blame] | 1954 | if (!edp_have_panel_vdd(intel_dp)) |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1955 | return; |
Paulo Zanoni | b0665d5 | 2013-10-30 19:50:27 -0200 | [diff] [blame] | 1956 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1957 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
| 1958 | port_name(intel_dig_port->port)); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1959 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1960 | pp = ironlake_get_pp_control(intel_dp); |
| 1961 | pp &= ~EDP_FORCE_VDD; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1962 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1963 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1964 | pp_stat_reg = _pp_stat_reg(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1965 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1966 | I915_WRITE(pp_ctrl_reg, pp); |
| 1967 | POSTING_READ(pp_ctrl_reg); |
Paulo Zanoni | 90791a5 | 2013-12-06 17:32:42 -0200 | [diff] [blame] | 1968 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1969 | /* Make sure sequencer is idle before allowing subsequent activity */ |
| 1970 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1971 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 1972 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1973 | if ((pp & POWER_TARGET_ON) == 0) |
| 1974 | intel_dp->last_power_cycle = jiffies; |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 1975 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 1976 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1977 | intel_display_power_put(dev_priv, power_domain); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1978 | } |
| 1979 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1980 | static void edp_panel_vdd_work(struct work_struct *__work) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1981 | { |
| 1982 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
| 1983 | struct intel_dp, panel_vdd_work); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1984 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1985 | pps_lock(intel_dp); |
Ville Syrjälä | 15e899a | 2014-08-18 22:16:02 +0300 | [diff] [blame] | 1986 | if (!intel_dp->want_panel_vdd) |
| 1987 | edp_panel_vdd_off_sync(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1988 | pps_unlock(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1989 | } |
| 1990 | |
Imre Deak | aba8689 | 2014-07-30 15:57:31 +0300 | [diff] [blame] | 1991 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
| 1992 | { |
| 1993 | unsigned long delay; |
| 1994 | |
| 1995 | /* |
| 1996 | * Queue the timer to fire a long time from now (relative to the power |
| 1997 | * down delay) to keep the panel power up across a sequence of |
| 1998 | * operations. |
| 1999 | */ |
| 2000 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
| 2001 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
| 2002 | } |
| 2003 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 2004 | /* |
| 2005 | * Must be paired with edp_panel_vdd_on(). |
| 2006 | * Must hold pps_mutex around the whole on/off sequence. |
| 2007 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| 2008 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2009 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2010 | { |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2011 | struct drm_i915_private *dev_priv = |
| 2012 | intel_dp_to_dev(intel_dp)->dev_private; |
| 2013 | |
| 2014 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2015 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 2016 | if (!is_edp(intel_dp)) |
| 2017 | return; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2018 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 2019 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 2020 | port_name(dp_to_dig_port(intel_dp)->port)); |
Keith Packard | f2e8b18 | 2011-11-01 20:01:35 -0700 | [diff] [blame] | 2021 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2022 | intel_dp->want_panel_vdd = false; |
| 2023 | |
Imre Deak | aba8689 | 2014-07-30 15:57:31 +0300 | [diff] [blame] | 2024 | if (sync) |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2025 | edp_panel_vdd_off_sync(intel_dp); |
Imre Deak | aba8689 | 2014-07-30 15:57:31 +0300 | [diff] [blame] | 2026 | else |
| 2027 | edp_panel_vdd_schedule_off(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2028 | } |
| 2029 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2030 | static void edp_panel_on(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2031 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2032 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2033 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2034 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2035 | i915_reg_t pp_ctrl_reg; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2036 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2037 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2038 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 2039 | if (!is_edp(intel_dp)) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2040 | return; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2041 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 2042 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
| 2043 | port_name(dp_to_dig_port(intel_dp)->port)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2044 | |
Ville Syrjälä | e7a89ac | 2014-10-16 21:30:07 +0300 | [diff] [blame] | 2045 | if (WARN(edp_have_panel_power(intel_dp), |
| 2046 | "eDP port %c panel power already on\n", |
| 2047 | port_name(dp_to_dig_port(intel_dp)->port))) |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2048 | return; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2049 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2050 | wait_panel_power_cycle(intel_dp); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 2051 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2052 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2053 | pp = ironlake_get_pp_control(intel_dp); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 2054 | if (IS_GEN5(dev)) { |
| 2055 | /* ILK workaround: disable reset around power sequence */ |
| 2056 | pp &= ~PANEL_POWER_RESET; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2057 | I915_WRITE(pp_ctrl_reg, pp); |
| 2058 | POSTING_READ(pp_ctrl_reg); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 2059 | } |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 2060 | |
Keith Packard | 1c0ae80 | 2011-09-19 13:59:29 -0700 | [diff] [blame] | 2061 | pp |= POWER_TARGET_ON; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2062 | if (!IS_GEN5(dev)) |
| 2063 | pp |= PANEL_POWER_RESET; |
| 2064 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2065 | I915_WRITE(pp_ctrl_reg, pp); |
| 2066 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2067 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2068 | wait_panel_on(intel_dp); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 2069 | intel_dp->last_power_on = jiffies; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2070 | |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 2071 | if (IS_GEN5(dev)) { |
| 2072 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2073 | I915_WRITE(pp_ctrl_reg, pp); |
| 2074 | POSTING_READ(pp_ctrl_reg); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 2075 | } |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2076 | } |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2077 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2078 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
| 2079 | { |
| 2080 | if (!is_edp(intel_dp)) |
| 2081 | return; |
| 2082 | |
| 2083 | pps_lock(intel_dp); |
| 2084 | edp_panel_on(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2085 | pps_unlock(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2086 | } |
| 2087 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2088 | |
| 2089 | static void edp_panel_off(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2090 | { |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 2091 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2092 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2093 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2094 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 2095 | enum intel_display_power_domain power_domain; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2096 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2097 | i915_reg_t pp_ctrl_reg; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2098 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2099 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2100 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 2101 | if (!is_edp(intel_dp)) |
| 2102 | return; |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 2103 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 2104 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
| 2105 | port_name(dp_to_dig_port(intel_dp)->port)); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 2106 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 2107 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
| 2108 | port_name(dp_to_dig_port(intel_dp)->port)); |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 2109 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2110 | pp = ironlake_get_pp_control(intel_dp); |
Daniel Vetter | 35a3855 | 2012-08-12 22:17:14 +0200 | [diff] [blame] | 2111 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
| 2112 | * panels get very unhappy and cease to work. */ |
Patrik Jakobsson | b306415 | 2014-03-04 00:42:44 +0100 | [diff] [blame] | 2113 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
| 2114 | EDP_BLC_ENABLE); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2115 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2116 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2117 | |
Paulo Zanoni | 849e39f | 2014-03-07 20:05:20 -0300 | [diff] [blame] | 2118 | intel_dp->want_panel_vdd = false; |
| 2119 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2120 | I915_WRITE(pp_ctrl_reg, pp); |
| 2121 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2122 | |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 2123 | intel_dp->last_power_cycle = jiffies; |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2124 | wait_panel_off(intel_dp); |
Paulo Zanoni | 849e39f | 2014-03-07 20:05:20 -0300 | [diff] [blame] | 2125 | |
| 2126 | /* We got a reference when we enabled the VDD. */ |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 2127 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 2128 | intel_display_power_put(dev_priv, power_domain); |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2129 | } |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2130 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2131 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
| 2132 | { |
| 2133 | if (!is_edp(intel_dp)) |
| 2134 | return; |
| 2135 | |
| 2136 | pps_lock(intel_dp); |
| 2137 | edp_panel_off(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2138 | pps_unlock(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2139 | } |
| 2140 | |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2141 | /* Enable backlight in the panel power control. */ |
| 2142 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2143 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2144 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2145 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2146 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2147 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2148 | i915_reg_t pp_ctrl_reg; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2149 | |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 2150 | /* |
| 2151 | * If we enable the backlight right away following a panel power |
| 2152 | * on, we may see slight flicker as the panel syncs with the eDP |
| 2153 | * link. So delay a bit to make sure the image is solid before |
| 2154 | * allowing it to appear. |
| 2155 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2156 | wait_backlight_on(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2157 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2158 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2159 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2160 | pp = ironlake_get_pp_control(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2161 | pp |= EDP_BLC_ENABLE; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2162 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2163 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2164 | |
| 2165 | I915_WRITE(pp_ctrl_reg, pp); |
| 2166 | POSTING_READ(pp_ctrl_reg); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2167 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2168 | pps_unlock(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2169 | } |
| 2170 | |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2171 | /* Enable backlight PWM and backlight PP control. */ |
| 2172 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
| 2173 | { |
| 2174 | if (!is_edp(intel_dp)) |
| 2175 | return; |
| 2176 | |
| 2177 | DRM_DEBUG_KMS("\n"); |
| 2178 | |
| 2179 | intel_panel_enable_backlight(intel_dp->attached_connector); |
| 2180 | _intel_edp_backlight_on(intel_dp); |
| 2181 | } |
| 2182 | |
| 2183 | /* Disable backlight in the panel power control. */ |
| 2184 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2185 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2186 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2187 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2188 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2189 | i915_reg_t pp_ctrl_reg; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2190 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2191 | if (!is_edp(intel_dp)) |
| 2192 | return; |
| 2193 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2194 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2195 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2196 | pp = ironlake_get_pp_control(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2197 | pp &= ~EDP_BLC_ENABLE; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2198 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2199 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2200 | |
| 2201 | I915_WRITE(pp_ctrl_reg, pp); |
| 2202 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2203 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2204 | pps_unlock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2205 | |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 2206 | intel_dp->last_backlight_off = jiffies; |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2207 | edp_wait_backlight_off(intel_dp); |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2208 | } |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2209 | |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2210 | /* Disable backlight PP control and backlight PWM. */ |
| 2211 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
| 2212 | { |
| 2213 | if (!is_edp(intel_dp)) |
| 2214 | return; |
| 2215 | |
| 2216 | DRM_DEBUG_KMS("\n"); |
| 2217 | |
| 2218 | _intel_edp_backlight_off(intel_dp); |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2219 | intel_panel_disable_backlight(intel_dp->attached_connector); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2220 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2221 | |
Jani Nikula | 73580fb7 | 2014-08-12 17:11:41 +0300 | [diff] [blame] | 2222 | /* |
| 2223 | * Hook for controlling the panel power control backlight through the bl_power |
| 2224 | * sysfs attribute. Take care to handle multiple calls. |
| 2225 | */ |
| 2226 | static void intel_edp_backlight_power(struct intel_connector *connector, |
| 2227 | bool enable) |
| 2228 | { |
| 2229 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2230 | bool is_enabled; |
| 2231 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2232 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2233 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2234 | pps_unlock(intel_dp); |
Jani Nikula | 73580fb7 | 2014-08-12 17:11:41 +0300 | [diff] [blame] | 2235 | |
| 2236 | if (is_enabled == enable) |
| 2237 | return; |
| 2238 | |
Jani Nikula | 23ba937 | 2014-08-27 14:08:43 +0300 | [diff] [blame] | 2239 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
| 2240 | enable ? "enable" : "disable"); |
Jani Nikula | 73580fb7 | 2014-08-12 17:11:41 +0300 | [diff] [blame] | 2241 | |
| 2242 | if (enable) |
| 2243 | _intel_edp_backlight_on(intel_dp); |
| 2244 | else |
| 2245 | _intel_edp_backlight_off(intel_dp); |
| 2246 | } |
| 2247 | |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2248 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
| 2249 | { |
| 2250 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 2251 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
| 2252 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; |
| 2253 | |
| 2254 | I915_STATE_WARN(cur_state != state, |
| 2255 | "DP port %c state assertion failure (expected %s, current %s)\n", |
| 2256 | port_name(dig_port->port), |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 2257 | onoff(state), onoff(cur_state)); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2258 | } |
| 2259 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) |
| 2260 | |
| 2261 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) |
| 2262 | { |
| 2263 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; |
| 2264 | |
| 2265 | I915_STATE_WARN(cur_state != state, |
| 2266 | "eDP PLL state assertion failure (expected %s, current %s)\n", |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 2267 | onoff(state), onoff(cur_state)); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2268 | } |
| 2269 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) |
| 2270 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) |
| 2271 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2272 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2273 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2274 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2275 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
| 2276 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2277 | |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2278 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 2279 | assert_dp_port_disabled(intel_dp); |
| 2280 | assert_edp_pll_disabled(dev_priv); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2281 | |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2282 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
| 2283 | crtc->config->port_clock); |
| 2284 | |
| 2285 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; |
| 2286 | |
| 2287 | if (crtc->config->port_clock == 162000) |
| 2288 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
| 2289 | else |
| 2290 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
| 2291 | |
| 2292 | I915_WRITE(DP_A, intel_dp->DP); |
| 2293 | POSTING_READ(DP_A); |
| 2294 | udelay(500); |
| 2295 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 2296 | intel_dp->DP |= DP_PLL_ENABLE; |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2297 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 2298 | I915_WRITE(DP_A, intel_dp->DP); |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 2299 | POSTING_READ(DP_A); |
| 2300 | udelay(200); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2301 | } |
| 2302 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2303 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2304 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2305 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2306 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
| 2307 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2308 | |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2309 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 2310 | assert_dp_port_disabled(intel_dp); |
| 2311 | assert_edp_pll_enabled(dev_priv); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2312 | |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2313 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
| 2314 | |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2315 | intel_dp->DP &= ~DP_PLL_ENABLE; |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 2316 | |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2317 | I915_WRITE(DP_A, intel_dp->DP); |
Chris Wilson | 1af5fa1 | 2010-09-08 21:07:28 +0100 | [diff] [blame] | 2318 | POSTING_READ(DP_A); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2319 | udelay(200); |
| 2320 | } |
| 2321 | |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2322 | /* If the sink supports it, try to set the power state appropriately */ |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2323 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2324 | { |
| 2325 | int ret, i; |
| 2326 | |
| 2327 | /* Should have a valid DPCD by this point */ |
| 2328 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
| 2329 | return; |
| 2330 | |
| 2331 | if (mode != DRM_MODE_DPMS_ON) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2332 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
| 2333 | DP_SET_POWER_D3); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2334 | } else { |
| 2335 | /* |
| 2336 | * When turning on, we need to retry for 1ms to give the sink |
| 2337 | * time to wake up. |
| 2338 | */ |
| 2339 | for (i = 0; i < 3; i++) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2340 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
| 2341 | DP_SET_POWER_D0); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2342 | if (ret == 1) |
| 2343 | break; |
| 2344 | msleep(1); |
| 2345 | } |
| 2346 | } |
Jani Nikula | f9cac72 | 2014-09-02 16:33:52 +0300 | [diff] [blame] | 2347 | |
| 2348 | if (ret != 1) |
| 2349 | DRM_DEBUG_KMS("failed to %s sink power state\n", |
| 2350 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2351 | } |
| 2352 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2353 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
| 2354 | enum pipe *pipe) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2355 | { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2356 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2357 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2358 | struct drm_device *dev = encoder->base.dev; |
| 2359 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 2360 | enum intel_display_power_domain power_domain; |
| 2361 | u32 tmp; |
| 2362 | |
| 2363 | power_domain = intel_display_port_power_domain(encoder); |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 2364 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 2365 | return false; |
| 2366 | |
| 2367 | tmp = I915_READ(intel_dp->output_reg); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2368 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2369 | if (!(tmp & DP_PORT_EN)) |
| 2370 | return false; |
| 2371 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2372 | if (IS_GEN7(dev) && port == PORT_A) { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2373 | *pipe = PORT_TO_PIPE_CPT(tmp); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2374 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
Ville Syrjälä | adc289d | 2015-05-05 17:17:30 +0300 | [diff] [blame] | 2375 | enum pipe p; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2376 | |
Ville Syrjälä | adc289d | 2015-05-05 17:17:30 +0300 | [diff] [blame] | 2377 | for_each_pipe(dev_priv, p) { |
| 2378 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); |
| 2379 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { |
| 2380 | *pipe = p; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2381 | return true; |
| 2382 | } |
| 2383 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2384 | |
Daniel Vetter | 4a0833e | 2012-10-26 10:58:11 +0200 | [diff] [blame] | 2385 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2386 | i915_mmio_reg_offset(intel_dp->output_reg)); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2387 | } else if (IS_CHERRYVIEW(dev)) { |
| 2388 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
| 2389 | } else { |
| 2390 | *pipe = PORT_TO_PIPE(tmp); |
Daniel Vetter | 4a0833e | 2012-10-26 10:58:11 +0200 | [diff] [blame] | 2391 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2392 | |
| 2393 | return true; |
| 2394 | } |
| 2395 | |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2396 | static void intel_dp_get_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 2397 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2398 | { |
| 2399 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2400 | u32 tmp, flags = 0; |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2401 | struct drm_device *dev = encoder->base.dev; |
| 2402 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2403 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 2404 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 2405 | int dotclock; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2406 | |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 2407 | tmp = I915_READ(intel_dp->output_reg); |
Jani Nikula | 9fcb170 | 2015-05-05 16:32:12 +0300 | [diff] [blame] | 2408 | |
| 2409 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 2410 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2411 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
Ville Syrjälä | b81e34c | 2015-07-06 15:10:03 +0300 | [diff] [blame] | 2412 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
| 2413 | |
| 2414 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2415 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 2416 | else |
| 2417 | flags |= DRM_MODE_FLAG_NHSYNC; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2418 | |
Ville Syrjälä | b81e34c | 2015-07-06 15:10:03 +0300 | [diff] [blame] | 2419 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2420 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 2421 | else |
| 2422 | flags |= DRM_MODE_FLAG_NVSYNC; |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2423 | } else { |
| 2424 | if (tmp & DP_SYNC_HS_HIGH) |
| 2425 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 2426 | else |
| 2427 | flags |= DRM_MODE_FLAG_NHSYNC; |
| 2428 | |
| 2429 | if (tmp & DP_SYNC_VS_HIGH) |
| 2430 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 2431 | else |
| 2432 | flags |= DRM_MODE_FLAG_NVSYNC; |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2433 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2434 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 2435 | pipe_config->base.adjusted_mode.flags |= flags; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 2436 | |
Ville Syrjälä | 8c875fc | 2014-09-12 15:46:29 +0300 | [diff] [blame] | 2437 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2438 | !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) |
Ville Syrjälä | 8c875fc | 2014-09-12 15:46:29 +0300 | [diff] [blame] | 2439 | pipe_config->limited_color_range = true; |
| 2440 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 2441 | pipe_config->has_dp_encoder = true; |
| 2442 | |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 2443 | pipe_config->lane_count = |
| 2444 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; |
| 2445 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 2446 | intel_dp_get_m_n(crtc, pipe_config); |
| 2447 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 2448 | if (port == PORT_A) { |
Ville Syrjälä | b377e0d | 2015-10-29 21:25:59 +0200 | [diff] [blame] | 2449 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 2450 | pipe_config->port_clock = 162000; |
| 2451 | else |
| 2452 | pipe_config->port_clock = 270000; |
| 2453 | } |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 2454 | |
| 2455 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
| 2456 | &pipe_config->dp_m_n); |
| 2457 | |
| 2458 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) |
| 2459 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
| 2460 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 2461 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
Daniel Vetter | 7f16e5c | 2013-11-04 16:28:47 +0100 | [diff] [blame] | 2462 | |
Jani Nikula | c6cd2ee | 2013-10-21 10:52:07 +0300 | [diff] [blame] | 2463 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
| 2464 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
| 2465 | /* |
| 2466 | * This is a big fat ugly hack. |
| 2467 | * |
| 2468 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
| 2469 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
| 2470 | * unknown we fail to light up. Yet the same BIOS boots up with |
| 2471 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
| 2472 | * max, not what it tells us to use. |
| 2473 | * |
| 2474 | * Note: This will still be broken if the eDP panel is not lit |
| 2475 | * up by the BIOS, and thus we can't get the mode at module |
| 2476 | * load. |
| 2477 | */ |
| 2478 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
| 2479 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
| 2480 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
| 2481 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2482 | } |
| 2483 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2484 | static void intel_disable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2485 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2486 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 2487 | struct drm_device *dev = encoder->base.dev; |
Jani Nikula | 495a5bb | 2014-10-27 16:26:55 +0200 | [diff] [blame] | 2488 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 2489 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2490 | if (crtc->config->has_audio) |
Jani Nikula | 495a5bb | 2014-10-27 16:26:55 +0200 | [diff] [blame] | 2491 | intel_audio_codec_disable(encoder); |
Daniel Vetter | 6cb4983 | 2012-05-20 17:14:50 +0200 | [diff] [blame] | 2492 | |
Rodrigo Vivi | b32c6f4 | 2014-11-20 03:44:37 -0800 | [diff] [blame] | 2493 | if (HAS_PSR(dev) && !HAS_DDI(dev)) |
| 2494 | intel_psr_disable(intel_dp); |
| 2495 | |
Daniel Vetter | 6cb4983 | 2012-05-20 17:14:50 +0200 | [diff] [blame] | 2496 | /* Make sure the panel is off before trying to change the mode. But also |
| 2497 | * ensure that we have vdd while we switch off the panel. */ |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 2498 | intel_edp_panel_vdd_on(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2499 | intel_edp_backlight_off(intel_dp); |
Jani Nikula | fdbc3b1 | 2013-11-12 17:10:13 +0200 | [diff] [blame] | 2500 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2501 | intel_edp_panel_off(intel_dp); |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 2502 | |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 2503 | /* disable the port before the pipe on g4x */ |
| 2504 | if (INTEL_INFO(dev)->gen < 5) |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 2505 | intel_dp_link_down(intel_dp); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2506 | } |
| 2507 | |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 2508 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2509 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2510 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 2511 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2512 | |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 2513 | intel_dp_link_down(intel_dp); |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2514 | |
| 2515 | /* Only ilk+ has port A */ |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 2516 | if (port == PORT_A) |
| 2517 | ironlake_edp_pll_off(intel_dp); |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 2518 | } |
| 2519 | |
| 2520 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
| 2521 | { |
| 2522 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2523 | |
| 2524 | intel_dp_link_down(intel_dp); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2525 | } |
| 2526 | |
Ville Syrjälä | a8f327f | 2015-07-09 20:14:11 +0300 | [diff] [blame] | 2527 | static void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
| 2528 | bool reset) |
| 2529 | { |
| 2530 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 2531 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); |
| 2532 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 2533 | enum pipe pipe = crtc->pipe; |
| 2534 | uint32_t val; |
| 2535 | |
| 2536 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
| 2537 | if (reset) |
| 2538 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
| 2539 | else |
| 2540 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
| 2541 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
| 2542 | |
| 2543 | if (crtc->config->lane_count > 2) { |
| 2544 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
| 2545 | if (reset) |
| 2546 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
| 2547 | else |
| 2548 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
| 2549 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
| 2550 | } |
| 2551 | |
| 2552 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
| 2553 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
| 2554 | if (reset) |
| 2555 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
| 2556 | else |
| 2557 | val |= DPIO_PCS_CLK_SOFT_RESET; |
| 2558 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
| 2559 | |
| 2560 | if (crtc->config->lane_count > 2) { |
| 2561 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
| 2562 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
| 2563 | if (reset) |
| 2564 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
| 2565 | else |
| 2566 | val |= DPIO_PCS_CLK_SOFT_RESET; |
| 2567 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
| 2568 | } |
| 2569 | } |
| 2570 | |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2571 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
| 2572 | { |
| 2573 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2574 | struct drm_device *dev = encoder->base.dev; |
| 2575 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2576 | |
| 2577 | intel_dp_link_down(intel_dp); |
| 2578 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2579 | mutex_lock(&dev_priv->sb_lock); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2580 | |
Ville Syrjälä | a8f327f | 2015-07-09 20:14:11 +0300 | [diff] [blame] | 2581 | /* Assert data lane reset */ |
| 2582 | chv_data_lane_soft_reset(encoder, true); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2583 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2584 | mutex_unlock(&dev_priv->sb_lock); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2585 | } |
| 2586 | |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2587 | static void |
| 2588 | _intel_dp_set_link_train(struct intel_dp *intel_dp, |
| 2589 | uint32_t *DP, |
| 2590 | uint8_t dp_train_pat) |
| 2591 | { |
| 2592 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2593 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 2594 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2595 | enum port port = intel_dig_port->port; |
| 2596 | |
| 2597 | if (HAS_DDI(dev)) { |
| 2598 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
| 2599 | |
| 2600 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
| 2601 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2602 | else |
| 2603 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2604 | |
| 2605 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 2606 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2607 | case DP_TRAINING_PATTERN_DISABLE: |
| 2608 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
| 2609 | |
| 2610 | break; |
| 2611 | case DP_TRAINING_PATTERN_1: |
| 2612 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 2613 | break; |
| 2614 | case DP_TRAINING_PATTERN_2: |
| 2615 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
| 2616 | break; |
| 2617 | case DP_TRAINING_PATTERN_3: |
| 2618 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
| 2619 | break; |
| 2620 | } |
| 2621 | I915_WRITE(DP_TP_CTL(port), temp); |
| 2622 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2623 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
| 2624 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2625 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
| 2626 | |
| 2627 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2628 | case DP_TRAINING_PATTERN_DISABLE: |
| 2629 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
| 2630 | break; |
| 2631 | case DP_TRAINING_PATTERN_1: |
| 2632 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
| 2633 | break; |
| 2634 | case DP_TRAINING_PATTERN_2: |
| 2635 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
| 2636 | break; |
| 2637 | case DP_TRAINING_PATTERN_3: |
| 2638 | DRM_ERROR("DP training pattern 3 not supported\n"); |
| 2639 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
| 2640 | break; |
| 2641 | } |
| 2642 | |
| 2643 | } else { |
| 2644 | if (IS_CHERRYVIEW(dev)) |
| 2645 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
| 2646 | else |
| 2647 | *DP &= ~DP_LINK_TRAIN_MASK; |
| 2648 | |
| 2649 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2650 | case DP_TRAINING_PATTERN_DISABLE: |
| 2651 | *DP |= DP_LINK_TRAIN_OFF; |
| 2652 | break; |
| 2653 | case DP_TRAINING_PATTERN_1: |
| 2654 | *DP |= DP_LINK_TRAIN_PAT_1; |
| 2655 | break; |
| 2656 | case DP_TRAINING_PATTERN_2: |
| 2657 | *DP |= DP_LINK_TRAIN_PAT_2; |
| 2658 | break; |
| 2659 | case DP_TRAINING_PATTERN_3: |
| 2660 | if (IS_CHERRYVIEW(dev)) { |
| 2661 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
| 2662 | } else { |
| 2663 | DRM_ERROR("DP training pattern 3 not supported\n"); |
| 2664 | *DP |= DP_LINK_TRAIN_PAT_2; |
| 2665 | } |
| 2666 | break; |
| 2667 | } |
| 2668 | } |
| 2669 | } |
| 2670 | |
| 2671 | static void intel_dp_enable_port(struct intel_dp *intel_dp) |
| 2672 | { |
| 2673 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 2674 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2675 | struct intel_crtc *crtc = |
| 2676 | to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2677 | |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2678 | /* enable with pattern 1 (as per spec) */ |
| 2679 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
| 2680 | DP_TRAINING_PATTERN_1); |
| 2681 | |
| 2682 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 2683 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | 7b713f5 | 2014-10-16 21:27:35 +0300 | [diff] [blame] | 2684 | |
| 2685 | /* |
| 2686 | * Magic for VLV/CHV. We _must_ first set up the register |
| 2687 | * without actually enabling the port, and then do another |
| 2688 | * write to enable the port. Otherwise link training will |
| 2689 | * fail when the power sequencer is freshly used for this port. |
| 2690 | */ |
| 2691 | intel_dp->DP |= DP_PORT_EN; |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2692 | if (crtc->config->has_audio) |
| 2693 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
Ville Syrjälä | 7b713f5 | 2014-10-16 21:27:35 +0300 | [diff] [blame] | 2694 | |
| 2695 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 2696 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2697 | } |
| 2698 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2699 | static void intel_enable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2700 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2701 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2702 | struct drm_device *dev = encoder->base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2703 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2704 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2705 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2706 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 2707 | enum pipe pipe = crtc->pipe; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2708 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 2709 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
| 2710 | return; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2711 | |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2712 | pps_lock(intel_dp); |
| 2713 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2714 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2715 | vlv_init_panel_power_sequencer(intel_dp); |
| 2716 | |
Ville Syrjälä | 7864578 | 2015-11-20 22:09:19 +0200 | [diff] [blame] | 2717 | /* |
| 2718 | * We get an occasional spurious underrun between the port |
| 2719 | * enable and vdd enable, when enabling port A eDP. |
| 2720 | * |
| 2721 | * FIXME: Not sure if this applies to (PCH) port D eDP as well |
| 2722 | */ |
| 2723 | if (port == PORT_A) |
| 2724 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
| 2725 | |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2726 | intel_dp_enable_port(intel_dp); |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2727 | |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2728 | if (port == PORT_A && IS_GEN5(dev_priv)) { |
| 2729 | /* |
| 2730 | * Underrun reporting for the other pipe was disabled in |
| 2731 | * g4x_pre_enable_dp(). The eDP PLL and port have now been |
| 2732 | * enabled, so it's now safe to re-enable underrun reporting. |
| 2733 | */ |
| 2734 | intel_wait_for_vblank_if_active(dev_priv->dev, !pipe); |
| 2735 | intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true); |
| 2736 | intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true); |
| 2737 | } |
| 2738 | |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2739 | edp_panel_vdd_on(intel_dp); |
| 2740 | edp_panel_on(intel_dp); |
| 2741 | edp_panel_vdd_off(intel_dp, true); |
| 2742 | |
Ville Syrjälä | 7864578 | 2015-11-20 22:09:19 +0200 | [diff] [blame] | 2743 | if (port == PORT_A) |
| 2744 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
| 2745 | |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2746 | pps_unlock(intel_dp); |
| 2747 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2748 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2749 | unsigned int lane_mask = 0x0; |
| 2750 | |
| 2751 | if (IS_CHERRYVIEW(dev)) |
| 2752 | lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); |
| 2753 | |
Ville Syrjälä | 9b6de0a | 2015-04-10 18:21:31 +0300 | [diff] [blame] | 2754 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
| 2755 | lane_mask); |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2756 | } |
Ville Syrjälä | 61234fa | 2014-10-16 21:27:34 +0300 | [diff] [blame] | 2757 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2758 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
| 2759 | intel_dp_start_link_train(intel_dp); |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2760 | intel_dp_stop_link_train(intel_dp); |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2761 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2762 | if (crtc->config->has_audio) { |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2763 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2764 | pipe_name(pipe)); |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2765 | intel_audio_codec_enable(encoder); |
| 2766 | } |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2767 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2768 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 2769 | static void g4x_enable_dp(struct intel_encoder *encoder) |
| 2770 | { |
Jani Nikula | 828f5c6 | 2013-09-05 16:44:45 +0300 | [diff] [blame] | 2771 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2772 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 2773 | intel_enable_dp(encoder); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2774 | intel_edp_backlight_on(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2775 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2776 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2777 | static void vlv_enable_dp(struct intel_encoder *encoder) |
| 2778 | { |
Jani Nikula | 828f5c6 | 2013-09-05 16:44:45 +0300 | [diff] [blame] | 2779 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2780 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2781 | intel_edp_backlight_on(intel_dp); |
Rodrigo Vivi | b32c6f4 | 2014-11-20 03:44:37 -0800 | [diff] [blame] | 2782 | intel_psr_enable(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2783 | } |
| 2784 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 2785 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2786 | { |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2787 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2788 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2789 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 2790 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2791 | |
Daniel Vetter | 8ac33ed | 2014-04-24 23:54:54 +0200 | [diff] [blame] | 2792 | intel_dp_prepare(encoder); |
| 2793 | |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2794 | if (port == PORT_A && IS_GEN5(dev_priv)) { |
| 2795 | /* |
| 2796 | * We get FIFO underruns on the other pipe when |
| 2797 | * enabling the CPU eDP PLL, and when enabling CPU |
| 2798 | * eDP port. We could potentially avoid the PLL |
| 2799 | * underrun with a vblank wait just prior to enabling |
| 2800 | * the PLL, but that doesn't appear to help the port |
| 2801 | * enable case. Just sweep it all under the rug. |
| 2802 | */ |
| 2803 | intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false); |
| 2804 | intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false); |
| 2805 | } |
| 2806 | |
Daniel Vetter | d41f1ef | 2014-04-24 23:54:53 +0200 | [diff] [blame] | 2807 | /* Only ilk+ has port A */ |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2808 | if (port == PORT_A) |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2809 | ironlake_edp_pll_on(intel_dp); |
| 2810 | } |
| 2811 | |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2812 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
| 2813 | { |
| 2814 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2815 | struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; |
| 2816 | enum pipe pipe = intel_dp->pps_pipe; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2817 | i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2818 | |
| 2819 | edp_panel_vdd_off_sync(intel_dp); |
| 2820 | |
| 2821 | /* |
| 2822 | * VLV seems to get confused when multiple power seqeuencers |
| 2823 | * have the same port selected (even if only one has power/vdd |
| 2824 | * enabled). The failure manifests as vlv_wait_port_ready() failing |
| 2825 | * CHV on the other hand doesn't seem to mind having the same port |
| 2826 | * selected in multiple power seqeuencers, but let's clear the |
| 2827 | * port select always when logically disconnecting a power sequencer |
| 2828 | * from a port. |
| 2829 | */ |
| 2830 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", |
| 2831 | pipe_name(pipe), port_name(intel_dig_port->port)); |
| 2832 | I915_WRITE(pp_on_reg, 0); |
| 2833 | POSTING_READ(pp_on_reg); |
| 2834 | |
| 2835 | intel_dp->pps_pipe = INVALID_PIPE; |
| 2836 | } |
| 2837 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2838 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
| 2839 | enum pipe pipe) |
| 2840 | { |
| 2841 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2842 | struct intel_encoder *encoder; |
| 2843 | |
| 2844 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2845 | |
Ville Syrjälä | ac3c12e | 2014-10-16 21:29:56 +0300 | [diff] [blame] | 2846 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
| 2847 | return; |
| 2848 | |
Jani Nikula | 19c8054 | 2015-12-16 12:48:16 +0200 | [diff] [blame] | 2849 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2850 | struct intel_dp *intel_dp; |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2851 | enum port port; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2852 | |
| 2853 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 2854 | continue; |
| 2855 | |
| 2856 | intel_dp = enc_to_intel_dp(&encoder->base); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2857 | port = dp_to_dig_port(intel_dp)->port; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2858 | |
| 2859 | if (intel_dp->pps_pipe != pipe) |
| 2860 | continue; |
| 2861 | |
| 2862 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2863 | pipe_name(pipe), port_name(port)); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2864 | |
Maarten Lankhorst | e02f9a0 | 2015-08-05 12:37:08 +0200 | [diff] [blame] | 2865 | WARN(encoder->base.crtc, |
Ville Syrjälä | 034e43c | 2014-10-16 21:27:28 +0300 | [diff] [blame] | 2866 | "stealing pipe %c power sequencer from active eDP port %c\n", |
| 2867 | pipe_name(pipe), port_name(port)); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2868 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2869 | /* make sure vdd is off before we steal it */ |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2870 | vlv_detach_power_sequencer(intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2871 | } |
| 2872 | } |
| 2873 | |
| 2874 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) |
| 2875 | { |
| 2876 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2877 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 2878 | struct drm_device *dev = encoder->base.dev; |
| 2879 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2880 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2881 | |
| 2882 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2883 | |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2884 | if (!is_edp(intel_dp)) |
| 2885 | return; |
| 2886 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2887 | if (intel_dp->pps_pipe == crtc->pipe) |
| 2888 | return; |
| 2889 | |
| 2890 | /* |
| 2891 | * If another power sequencer was being used on this |
| 2892 | * port previously make sure to turn off vdd there while |
| 2893 | * we still have control of it. |
| 2894 | */ |
| 2895 | if (intel_dp->pps_pipe != INVALID_PIPE) |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2896 | vlv_detach_power_sequencer(intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2897 | |
| 2898 | /* |
| 2899 | * We may be stealing the power |
| 2900 | * sequencer from another port. |
| 2901 | */ |
| 2902 | vlv_steal_power_sequencer(dev, crtc->pipe); |
| 2903 | |
| 2904 | /* now it's all ours */ |
| 2905 | intel_dp->pps_pipe = crtc->pipe; |
| 2906 | |
| 2907 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", |
| 2908 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); |
| 2909 | |
| 2910 | /* init power sequencer on this pipe and port */ |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 2911 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 2912 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2913 | } |
| 2914 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2915 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
| 2916 | { |
| 2917 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2918 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
Jesse Barnes | b263401 | 2013-03-28 09:55:40 -0700 | [diff] [blame] | 2919 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2920 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2921 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 2922 | enum dpio_channel port = vlv_dport_to_channel(dport); |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2923 | int pipe = intel_crtc->pipe; |
| 2924 | u32 val; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2925 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2926 | mutex_lock(&dev_priv->sb_lock); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2927 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2928 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2929 | val = 0; |
| 2930 | if (pipe) |
| 2931 | val |= (1<<21); |
| 2932 | else |
| 2933 | val &= ~(1<<21); |
| 2934 | val |= 0x001000c4; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2935 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
| 2936 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
| 2937 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2938 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2939 | mutex_unlock(&dev_priv->sb_lock); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2940 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2941 | intel_enable_dp(encoder); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2942 | } |
| 2943 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 2944 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2945 | { |
| 2946 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
| 2947 | struct drm_device *dev = encoder->base.dev; |
| 2948 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 2949 | struct intel_crtc *intel_crtc = |
| 2950 | to_intel_crtc(encoder->base.crtc); |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 2951 | enum dpio_channel port = vlv_dport_to_channel(dport); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 2952 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2953 | |
Daniel Vetter | 8ac33ed | 2014-04-24 23:54:54 +0200 | [diff] [blame] | 2954 | intel_dp_prepare(encoder); |
| 2955 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2956 | /* Program Tx lane resets to default */ |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2957 | mutex_lock(&dev_priv->sb_lock); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2958 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2959 | DPIO_PCS_TX_LANE2_RESET | |
| 2960 | DPIO_PCS_TX_LANE1_RESET); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2961 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2962 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
| 2963 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
| 2964 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | |
| 2965 | DPIO_PCS_CLK_SOFT_RESET); |
| 2966 | |
| 2967 | /* Fix up inter-pair skew failure */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2968 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
| 2969 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
| 2970 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2971 | mutex_unlock(&dev_priv->sb_lock); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2972 | } |
| 2973 | |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2974 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
| 2975 | { |
| 2976 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2977 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 2978 | struct drm_device *dev = encoder->base.dev; |
| 2979 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2980 | struct intel_crtc *intel_crtc = |
| 2981 | to_intel_crtc(encoder->base.crtc); |
| 2982 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 2983 | int pipe = intel_crtc->pipe; |
Ville Syrjälä | 2e523e9 | 2015-04-10 18:21:27 +0300 | [diff] [blame] | 2984 | int data, i, stagger; |
Ville Syrjälä | 949c1d4 | 2014-04-09 13:28:58 +0300 | [diff] [blame] | 2985 | u32 val; |
| 2986 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2987 | mutex_lock(&dev_priv->sb_lock); |
Ville Syrjälä | 949c1d4 | 2014-04-09 13:28:58 +0300 | [diff] [blame] | 2988 | |
Ville Syrjälä | 570e2a7 | 2014-08-18 14:42:46 +0300 | [diff] [blame] | 2989 | /* allow hardware to manage TX FIFO reset source */ |
| 2990 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
| 2991 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
| 2992 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
| 2993 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2994 | if (intel_crtc->config->lane_count > 2) { |
| 2995 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
| 2996 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
| 2997 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
| 2998 | } |
Ville Syrjälä | 570e2a7 | 2014-08-18 14:42:46 +0300 | [diff] [blame] | 2999 | |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3000 | /* Program Tx lane latency optimal setting*/ |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3001 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3002 | /* Set the upar bit */ |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3003 | if (intel_crtc->config->lane_count == 1) |
| 3004 | data = 0x0; |
| 3005 | else |
| 3006 | data = (i == 1) ? 0x0 : 0x1; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3007 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
| 3008 | data << DPIO_UPAR_SHIFT); |
| 3009 | } |
| 3010 | |
| 3011 | /* Data lane stagger programming */ |
Ville Syrjälä | 2e523e9 | 2015-04-10 18:21:27 +0300 | [diff] [blame] | 3012 | if (intel_crtc->config->port_clock > 270000) |
| 3013 | stagger = 0x18; |
| 3014 | else if (intel_crtc->config->port_clock > 135000) |
| 3015 | stagger = 0xd; |
| 3016 | else if (intel_crtc->config->port_clock > 67500) |
| 3017 | stagger = 0x7; |
| 3018 | else if (intel_crtc->config->port_clock > 33750) |
| 3019 | stagger = 0x4; |
| 3020 | else |
| 3021 | stagger = 0x2; |
| 3022 | |
| 3023 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
| 3024 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
| 3025 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
| 3026 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3027 | if (intel_crtc->config->lane_count > 2) { |
| 3028 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
| 3029 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
| 3030 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
| 3031 | } |
Ville Syrjälä | 2e523e9 | 2015-04-10 18:21:27 +0300 | [diff] [blame] | 3032 | |
| 3033 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), |
| 3034 | DPIO_LANESTAGGER_STRAP(stagger) | |
| 3035 | DPIO_LANESTAGGER_STRAP_OVRD | |
| 3036 | DPIO_TX1_STAGGER_MASK(0x1f) | |
| 3037 | DPIO_TX1_STAGGER_MULT(6) | |
| 3038 | DPIO_TX2_STAGGER_MULT(0)); |
| 3039 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3040 | if (intel_crtc->config->lane_count > 2) { |
| 3041 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), |
| 3042 | DPIO_LANESTAGGER_STRAP(stagger) | |
| 3043 | DPIO_LANESTAGGER_STRAP_OVRD | |
| 3044 | DPIO_TX1_STAGGER_MASK(0x1f) | |
| 3045 | DPIO_TX1_STAGGER_MULT(7) | |
| 3046 | DPIO_TX2_STAGGER_MULT(5)); |
| 3047 | } |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3048 | |
Ville Syrjälä | a8f327f | 2015-07-09 20:14:11 +0300 | [diff] [blame] | 3049 | /* Deassert data lane reset */ |
| 3050 | chv_data_lane_soft_reset(encoder, false); |
| 3051 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 3052 | mutex_unlock(&dev_priv->sb_lock); |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3053 | |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3054 | intel_enable_dp(encoder); |
Ville Syrjälä | b0b3384 | 2015-07-08 23:45:55 +0300 | [diff] [blame] | 3055 | |
| 3056 | /* Second common lane will stay alive on its own now */ |
| 3057 | if (dport->release_cl2_override) { |
| 3058 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); |
| 3059 | dport->release_cl2_override = false; |
| 3060 | } |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3061 | } |
| 3062 | |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 3063 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
| 3064 | { |
| 3065 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
| 3066 | struct drm_device *dev = encoder->base.dev; |
| 3067 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3068 | struct intel_crtc *intel_crtc = |
| 3069 | to_intel_crtc(encoder->base.crtc); |
| 3070 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 3071 | enum pipe pipe = intel_crtc->pipe; |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3072 | unsigned int lane_mask = |
| 3073 | intel_dp_unused_lane_mask(intel_crtc->config->lane_count); |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 3074 | u32 val; |
| 3075 | |
Ville Syrjälä | 625695f | 2014-06-28 02:04:02 +0300 | [diff] [blame] | 3076 | intel_dp_prepare(encoder); |
| 3077 | |
Ville Syrjälä | b0b3384 | 2015-07-08 23:45:55 +0300 | [diff] [blame] | 3078 | /* |
| 3079 | * Must trick the second common lane into life. |
| 3080 | * Otherwise we can't even access the PLL. |
| 3081 | */ |
| 3082 | if (ch == DPIO_CH0 && pipe == PIPE_B) |
| 3083 | dport->release_cl2_override = |
| 3084 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); |
| 3085 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3086 | chv_phy_powergate_lanes(encoder, true, lane_mask); |
| 3087 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 3088 | mutex_lock(&dev_priv->sb_lock); |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 3089 | |
Ville Syrjälä | a8f327f | 2015-07-09 20:14:11 +0300 | [diff] [blame] | 3090 | /* Assert data lane reset */ |
| 3091 | chv_data_lane_soft_reset(encoder, true); |
| 3092 | |
Ville Syrjälä | b9e5ac3 | 2014-05-27 16:30:18 +0300 | [diff] [blame] | 3093 | /* program left/right clock distribution */ |
| 3094 | if (pipe != PIPE_B) { |
| 3095 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
| 3096 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
| 3097 | if (ch == DPIO_CH0) |
| 3098 | val |= CHV_BUFLEFTENA1_FORCE; |
| 3099 | if (ch == DPIO_CH1) |
| 3100 | val |= CHV_BUFRIGHTENA1_FORCE; |
| 3101 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
| 3102 | } else { |
| 3103 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
| 3104 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
| 3105 | if (ch == DPIO_CH0) |
| 3106 | val |= CHV_BUFLEFTENA2_FORCE; |
| 3107 | if (ch == DPIO_CH1) |
| 3108 | val |= CHV_BUFRIGHTENA2_FORCE; |
| 3109 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
| 3110 | } |
| 3111 | |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 3112 | /* program clock channel usage */ |
| 3113 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
| 3114 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
| 3115 | if (pipe != PIPE_B) |
| 3116 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
| 3117 | else |
| 3118 | val |= CHV_PCS_USEDCLKCHANNEL; |
| 3119 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
| 3120 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3121 | if (intel_crtc->config->lane_count > 2) { |
| 3122 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
| 3123 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
| 3124 | if (pipe != PIPE_B) |
| 3125 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
| 3126 | else |
| 3127 | val |= CHV_PCS_USEDCLKCHANNEL; |
| 3128 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
| 3129 | } |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 3130 | |
| 3131 | /* |
| 3132 | * This a a bit weird since generally CL |
| 3133 | * matches the pipe, but here we need to |
| 3134 | * pick the CL based on the port. |
| 3135 | */ |
| 3136 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
| 3137 | if (pipe != PIPE_B) |
| 3138 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
| 3139 | else |
| 3140 | val |= CHV_CMN_USEDCLKCHANNEL; |
| 3141 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
| 3142 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 3143 | mutex_unlock(&dev_priv->sb_lock); |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 3144 | } |
| 3145 | |
Ville Syrjälä | d6db995 | 2015-07-08 23:45:49 +0300 | [diff] [blame] | 3146 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder) |
| 3147 | { |
| 3148 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 3149 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
| 3150 | u32 val; |
| 3151 | |
| 3152 | mutex_lock(&dev_priv->sb_lock); |
| 3153 | |
| 3154 | /* disable left/right clock distribution */ |
| 3155 | if (pipe != PIPE_B) { |
| 3156 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
| 3157 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
| 3158 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
| 3159 | } else { |
| 3160 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
| 3161 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
| 3162 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
| 3163 | } |
| 3164 | |
| 3165 | mutex_unlock(&dev_priv->sb_lock); |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3166 | |
Ville Syrjälä | b0b3384 | 2015-07-08 23:45:55 +0300 | [diff] [blame] | 3167 | /* |
| 3168 | * Leave the power down bit cleared for at least one |
| 3169 | * lane so that chv_powergate_phy_ch() will power |
| 3170 | * on something when the channel is otherwise unused. |
| 3171 | * When the port is off and the override is removed |
| 3172 | * the lanes power down anyway, so otherwise it doesn't |
| 3173 | * really matter what the state of power down bits is |
| 3174 | * after this. |
| 3175 | */ |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3176 | chv_phy_powergate_lanes(encoder, false, 0x0); |
Ville Syrjälä | d6db995 | 2015-07-08 23:45:49 +0300 | [diff] [blame] | 3177 | } |
| 3178 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3179 | /* |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 3180 | * Native read with retry for link status and receiver capability reads for |
| 3181 | * cases where the sink may still be asleep. |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3182 | * |
| 3183 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also |
| 3184 | * supposed to retry 3 times per the spec. |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 3185 | */ |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3186 | static ssize_t |
| 3187 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
| 3188 | void *buffer, size_t size) |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 3189 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3190 | ssize_t ret; |
| 3191 | int i; |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 3192 | |
Ville Syrjälä | f6a1906 | 2014-10-16 20:46:09 +0300 | [diff] [blame] | 3193 | /* |
| 3194 | * Sometime we just get the same incorrect byte repeated |
| 3195 | * over the entire buffer. Doing just one throw away read |
| 3196 | * initially seems to "solve" it. |
| 3197 | */ |
| 3198 | drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1); |
| 3199 | |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 3200 | for (i = 0; i < 3; i++) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3201 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
| 3202 | if (ret == size) |
| 3203 | return ret; |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 3204 | msleep(1); |
| 3205 | } |
| 3206 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3207 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3208 | } |
| 3209 | |
| 3210 | /* |
| 3211 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
| 3212 | * link status information |
| 3213 | */ |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3214 | bool |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 3215 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3216 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3217 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 3218 | DP_LANE0_1_STATUS, |
| 3219 | link_status, |
| 3220 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3221 | } |
| 3222 | |
Paulo Zanoni | 1100244 | 2014-06-13 18:45:41 -0300 | [diff] [blame] | 3223 | /* These are source-specific values. */ |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3224 | uint8_t |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3225 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3226 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 3227 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Sonika Jindal | 7ad14a2 | 2015-02-25 10:29:12 +0530 | [diff] [blame] | 3228 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3229 | enum port port = dp_to_dig_port(intel_dp)->port; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3230 | |
Vandana Kannan | 9314726 | 2014-11-18 15:45:29 +0530 | [diff] [blame] | 3231 | if (IS_BROXTON(dev)) |
| 3232 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
| 3233 | else if (INTEL_INFO(dev)->gen >= 9) { |
Sonika Jindal | 9e45803 | 2015-05-06 17:35:48 +0530 | [diff] [blame] | 3234 | if (dev_priv->edp_low_vswing && port == PORT_A) |
Sonika Jindal | 7ad14a2 | 2015-02-25 10:29:12 +0530 | [diff] [blame] | 3235 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
Damien Lespiau | 5a9d1f1 | 2013-12-03 13:56:26 +0000 | [diff] [blame] | 3236 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 3237 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3238 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3239 | else if (IS_GEN7(dev) && port == PORT_A) |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3240 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3241 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3242 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3243 | else |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3244 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3245 | } |
| 3246 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3247 | uint8_t |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3248 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
| 3249 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 3250 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3251 | enum port port = dp_to_dig_port(intel_dp)->port; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3252 | |
Damien Lespiau | 5a9d1f1 | 2013-12-03 13:56:26 +0000 | [diff] [blame] | 3253 | if (INTEL_INFO(dev)->gen >= 9) { |
| 3254 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3255 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3256 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 3257 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3258 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3259 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3260 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
Sonika Jindal | 7ad14a2 | 2015-02-25 10:29:12 +0530 | [diff] [blame] | 3261 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 3262 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Damien Lespiau | 5a9d1f1 | 2013-12-03 13:56:26 +0000 | [diff] [blame] | 3263 | default: |
| 3264 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 3265 | } |
| 3266 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 3267 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3268 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3269 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 3270 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3271 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3272 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3273 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 3274 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 3275 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3276 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 3277 | } |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 3278 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3279 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3280 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3281 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 3282 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3283 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3284 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3285 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 3286 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3287 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3288 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3289 | } |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3290 | } else if (IS_GEN7(dev) && port == PORT_A) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3291 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3292 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3293 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3294 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3295 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3296 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3297 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3298 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3299 | } |
| 3300 | } else { |
| 3301 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3302 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3303 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3304 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3305 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 3306 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3307 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 3308 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3309 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3310 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3311 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3312 | } |
| 3313 | } |
| 3314 | |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3315 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3316 | { |
| 3317 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 3318 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3319 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 3320 | struct intel_crtc *intel_crtc = |
| 3321 | to_intel_crtc(dport->base.base.crtc); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3322 | unsigned long demph_reg_value, preemph_reg_value, |
| 3323 | uniqtranscale_reg_value; |
| 3324 | uint8_t train_set = intel_dp->train_set[0]; |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 3325 | enum dpio_channel port = vlv_dport_to_channel(dport); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 3326 | int pipe = intel_crtc->pipe; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3327 | |
| 3328 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3329 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3330 | preemph_reg_value = 0x0004000; |
| 3331 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3332 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3333 | demph_reg_value = 0x2B405555; |
| 3334 | uniqtranscale_reg_value = 0x552AB83A; |
| 3335 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3336 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3337 | demph_reg_value = 0x2B404040; |
| 3338 | uniqtranscale_reg_value = 0x5548B83A; |
| 3339 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3340 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3341 | demph_reg_value = 0x2B245555; |
| 3342 | uniqtranscale_reg_value = 0x5560B83A; |
| 3343 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3344 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3345 | demph_reg_value = 0x2B405555; |
| 3346 | uniqtranscale_reg_value = 0x5598DA3A; |
| 3347 | break; |
| 3348 | default: |
| 3349 | return 0; |
| 3350 | } |
| 3351 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3352 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3353 | preemph_reg_value = 0x0002000; |
| 3354 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3355 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3356 | demph_reg_value = 0x2B404040; |
| 3357 | uniqtranscale_reg_value = 0x5552B83A; |
| 3358 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3359 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3360 | demph_reg_value = 0x2B404848; |
| 3361 | uniqtranscale_reg_value = 0x5580B83A; |
| 3362 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3363 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3364 | demph_reg_value = 0x2B404040; |
| 3365 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3366 | break; |
| 3367 | default: |
| 3368 | return 0; |
| 3369 | } |
| 3370 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3371 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3372 | preemph_reg_value = 0x0000000; |
| 3373 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3374 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3375 | demph_reg_value = 0x2B305555; |
| 3376 | uniqtranscale_reg_value = 0x5570B83A; |
| 3377 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3378 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3379 | demph_reg_value = 0x2B2B4040; |
| 3380 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3381 | break; |
| 3382 | default: |
| 3383 | return 0; |
| 3384 | } |
| 3385 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3386 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3387 | preemph_reg_value = 0x0006000; |
| 3388 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3389 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3390 | demph_reg_value = 0x1B405555; |
| 3391 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3392 | break; |
| 3393 | default: |
| 3394 | return 0; |
| 3395 | } |
| 3396 | break; |
| 3397 | default: |
| 3398 | return 0; |
| 3399 | } |
| 3400 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 3401 | mutex_lock(&dev_priv->sb_lock); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 3402 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
| 3403 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
| 3404 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3405 | uniqtranscale_reg_value); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 3406 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
| 3407 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
| 3408 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
| 3409 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 3410 | mutex_unlock(&dev_priv->sb_lock); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3411 | |
| 3412 | return 0; |
| 3413 | } |
| 3414 | |
Ville Syrjälä | 67fa24b | 2015-07-08 23:45:48 +0300 | [diff] [blame] | 3415 | static bool chv_need_uniq_trans_scale(uint8_t train_set) |
| 3416 | { |
| 3417 | return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 && |
| 3418 | (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
| 3419 | } |
| 3420 | |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3421 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3422 | { |
| 3423 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 3424 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3425 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 3426 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); |
Ville Syrjälä | f72df8d | 2014-04-09 13:29:03 +0300 | [diff] [blame] | 3427 | u32 deemph_reg_value, margin_reg_value, val; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3428 | uint8_t train_set = intel_dp->train_set[0]; |
| 3429 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
Ville Syrjälä | f72df8d | 2014-04-09 13:29:03 +0300 | [diff] [blame] | 3430 | enum pipe pipe = intel_crtc->pipe; |
| 3431 | int i; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3432 | |
| 3433 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3434 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3435 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3436 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3437 | deemph_reg_value = 128; |
| 3438 | margin_reg_value = 52; |
| 3439 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3440 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3441 | deemph_reg_value = 128; |
| 3442 | margin_reg_value = 77; |
| 3443 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3444 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3445 | deemph_reg_value = 128; |
| 3446 | margin_reg_value = 102; |
| 3447 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3448 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3449 | deemph_reg_value = 128; |
| 3450 | margin_reg_value = 154; |
| 3451 | /* FIXME extra to set for 1200 */ |
| 3452 | break; |
| 3453 | default: |
| 3454 | return 0; |
| 3455 | } |
| 3456 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3457 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3458 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3459 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3460 | deemph_reg_value = 85; |
| 3461 | margin_reg_value = 78; |
| 3462 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3463 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3464 | deemph_reg_value = 85; |
| 3465 | margin_reg_value = 116; |
| 3466 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3467 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3468 | deemph_reg_value = 85; |
| 3469 | margin_reg_value = 154; |
| 3470 | break; |
| 3471 | default: |
| 3472 | return 0; |
| 3473 | } |
| 3474 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3475 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3476 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3477 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3478 | deemph_reg_value = 64; |
| 3479 | margin_reg_value = 104; |
| 3480 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3481 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3482 | deemph_reg_value = 64; |
| 3483 | margin_reg_value = 154; |
| 3484 | break; |
| 3485 | default: |
| 3486 | return 0; |
| 3487 | } |
| 3488 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3489 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3490 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3491 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3492 | deemph_reg_value = 43; |
| 3493 | margin_reg_value = 154; |
| 3494 | break; |
| 3495 | default: |
| 3496 | return 0; |
| 3497 | } |
| 3498 | break; |
| 3499 | default: |
| 3500 | return 0; |
| 3501 | } |
| 3502 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 3503 | mutex_lock(&dev_priv->sb_lock); |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3504 | |
| 3505 | /* Clear calc init */ |
Ville Syrjälä | 1966e59 | 2014-04-09 13:29:04 +0300 | [diff] [blame] | 3506 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
| 3507 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
Ville Syrjälä | a02ef3c | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 3508 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
| 3509 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
Ville Syrjälä | 1966e59 | 2014-04-09 13:29:04 +0300 | [diff] [blame] | 3510 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
| 3511 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3512 | if (intel_crtc->config->lane_count > 2) { |
| 3513 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
| 3514 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
| 3515 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
| 3516 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
| 3517 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
| 3518 | } |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3519 | |
Ville Syrjälä | a02ef3c | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 3520 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
| 3521 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
| 3522 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
| 3523 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
| 3524 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3525 | if (intel_crtc->config->lane_count > 2) { |
| 3526 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
| 3527 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
| 3528 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
| 3529 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
| 3530 | } |
Ville Syrjälä | a02ef3c | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 3531 | |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3532 | /* Program swing deemph */ |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3533 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
Ville Syrjälä | f72df8d | 2014-04-09 13:29:03 +0300 | [diff] [blame] | 3534 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
| 3535 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
| 3536 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; |
| 3537 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
| 3538 | } |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3539 | |
| 3540 | /* Program swing margin */ |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3541 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
Ville Syrjälä | f72df8d | 2014-04-09 13:29:03 +0300 | [diff] [blame] | 3542 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
Ville Syrjälä | 67fa24b | 2015-07-08 23:45:48 +0300 | [diff] [blame] | 3543 | |
Ville Syrjälä | 1fb4450 | 2014-06-28 02:04:03 +0300 | [diff] [blame] | 3544 | val &= ~DPIO_SWING_MARGIN000_MASK; |
| 3545 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; |
Ville Syrjälä | 67fa24b | 2015-07-08 23:45:48 +0300 | [diff] [blame] | 3546 | |
| 3547 | /* |
| 3548 | * Supposedly this value shouldn't matter when unique transition |
| 3549 | * scale is disabled, but in fact it does matter. Let's just |
| 3550 | * always program the same value and hope it's OK. |
| 3551 | */ |
| 3552 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
| 3553 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; |
| 3554 | |
Ville Syrjälä | f72df8d | 2014-04-09 13:29:03 +0300 | [diff] [blame] | 3555 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
| 3556 | } |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3557 | |
Ville Syrjälä | 67fa24b | 2015-07-08 23:45:48 +0300 | [diff] [blame] | 3558 | /* |
| 3559 | * The document said it needs to set bit 27 for ch0 and bit 26 |
| 3560 | * for ch1. Might be a typo in the doc. |
| 3561 | * For now, for this unique transition scale selection, set bit |
| 3562 | * 27 for ch0 and ch1. |
| 3563 | */ |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3564 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
Ville Syrjälä | f72df8d | 2014-04-09 13:29:03 +0300 | [diff] [blame] | 3565 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
Ville Syrjälä | 67fa24b | 2015-07-08 23:45:48 +0300 | [diff] [blame] | 3566 | if (chv_need_uniq_trans_scale(train_set)) |
Ville Syrjälä | f72df8d | 2014-04-09 13:29:03 +0300 | [diff] [blame] | 3567 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; |
Ville Syrjälä | 67fa24b | 2015-07-08 23:45:48 +0300 | [diff] [blame] | 3568 | else |
| 3569 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
| 3570 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3571 | } |
| 3572 | |
| 3573 | /* Start swing calculation */ |
Ville Syrjälä | 1966e59 | 2014-04-09 13:29:04 +0300 | [diff] [blame] | 3574 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
| 3575 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
| 3576 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
| 3577 | |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 3578 | if (intel_crtc->config->lane_count > 2) { |
| 3579 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
| 3580 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
| 3581 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
| 3582 | } |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3583 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 3584 | mutex_unlock(&dev_priv->sb_lock); |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3585 | |
| 3586 | return 0; |
| 3587 | } |
| 3588 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3589 | static uint32_t |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3590 | gen4_signal_levels(uint8_t train_set) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3591 | { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 3592 | uint32_t signal_levels = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3593 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 3594 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3595 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3596 | default: |
| 3597 | signal_levels |= DP_VOLTAGE_0_4; |
| 3598 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3599 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3600 | signal_levels |= DP_VOLTAGE_0_6; |
| 3601 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3602 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3603 | signal_levels |= DP_VOLTAGE_0_8; |
| 3604 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3605 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3606 | signal_levels |= DP_VOLTAGE_1_2; |
| 3607 | break; |
| 3608 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 3609 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3610 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3611 | default: |
| 3612 | signal_levels |= DP_PRE_EMPHASIS_0; |
| 3613 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3614 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3615 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
| 3616 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3617 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3618 | signal_levels |= DP_PRE_EMPHASIS_6; |
| 3619 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3620 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3621 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
| 3622 | break; |
| 3623 | } |
| 3624 | return signal_levels; |
| 3625 | } |
| 3626 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3627 | /* Gen6's DP voltage swing and pre-emphasis control */ |
| 3628 | static uint32_t |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3629 | gen6_edp_signal_levels(uint8_t train_set) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3630 | { |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3631 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 3632 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 3633 | switch (signal_levels) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3634 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3635 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3636 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3637 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3638 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3639 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3640 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3641 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3642 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3643 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3644 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3645 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3646 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3647 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3648 | default: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3649 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 3650 | "0x%x\n", signal_levels); |
| 3651 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3652 | } |
| 3653 | } |
| 3654 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3655 | /* Gen7's DP voltage swing and pre-emphasis control */ |
| 3656 | static uint32_t |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3657 | gen7_edp_signal_levels(uint8_t train_set) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3658 | { |
| 3659 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 3660 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 3661 | switch (signal_levels) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3662 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3663 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3664 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3665 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3666 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3667 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
| 3668 | |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3669 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3670 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3671 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3672 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
| 3673 | |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3674 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3675 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3676 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3677 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
| 3678 | |
| 3679 | default: |
| 3680 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 3681 | "0x%x\n", signal_levels); |
| 3682 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
| 3683 | } |
| 3684 | } |
| 3685 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3686 | void |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3687 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3688 | { |
| 3689 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3690 | enum port port = intel_dig_port->port; |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3691 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Ander Conselvan de Oliveira | b905a91 | 2015-10-23 13:01:47 +0300 | [diff] [blame] | 3692 | struct drm_i915_private *dev_priv = to_i915(dev); |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 3693 | uint32_t signal_levels, mask = 0; |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3694 | uint8_t train_set = intel_dp->train_set[0]; |
| 3695 | |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 3696 | if (HAS_DDI(dev)) { |
| 3697 | signal_levels = ddi_signal_levels(intel_dp); |
| 3698 | |
| 3699 | if (IS_BROXTON(dev)) |
| 3700 | signal_levels = 0; |
| 3701 | else |
| 3702 | mask = DDI_BUF_EMP_MASK; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3703 | } else if (IS_CHERRYVIEW(dev)) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3704 | signal_levels = chv_signal_levels(intel_dp); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3705 | } else if (IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3706 | signal_levels = vlv_signal_levels(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3707 | } else if (IS_GEN7(dev) && port == PORT_A) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3708 | signal_levels = gen7_edp_signal_levels(train_set); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3709 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3710 | } else if (IS_GEN6(dev) && port == PORT_A) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3711 | signal_levels = gen6_edp_signal_levels(train_set); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3712 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
| 3713 | } else { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3714 | signal_levels = gen4_signal_levels(train_set); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3715 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
| 3716 | } |
| 3717 | |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 3718 | if (mask) |
| 3719 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
| 3720 | |
| 3721 | DRM_DEBUG_KMS("Using vswing level %d\n", |
| 3722 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); |
| 3723 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", |
| 3724 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
| 3725 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3726 | |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3727 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
Ander Conselvan de Oliveira | b905a91 | 2015-10-23 13:01:47 +0300 | [diff] [blame] | 3728 | |
| 3729 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 3730 | POSTING_READ(intel_dp->output_reg); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3731 | } |
| 3732 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3733 | void |
Ander Conselvan de Oliveira | e9c176d | 2015-10-23 13:01:45 +0300 | [diff] [blame] | 3734 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
| 3735 | uint8_t dp_train_pat) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3736 | { |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 3737 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 3738 | struct drm_i915_private *dev_priv = |
| 3739 | to_i915(intel_dig_port->base.base.dev); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3740 | |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3741 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 3742 | |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3743 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3744 | POSTING_READ(intel_dp->output_reg); |
Ander Conselvan de Oliveira | e9c176d | 2015-10-23 13:01:45 +0300 | [diff] [blame] | 3745 | } |
| 3746 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3747 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 3748 | { |
| 3749 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3750 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 3751 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3752 | enum port port = intel_dig_port->port; |
| 3753 | uint32_t val; |
| 3754 | |
| 3755 | if (!HAS_DDI(dev)) |
| 3756 | return; |
| 3757 | |
| 3758 | val = I915_READ(DP_TP_CTL(port)); |
| 3759 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 3760 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
| 3761 | I915_WRITE(DP_TP_CTL(port), val); |
| 3762 | |
| 3763 | /* |
| 3764 | * On PORT_A we can have only eDP in SST mode. There the only reason |
| 3765 | * we need to set idle transmission mode is to work around a HW issue |
| 3766 | * where we enable the pipe while not in idle link-training mode. |
| 3767 | * In this case there is requirement to wait for a minimum number of |
| 3768 | * idle patterns to be sent. |
| 3769 | */ |
| 3770 | if (port == PORT_A) |
| 3771 | return; |
| 3772 | |
| 3773 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
| 3774 | 1)) |
| 3775 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
| 3776 | } |
| 3777 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3778 | static void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3779 | intel_dp_link_down(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3780 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3781 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3782 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3783 | enum port port = intel_dig_port->port; |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3784 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3785 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3786 | uint32_t DP = intel_dp->DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3787 | |
Daniel Vetter | bc76e320 | 2014-05-20 22:46:50 +0200 | [diff] [blame] | 3788 | if (WARN_ON(HAS_DDI(dev))) |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 3789 | return; |
| 3790 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 3791 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 3792 | return; |
| 3793 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3794 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3795 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 3796 | if ((IS_GEN7(dev) && port == PORT_A) || |
| 3797 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3798 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3799 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3800 | } else { |
Ville Syrjälä | aad3d14 | 2014-06-28 02:04:25 +0300 | [diff] [blame] | 3801 | if (IS_CHERRYVIEW(dev)) |
| 3802 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
| 3803 | else |
| 3804 | DP &= ~DP_LINK_TRAIN_MASK; |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3805 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3806 | } |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3807 | I915_WRITE(intel_dp->output_reg, DP); |
Chris Wilson | fe255d0 | 2010-09-11 21:37:48 +0100 | [diff] [blame] | 3808 | POSTING_READ(intel_dp->output_reg); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3809 | |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3810 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
| 3811 | I915_WRITE(intel_dp->output_reg, DP); |
| 3812 | POSTING_READ(intel_dp->output_reg); |
| 3813 | |
| 3814 | /* |
| 3815 | * HW workaround for IBX, we need to move the port |
| 3816 | * to transcoder A after disabling it to allow the |
| 3817 | * matching HDMI port to be enabled on transcoder A. |
| 3818 | */ |
| 3819 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { |
Ville Syrjälä | 0c241d5 | 2015-10-30 19:23:22 +0200 | [diff] [blame] | 3820 | /* |
| 3821 | * We get CPU/PCH FIFO underruns on the other pipe when |
| 3822 | * doing the workaround. Sweep them under the rug. |
| 3823 | */ |
| 3824 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
| 3825 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
| 3826 | |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3827 | /* always enable with pattern 1 (as per spec) */ |
| 3828 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); |
| 3829 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; |
| 3830 | I915_WRITE(intel_dp->output_reg, DP); |
| 3831 | POSTING_READ(intel_dp->output_reg); |
| 3832 | |
| 3833 | DP &= ~DP_PORT_EN; |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 3834 | I915_WRITE(intel_dp->output_reg, DP); |
Daniel Vetter | 0ca0968 | 2014-11-24 16:54:11 +0100 | [diff] [blame] | 3835 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | 0c241d5 | 2015-10-30 19:23:22 +0200 | [diff] [blame] | 3836 | |
| 3837 | intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); |
| 3838 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
| 3839 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 3840 | } |
| 3841 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 3842 | msleep(intel_dp->panel_power_down_delay); |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 3843 | |
| 3844 | intel_dp->DP = DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3845 | } |
| 3846 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3847 | static bool |
| 3848 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3849 | { |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 3850 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3851 | struct drm_device *dev = dig_port->base.base.dev; |
| 3852 | struct drm_i915_private *dev_priv = dev->dev_private; |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 3853 | uint8_t rev; |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 3854 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3855 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
| 3856 | sizeof(intel_dp->dpcd)) < 0) |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3857 | return false; /* aux transfer failed */ |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3858 | |
Andy Shevchenko | a8e9815 | 2014-09-01 14:12:01 +0300 | [diff] [blame] | 3859 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
Damien Lespiau | 577c7a5 | 2012-12-13 16:09:02 +0000 | [diff] [blame] | 3860 | |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3861 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
| 3862 | return false; /* DPCD not present */ |
| 3863 | |
Shobhit Kumar | 2293bb5 | 2013-07-11 18:44:56 -0300 | [diff] [blame] | 3864 | /* Check if the panel supports PSR */ |
| 3865 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
Jani Nikula | 5000393 | 2013-09-20 16:42:17 +0300 | [diff] [blame] | 3866 | if (is_edp(intel_dp)) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3867 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
| 3868 | intel_dp->psr_dpcd, |
| 3869 | sizeof(intel_dp->psr_dpcd)); |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 3870 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
| 3871 | dev_priv->psr.sink_support = true; |
Jani Nikula | 5000393 | 2013-09-20 16:42:17 +0300 | [diff] [blame] | 3872 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 3873 | } |
Sonika Jindal | 474d1ec | 2015-04-02 11:02:44 +0530 | [diff] [blame] | 3874 | |
| 3875 | if (INTEL_INFO(dev)->gen >= 9 && |
| 3876 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { |
| 3877 | uint8_t frame_sync_cap; |
| 3878 | |
| 3879 | dev_priv->psr.sink_support = true; |
| 3880 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 3881 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, |
| 3882 | &frame_sync_cap, 1); |
| 3883 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; |
| 3884 | /* PSR2 needs frame sync as well */ |
| 3885 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; |
| 3886 | DRM_DEBUG_KMS("PSR2 %s on sink", |
| 3887 | dev_priv->psr.psr2_support ? "supported" : "not supported"); |
| 3888 | } |
Jani Nikula | 5000393 | 2013-09-20 16:42:17 +0300 | [diff] [blame] | 3889 | } |
| 3890 | |
Jani Nikula | bc5133d | 2015-09-03 11:16:07 +0300 | [diff] [blame] | 3891 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 3892 | yesno(intel_dp_source_supports_hbr2(intel_dp)), |
Jani Nikula | 742f491 | 2015-09-03 11:16:09 +0300 | [diff] [blame] | 3893 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 3894 | |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 3895 | /* Intermediate frequency support */ |
| 3896 | if (is_edp(intel_dp) && |
| 3897 | (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && |
| 3898 | (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && |
| 3899 | (rev >= 0x03)) { /* eDp v1.4 or higher */ |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 3900 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
Ville Syrjälä | ea2d8a4 | 2015-03-12 17:10:28 +0200 | [diff] [blame] | 3901 | int i; |
| 3902 | |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 3903 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 3904 | DP_SUPPORTED_LINK_RATES, |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 3905 | sink_rates, |
| 3906 | sizeof(sink_rates)); |
Ville Syrjälä | ea2d8a4 | 2015-03-12 17:10:28 +0200 | [diff] [blame] | 3907 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 3908 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
| 3909 | int val = le16_to_cpu(sink_rates[i]); |
Ville Syrjälä | ea2d8a4 | 2015-03-12 17:10:28 +0200 | [diff] [blame] | 3910 | |
| 3911 | if (val == 0) |
| 3912 | break; |
| 3913 | |
Sonika Jindal | af77b97 | 2015-05-07 13:59:28 +0530 | [diff] [blame] | 3914 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
| 3915 | intel_dp->sink_rates[i] = (val * 200) / 10; |
Ville Syrjälä | ea2d8a4 | 2015-03-12 17:10:28 +0200 | [diff] [blame] | 3916 | } |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 3917 | intel_dp->num_sink_rates = i; |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 3918 | } |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 3919 | |
| 3920 | intel_dp_print_rates(intel_dp); |
| 3921 | |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3922 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 3923 | DP_DWN_STRM_PORT_PRESENT)) |
| 3924 | return true; /* native DP sink */ |
| 3925 | |
| 3926 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
| 3927 | return true; /* no per-port downstream info */ |
| 3928 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3929 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
| 3930 | intel_dp->downstream_ports, |
| 3931 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3932 | return false; /* downstream port status fetch failed */ |
| 3933 | |
| 3934 | return true; |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3935 | } |
| 3936 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3937 | static void |
| 3938 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
| 3939 | { |
| 3940 | u8 buf[3]; |
| 3941 | |
| 3942 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
| 3943 | return; |
| 3944 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3945 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3946 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
| 3947 | buf[0], buf[1], buf[2]); |
| 3948 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3949 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3950 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
| 3951 | buf[0], buf[1], buf[2]); |
| 3952 | } |
| 3953 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3954 | static bool |
| 3955 | intel_dp_probe_mst(struct intel_dp *intel_dp) |
| 3956 | { |
| 3957 | u8 buf[1]; |
| 3958 | |
| 3959 | if (!intel_dp->can_mst) |
| 3960 | return false; |
| 3961 | |
| 3962 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
| 3963 | return false; |
| 3964 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3965 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
| 3966 | if (buf[0] & DP_MST_CAP) { |
| 3967 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
| 3968 | intel_dp->is_mst = true; |
| 3969 | } else { |
| 3970 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
| 3971 | intel_dp->is_mst = false; |
| 3972 | } |
| 3973 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3974 | |
| 3975 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
| 3976 | return intel_dp->is_mst; |
| 3977 | } |
| 3978 | |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3979 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3980 | { |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3981 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
Rodrigo Vivi | d72f9d9 | 2015-11-05 10:50:19 -0800 | [diff] [blame] | 3982 | struct drm_device *dev = dig_port->base.base.dev; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3983 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 3984 | u8 buf; |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3985 | int ret = 0; |
Rodrigo Vivi | c629784 | 2015-11-05 10:50:20 -0800 | [diff] [blame] | 3986 | int count = 0; |
| 3987 | int attempts = 10; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3988 | |
| 3989 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3990 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3991 | ret = -EIO; |
| 3992 | goto out; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3993 | } |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3994 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3995 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3996 | buf & ~DP_TEST_SINK_START) < 0) { |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3997 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3998 | ret = -EIO; |
| 3999 | goto out; |
| 4000 | } |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 4001 | |
Rodrigo Vivi | c629784 | 2015-11-05 10:50:20 -0800 | [diff] [blame] | 4002 | do { |
| 4003 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 4004 | |
| 4005 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
| 4006 | DP_TEST_SINK_MISC, &buf) < 0) { |
| 4007 | ret = -EIO; |
| 4008 | goto out; |
| 4009 | } |
| 4010 | count = buf & DP_TEST_COUNT_MASK; |
| 4011 | } while (--attempts && count); |
| 4012 | |
| 4013 | if (attempts == 0) { |
Rodrigo Vivi | dc5a903 | 2016-01-29 14:44:59 -0800 | [diff] [blame] | 4014 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
Rodrigo Vivi | c629784 | 2015-11-05 10:50:20 -0800 | [diff] [blame] | 4015 | ret = -ETIMEDOUT; |
| 4016 | } |
| 4017 | |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 4018 | out: |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 4019 | hsw_enable_ips(intel_crtc); |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 4020 | return ret; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 4021 | } |
| 4022 | |
| 4023 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) |
| 4024 | { |
| 4025 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
Rodrigo Vivi | d72f9d9 | 2015-11-05 10:50:19 -0800 | [diff] [blame] | 4026 | struct drm_device *dev = dig_port->base.base.dev; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 4027 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 4028 | u8 buf; |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 4029 | int ret; |
| 4030 | |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 4031 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
| 4032 | return -EIO; |
| 4033 | |
| 4034 | if (!(buf & DP_TEST_CRC_SUPPORTED)) |
| 4035 | return -ENOTTY; |
| 4036 | |
| 4037 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
| 4038 | return -EIO; |
| 4039 | |
Rodrigo Vivi | 6d8175d | 2015-11-05 10:50:22 -0800 | [diff] [blame] | 4040 | if (buf & DP_TEST_SINK_START) { |
| 4041 | ret = intel_dp_sink_crc_stop(intel_dp); |
| 4042 | if (ret) |
| 4043 | return ret; |
| 4044 | } |
| 4045 | |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 4046 | hsw_disable_ips(intel_crtc); |
| 4047 | |
| 4048 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
| 4049 | buf | DP_TEST_SINK_START) < 0) { |
| 4050 | hsw_enable_ips(intel_crtc); |
| 4051 | return -EIO; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 4052 | } |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 4053 | |
Rodrigo Vivi | d72f9d9 | 2015-11-05 10:50:19 -0800 | [diff] [blame] | 4054 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 4055 | return 0; |
| 4056 | } |
| 4057 | |
| 4058 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
| 4059 | { |
| 4060 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 4061 | struct drm_device *dev = dig_port->base.base.dev; |
| 4062 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 4063 | u8 buf; |
Rodrigo Vivi | 621d4c7 | 2015-07-23 16:35:49 -0700 | [diff] [blame] | 4064 | int count, ret; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 4065 | int attempts = 6; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 4066 | |
| 4067 | ret = intel_dp_sink_crc_start(intel_dp); |
| 4068 | if (ret) |
| 4069 | return ret; |
| 4070 | |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 4071 | do { |
Rodrigo Vivi | 621d4c7 | 2015-07-23 16:35:49 -0700 | [diff] [blame] | 4072 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 4073 | |
Rodrigo Vivi | 1dda5f9 | 2014-10-01 07:32:37 -0700 | [diff] [blame] | 4074 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 4075 | DP_TEST_SINK_MISC, &buf) < 0) { |
| 4076 | ret = -EIO; |
Rodrigo Vivi | afe0d67 | 2015-07-23 16:35:45 -0700 | [diff] [blame] | 4077 | goto stop; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 4078 | } |
Rodrigo Vivi | 621d4c7 | 2015-07-23 16:35:49 -0700 | [diff] [blame] | 4079 | count = buf & DP_TEST_COUNT_MASK; |
Rodrigo Vivi | aabc95d | 2015-07-23 16:35:50 -0700 | [diff] [blame] | 4080 | |
Rodrigo Vivi | 7e38eef | 2015-11-05 10:50:21 -0800 | [diff] [blame] | 4081 | } while (--attempts && count == 0); |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 4082 | |
| 4083 | if (attempts == 0) { |
Rodrigo Vivi | 7e38eef | 2015-11-05 10:50:21 -0800 | [diff] [blame] | 4084 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
| 4085 | ret = -ETIMEDOUT; |
| 4086 | goto stop; |
| 4087 | } |
| 4088 | |
| 4089 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { |
| 4090 | ret = -EIO; |
| 4091 | goto stop; |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 4092 | } |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 4093 | |
Rodrigo Vivi | afe0d67 | 2015-07-23 16:35:45 -0700 | [diff] [blame] | 4094 | stop: |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 4095 | intel_dp_sink_crc_stop(intel_dp); |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 4096 | return ret; |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 4097 | } |
| 4098 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4099 | static bool |
| 4100 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 4101 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 4102 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 4103 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 4104 | sink_irq_vector, 1) == 1; |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4105 | } |
| 4106 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4107 | static bool |
| 4108 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 4109 | { |
| 4110 | int ret; |
| 4111 | |
| 4112 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 4113 | DP_SINK_COUNT_ESI, |
| 4114 | sink_irq_vector, 14); |
| 4115 | if (ret != 14) |
| 4116 | return false; |
| 4117 | |
| 4118 | return true; |
| 4119 | } |
| 4120 | |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 4121 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4122 | { |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 4123 | uint8_t test_result = DP_TEST_ACK; |
| 4124 | return test_result; |
| 4125 | } |
| 4126 | |
| 4127 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
| 4128 | { |
| 4129 | uint8_t test_result = DP_TEST_NAK; |
| 4130 | return test_result; |
| 4131 | } |
| 4132 | |
| 4133 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) |
| 4134 | { |
| 4135 | uint8_t test_result = DP_TEST_NAK; |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 4136 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4137 | struct drm_connector *connector = &intel_connector->base; |
| 4138 | |
| 4139 | if (intel_connector->detect_edid == NULL || |
Daniel Vetter | ac6f2e2 | 2015-05-08 16:15:41 +0200 | [diff] [blame] | 4140 | connector->edid_corrupt || |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 4141 | intel_dp->aux.i2c_defer_count > 6) { |
| 4142 | /* Check EDID read for NACKs, DEFERs and corruption |
| 4143 | * (DP CTS 1.2 Core r1.1) |
| 4144 | * 4.2.2.4 : Failed EDID read, I2C_NAK |
| 4145 | * 4.2.2.5 : Failed EDID read, I2C_DEFER |
| 4146 | * 4.2.2.6 : EDID corruption detected |
| 4147 | * Use failsafe mode for all cases |
| 4148 | */ |
| 4149 | if (intel_dp->aux.i2c_nack_count > 0 || |
| 4150 | intel_dp->aux.i2c_defer_count > 0) |
| 4151 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", |
| 4152 | intel_dp->aux.i2c_nack_count, |
| 4153 | intel_dp->aux.i2c_defer_count); |
| 4154 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; |
| 4155 | } else { |
Thulasimani,Sivakumar | f79b468e | 2015-08-07 15:14:30 +0530 | [diff] [blame] | 4156 | struct edid *block = intel_connector->detect_edid; |
| 4157 | |
| 4158 | /* We have to write the checksum |
| 4159 | * of the last block read |
| 4160 | */ |
| 4161 | block += intel_connector->detect_edid->extensions; |
| 4162 | |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 4163 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
| 4164 | DP_TEST_EDID_CHECKSUM, |
Thulasimani,Sivakumar | f79b468e | 2015-08-07 15:14:30 +0530 | [diff] [blame] | 4165 | &block->checksum, |
Dan Carpenter | 5a1cc65 | 2015-05-12 21:07:37 +0300 | [diff] [blame] | 4166 | 1)) |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 4167 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
| 4168 | |
| 4169 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; |
| 4170 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; |
| 4171 | } |
| 4172 | |
| 4173 | /* Set test active flag here so userspace doesn't interrupt things */ |
| 4174 | intel_dp->compliance_test_active = 1; |
| 4175 | |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 4176 | return test_result; |
| 4177 | } |
| 4178 | |
| 4179 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
| 4180 | { |
| 4181 | uint8_t test_result = DP_TEST_NAK; |
| 4182 | return test_result; |
| 4183 | } |
| 4184 | |
| 4185 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) |
| 4186 | { |
| 4187 | uint8_t response = DP_TEST_NAK; |
| 4188 | uint8_t rxdata = 0; |
| 4189 | int status = 0; |
| 4190 | |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 4191 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
| 4192 | if (status <= 0) { |
| 4193 | DRM_DEBUG_KMS("Could not read test request from sink\n"); |
| 4194 | goto update_status; |
| 4195 | } |
| 4196 | |
| 4197 | switch (rxdata) { |
| 4198 | case DP_TEST_LINK_TRAINING: |
| 4199 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); |
| 4200 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; |
| 4201 | response = intel_dp_autotest_link_training(intel_dp); |
| 4202 | break; |
| 4203 | case DP_TEST_LINK_VIDEO_PATTERN: |
| 4204 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); |
| 4205 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; |
| 4206 | response = intel_dp_autotest_video_pattern(intel_dp); |
| 4207 | break; |
| 4208 | case DP_TEST_LINK_EDID_READ: |
| 4209 | DRM_DEBUG_KMS("EDID test requested\n"); |
| 4210 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; |
| 4211 | response = intel_dp_autotest_edid(intel_dp); |
| 4212 | break; |
| 4213 | case DP_TEST_LINK_PHY_TEST_PATTERN: |
| 4214 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); |
| 4215 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; |
| 4216 | response = intel_dp_autotest_phy_pattern(intel_dp); |
| 4217 | break; |
| 4218 | default: |
| 4219 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); |
| 4220 | break; |
| 4221 | } |
| 4222 | |
| 4223 | update_status: |
| 4224 | status = drm_dp_dpcd_write(&intel_dp->aux, |
| 4225 | DP_TEST_RESPONSE, |
| 4226 | &response, 1); |
| 4227 | if (status <= 0) |
| 4228 | DRM_DEBUG_KMS("Could not write test response to sink\n"); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4229 | } |
| 4230 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4231 | static int |
| 4232 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
| 4233 | { |
| 4234 | bool bret; |
| 4235 | |
| 4236 | if (intel_dp->is_mst) { |
| 4237 | u8 esi[16] = { 0 }; |
| 4238 | int ret = 0; |
| 4239 | int retry; |
| 4240 | bool handled; |
| 4241 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
| 4242 | go_again: |
| 4243 | if (bret == true) { |
| 4244 | |
| 4245 | /* check link status - esi[10] = 0x200c */ |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 4246 | if (intel_dp->active_mst_links && |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 4247 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4248 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
| 4249 | intel_dp_start_link_train(intel_dp); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4250 | intel_dp_stop_link_train(intel_dp); |
| 4251 | } |
| 4252 | |
Andy Shevchenko | 6f34cc3 | 2015-01-15 13:45:09 +0200 | [diff] [blame] | 4253 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4254 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
| 4255 | |
| 4256 | if (handled) { |
| 4257 | for (retry = 0; retry < 3; retry++) { |
| 4258 | int wret; |
| 4259 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
| 4260 | DP_SINK_COUNT_ESI+1, |
| 4261 | &esi[1], 3); |
| 4262 | if (wret == 3) { |
| 4263 | break; |
| 4264 | } |
| 4265 | } |
| 4266 | |
| 4267 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
| 4268 | if (bret == true) { |
Andy Shevchenko | 6f34cc3 | 2015-01-15 13:45:09 +0200 | [diff] [blame] | 4269 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4270 | goto go_again; |
| 4271 | } |
| 4272 | } else |
| 4273 | ret = 0; |
| 4274 | |
| 4275 | return ret; |
| 4276 | } else { |
| 4277 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4278 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
| 4279 | intel_dp->is_mst = false; |
| 4280 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
| 4281 | /* send a hotplug event */ |
| 4282 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
| 4283 | } |
| 4284 | } |
| 4285 | return -EINVAL; |
| 4286 | } |
| 4287 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4288 | /* |
| 4289 | * According to DP spec |
| 4290 | * 5.1.2: |
| 4291 | * 1. Read DPCD |
| 4292 | * 2. Configure link according to Receiver Capabilities |
| 4293 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
| 4294 | * 4. Check link status on receipt of hot-plug interrupt |
| 4295 | */ |
Damien Lespiau | a514620 | 2015-02-10 19:32:22 +0000 | [diff] [blame] | 4296 | static void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 4297 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4298 | { |
Dave Airlie | 5b215bc | 2014-08-05 10:40:20 +1000 | [diff] [blame] | 4299 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 4300 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4301 | u8 sink_irq_vector; |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 4302 | u8 link_status[DP_LINK_STATUS_SIZE]; |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4303 | |
Dave Airlie | 5b215bc | 2014-08-05 10:40:20 +1000 | [diff] [blame] | 4304 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
| 4305 | |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4306 | /* |
| 4307 | * Clearing compliance test variables to allow capturing |
| 4308 | * of values for next automated test request. |
| 4309 | */ |
| 4310 | intel_dp->compliance_test_active = 0; |
| 4311 | intel_dp->compliance_test_type = 0; |
| 4312 | intel_dp->compliance_test_data = 0; |
| 4313 | |
Maarten Lankhorst | e02f9a0 | 2015-08-05 12:37:08 +0200 | [diff] [blame] | 4314 | if (!intel_encoder->base.crtc) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4315 | return; |
| 4316 | |
Imre Deak | 1a125d8 | 2014-08-18 14:42:46 +0300 | [diff] [blame] | 4317 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
| 4318 | return; |
| 4319 | |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 4320 | /* Try to read receiver status if the link appears to be up */ |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 4321 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4322 | return; |
| 4323 | } |
| 4324 | |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 4325 | /* Now read the DPCD to see if it's actually running */ |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 4326 | if (!intel_dp_get_dpcd(intel_dp)) { |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 4327 | return; |
| 4328 | } |
| 4329 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4330 | /* Try to read the source of the interrupt */ |
| 4331 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 4332 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
| 4333 | /* Clear interrupt source */ |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 4334 | drm_dp_dpcd_writeb(&intel_dp->aux, |
| 4335 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 4336 | sink_irq_vector); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4337 | |
| 4338 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
Todd Previte | 09b1eb1 | 2015-04-20 15:27:34 -0700 | [diff] [blame] | 4339 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 4340 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 4341 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 4342 | } |
| 4343 | |
Shubhangi Shrivastava | 14631e9 | 2015-10-14 14:56:49 +0530 | [diff] [blame] | 4344 | /* if link training is requested we should perform it always */ |
| 4345 | if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || |
| 4346 | (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 4347 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
Jani Nikula | 8e329a0 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 4348 | intel_encoder->base.name); |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 4349 | intel_dp_start_link_train(intel_dp); |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 4350 | intel_dp_stop_link_train(intel_dp); |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 4351 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4352 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4353 | |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4354 | /* XXX this is probably wrong for multiple downstream ports */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4355 | static enum drm_connector_status |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 4356 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 4357 | { |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4358 | uint8_t *dpcd = intel_dp->dpcd; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4359 | uint8_t type; |
| 4360 | |
| 4361 | if (!intel_dp_get_dpcd(intel_dp)) |
| 4362 | return connector_status_disconnected; |
| 4363 | |
| 4364 | /* if there's no downstream port, we're done */ |
| 4365 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 4366 | return connector_status_connected; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4367 | |
| 4368 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
Jani Nikula | c9ff160 | 2013-09-27 14:48:42 +0300 | [diff] [blame] | 4369 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 4370 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
Adam Jackson | 2323517 | 2012-09-20 16:42:45 -0400 | [diff] [blame] | 4371 | uint8_t reg; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 4372 | |
| 4373 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
| 4374 | ®, 1) < 0) |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4375 | return connector_status_unknown; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 4376 | |
Adam Jackson | 2323517 | 2012-09-20 16:42:45 -0400 | [diff] [blame] | 4377 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
| 4378 | : connector_status_disconnected; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4379 | } |
| 4380 | |
| 4381 | /* If no HPD, poke DDC gently */ |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 4382 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4383 | return connector_status_connected; |
| 4384 | |
| 4385 | /* Well we tried, say unknown for unreliable port types */ |
Jani Nikula | c9ff160 | 2013-09-27 14:48:42 +0300 | [diff] [blame] | 4386 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
| 4387 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
| 4388 | if (type == DP_DS_PORT_TYPE_VGA || |
| 4389 | type == DP_DS_PORT_TYPE_NON_EDID) |
| 4390 | return connector_status_unknown; |
| 4391 | } else { |
| 4392 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 4393 | DP_DWN_STRM_PORT_TYPE_MASK; |
| 4394 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
| 4395 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
| 4396 | return connector_status_unknown; |
| 4397 | } |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4398 | |
| 4399 | /* Anything else is out of spec, warn and ignore */ |
| 4400 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 4401 | return connector_status_disconnected; |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 4402 | } |
| 4403 | |
| 4404 | static enum drm_connector_status |
Chris Wilson | d410b56 | 2014-09-02 20:03:59 +0100 | [diff] [blame] | 4405 | edp_detect(struct intel_dp *intel_dp) |
| 4406 | { |
| 4407 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 4408 | enum drm_connector_status status; |
| 4409 | |
| 4410 | status = intel_panel_detect(dev); |
| 4411 | if (status == connector_status_unknown) |
| 4412 | status = connector_status_connected; |
| 4413 | |
| 4414 | return status; |
| 4415 | } |
| 4416 | |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4417 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4418 | struct intel_digital_port *port) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4419 | { |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4420 | u32 bit; |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 4421 | |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4422 | switch (port->port) { |
| 4423 | case PORT_A: |
| 4424 | return true; |
| 4425 | case PORT_B: |
| 4426 | bit = SDE_PORTB_HOTPLUG; |
| 4427 | break; |
| 4428 | case PORT_C: |
| 4429 | bit = SDE_PORTC_HOTPLUG; |
| 4430 | break; |
| 4431 | case PORT_D: |
| 4432 | bit = SDE_PORTD_HOTPLUG; |
| 4433 | break; |
| 4434 | default: |
| 4435 | MISSING_CASE(port->port); |
| 4436 | return false; |
| 4437 | } |
| 4438 | |
| 4439 | return I915_READ(SDEISR) & bit; |
| 4440 | } |
| 4441 | |
| 4442 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4443 | struct intel_digital_port *port) |
| 4444 | { |
| 4445 | u32 bit; |
| 4446 | |
| 4447 | switch (port->port) { |
| 4448 | case PORT_A: |
| 4449 | return true; |
| 4450 | case PORT_B: |
| 4451 | bit = SDE_PORTB_HOTPLUG_CPT; |
| 4452 | break; |
| 4453 | case PORT_C: |
| 4454 | bit = SDE_PORTC_HOTPLUG_CPT; |
| 4455 | break; |
| 4456 | case PORT_D: |
| 4457 | bit = SDE_PORTD_HOTPLUG_CPT; |
| 4458 | break; |
Jani Nikula | a78695d | 2015-09-18 15:54:50 +0300 | [diff] [blame] | 4459 | case PORT_E: |
| 4460 | bit = SDE_PORTE_HOTPLUG_SPT; |
| 4461 | break; |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4462 | default: |
| 4463 | MISSING_CASE(port->port); |
| 4464 | return false; |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4465 | } |
Damien Lespiau | 1b46963 | 2012-12-13 16:09:01 +0000 | [diff] [blame] | 4466 | |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4467 | return I915_READ(SDEISR) & bit; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4468 | } |
| 4469 | |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4470 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
Jani Nikula | 1d24598 | 2015-08-20 10:47:37 +0300 | [diff] [blame] | 4471 | struct intel_digital_port *port) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4472 | { |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4473 | u32 bit; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4474 | |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4475 | switch (port->port) { |
| 4476 | case PORT_B: |
| 4477 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
| 4478 | break; |
| 4479 | case PORT_C: |
| 4480 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
| 4481 | break; |
| 4482 | case PORT_D: |
| 4483 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
| 4484 | break; |
| 4485 | default: |
| 4486 | MISSING_CASE(port->port); |
| 4487 | return false; |
| 4488 | } |
| 4489 | |
| 4490 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
| 4491 | } |
| 4492 | |
| 4493 | static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4494 | struct intel_digital_port *port) |
| 4495 | { |
| 4496 | u32 bit; |
| 4497 | |
| 4498 | switch (port->port) { |
| 4499 | case PORT_B: |
| 4500 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; |
| 4501 | break; |
| 4502 | case PORT_C: |
| 4503 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; |
| 4504 | break; |
| 4505 | case PORT_D: |
| 4506 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; |
| 4507 | break; |
| 4508 | default: |
| 4509 | MISSING_CASE(port->port); |
| 4510 | return false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4511 | } |
| 4512 | |
Jani Nikula | 1d24598 | 2015-08-20 10:47:37 +0300 | [diff] [blame] | 4513 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
Dave Airlie | 2a592be | 2014-09-01 16:58:12 +1000 | [diff] [blame] | 4514 | } |
| 4515 | |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4516 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4517 | struct intel_digital_port *intel_dig_port) |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4518 | { |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4519 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 4520 | enum port port; |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4521 | u32 bit; |
| 4522 | |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4523 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
| 4524 | switch (port) { |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4525 | case PORT_A: |
| 4526 | bit = BXT_DE_PORT_HP_DDIA; |
| 4527 | break; |
| 4528 | case PORT_B: |
| 4529 | bit = BXT_DE_PORT_HP_DDIB; |
| 4530 | break; |
| 4531 | case PORT_C: |
| 4532 | bit = BXT_DE_PORT_HP_DDIC; |
| 4533 | break; |
| 4534 | default: |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4535 | MISSING_CASE(port); |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4536 | return false; |
| 4537 | } |
| 4538 | |
| 4539 | return I915_READ(GEN8_DE_PORT_ISR) & bit; |
| 4540 | } |
| 4541 | |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4542 | /* |
| 4543 | * intel_digital_port_connected - is the specified port connected? |
| 4544 | * @dev_priv: i915 private structure |
| 4545 | * @port: the port to test |
| 4546 | * |
| 4547 | * Return %true if @port is connected, %false otherwise. |
| 4548 | */ |
Sonika Jindal | 237ed86 | 2015-09-15 09:44:20 +0530 | [diff] [blame] | 4549 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4550 | struct intel_digital_port *port) |
| 4551 | { |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4552 | if (HAS_PCH_IBX(dev_priv)) |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4553 | return ibx_digital_port_connected(dev_priv, port); |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4554 | if (HAS_PCH_SPLIT(dev_priv)) |
| 4555 | return cpt_digital_port_connected(dev_priv, port); |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4556 | else if (IS_BROXTON(dev_priv)) |
| 4557 | return bxt_digital_port_connected(dev_priv, port); |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 4558 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4559 | return vlv_digital_port_connected(dev_priv, port); |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4560 | else |
| 4561 | return g4x_digital_port_connected(dev_priv, port); |
| 4562 | } |
| 4563 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4564 | static struct edid * |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4565 | intel_dp_get_edid(struct intel_dp *intel_dp) |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4566 | { |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4567 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4568 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4569 | /* use cached edid if we have one */ |
| 4570 | if (intel_connector->edid) { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4571 | /* invalid edid */ |
| 4572 | if (IS_ERR(intel_connector->edid)) |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 4573 | return NULL; |
| 4574 | |
Jani Nikula | 55e9ede | 2013-10-01 10:38:54 +0300 | [diff] [blame] | 4575 | return drm_edid_duplicate(intel_connector->edid); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4576 | } else |
| 4577 | return drm_get_edid(&intel_connector->base, |
| 4578 | &intel_dp->aux.ddc); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4579 | } |
| 4580 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4581 | static void |
| 4582 | intel_dp_set_edid(struct intel_dp *intel_dp) |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4583 | { |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4584 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4585 | struct edid *edid; |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4586 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4587 | edid = intel_dp_get_edid(intel_dp); |
| 4588 | intel_connector->detect_edid = edid; |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4589 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4590 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) |
| 4591 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; |
| 4592 | else |
| 4593 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
| 4594 | } |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 4595 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4596 | static void |
| 4597 | intel_dp_unset_edid(struct intel_dp *intel_dp) |
| 4598 | { |
| 4599 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4600 | |
| 4601 | kfree(intel_connector->detect_edid); |
| 4602 | intel_connector->detect_edid = NULL; |
| 4603 | |
| 4604 | intel_dp->has_audio = false; |
| 4605 | } |
| 4606 | |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4607 | static enum drm_connector_status |
| 4608 | intel_dp_detect(struct drm_connector *connector, bool force) |
| 4609 | { |
| 4610 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Paulo Zanoni | d63885d | 2012-10-26 19:05:49 -0200 | [diff] [blame] | 4611 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4612 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 4613 | struct drm_device *dev = connector->dev; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4614 | enum drm_connector_status status; |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 4615 | enum intel_display_power_domain power_domain; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4616 | bool ret; |
Todd Previte | 09b1eb1 | 2015-04-20 15:27:34 -0700 | [diff] [blame] | 4617 | u8 sink_irq_vector; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4618 | |
Chris Wilson | 164c859 | 2013-07-20 20:27:08 +0100 | [diff] [blame] | 4619 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 4620 | connector->base.id, connector->name); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4621 | intel_dp_unset_edid(intel_dp); |
Chris Wilson | 164c859 | 2013-07-20 20:27:08 +0100 | [diff] [blame] | 4622 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4623 | if (intel_dp->is_mst) { |
| 4624 | /* MST devices are disconnected from a monitor POV */ |
| 4625 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4626 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4627 | return connector_status_disconnected; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4628 | } |
| 4629 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4630 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
| 4631 | intel_display_power_get(to_i915(dev), power_domain); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4632 | |
Chris Wilson | d410b56 | 2014-09-02 20:03:59 +0100 | [diff] [blame] | 4633 | /* Can't disconnect eDP, but you can close the lid... */ |
| 4634 | if (is_edp(intel_dp)) |
| 4635 | status = edp_detect(intel_dp); |
Ander Conselvan de Oliveira | c555a81 | 2015-11-18 17:19:30 +0200 | [diff] [blame] | 4636 | else if (intel_digital_port_connected(to_i915(dev), |
| 4637 | dp_to_dig_port(intel_dp))) |
| 4638 | status = intel_dp_detect_dpcd(intel_dp); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4639 | else |
Ander Conselvan de Oliveira | c555a81 | 2015-11-18 17:19:30 +0200 | [diff] [blame] | 4640 | status = connector_status_disconnected; |
| 4641 | |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4642 | if (status != connector_status_connected) { |
| 4643 | intel_dp->compliance_test_active = 0; |
| 4644 | intel_dp->compliance_test_type = 0; |
| 4645 | intel_dp->compliance_test_data = 0; |
| 4646 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4647 | goto out; |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4648 | } |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4649 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 4650 | intel_dp_probe_oui(intel_dp); |
| 4651 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4652 | ret = intel_dp_probe_mst(intel_dp); |
| 4653 | if (ret) { |
| 4654 | /* if we are in MST mode then this connector |
| 4655 | won't appear connected or have anything with EDID on it */ |
| 4656 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4657 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 4658 | status = connector_status_disconnected; |
| 4659 | goto out; |
| 4660 | } |
| 4661 | |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4662 | /* |
| 4663 | * Clearing NACK and defer counts to get their exact values |
| 4664 | * while reading EDID which are required by Compliance tests |
| 4665 | * 4.2.2.4 and 4.2.2.5 |
| 4666 | */ |
| 4667 | intel_dp->aux.i2c_nack_count = 0; |
| 4668 | intel_dp->aux.i2c_defer_count = 0; |
| 4669 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4670 | intel_dp_set_edid(intel_dp); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4671 | |
Paulo Zanoni | d63885d | 2012-10-26 19:05:49 -0200 | [diff] [blame] | 4672 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4673 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4674 | status = connector_status_connected; |
| 4675 | |
Todd Previte | 09b1eb1 | 2015-04-20 15:27:34 -0700 | [diff] [blame] | 4676 | /* Try to read the source of the interrupt */ |
| 4677 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 4678 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
| 4679 | /* Clear interrupt source */ |
| 4680 | drm_dp_dpcd_writeb(&intel_dp->aux, |
| 4681 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 4682 | sink_irq_vector); |
| 4683 | |
| 4684 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
| 4685 | intel_dp_handle_test_request(intel_dp); |
| 4686 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 4687 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 4688 | } |
| 4689 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4690 | out: |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4691 | intel_display_power_put(to_i915(dev), power_domain); |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4692 | return status; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4693 | } |
| 4694 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4695 | static void |
| 4696 | intel_dp_force(struct drm_connector *connector) |
| 4697 | { |
| 4698 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 4699 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4700 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4701 | enum intel_display_power_domain power_domain; |
| 4702 | |
| 4703 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 4704 | connector->base.id, connector->name); |
| 4705 | intel_dp_unset_edid(intel_dp); |
| 4706 | |
| 4707 | if (connector->status != connector_status_connected) |
| 4708 | return; |
| 4709 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4710 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
| 4711 | intel_display_power_get(dev_priv, power_domain); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4712 | |
| 4713 | intel_dp_set_edid(intel_dp); |
| 4714 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4715 | intel_display_power_put(dev_priv, power_domain); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4716 | |
| 4717 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4718 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 4719 | } |
| 4720 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4721 | static int intel_dp_get_modes(struct drm_connector *connector) |
| 4722 | { |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 4723 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4724 | struct edid *edid; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4725 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4726 | edid = intel_connector->detect_edid; |
| 4727 | if (edid) { |
| 4728 | int ret = intel_connector_update_modes(connector, edid); |
| 4729 | if (ret) |
| 4730 | return ret; |
| 4731 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4732 | |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 4733 | /* if eDP has no EDID, fall back to fixed mode */ |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4734 | if (is_edp(intel_attached_dp(connector)) && |
| 4735 | intel_connector->panel.fixed_mode) { |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 4736 | struct drm_display_mode *mode; |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4737 | |
| 4738 | mode = drm_mode_duplicate(connector->dev, |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 4739 | intel_connector->panel.fixed_mode); |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 4740 | if (mode) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4741 | drm_mode_probed_add(connector, mode); |
| 4742 | return 1; |
| 4743 | } |
| 4744 | } |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4745 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4746 | return 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4747 | } |
| 4748 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4749 | static bool |
| 4750 | intel_dp_detect_audio(struct drm_connector *connector) |
| 4751 | { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4752 | bool has_audio = false; |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4753 | struct edid *edid; |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4754 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4755 | edid = to_intel_connector(connector)->detect_edid; |
| 4756 | if (edid) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4757 | has_audio = drm_detect_monitor_audio(edid); |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 4758 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4759 | return has_audio; |
| 4760 | } |
| 4761 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4762 | static int |
| 4763 | intel_dp_set_property(struct drm_connector *connector, |
| 4764 | struct drm_property *property, |
| 4765 | uint64_t val) |
| 4766 | { |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 4767 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4768 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 4769 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
| 4770 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4771 | int ret; |
| 4772 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 4773 | ret = drm_object_property_set_value(&connector->base, property, val); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4774 | if (ret) |
| 4775 | return ret; |
| 4776 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 4777 | if (property == dev_priv->force_audio_property) { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4778 | int i = val; |
| 4779 | bool has_audio; |
| 4780 | |
| 4781 | if (i == intel_dp->force_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4782 | return 0; |
| 4783 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4784 | intel_dp->force_audio = i; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4785 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 4786 | if (i == HDMI_AUDIO_AUTO) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4787 | has_audio = intel_dp_detect_audio(connector); |
| 4788 | else |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 4789 | has_audio = (i == HDMI_AUDIO_ON); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4790 | |
| 4791 | if (has_audio == intel_dp->has_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4792 | return 0; |
| 4793 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4794 | intel_dp->has_audio = has_audio; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4795 | goto done; |
| 4796 | } |
| 4797 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 4798 | if (property == dev_priv->broadcast_rgb_property) { |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4799 | bool old_auto = intel_dp->color_range_auto; |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4800 | bool old_range = intel_dp->limited_color_range; |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4801 | |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4802 | switch (val) { |
| 4803 | case INTEL_BROADCAST_RGB_AUTO: |
| 4804 | intel_dp->color_range_auto = true; |
| 4805 | break; |
| 4806 | case INTEL_BROADCAST_RGB_FULL: |
| 4807 | intel_dp->color_range_auto = false; |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4808 | intel_dp->limited_color_range = false; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4809 | break; |
| 4810 | case INTEL_BROADCAST_RGB_LIMITED: |
| 4811 | intel_dp->color_range_auto = false; |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4812 | intel_dp->limited_color_range = true; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4813 | break; |
| 4814 | default: |
| 4815 | return -EINVAL; |
| 4816 | } |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4817 | |
| 4818 | if (old_auto == intel_dp->color_range_auto && |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4819 | old_range == intel_dp->limited_color_range) |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4820 | return 0; |
| 4821 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 4822 | goto done; |
| 4823 | } |
| 4824 | |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4825 | if (is_edp(intel_dp) && |
| 4826 | property == connector->dev->mode_config.scaling_mode_property) { |
| 4827 | if (val == DRM_MODE_SCALE_NONE) { |
| 4828 | DRM_DEBUG_KMS("no scaling not supported\n"); |
| 4829 | return -EINVAL; |
| 4830 | } |
| 4831 | |
| 4832 | if (intel_connector->panel.fitting_mode == val) { |
| 4833 | /* the eDP scaling property is not changed */ |
| 4834 | return 0; |
| 4835 | } |
| 4836 | intel_connector->panel.fitting_mode = val; |
| 4837 | |
| 4838 | goto done; |
| 4839 | } |
| 4840 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4841 | return -EINVAL; |
| 4842 | |
| 4843 | done: |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 4844 | if (intel_encoder->base.crtc) |
| 4845 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4846 | |
| 4847 | return 0; |
| 4848 | } |
| 4849 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4850 | static void |
Paulo Zanoni | 73845ad | 2013-06-12 17:27:30 -0300 | [diff] [blame] | 4851 | intel_dp_connector_destroy(struct drm_connector *connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4852 | { |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 4853 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 4854 | |
Chris Wilson | 10e972d | 2014-09-04 21:43:45 +0100 | [diff] [blame] | 4855 | kfree(intel_connector->detect_edid); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4856 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4857 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
| 4858 | kfree(intel_connector->edid); |
| 4859 | |
Paulo Zanoni | acd8db10 | 2013-06-12 17:27:23 -0300 | [diff] [blame] | 4860 | /* Can't call is_edp() since the encoder may have been destroyed |
| 4861 | * already. */ |
| 4862 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 4863 | intel_panel_fini(&intel_connector->panel); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 4864 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4865 | drm_connector_cleanup(connector); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 4866 | kfree(connector); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4867 | } |
| 4868 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 4869 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4870 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 4871 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
| 4872 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4873 | |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 4874 | intel_dp_aux_fini(intel_dp); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4875 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 4876 | if (is_edp(intel_dp)) { |
| 4877 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 4878 | /* |
| 4879 | * vdd might still be enabled do to the delayed vdd off. |
| 4880 | * Make sure vdd is actually turned off here. |
| 4881 | */ |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4882 | pps_lock(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 4883 | edp_panel_vdd_off_sync(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4884 | pps_unlock(intel_dp); |
| 4885 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 4886 | if (intel_dp->edp_notifier.notifier_call) { |
| 4887 | unregister_reboot_notifier(&intel_dp->edp_notifier); |
| 4888 | intel_dp->edp_notifier.notifier_call = NULL; |
| 4889 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 4890 | } |
Imre Deak | c8bd0e4 | 2014-12-12 17:57:38 +0200 | [diff] [blame] | 4891 | drm_encoder_cleanup(encoder); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 4892 | kfree(intel_dig_port); |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4893 | } |
| 4894 | |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 4895 | static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
| 4896 | { |
| 4897 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 4898 | |
| 4899 | if (!is_edp(intel_dp)) |
| 4900 | return; |
| 4901 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 4902 | /* |
| 4903 | * vdd might still be enabled do to the delayed vdd off. |
| 4904 | * Make sure vdd is actually turned off here. |
| 4905 | */ |
Ville Syrjälä | afa4e53 | 2014-11-25 15:43:48 +0200 | [diff] [blame] | 4906 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4907 | pps_lock(intel_dp); |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 4908 | edp_panel_vdd_off_sync(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4909 | pps_unlock(intel_dp); |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 4910 | } |
| 4911 | |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4912 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
| 4913 | { |
| 4914 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4915 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 4916 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4917 | enum intel_display_power_domain power_domain; |
| 4918 | |
| 4919 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 4920 | |
| 4921 | if (!edp_have_panel_vdd(intel_dp)) |
| 4922 | return; |
| 4923 | |
| 4924 | /* |
| 4925 | * The VDD bit needs a power domain reference, so if the bit is |
| 4926 | * already enabled when we boot or resume, grab this reference and |
| 4927 | * schedule a vdd off, so we don't hold on to the reference |
| 4928 | * indefinitely. |
| 4929 | */ |
| 4930 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4931 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4932 | intel_display_power_get(dev_priv, power_domain); |
| 4933 | |
| 4934 | edp_panel_vdd_schedule_off(intel_dp); |
| 4935 | } |
| 4936 | |
Imre Deak | 6d93c0c | 2014-07-31 14:03:36 +0300 | [diff] [blame] | 4937 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) |
| 4938 | { |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4939 | struct intel_dp *intel_dp; |
| 4940 | |
| 4941 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) |
| 4942 | return; |
| 4943 | |
| 4944 | intel_dp = enc_to_intel_dp(encoder); |
| 4945 | |
| 4946 | pps_lock(intel_dp); |
| 4947 | |
| 4948 | /* |
| 4949 | * Read out the current power sequencer assignment, |
| 4950 | * in case the BIOS did something with it. |
| 4951 | */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 4952 | if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev)) |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4953 | vlv_initial_power_sequencer_setup(intel_dp); |
| 4954 | |
| 4955 | intel_edp_panel_vdd_sanitize(intel_dp); |
| 4956 | |
| 4957 | pps_unlock(intel_dp); |
Imre Deak | 6d93c0c | 2014-07-31 14:03:36 +0300 | [diff] [blame] | 4958 | } |
| 4959 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4960 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
Maarten Lankhorst | 4d688a2 | 2015-08-05 12:37:06 +0200 | [diff] [blame] | 4961 | .dpms = drm_atomic_helper_connector_dpms, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4962 | .detect = intel_dp_detect, |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4963 | .force = intel_dp_force, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4964 | .fill_modes = drm_helper_probe_single_connector_modes, |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4965 | .set_property = intel_dp_set_property, |
Matt Roper | 2545e4a | 2015-01-22 16:51:27 -0800 | [diff] [blame] | 4966 | .atomic_get_property = intel_connector_atomic_get_property, |
Paulo Zanoni | 73845ad | 2013-06-12 17:27:30 -0300 | [diff] [blame] | 4967 | .destroy = intel_dp_connector_destroy, |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 4968 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
Ander Conselvan de Oliveira | 9896972 | 2015-03-20 16:18:06 +0200 | [diff] [blame] | 4969 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4970 | }; |
| 4971 | |
| 4972 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
| 4973 | .get_modes = intel_dp_get_modes, |
| 4974 | .mode_valid = intel_dp_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 4975 | .best_encoder = intel_best_encoder, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4976 | }; |
| 4977 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4978 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
Imre Deak | 6d93c0c | 2014-07-31 14:03:36 +0300 | [diff] [blame] | 4979 | .reset = intel_dp_encoder_reset, |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4980 | .destroy = intel_dp_encoder_destroy, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4981 | }; |
| 4982 | |
Daniel Vetter | b2c5c18 | 2015-01-23 06:00:31 +0100 | [diff] [blame] | 4983 | enum irqreturn |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4984 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
| 4985 | { |
| 4986 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4987 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4988 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 4989 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4990 | enum intel_display_power_domain power_domain; |
Daniel Vetter | b2c5c18 | 2015-01-23 06:00:31 +0100 | [diff] [blame] | 4991 | enum irqreturn ret = IRQ_NONE; |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4992 | |
Takashi Iwai | 2540058 | 2015-11-19 12:09:56 +0100 | [diff] [blame] | 4993 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
| 4994 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4995 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4996 | |
Ville Syrjälä | 7a7f84c | 2014-10-16 20:46:10 +0300 | [diff] [blame] | 4997 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
| 4998 | /* |
| 4999 | * vdd off can generate a long pulse on eDP which |
| 5000 | * would require vdd on to handle it, and thus we |
| 5001 | * would end up in an endless cycle of |
| 5002 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." |
| 5003 | */ |
| 5004 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", |
| 5005 | port_name(intel_dig_port->port)); |
Ville Syrjälä | a8b3d52 | 2015-02-10 14:11:46 +0200 | [diff] [blame] | 5006 | return IRQ_HANDLED; |
Ville Syrjälä | 7a7f84c | 2014-10-16 20:46:10 +0300 | [diff] [blame] | 5007 | } |
| 5008 | |
Ville Syrjälä | 26fbb77 | 2014-08-11 18:37:37 +0300 | [diff] [blame] | 5009 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
| 5010 | port_name(intel_dig_port->port), |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5011 | long_hpd ? "long" : "short"); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 5012 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 5013 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 5014 | intel_display_power_get(dev_priv, power_domain); |
| 5015 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5016 | if (long_hpd) { |
Mika Kahola | 5fa836a | 2015-04-29 09:17:40 +0300 | [diff] [blame] | 5017 | /* indicate that we need to restart link training */ |
| 5018 | intel_dp->train_set_valid = false; |
Dave Airlie | 2a592be | 2014-09-01 16:58:12 +1000 | [diff] [blame] | 5019 | |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 5020 | if (!intel_digital_port_connected(dev_priv, intel_dig_port)) |
| 5021 | goto mst_fail; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5022 | |
| 5023 | if (!intel_dp_get_dpcd(intel_dp)) { |
| 5024 | goto mst_fail; |
| 5025 | } |
| 5026 | |
| 5027 | intel_dp_probe_oui(intel_dp); |
| 5028 | |
Ville Syrjälä | d14e7b6 | 2015-08-20 19:37:29 +0300 | [diff] [blame] | 5029 | if (!intel_dp_probe_mst(intel_dp)) { |
| 5030 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
| 5031 | intel_dp_check_link_status(intel_dp); |
| 5032 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5033 | goto mst_fail; |
Ville Syrjälä | d14e7b6 | 2015-08-20 19:37:29 +0300 | [diff] [blame] | 5034 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5035 | } else { |
| 5036 | if (intel_dp->is_mst) { |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 5037 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5038 | goto mst_fail; |
| 5039 | } |
| 5040 | |
| 5041 | if (!intel_dp->is_mst) { |
Dave Airlie | 5b215bc | 2014-08-05 10:40:20 +1000 | [diff] [blame] | 5042 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5043 | intel_dp_check_link_status(intel_dp); |
Dave Airlie | 5b215bc | 2014-08-05 10:40:20 +1000 | [diff] [blame] | 5044 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5045 | } |
| 5046 | } |
Daniel Vetter | b2c5c18 | 2015-01-23 06:00:31 +0100 | [diff] [blame] | 5047 | |
| 5048 | ret = IRQ_HANDLED; |
| 5049 | |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 5050 | goto put_power; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5051 | mst_fail: |
| 5052 | /* if we were in MST mode, and device is not there get out of MST mode */ |
| 5053 | if (intel_dp->is_mst) { |
| 5054 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
| 5055 | intel_dp->is_mst = false; |
| 5056 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
| 5057 | } |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 5058 | put_power: |
| 5059 | intel_display_power_put(dev_priv, power_domain); |
| 5060 | |
| 5061 | return ret; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 5062 | } |
| 5063 | |
Rodrigo Vivi | 477ec32 | 2015-08-06 15:51:39 +0800 | [diff] [blame] | 5064 | /* check the VBT to see whether the eDP is on another port */ |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 5065 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 5066 | { |
| 5067 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 768f69c | 2013-09-11 18:02:47 -0300 | [diff] [blame] | 5068 | union child_device_config *p_child; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 5069 | int i; |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 5070 | static const short port_mapping[] = { |
Rodrigo Vivi | 477ec32 | 2015-08-06 15:51:39 +0800 | [diff] [blame] | 5071 | [PORT_B] = DVO_PORT_DPB, |
| 5072 | [PORT_C] = DVO_PORT_DPC, |
| 5073 | [PORT_D] = DVO_PORT_DPD, |
| 5074 | [PORT_E] = DVO_PORT_DPE, |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 5075 | }; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 5076 | |
Ville Syrjälä | 53ce81a | 2015-09-11 21:04:38 +0300 | [diff] [blame] | 5077 | /* |
| 5078 | * eDP not supported on g4x. so bail out early just |
| 5079 | * for a bit extra safety in case the VBT is bonkers. |
| 5080 | */ |
| 5081 | if (INTEL_INFO(dev)->gen < 5) |
| 5082 | return false; |
| 5083 | |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 5084 | if (port == PORT_A) |
| 5085 | return true; |
| 5086 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 5087 | if (!dev_priv->vbt.child_dev_num) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 5088 | return false; |
| 5089 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 5090 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
| 5091 | p_child = dev_priv->vbt.child_dev + i; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 5092 | |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 5093 | if (p_child->common.dvo_port == port_mapping[port] && |
Ville Syrjälä | f02586d | 2013-11-01 20:32:08 +0200 | [diff] [blame] | 5094 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
| 5095 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 5096 | return true; |
| 5097 | } |
| 5098 | return false; |
| 5099 | } |
| 5100 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5101 | void |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 5102 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
| 5103 | { |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 5104 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 5105 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 5106 | intel_attach_force_audio_property(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 5107 | intel_attach_broadcast_rgb_property(connector); |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 5108 | intel_dp->color_range_auto = true; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 5109 | |
| 5110 | if (is_edp(intel_dp)) { |
| 5111 | drm_mode_create_scaling_mode_property(connector->dev); |
Rob Clark | 6de6d84 | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 5112 | drm_object_attach_property( |
| 5113 | &connector->base, |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 5114 | connector->dev->mode_config.scaling_mode_property, |
Yuly Novikov | 8e740cd | 2012-10-26 12:04:01 +0300 | [diff] [blame] | 5115 | DRM_MODE_SCALE_ASPECT); |
| 5116 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 5117 | } |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 5118 | } |
| 5119 | |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 5120 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
| 5121 | { |
| 5122 | intel_dp->last_power_cycle = jiffies; |
| 5123 | intel_dp->last_power_on = jiffies; |
| 5124 | intel_dp->last_backlight_off = jiffies; |
| 5125 | } |
| 5126 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5127 | static void |
| 5128 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5129 | struct intel_dp *intel_dp) |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5130 | { |
| 5131 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5132 | struct edp_power_seq cur, vbt, spec, |
| 5133 | *final = &intel_dp->pps_delays; |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5134 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5135 | i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5136 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 5137 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 5138 | |
Ville Syrjälä | 81ddbc6 | 2014-10-16 21:27:31 +0300 | [diff] [blame] | 5139 | /* already initialized? */ |
| 5140 | if (final->t11_t12 != 0) |
| 5141 | return; |
| 5142 | |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5143 | if (IS_BROXTON(dev)) { |
| 5144 | /* |
| 5145 | * TODO: BXT has 2 sets of PPS registers. |
| 5146 | * Correct Register for Broxton need to be identified |
| 5147 | * using VBT. hardcoding for now |
| 5148 | */ |
| 5149 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
| 5150 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
| 5151 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
| 5152 | } else if (HAS_PCH_SPLIT(dev)) { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 5153 | pp_ctrl_reg = PCH_PP_CONTROL; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5154 | pp_on_reg = PCH_PP_ON_DELAYS; |
| 5155 | pp_off_reg = PCH_PP_OFF_DELAYS; |
| 5156 | pp_div_reg = PCH_PP_DIVISOR; |
| 5157 | } else { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 5158 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 5159 | |
| 5160 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
| 5161 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
| 5162 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
| 5163 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5164 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5165 | |
| 5166 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
| 5167 | * the very first thing. */ |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5168 | pp_ctl = ironlake_get_pp_control(intel_dp); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5169 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5170 | pp_on = I915_READ(pp_on_reg); |
| 5171 | pp_off = I915_READ(pp_off_reg); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5172 | if (!IS_BROXTON(dev)) { |
| 5173 | I915_WRITE(pp_ctrl_reg, pp_ctl); |
| 5174 | pp_div = I915_READ(pp_div_reg); |
| 5175 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5176 | |
| 5177 | /* Pull timing values out of registers */ |
| 5178 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
| 5179 | PANEL_POWER_UP_DELAY_SHIFT; |
| 5180 | |
| 5181 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
| 5182 | PANEL_LIGHT_ON_DELAY_SHIFT; |
| 5183 | |
| 5184 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
| 5185 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
| 5186 | |
| 5187 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
| 5188 | PANEL_POWER_DOWN_DELAY_SHIFT; |
| 5189 | |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5190 | if (IS_BROXTON(dev)) { |
| 5191 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
| 5192 | BXT_POWER_CYCLE_DELAY_SHIFT; |
| 5193 | if (tmp > 0) |
| 5194 | cur.t11_t12 = (tmp - 1) * 1000; |
| 5195 | else |
| 5196 | cur.t11_t12 = 0; |
| 5197 | } else { |
| 5198 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5199 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5200 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5201 | |
| 5202 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 5203 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
| 5204 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 5205 | vbt = dev_priv->vbt.edp_pps; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5206 | |
| 5207 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
| 5208 | * our hw here, which are all in 100usec. */ |
| 5209 | spec.t1_t3 = 210 * 10; |
| 5210 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
| 5211 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
| 5212 | spec.t10 = 500 * 10; |
| 5213 | /* This one is special and actually in units of 100ms, but zero |
| 5214 | * based in the hw (so we need to add 100 ms). But the sw vbt |
| 5215 | * table multiplies it with 1000 to make it in units of 100usec, |
| 5216 | * too. */ |
| 5217 | spec.t11_t12 = (510 + 100) * 10; |
| 5218 | |
| 5219 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 5220 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
| 5221 | |
| 5222 | /* Use the max of the register settings and vbt. If both are |
| 5223 | * unset, fall back to the spec limits. */ |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5224 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5225 | spec.field : \ |
| 5226 | max(cur.field, vbt.field)) |
| 5227 | assign_final(t1_t3); |
| 5228 | assign_final(t8); |
| 5229 | assign_final(t9); |
| 5230 | assign_final(t10); |
| 5231 | assign_final(t11_t12); |
| 5232 | #undef assign_final |
| 5233 | |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5234 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5235 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
| 5236 | intel_dp->backlight_on_delay = get_delay(t8); |
| 5237 | intel_dp->backlight_off_delay = get_delay(t9); |
| 5238 | intel_dp->panel_power_down_delay = get_delay(t10); |
| 5239 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
| 5240 | #undef get_delay |
| 5241 | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5242 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
| 5243 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
| 5244 | intel_dp->panel_power_cycle_delay); |
| 5245 | |
| 5246 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
| 5247 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5248 | } |
| 5249 | |
| 5250 | static void |
| 5251 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5252 | struct intel_dp *intel_dp) |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5253 | { |
| 5254 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5255 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
| 5256 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5257 | i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg; |
Ville Syrjälä | ad933b5 | 2014-08-18 22:15:56 +0300 | [diff] [blame] | 5258 | enum port port = dp_to_dig_port(intel_dp)->port; |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5259 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5260 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 5261 | lockdep_assert_held(&dev_priv->pps_mutex); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5262 | |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5263 | if (IS_BROXTON(dev)) { |
| 5264 | /* |
| 5265 | * TODO: BXT has 2 sets of PPS registers. |
| 5266 | * Correct Register for Broxton need to be identified |
| 5267 | * using VBT. hardcoding for now |
| 5268 | */ |
| 5269 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
| 5270 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
| 5271 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
| 5272 | |
| 5273 | } else if (HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5274 | pp_on_reg = PCH_PP_ON_DELAYS; |
| 5275 | pp_off_reg = PCH_PP_OFF_DELAYS; |
| 5276 | pp_div_reg = PCH_PP_DIVISOR; |
| 5277 | } else { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 5278 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 5279 | |
| 5280 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
| 5281 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
| 5282 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5283 | } |
| 5284 | |
Paulo Zanoni | b2f19d1 | 2013-12-19 14:29:44 -0200 | [diff] [blame] | 5285 | /* |
| 5286 | * And finally store the new values in the power sequencer. The |
| 5287 | * backlight delays are set to 1 because we do manual waits on them. For |
| 5288 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
| 5289 | * we'll end up waiting for the backlight off delay twice: once when we |
| 5290 | * do the manual sleep, and once when we disable the panel and wait for |
| 5291 | * the PP_STATUS bit to become zero. |
| 5292 | */ |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5293 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
Paulo Zanoni | b2f19d1 | 2013-12-19 14:29:44 -0200 | [diff] [blame] | 5294 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
| 5295 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 5296 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5297 | /* Compute the divisor for the pp clock, simply match the Bspec |
| 5298 | * formula. */ |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5299 | if (IS_BROXTON(dev)) { |
| 5300 | pp_div = I915_READ(pp_ctrl_reg); |
| 5301 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
| 5302 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) |
| 5303 | << BXT_POWER_CYCLE_DELAY_SHIFT); |
| 5304 | } else { |
| 5305 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
| 5306 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
| 5307 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
| 5308 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5309 | |
| 5310 | /* Haswell doesn't have any port selection bits for the panel |
| 5311 | * power sequencer any more. */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5312 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | ad933b5 | 2014-08-18 22:15:56 +0300 | [diff] [blame] | 5313 | port_sel = PANEL_PORT_SELECT_VLV(port); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 5314 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
Ville Syrjälä | ad933b5 | 2014-08-18 22:15:56 +0300 | [diff] [blame] | 5315 | if (port == PORT_A) |
Jani Nikula | a24c144 | 2013-09-05 16:44:46 +0300 | [diff] [blame] | 5316 | port_sel = PANEL_PORT_SELECT_DPA; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5317 | else |
Jani Nikula | a24c144 | 2013-09-05 16:44:46 +0300 | [diff] [blame] | 5318 | port_sel = PANEL_PORT_SELECT_DPD; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5319 | } |
| 5320 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5321 | pp_on |= port_sel; |
| 5322 | |
| 5323 | I915_WRITE(pp_on_reg, pp_on); |
| 5324 | I915_WRITE(pp_off_reg, pp_off); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5325 | if (IS_BROXTON(dev)) |
| 5326 | I915_WRITE(pp_ctrl_reg, pp_div); |
| 5327 | else |
| 5328 | I915_WRITE(pp_div_reg, pp_div); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5329 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5330 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5331 | I915_READ(pp_on_reg), |
| 5332 | I915_READ(pp_off_reg), |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5333 | IS_BROXTON(dev) ? |
| 5334 | (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) : |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 5335 | I915_READ(pp_div_reg)); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 5336 | } |
| 5337 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5338 | /** |
| 5339 | * intel_dp_set_drrs_state - program registers for RR switch to take effect |
| 5340 | * @dev: DRM device |
| 5341 | * @refresh_rate: RR to be programmed |
| 5342 | * |
| 5343 | * This function gets called when refresh rate (RR) has to be changed from |
| 5344 | * one frequency to another. Switches can be between high and low RR |
| 5345 | * supported by the panel or to any other RR based on media playback (in |
| 5346 | * this case, RR value needs to be passed from user space). |
| 5347 | * |
| 5348 | * The caller of this function needs to take a lock on dev_priv->drrs. |
| 5349 | */ |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5350 | static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5351 | { |
| 5352 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5353 | struct intel_encoder *encoder; |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5354 | struct intel_digital_port *dig_port = NULL; |
| 5355 | struct intel_dp *intel_dp = dev_priv->drrs.dp; |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 5356 | struct intel_crtc_state *config = NULL; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5357 | struct intel_crtc *intel_crtc = NULL; |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5358 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5359 | |
| 5360 | if (refresh_rate <= 0) { |
| 5361 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
| 5362 | return; |
| 5363 | } |
| 5364 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5365 | if (intel_dp == NULL) { |
| 5366 | DRM_DEBUG_KMS("DRRS not supported.\n"); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5367 | return; |
| 5368 | } |
| 5369 | |
Daniel Vetter | 1fcc9d1 | 2014-07-11 10:30:10 -0700 | [diff] [blame] | 5370 | /* |
Rodrigo Vivi | e4d59f6 | 2014-11-20 02:22:08 -0800 | [diff] [blame] | 5371 | * FIXME: This needs proper synchronization with psr state for some |
| 5372 | * platforms that cannot have PSR and DRRS enabled at the same time. |
Daniel Vetter | 1fcc9d1 | 2014-07-11 10:30:10 -0700 | [diff] [blame] | 5373 | */ |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5374 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5375 | dig_port = dp_to_dig_port(intel_dp); |
| 5376 | encoder = &dig_port->base; |
Ander Conselvan de Oliveira | 723f9aa | 2015-03-20 16:18:18 +0200 | [diff] [blame] | 5377 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5378 | |
| 5379 | if (!intel_crtc) { |
| 5380 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
| 5381 | return; |
| 5382 | } |
| 5383 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5384 | config = intel_crtc->config; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5385 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5386 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5387 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
| 5388 | return; |
| 5389 | } |
| 5390 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5391 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
| 5392 | refresh_rate) |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5393 | index = DRRS_LOW_RR; |
| 5394 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5395 | if (index == dev_priv->drrs.refresh_rate_type) { |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5396 | DRM_DEBUG_KMS( |
| 5397 | "DRRS requested for previously set RR...ignoring\n"); |
| 5398 | return; |
| 5399 | } |
| 5400 | |
| 5401 | if (!intel_crtc->active) { |
| 5402 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
| 5403 | return; |
| 5404 | } |
| 5405 | |
Durgadoss R | 44395bf | 2015-02-13 15:33:02 +0530 | [diff] [blame] | 5406 | if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { |
Vandana Kannan | a4c30b1 | 2015-02-13 15:33:00 +0530 | [diff] [blame] | 5407 | switch (index) { |
| 5408 | case DRRS_HIGH_RR: |
| 5409 | intel_dp_set_m_n(intel_crtc, M1_N1); |
| 5410 | break; |
| 5411 | case DRRS_LOW_RR: |
| 5412 | intel_dp_set_m_n(intel_crtc, M2_N2); |
| 5413 | break; |
| 5414 | case DRRS_MAX_RR: |
| 5415 | default: |
| 5416 | DRM_ERROR("Unsupported refreshrate type\n"); |
| 5417 | } |
| 5418 | } else if (INTEL_INFO(dev)->gen > 6) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5419 | i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 5420 | u32 val; |
Vandana Kannan | a4c30b1 | 2015-02-13 15:33:00 +0530 | [diff] [blame] | 5421 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 5422 | val = I915_READ(reg); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5423 | if (index > DRRS_HIGH_RR) { |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5424 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Vandana Kannan | 6fa7aec | 2015-02-13 15:33:01 +0530 | [diff] [blame] | 5425 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
| 5426 | else |
| 5427 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5428 | } else { |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5429 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Vandana Kannan | 6fa7aec | 2015-02-13 15:33:01 +0530 | [diff] [blame] | 5430 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
| 5431 | else |
| 5432 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5433 | } |
| 5434 | I915_WRITE(reg, val); |
| 5435 | } |
| 5436 | |
Vandana Kannan | 4e9ac94 | 2015-01-22 15:14:45 +0530 | [diff] [blame] | 5437 | dev_priv->drrs.refresh_rate_type = index; |
| 5438 | |
| 5439 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
| 5440 | } |
| 5441 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5442 | /** |
| 5443 | * intel_edp_drrs_enable - init drrs struct if supported |
| 5444 | * @intel_dp: DP struct |
| 5445 | * |
| 5446 | * Initializes frontbuffer_bits and drrs.dp |
| 5447 | */ |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5448 | void intel_edp_drrs_enable(struct intel_dp *intel_dp) |
| 5449 | { |
| 5450 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 5451 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5452 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 5453 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
| 5454 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5455 | |
| 5456 | if (!intel_crtc->config->has_drrs) { |
| 5457 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
| 5458 | return; |
| 5459 | } |
| 5460 | |
| 5461 | mutex_lock(&dev_priv->drrs.mutex); |
| 5462 | if (WARN_ON(dev_priv->drrs.dp)) { |
| 5463 | DRM_ERROR("DRRS already enabled\n"); |
| 5464 | goto unlock; |
| 5465 | } |
| 5466 | |
| 5467 | dev_priv->drrs.busy_frontbuffer_bits = 0; |
| 5468 | |
| 5469 | dev_priv->drrs.dp = intel_dp; |
| 5470 | |
| 5471 | unlock: |
| 5472 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5473 | } |
| 5474 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5475 | /** |
| 5476 | * intel_edp_drrs_disable - Disable DRRS |
| 5477 | * @intel_dp: DP struct |
| 5478 | * |
| 5479 | */ |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5480 | void intel_edp_drrs_disable(struct intel_dp *intel_dp) |
| 5481 | { |
| 5482 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 5483 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5484 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 5485 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
| 5486 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5487 | |
| 5488 | if (!intel_crtc->config->has_drrs) |
| 5489 | return; |
| 5490 | |
| 5491 | mutex_lock(&dev_priv->drrs.mutex); |
| 5492 | if (!dev_priv->drrs.dp) { |
| 5493 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5494 | return; |
| 5495 | } |
| 5496 | |
| 5497 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
| 5498 | intel_dp_set_drrs_state(dev_priv->dev, |
| 5499 | intel_dp->attached_connector->panel. |
| 5500 | fixed_mode->vrefresh); |
| 5501 | |
| 5502 | dev_priv->drrs.dp = NULL; |
| 5503 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5504 | |
| 5505 | cancel_delayed_work_sync(&dev_priv->drrs.work); |
| 5506 | } |
| 5507 | |
Vandana Kannan | 4e9ac94 | 2015-01-22 15:14:45 +0530 | [diff] [blame] | 5508 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
| 5509 | { |
| 5510 | struct drm_i915_private *dev_priv = |
| 5511 | container_of(work, typeof(*dev_priv), drrs.work.work); |
| 5512 | struct intel_dp *intel_dp; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5513 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5514 | mutex_lock(&dev_priv->drrs.mutex); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5515 | |
Vandana Kannan | 4e9ac94 | 2015-01-22 15:14:45 +0530 | [diff] [blame] | 5516 | intel_dp = dev_priv->drrs.dp; |
| 5517 | |
| 5518 | if (!intel_dp) |
| 5519 | goto unlock; |
| 5520 | |
| 5521 | /* |
| 5522 | * The delayed work can race with an invalidate hence we need to |
| 5523 | * recheck. |
| 5524 | */ |
| 5525 | |
| 5526 | if (dev_priv->drrs.busy_frontbuffer_bits) |
| 5527 | goto unlock; |
| 5528 | |
| 5529 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) |
| 5530 | intel_dp_set_drrs_state(dev_priv->dev, |
| 5531 | intel_dp->attached_connector->panel. |
| 5532 | downclock_mode->vrefresh); |
| 5533 | |
| 5534 | unlock: |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5535 | mutex_unlock(&dev_priv->drrs.mutex); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5536 | } |
| 5537 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5538 | /** |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5539 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5540 | * @dev: DRM device |
| 5541 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 5542 | * |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5543 | * This function gets called everytime rendering on the given planes start. |
| 5544 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5545 | * |
| 5546 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
| 5547 | */ |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5548 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
| 5549 | unsigned frontbuffer_bits) |
| 5550 | { |
| 5551 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5552 | struct drm_crtc *crtc; |
| 5553 | enum pipe pipe; |
| 5554 | |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5555 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5556 | return; |
| 5557 | |
Daniel Vetter | 88f933a | 2015-04-09 16:44:16 +0200 | [diff] [blame] | 5558 | cancel_delayed_work(&dev_priv->drrs.work); |
Ramalingam C | 3954e73 | 2015-03-03 12:11:46 +0530 | [diff] [blame] | 5559 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5560 | mutex_lock(&dev_priv->drrs.mutex); |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5561 | if (!dev_priv->drrs.dp) { |
| 5562 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5563 | return; |
| 5564 | } |
| 5565 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5566 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
| 5567 | pipe = to_intel_crtc(crtc)->pipe; |
| 5568 | |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5569 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
| 5570 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; |
| 5571 | |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5572 | /* invalidate means busy screen hence upclock */ |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5573 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5574 | intel_dp_set_drrs_state(dev_priv->dev, |
| 5575 | dev_priv->drrs.dp->attached_connector->panel. |
| 5576 | fixed_mode->vrefresh); |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5577 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5578 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5579 | } |
| 5580 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5581 | /** |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5582 | * intel_edp_drrs_flush - Restart Idleness DRRS |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5583 | * @dev: DRM device |
| 5584 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 5585 | * |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5586 | * This function gets called every time rendering on the given planes has |
| 5587 | * completed or flip on a crtc is completed. So DRRS should be upclocked |
| 5588 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, |
| 5589 | * if no other planes are dirty. |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5590 | * |
| 5591 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
| 5592 | */ |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5593 | void intel_edp_drrs_flush(struct drm_device *dev, |
| 5594 | unsigned frontbuffer_bits) |
| 5595 | { |
| 5596 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5597 | struct drm_crtc *crtc; |
| 5598 | enum pipe pipe; |
| 5599 | |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5600 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5601 | return; |
| 5602 | |
Daniel Vetter | 88f933a | 2015-04-09 16:44:16 +0200 | [diff] [blame] | 5603 | cancel_delayed_work(&dev_priv->drrs.work); |
Ramalingam C | 3954e73 | 2015-03-03 12:11:46 +0530 | [diff] [blame] | 5604 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5605 | mutex_lock(&dev_priv->drrs.mutex); |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5606 | if (!dev_priv->drrs.dp) { |
| 5607 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5608 | return; |
| 5609 | } |
| 5610 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5611 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
| 5612 | pipe = to_intel_crtc(crtc)->pipe; |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5613 | |
| 5614 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5615 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
| 5616 | |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5617 | /* flush means busy screen hence upclock */ |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5618 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5619 | intel_dp_set_drrs_state(dev_priv->dev, |
| 5620 | dev_priv->drrs.dp->attached_connector->panel. |
| 5621 | fixed_mode->vrefresh); |
| 5622 | |
| 5623 | /* |
| 5624 | * flush also means no more activity hence schedule downclock, if all |
| 5625 | * other fbs are quiescent too |
| 5626 | */ |
| 5627 | if (!dev_priv->drrs.busy_frontbuffer_bits) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5628 | schedule_delayed_work(&dev_priv->drrs.work, |
| 5629 | msecs_to_jiffies(1000)); |
| 5630 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5631 | } |
| 5632 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5633 | /** |
| 5634 | * DOC: Display Refresh Rate Switching (DRRS) |
| 5635 | * |
| 5636 | * Display Refresh Rate Switching (DRRS) is a power conservation feature |
| 5637 | * which enables swtching between low and high refresh rates, |
| 5638 | * dynamically, based on the usage scenario. This feature is applicable |
| 5639 | * for internal panels. |
| 5640 | * |
| 5641 | * Indication that the panel supports DRRS is given by the panel EDID, which |
| 5642 | * would list multiple refresh rates for one resolution. |
| 5643 | * |
| 5644 | * DRRS is of 2 types - static and seamless. |
| 5645 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset |
| 5646 | * (may appear as a blink on screen) and is used in dock-undock scenario. |
| 5647 | * Seamless DRRS involves changing RR without any visual effect to the user |
| 5648 | * and can be used during normal system usage. This is done by programming |
| 5649 | * certain registers. |
| 5650 | * |
| 5651 | * Support for static/seamless DRRS may be indicated in the VBT based on |
| 5652 | * inputs from the panel spec. |
| 5653 | * |
| 5654 | * DRRS saves power by switching to low RR based on usage scenarios. |
| 5655 | * |
| 5656 | * eDP DRRS:- |
| 5657 | * The implementation is based on frontbuffer tracking implementation. |
| 5658 | * When there is a disturbance on the screen triggered by user activity or a |
| 5659 | * periodic system activity, DRRS is disabled (RR is changed to high RR). |
| 5660 | * When there is no movement on screen, after a timeout of 1 second, a switch |
| 5661 | * to low RR is made. |
| 5662 | * For integration with frontbuffer tracking code, |
| 5663 | * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called. |
| 5664 | * |
| 5665 | * DRRS can be further extended to support other internal panels and also |
| 5666 | * the scenario of video playback wherein RR is set based on the rate |
| 5667 | * requested by userspace. |
| 5668 | */ |
| 5669 | |
| 5670 | /** |
| 5671 | * intel_dp_drrs_init - Init basic DRRS work and mutex. |
| 5672 | * @intel_connector: eDP connector |
| 5673 | * @fixed_mode: preferred mode of panel |
| 5674 | * |
| 5675 | * This function is called only once at driver load to initialize basic |
| 5676 | * DRRS stuff. |
| 5677 | * |
| 5678 | * Returns: |
| 5679 | * Downclock mode if panel supports it, else return NULL. |
| 5680 | * DRRS support is determined by the presence of downclock mode (apart |
| 5681 | * from VBT setting). |
| 5682 | */ |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5683 | static struct drm_display_mode * |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5684 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
| 5685 | struct drm_display_mode *fixed_mode) |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5686 | { |
| 5687 | struct drm_connector *connector = &intel_connector->base; |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5688 | struct drm_device *dev = connector->dev; |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5689 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5690 | struct drm_display_mode *downclock_mode = NULL; |
| 5691 | |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5692 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
| 5693 | mutex_init(&dev_priv->drrs.mutex); |
| 5694 | |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5695 | if (INTEL_INFO(dev)->gen <= 6) { |
| 5696 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
| 5697 | return NULL; |
| 5698 | } |
| 5699 | |
| 5700 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
Damien Lespiau | 4079b8d | 2014-08-05 10:39:42 +0100 | [diff] [blame] | 5701 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5702 | return NULL; |
| 5703 | } |
| 5704 | |
| 5705 | downclock_mode = intel_find_panel_downclock |
| 5706 | (dev, fixed_mode, connector); |
| 5707 | |
| 5708 | if (!downclock_mode) { |
Ramalingam C | a1d2634 | 2015-02-23 17:38:33 +0530 | [diff] [blame] | 5709 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5710 | return NULL; |
| 5711 | } |
| 5712 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5713 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5714 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5715 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
Damien Lespiau | 4079b8d | 2014-08-05 10:39:42 +0100 | [diff] [blame] | 5716 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5717 | return downclock_mode; |
| 5718 | } |
| 5719 | |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5720 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5721 | struct intel_connector *intel_connector) |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5722 | { |
| 5723 | struct drm_connector *connector = &intel_connector->base; |
| 5724 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Paulo Zanoni | 6363521 | 2014-04-22 19:55:42 -0300 | [diff] [blame] | 5725 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 5726 | struct drm_device *dev = intel_encoder->base.dev; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5727 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5728 | struct drm_display_mode *fixed_mode = NULL; |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5729 | struct drm_display_mode *downclock_mode = NULL; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5730 | bool has_dpcd; |
| 5731 | struct drm_display_mode *scan; |
| 5732 | struct edid *edid; |
Ville Syrjälä | 6517d27 | 2014-11-07 11:16:02 +0200 | [diff] [blame] | 5733 | enum pipe pipe = INVALID_PIPE; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5734 | |
| 5735 | if (!is_edp(intel_dp)) |
| 5736 | return true; |
| 5737 | |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 5738 | pps_lock(intel_dp); |
| 5739 | intel_edp_panel_vdd_sanitize(intel_dp); |
| 5740 | pps_unlock(intel_dp); |
Paulo Zanoni | 6363521 | 2014-04-22 19:55:42 -0300 | [diff] [blame] | 5741 | |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5742 | /* Cache DPCD and EDID for edp. */ |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5743 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5744 | |
| 5745 | if (has_dpcd) { |
| 5746 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
| 5747 | dev_priv->no_aux_handshake = |
| 5748 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
| 5749 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
| 5750 | } else { |
| 5751 | /* if this fails, presume the device is a ghost */ |
| 5752 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5753 | return false; |
| 5754 | } |
| 5755 | |
| 5756 | /* We now know it's not a ghost, init power sequence regs. */ |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 5757 | pps_lock(intel_dp); |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5758 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 5759 | pps_unlock(intel_dp); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5760 | |
Daniel Vetter | 060c877 | 2014-03-21 23:22:35 +0100 | [diff] [blame] | 5761 | mutex_lock(&dev->mode_config.mutex); |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 5762 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5763 | if (edid) { |
| 5764 | if (drm_add_edid_modes(connector, edid)) { |
| 5765 | drm_mode_connector_update_edid_property(connector, |
| 5766 | edid); |
| 5767 | drm_edid_to_eld(connector, edid); |
| 5768 | } else { |
| 5769 | kfree(edid); |
| 5770 | edid = ERR_PTR(-EINVAL); |
| 5771 | } |
| 5772 | } else { |
| 5773 | edid = ERR_PTR(-ENOENT); |
| 5774 | } |
| 5775 | intel_connector->edid = edid; |
| 5776 | |
| 5777 | /* prefer fixed mode from EDID if available */ |
| 5778 | list_for_each_entry(scan, &connector->probed_modes, head) { |
| 5779 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
| 5780 | fixed_mode = drm_mode_duplicate(dev, scan); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5781 | downclock_mode = intel_dp_drrs_init( |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5782 | intel_connector, fixed_mode); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5783 | break; |
| 5784 | } |
| 5785 | } |
| 5786 | |
| 5787 | /* fallback to VBT if available for eDP */ |
| 5788 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
| 5789 | fixed_mode = drm_mode_duplicate(dev, |
| 5790 | dev_priv->vbt.lfp_lvds_vbt_mode); |
| 5791 | if (fixed_mode) |
| 5792 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
| 5793 | } |
Daniel Vetter | 060c877 | 2014-03-21 23:22:35 +0100 | [diff] [blame] | 5794 | mutex_unlock(&dev->mode_config.mutex); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5795 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5796 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 5797 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
| 5798 | register_reboot_notifier(&intel_dp->edp_notifier); |
Ville Syrjälä | 6517d27 | 2014-11-07 11:16:02 +0200 | [diff] [blame] | 5799 | |
| 5800 | /* |
| 5801 | * Figure out the current pipe for the initial backlight setup. |
| 5802 | * If the current pipe isn't valid, try the PPS pipe, and if that |
| 5803 | * fails just assume pipe A. |
| 5804 | */ |
| 5805 | if (IS_CHERRYVIEW(dev)) |
| 5806 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); |
| 5807 | else |
| 5808 | pipe = PORT_TO_PIPE(intel_dp->DP); |
| 5809 | |
| 5810 | if (pipe != PIPE_A && pipe != PIPE_B) |
| 5811 | pipe = intel_dp->pps_pipe; |
| 5812 | |
| 5813 | if (pipe != PIPE_A && pipe != PIPE_B) |
| 5814 | pipe = PIPE_A; |
| 5815 | |
| 5816 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", |
| 5817 | pipe_name(pipe)); |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 5818 | } |
| 5819 | |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5820 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
Jani Nikula | 5507fae | 2015-09-14 14:03:48 +0300 | [diff] [blame] | 5821 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
Ville Syrjälä | 6517d27 | 2014-11-07 11:16:02 +0200 | [diff] [blame] | 5822 | intel_panel_setup_backlight(connector, pipe); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5823 | |
| 5824 | return true; |
| 5825 | } |
| 5826 | |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 5827 | bool |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5828 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 5829 | struct intel_connector *intel_connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5830 | { |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5831 | struct drm_connector *connector = &intel_connector->base; |
| 5832 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 5833 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 5834 | struct drm_device *dev = intel_encoder->base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5835 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 5836 | enum port port = intel_dig_port->port; |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 5837 | int type, ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5838 | |
Ville Syrjälä | ccb1a83 | 2015-12-08 19:59:38 +0200 | [diff] [blame] | 5839 | if (WARN(intel_dig_port->max_lanes < 1, |
| 5840 | "Not enough lanes (%d) for DP on port %c\n", |
| 5841 | intel_dig_port->max_lanes, port_name(port))) |
| 5842 | return false; |
| 5843 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 5844 | intel_dp->pps_pipe = INVALID_PIPE; |
| 5845 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 5846 | /* intel_dp vfuncs */ |
Damien Lespiau | b6b5e38 | 2014-01-20 16:00:59 +0000 | [diff] [blame] | 5847 | if (INTEL_INFO(dev)->gen >= 9) |
| 5848 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5849 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 5850 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
| 5851 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 5852 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
| 5853 | else if (HAS_PCH_SPLIT(dev)) |
| 5854 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
| 5855 | else |
| 5856 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
| 5857 | |
Damien Lespiau | b9ca5fa | 2014-01-20 16:01:00 +0000 | [diff] [blame] | 5858 | if (INTEL_INFO(dev)->gen >= 9) |
| 5859 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
| 5860 | else |
| 5861 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
Damien Lespiau | 153b110 | 2014-01-21 13:37:15 +0000 | [diff] [blame] | 5862 | |
Ander Conselvan de Oliveira | ad64217 | 2015-10-23 13:01:49 +0300 | [diff] [blame] | 5863 | if (HAS_DDI(dev)) |
| 5864 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
| 5865 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 5866 | /* Preserve the current hw state. */ |
| 5867 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 5868 | intel_dp->attached_connector = intel_connector; |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 5869 | |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 5870 | if (intel_dp_is_edp(dev, port)) |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 5871 | type = DRM_MODE_CONNECTOR_eDP; |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 5872 | else |
| 5873 | type = DRM_MODE_CONNECTOR_DisplayPort; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 5874 | |
Imre Deak | f7d2490 | 2013-05-08 13:14:05 +0300 | [diff] [blame] | 5875 | /* |
| 5876 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
| 5877 | * for DP the encoder type can be set by the caller to |
| 5878 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
| 5879 | */ |
| 5880 | if (type == DRM_MODE_CONNECTOR_eDP) |
| 5881 | intel_encoder->type = INTEL_OUTPUT_EDP; |
| 5882 | |
Ville Syrjälä | c17ed5b | 2014-10-16 21:27:27 +0300 | [diff] [blame] | 5883 | /* eDP only on port B and/or C on vlv/chv */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5884 | if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
| 5885 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) |
Ville Syrjälä | c17ed5b | 2014-10-16 21:27:27 +0300 | [diff] [blame] | 5886 | return false; |
| 5887 | |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 5888 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
| 5889 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
| 5890 | port_name(port)); |
| 5891 | |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 5892 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5893 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
| 5894 | |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5895 | connector->interlace_allowed = true; |
| 5896 | connector->doublescan_allowed = 0; |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 5897 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 5898 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 5899 | edp_panel_vdd_work); |
Zhenyu Wang | 6251ec0 | 2010-01-12 05:38:32 +0800 | [diff] [blame] | 5900 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 5901 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
Thomas Wood | 34ea3d3 | 2014-05-29 16:57:41 +0100 | [diff] [blame] | 5902 | drm_connector_register(connector); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5903 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 5904 | if (HAS_DDI(dev)) |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 5905 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
| 5906 | else |
| 5907 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
Imre Deak | 80f65de | 2014-02-11 17:12:49 +0200 | [diff] [blame] | 5908 | intel_connector->unregister = intel_dp_connector_unregister; |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 5909 | |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 5910 | /* Set up the hotplug pin. */ |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5911 | switch (port) { |
| 5912 | case PORT_A: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5913 | intel_encoder->hpd_pin = HPD_PORT_A; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5914 | break; |
| 5915 | case PORT_B: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5916 | intel_encoder->hpd_pin = HPD_PORT_B; |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 5917 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
Sonika Jindal | cf1d588 | 2015-08-10 10:35:36 +0530 | [diff] [blame] | 5918 | intel_encoder->hpd_pin = HPD_PORT_A; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5919 | break; |
| 5920 | case PORT_C: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5921 | intel_encoder->hpd_pin = HPD_PORT_C; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5922 | break; |
| 5923 | case PORT_D: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5924 | intel_encoder->hpd_pin = HPD_PORT_D; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5925 | break; |
Xiong Zhang | 26951ca | 2015-08-17 15:55:50 +0800 | [diff] [blame] | 5926 | case PORT_E: |
| 5927 | intel_encoder->hpd_pin = HPD_PORT_E; |
| 5928 | break; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5929 | default: |
Damien Lespiau | ad1c0b1 | 2013-03-07 15:30:28 +0000 | [diff] [blame] | 5930 | BUG(); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 5931 | } |
| 5932 | |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 5933 | if (is_edp(intel_dp)) { |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 5934 | pps_lock(intel_dp); |
Ville Syrjälä | 1e74a32 | 2014-10-28 16:15:51 +0200 | [diff] [blame] | 5935 | intel_dp_init_panel_power_timestamps(intel_dp); |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5936 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 5937 | vlv_initial_power_sequencer_setup(intel_dp); |
Ville Syrjälä | 1e74a32 | 2014-10-28 16:15:51 +0200 | [diff] [blame] | 5938 | else |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5939 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 5940 | pps_unlock(intel_dp); |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 5941 | } |
Paulo Zanoni | 0095e6d | 2013-12-19 14:29:39 -0200 | [diff] [blame] | 5942 | |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 5943 | ret = intel_dp_aux_init(intel_dp, intel_connector); |
| 5944 | if (ret) |
| 5945 | goto fail; |
Dave Airlie | c1f0526 | 2012-08-30 11:06:18 +1000 | [diff] [blame] | 5946 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5947 | /* init MST on ports that can support it */ |
Jani Nikula | 0c9b371 | 2015-05-18 17:10:01 +0300 | [diff] [blame] | 5948 | if (HAS_DP_MST(dev) && |
| 5949 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
| 5950 | intel_dp_mst_encoder_init(intel_dig_port, |
| 5951 | intel_connector->base.base.id); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5952 | |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5953 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 5954 | intel_dp_aux_fini(intel_dp); |
| 5955 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
| 5956 | goto fail; |
Paulo Zanoni | b2f246a | 2013-06-12 17:27:26 -0300 | [diff] [blame] | 5957 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 5958 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 5959 | intel_dp_add_properties(intel_dp, connector); |
| 5960 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5961 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 5962 | * 0xd. Failure to do so will result in spurious interrupts being |
| 5963 | * generated on the port when a cable is not attached. |
| 5964 | */ |
| 5965 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 5966 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 5967 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 5968 | } |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 5969 | |
Jani Nikula | aa7471d | 2015-04-01 11:15:21 +0300 | [diff] [blame] | 5970 | i915_debugfs_connector_add(connector); |
| 5971 | |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 5972 | return true; |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 5973 | |
| 5974 | fail: |
| 5975 | if (is_edp(intel_dp)) { |
| 5976 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
| 5977 | /* |
| 5978 | * vdd might still be enabled do to the delayed vdd off. |
| 5979 | * Make sure vdd is actually turned off here. |
| 5980 | */ |
| 5981 | pps_lock(intel_dp); |
| 5982 | edp_panel_vdd_off_sync(intel_dp); |
| 5983 | pps_unlock(intel_dp); |
| 5984 | } |
| 5985 | drm_connector_unregister(connector); |
| 5986 | drm_connector_cleanup(connector); |
| 5987 | |
| 5988 | return false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5989 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5990 | |
| 5991 | void |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5992 | intel_dp_init(struct drm_device *dev, |
| 5993 | i915_reg_t output_reg, enum port port) |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5994 | { |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 5995 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5996 | struct intel_digital_port *intel_dig_port; |
| 5997 | struct intel_encoder *intel_encoder; |
| 5998 | struct drm_encoder *encoder; |
| 5999 | struct intel_connector *intel_connector; |
| 6000 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 6001 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 6002 | if (!intel_dig_port) |
| 6003 | return; |
| 6004 | |
Ander Conselvan de Oliveira | 08d9bc9 | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 6005 | intel_connector = intel_connector_alloc(); |
Sudip Mukherjee | 11aee0f | 2015-10-08 19:27:59 +0530 | [diff] [blame] | 6006 | if (!intel_connector) |
| 6007 | goto err_connector_alloc; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 6008 | |
| 6009 | intel_encoder = &intel_dig_port->base; |
| 6010 | encoder = &intel_encoder->base; |
| 6011 | |
Sudip Mukherjee | 893da0c | 2015-10-08 19:28:00 +0530 | [diff] [blame] | 6012 | if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
Dave Airlie | ade1ba7 | 2015-12-23 14:22:09 +1000 | [diff] [blame] | 6013 | DRM_MODE_ENCODER_TMDS, NULL)) |
Sudip Mukherjee | 893da0c | 2015-10-08 19:28:00 +0530 | [diff] [blame] | 6014 | goto err_encoder_init; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 6015 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 6016 | intel_encoder->compute_config = intel_dp_compute_config; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 6017 | intel_encoder->disable = intel_disable_dp; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 6018 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 6019 | intel_encoder->get_config = intel_dp_get_config; |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 6020 | intel_encoder->suspend = intel_dp_encoder_suspend; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 6021 | if (IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 6022 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 6023 | intel_encoder->pre_enable = chv_pre_enable_dp; |
| 6024 | intel_encoder->enable = vlv_enable_dp; |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 6025 | intel_encoder->post_disable = chv_post_disable_dp; |
Ville Syrjälä | d6db995 | 2015-07-08 23:45:49 +0300 | [diff] [blame] | 6026 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 6027 | } else if (IS_VALLEYVIEW(dev)) { |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 6028 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 6029 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
| 6030 | intel_encoder->enable = vlv_enable_dp; |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 6031 | intel_encoder->post_disable = vlv_post_disable_dp; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 6032 | } else { |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 6033 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
| 6034 | intel_encoder->enable = g4x_enable_dp; |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 6035 | if (INTEL_INFO(dev)->gen >= 5) |
| 6036 | intel_encoder->post_disable = ilk_post_disable_dp; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 6037 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 6038 | |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 6039 | intel_dig_port->port = port; |
Takashi Iwai | 0bdf5a0 | 2015-11-30 18:19:39 +0100 | [diff] [blame] | 6040 | dev_priv->dig_port_map[port] = intel_encoder; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 6041 | intel_dig_port->dp.output_reg = output_reg; |
Ville Syrjälä | ccb1a83 | 2015-12-08 19:59:38 +0200 | [diff] [blame] | 6042 | intel_dig_port->max_lanes = 4; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 6043 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 6044 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
Ville Syrjälä | 882ec38 | 2014-04-28 14:07:43 +0300 | [diff] [blame] | 6045 | if (IS_CHERRYVIEW(dev)) { |
| 6046 | if (port == PORT_D) |
| 6047 | intel_encoder->crtc_mask = 1 << 2; |
| 6048 | else |
| 6049 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
| 6050 | } else { |
| 6051 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
| 6052 | } |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 6053 | intel_encoder->cloneable = 0; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 6054 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 6055 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 6056 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 6057 | |
Sudip Mukherjee | 11aee0f | 2015-10-08 19:27:59 +0530 | [diff] [blame] | 6058 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
| 6059 | goto err_init_connector; |
| 6060 | |
| 6061 | return; |
| 6062 | |
| 6063 | err_init_connector: |
| 6064 | drm_encoder_cleanup(encoder); |
Sudip Mukherjee | 893da0c | 2015-10-08 19:28:00 +0530 | [diff] [blame] | 6065 | err_encoder_init: |
Sudip Mukherjee | 11aee0f | 2015-10-08 19:27:59 +0530 | [diff] [blame] | 6066 | kfree(intel_connector); |
| 6067 | err_connector_alloc: |
| 6068 | kfree(intel_dig_port); |
| 6069 | |
| 6070 | return; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 6071 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 6072 | |
| 6073 | void intel_dp_mst_suspend(struct drm_device *dev) |
| 6074 | { |
| 6075 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6076 | int i; |
| 6077 | |
| 6078 | /* disable MST */ |
| 6079 | for (i = 0; i < I915_MAX_PORTS; i++) { |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 6080 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 6081 | if (!intel_dig_port) |
| 6082 | continue; |
| 6083 | |
| 6084 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
| 6085 | if (!intel_dig_port->dp.can_mst) |
| 6086 | continue; |
| 6087 | if (intel_dig_port->dp.is_mst) |
| 6088 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
| 6089 | } |
| 6090 | } |
| 6091 | } |
| 6092 | |
| 6093 | void intel_dp_mst_resume(struct drm_device *dev) |
| 6094 | { |
| 6095 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6096 | int i; |
| 6097 | |
| 6098 | for (i = 0; i < I915_MAX_PORTS; i++) { |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 6099 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 6100 | if (!intel_dig_port) |
| 6101 | continue; |
| 6102 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
| 6103 | int ret; |
| 6104 | |
| 6105 | if (!intel_dig_port->dp.can_mst) |
| 6106 | continue; |
| 6107 | |
| 6108 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
| 6109 | if (ret != 0) { |
| 6110 | intel_dp_check_mst_status(&intel_dig_port->dp); |
| 6111 | } |
| 6112 | } |
| 6113 | } |
| 6114 | } |