Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2009-2010 |
| 3 | * Nokia Siemens Networks, michael.lawnick.ext@nsn.com |
| 4 | * |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 5 | * Portions Copyright (C) 2010, 2011 Cavium Networks, Inc. |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 6 | * |
| 7 | * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors. |
| 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public |
| 10 | * License version 2. This program is licensed "as is" without any |
| 11 | * warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/interrupt.h> |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 16 | #include <linux/kernel.h> |
| 17 | #include <linux/module.h> |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 18 | #include <linux/of_i2c.h> |
| 19 | #include <linux/delay.h> |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 20 | #include <linux/sched.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 21 | #include <linux/slab.h> |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 22 | #include <linux/init.h> |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 23 | #include <linux/i2c.h> |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 24 | #include <linux/io.h> |
| 25 | #include <linux/of.h> |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 26 | |
| 27 | #include <asm/octeon/octeon.h> |
| 28 | |
| 29 | #define DRV_NAME "i2c-octeon" |
| 30 | |
| 31 | /* The previous out-of-tree version was implicitly version 1.0. */ |
| 32 | #define DRV_VERSION "2.0" |
| 33 | |
| 34 | /* register offsets */ |
| 35 | #define SW_TWSI 0x00 |
| 36 | #define TWSI_INT 0x10 |
| 37 | |
| 38 | /* Controller command patterns */ |
| 39 | #define SW_TWSI_V 0x8000000000000000ull |
| 40 | #define SW_TWSI_EOP_TWSI_DATA 0x0C00000100000000ull |
| 41 | #define SW_TWSI_EOP_TWSI_CTL 0x0C00000200000000ull |
| 42 | #define SW_TWSI_EOP_TWSI_CLKCTL 0x0C00000300000000ull |
| 43 | #define SW_TWSI_EOP_TWSI_STAT 0x0C00000300000000ull |
| 44 | #define SW_TWSI_EOP_TWSI_RST 0x0C00000700000000ull |
| 45 | #define SW_TWSI_OP_TWSI_CLK 0x0800000000000000ull |
| 46 | #define SW_TWSI_R 0x0100000000000000ull |
| 47 | |
| 48 | /* Controller command and status bits */ |
| 49 | #define TWSI_CTL_CE 0x80 |
| 50 | #define TWSI_CTL_ENAB 0x40 |
| 51 | #define TWSI_CTL_STA 0x20 |
| 52 | #define TWSI_CTL_STP 0x10 |
| 53 | #define TWSI_CTL_IFLG 0x08 |
| 54 | #define TWSI_CTL_AAK 0x04 |
| 55 | |
| 56 | /* Some status values */ |
| 57 | #define STAT_START 0x08 |
| 58 | #define STAT_RSTART 0x10 |
| 59 | #define STAT_TXADDR_ACK 0x18 |
| 60 | #define STAT_TXDATA_ACK 0x28 |
| 61 | #define STAT_RXADDR_ACK 0x40 |
| 62 | #define STAT_RXDATA_ACK 0x50 |
| 63 | #define STAT_IDLE 0xF8 |
| 64 | |
| 65 | struct octeon_i2c { |
| 66 | wait_queue_head_t queue; |
| 67 | struct i2c_adapter adap; |
| 68 | int irq; |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 69 | u32 twsi_freq; |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 70 | int sys_freq; |
| 71 | resource_size_t twsi_phys; |
| 72 | void __iomem *twsi_base; |
| 73 | resource_size_t regsize; |
| 74 | struct device *dev; |
| 75 | }; |
| 76 | |
| 77 | /** |
| 78 | * octeon_i2c_write_sw - write an I2C core register. |
| 79 | * @i2c: The struct octeon_i2c. |
| 80 | * @eop_reg: Register selector. |
| 81 | * @data: Value to be written. |
| 82 | * |
| 83 | * The I2C core registers are accessed indirectly via the SW_TWSI CSR. |
| 84 | */ |
| 85 | static void octeon_i2c_write_sw(struct octeon_i2c *i2c, |
| 86 | u64 eop_reg, |
| 87 | u8 data) |
| 88 | { |
| 89 | u64 tmp; |
| 90 | |
| 91 | __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI); |
| 92 | do { |
| 93 | tmp = __raw_readq(i2c->twsi_base + SW_TWSI); |
| 94 | } while ((tmp & SW_TWSI_V) != 0); |
| 95 | } |
| 96 | |
| 97 | /** |
| 98 | * octeon_i2c_read_sw - write an I2C core register. |
| 99 | * @i2c: The struct octeon_i2c. |
| 100 | * @eop_reg: Register selector. |
| 101 | * |
| 102 | * Returns the data. |
| 103 | * |
| 104 | * The I2C core registers are accessed indirectly via the SW_TWSI CSR. |
| 105 | */ |
| 106 | static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg) |
| 107 | { |
| 108 | u64 tmp; |
| 109 | |
| 110 | __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI); |
| 111 | do { |
| 112 | tmp = __raw_readq(i2c->twsi_base + SW_TWSI); |
| 113 | } while ((tmp & SW_TWSI_V) != 0); |
| 114 | |
| 115 | return tmp & 0xFF; |
| 116 | } |
| 117 | |
| 118 | /** |
| 119 | * octeon_i2c_write_int - write the TWSI_INT register |
| 120 | * @i2c: The struct octeon_i2c. |
| 121 | * @data: Value to be written. |
| 122 | */ |
| 123 | static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) |
| 124 | { |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 125 | __raw_writeq(data, i2c->twsi_base + TWSI_INT); |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 126 | __raw_readq(i2c->twsi_base + TWSI_INT); |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | /** |
| 130 | * octeon_i2c_int_enable - enable the TS interrupt. |
| 131 | * @i2c: The struct octeon_i2c. |
| 132 | * |
| 133 | * The interrupt will be asserted when there is non-STAT_IDLE state in |
| 134 | * the SW_TWSI_EOP_TWSI_STAT register. |
| 135 | */ |
| 136 | static void octeon_i2c_int_enable(struct octeon_i2c *i2c) |
| 137 | { |
| 138 | octeon_i2c_write_int(i2c, 0x40); |
| 139 | } |
| 140 | |
| 141 | /** |
| 142 | * octeon_i2c_int_disable - disable the TS interrupt. |
| 143 | * @i2c: The struct octeon_i2c. |
| 144 | */ |
| 145 | static void octeon_i2c_int_disable(struct octeon_i2c *i2c) |
| 146 | { |
| 147 | octeon_i2c_write_int(i2c, 0); |
| 148 | } |
| 149 | |
| 150 | /** |
| 151 | * octeon_i2c_unblock - unblock the bus. |
| 152 | * @i2c: The struct octeon_i2c. |
| 153 | * |
| 154 | * If there was a reset while a device was driving 0 to bus, |
| 155 | * bus is blocked. We toggle it free manually by some clock |
| 156 | * cycles and send a stop. |
| 157 | */ |
| 158 | static void octeon_i2c_unblock(struct octeon_i2c *i2c) |
| 159 | { |
| 160 | int i; |
| 161 | |
| 162 | dev_dbg(i2c->dev, "%s\n", __func__); |
| 163 | for (i = 0; i < 9; i++) { |
| 164 | octeon_i2c_write_int(i2c, 0x0); |
| 165 | udelay(5); |
| 166 | octeon_i2c_write_int(i2c, 0x200); |
| 167 | udelay(5); |
| 168 | } |
| 169 | octeon_i2c_write_int(i2c, 0x300); |
| 170 | udelay(5); |
| 171 | octeon_i2c_write_int(i2c, 0x100); |
| 172 | udelay(5); |
| 173 | octeon_i2c_write_int(i2c, 0x0); |
| 174 | } |
| 175 | |
| 176 | /** |
| 177 | * octeon_i2c_isr - the interrupt service routine. |
| 178 | * @int: The irq, unused. |
| 179 | * @dev_id: Our struct octeon_i2c. |
| 180 | */ |
| 181 | static irqreturn_t octeon_i2c_isr(int irq, void *dev_id) |
| 182 | { |
| 183 | struct octeon_i2c *i2c = dev_id; |
| 184 | |
| 185 | octeon_i2c_int_disable(i2c); |
| 186 | wake_up_interruptible(&i2c->queue); |
| 187 | |
| 188 | return IRQ_HANDLED; |
| 189 | } |
| 190 | |
| 191 | |
| 192 | static int octeon_i2c_test_iflg(struct octeon_i2c *i2c) |
| 193 | { |
| 194 | return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0; |
| 195 | } |
| 196 | |
| 197 | /** |
| 198 | * octeon_i2c_wait - wait for the IFLG to be set. |
| 199 | * @i2c: The struct octeon_i2c. |
| 200 | * |
| 201 | * Returns 0 on success, otherwise a negative errno. |
| 202 | */ |
| 203 | static int octeon_i2c_wait(struct octeon_i2c *i2c) |
| 204 | { |
| 205 | int result; |
| 206 | |
| 207 | octeon_i2c_int_enable(i2c); |
| 208 | |
| 209 | result = wait_event_interruptible_timeout(i2c->queue, |
| 210 | octeon_i2c_test_iflg(i2c), |
| 211 | i2c->adap.timeout); |
| 212 | |
| 213 | octeon_i2c_int_disable(i2c); |
| 214 | |
| 215 | if (result < 0) { |
| 216 | dev_dbg(i2c->dev, "%s: wait interrupted\n", __func__); |
| 217 | return result; |
| 218 | } else if (result == 0) { |
| 219 | dev_dbg(i2c->dev, "%s: timeout\n", __func__); |
Bernhard Walle | cc33e54 | 2010-09-27 12:55:16 +0200 | [diff] [blame] | 220 | return -ETIMEDOUT; |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 221 | } |
| 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | /** |
| 227 | * octeon_i2c_start - send START to the bus. |
| 228 | * @i2c: The struct octeon_i2c. |
| 229 | * |
| 230 | * Returns 0 on success, otherwise a negative errno. |
| 231 | */ |
| 232 | static int octeon_i2c_start(struct octeon_i2c *i2c) |
| 233 | { |
| 234 | u8 data; |
| 235 | int result; |
| 236 | |
| 237 | octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, |
| 238 | TWSI_CTL_ENAB | TWSI_CTL_STA); |
| 239 | |
| 240 | result = octeon_i2c_wait(i2c); |
| 241 | if (result) { |
| 242 | if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) { |
| 243 | /* |
| 244 | * Controller refused to send start flag May |
| 245 | * be a client is holding SDA low - let's try |
| 246 | * to free it. |
| 247 | */ |
| 248 | octeon_i2c_unblock(i2c); |
| 249 | octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, |
| 250 | TWSI_CTL_ENAB | TWSI_CTL_STA); |
| 251 | |
| 252 | result = octeon_i2c_wait(i2c); |
| 253 | } |
| 254 | if (result) |
| 255 | return result; |
| 256 | } |
| 257 | |
| 258 | data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT); |
| 259 | if ((data != STAT_START) && (data != STAT_RSTART)) { |
| 260 | dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data); |
| 261 | return -EIO; |
| 262 | } |
| 263 | |
| 264 | return 0; |
| 265 | } |
| 266 | |
| 267 | /** |
| 268 | * octeon_i2c_stop - send STOP to the bus. |
| 269 | * @i2c: The struct octeon_i2c. |
| 270 | * |
| 271 | * Returns 0 on success, otherwise a negative errno. |
| 272 | */ |
| 273 | static int octeon_i2c_stop(struct octeon_i2c *i2c) |
| 274 | { |
| 275 | u8 data; |
| 276 | |
| 277 | octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, |
| 278 | TWSI_CTL_ENAB | TWSI_CTL_STP); |
| 279 | |
| 280 | data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT); |
| 281 | |
| 282 | if (data != STAT_IDLE) { |
| 283 | dev_err(i2c->dev, "%s: bad status(0x%x)\n", __func__, data); |
| 284 | return -EIO; |
| 285 | } |
| 286 | return 0; |
| 287 | } |
| 288 | |
| 289 | /** |
| 290 | * octeon_i2c_write - send data to the bus. |
| 291 | * @i2c: The struct octeon_i2c. |
| 292 | * @target: Target address. |
| 293 | * @data: Pointer to the data to be sent. |
| 294 | * @length: Length of the data. |
| 295 | * |
| 296 | * The address is sent over the bus, then the data. |
| 297 | * |
| 298 | * Returns 0 on success, otherwise a negative errno. |
| 299 | */ |
| 300 | static int octeon_i2c_write(struct octeon_i2c *i2c, int target, |
| 301 | const u8 *data, int length) |
| 302 | { |
| 303 | int i, result; |
| 304 | u8 tmp; |
| 305 | |
| 306 | result = octeon_i2c_start(i2c); |
| 307 | if (result) |
| 308 | return result; |
| 309 | |
| 310 | octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1); |
| 311 | octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB); |
| 312 | |
| 313 | result = octeon_i2c_wait(i2c); |
| 314 | if (result) |
| 315 | return result; |
| 316 | |
| 317 | for (i = 0; i < length; i++) { |
| 318 | tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT); |
| 319 | if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) { |
| 320 | dev_err(i2c->dev, |
| 321 | "%s: bad status before write (0x%x)\n", |
| 322 | __func__, tmp); |
| 323 | return -EIO; |
| 324 | } |
| 325 | |
| 326 | octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]); |
| 327 | octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB); |
| 328 | |
| 329 | result = octeon_i2c_wait(i2c); |
| 330 | if (result) |
| 331 | return result; |
| 332 | } |
| 333 | |
| 334 | return 0; |
| 335 | } |
| 336 | |
| 337 | /** |
| 338 | * octeon_i2c_read - receive data from the bus. |
| 339 | * @i2c: The struct octeon_i2c. |
| 340 | * @target: Target address. |
| 341 | * @data: Pointer to the location to store the datae . |
| 342 | * @length: Length of the data. |
| 343 | * |
| 344 | * The address is sent over the bus, then the data is read. |
| 345 | * |
| 346 | * Returns 0 on success, otherwise a negative errno. |
| 347 | */ |
| 348 | static int octeon_i2c_read(struct octeon_i2c *i2c, int target, |
| 349 | u8 *data, int length) |
| 350 | { |
| 351 | int i, result; |
| 352 | u8 tmp; |
| 353 | |
| 354 | if (length < 1) |
| 355 | return -EINVAL; |
| 356 | |
| 357 | result = octeon_i2c_start(i2c); |
| 358 | if (result) |
| 359 | return result; |
| 360 | |
| 361 | octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target<<1) | 1); |
| 362 | octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB); |
| 363 | |
| 364 | result = octeon_i2c_wait(i2c); |
| 365 | if (result) |
| 366 | return result; |
| 367 | |
| 368 | for (i = 0; i < length; i++) { |
| 369 | tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT); |
| 370 | if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) { |
| 371 | dev_err(i2c->dev, |
| 372 | "%s: bad status before read (0x%x)\n", |
| 373 | __func__, tmp); |
| 374 | return -EIO; |
| 375 | } |
| 376 | |
| 377 | if (i+1 < length) |
| 378 | octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, |
| 379 | TWSI_CTL_ENAB | TWSI_CTL_AAK); |
| 380 | else |
| 381 | octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, |
| 382 | TWSI_CTL_ENAB); |
| 383 | |
| 384 | result = octeon_i2c_wait(i2c); |
| 385 | if (result) |
| 386 | return result; |
| 387 | |
| 388 | data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA); |
| 389 | } |
| 390 | return 0; |
| 391 | } |
| 392 | |
| 393 | /** |
| 394 | * octeon_i2c_xfer - The driver's master_xfer function. |
| 395 | * @adap: Pointer to the i2c_adapter structure. |
| 396 | * @msgs: Pointer to the messages to be processed. |
| 397 | * @num: Length of the MSGS array. |
| 398 | * |
| 399 | * Returns the number of messages processed, or a negative errno on |
| 400 | * failure. |
| 401 | */ |
| 402 | static int octeon_i2c_xfer(struct i2c_adapter *adap, |
| 403 | struct i2c_msg *msgs, |
| 404 | int num) |
| 405 | { |
| 406 | struct i2c_msg *pmsg; |
| 407 | int i; |
| 408 | int ret = 0; |
| 409 | struct octeon_i2c *i2c = i2c_get_adapdata(adap); |
| 410 | |
| 411 | for (i = 0; ret == 0 && i < num; i++) { |
| 412 | pmsg = &msgs[i]; |
| 413 | dev_dbg(i2c->dev, |
| 414 | "Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n", |
| 415 | pmsg->flags & I2C_M_RD ? "read" : "write", |
| 416 | pmsg->len, pmsg->addr, i + 1, num); |
| 417 | if (pmsg->flags & I2C_M_RD) |
| 418 | ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf, |
| 419 | pmsg->len); |
| 420 | else |
| 421 | ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf, |
| 422 | pmsg->len); |
| 423 | } |
| 424 | octeon_i2c_stop(i2c); |
| 425 | |
| 426 | return (ret != 0) ? ret : num; |
| 427 | } |
| 428 | |
| 429 | static u32 octeon_i2c_functionality(struct i2c_adapter *adap) |
| 430 | { |
| 431 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
| 432 | } |
| 433 | |
| 434 | static const struct i2c_algorithm octeon_i2c_algo = { |
| 435 | .master_xfer = octeon_i2c_xfer, |
| 436 | .functionality = octeon_i2c_functionality, |
| 437 | }; |
| 438 | |
| 439 | static struct i2c_adapter octeon_i2c_ops = { |
| 440 | .owner = THIS_MODULE, |
| 441 | .name = "OCTEON adapter", |
| 442 | .algo = &octeon_i2c_algo, |
| 443 | .timeout = 2, |
| 444 | }; |
| 445 | |
| 446 | /** |
| 447 | * octeon_i2c_setclock - Calculate and set clock divisors. |
| 448 | */ |
David Daney | 20f1216 | 2010-03-08 11:04:21 -0800 | [diff] [blame] | 449 | static int __devinit octeon_i2c_setclock(struct octeon_i2c *i2c) |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 450 | { |
| 451 | int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff; |
| 452 | int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000; |
| 453 | |
| 454 | for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) { |
| 455 | /* |
| 456 | * An mdiv value of less than 2 seems to not work well |
| 457 | * with ds1337 RTCs, so we constrain it to larger |
| 458 | * values. |
| 459 | */ |
| 460 | for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) { |
| 461 | /* |
| 462 | * For given ndiv and mdiv values check the |
| 463 | * two closest thp values. |
| 464 | */ |
| 465 | tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10; |
| 466 | tclk *= (1 << ndiv_idx); |
| 467 | thp_base = (i2c->sys_freq / (tclk * 2)) - 1; |
| 468 | for (inc = 0; inc <= 1; inc++) { |
| 469 | thp_idx = thp_base + inc; |
| 470 | if (thp_idx < 5 || thp_idx > 0xff) |
| 471 | continue; |
| 472 | |
| 473 | foscl = i2c->sys_freq / (2 * (thp_idx + 1)); |
| 474 | foscl = foscl / (1 << ndiv_idx); |
| 475 | foscl = foscl / (mdiv_idx + 1) / 10; |
| 476 | diff = abs(foscl - i2c->twsi_freq); |
| 477 | if (diff < delta_hz) { |
| 478 | delta_hz = diff; |
| 479 | thp = thp_idx; |
| 480 | mdiv = mdiv_idx; |
| 481 | ndiv = ndiv_idx; |
| 482 | } |
| 483 | } |
| 484 | } |
| 485 | } |
| 486 | octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp); |
| 487 | octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv); |
| 488 | |
| 489 | return 0; |
| 490 | } |
| 491 | |
David Daney | 20f1216 | 2010-03-08 11:04:21 -0800 | [diff] [blame] | 492 | static int __devinit octeon_i2c_initlowlevel(struct octeon_i2c *i2c) |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 493 | { |
| 494 | u8 status; |
| 495 | int tries; |
| 496 | |
| 497 | /* disable high level controller, enable bus access */ |
| 498 | octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB); |
| 499 | |
| 500 | /* reset controller */ |
| 501 | octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0); |
| 502 | |
| 503 | for (tries = 10; tries; tries--) { |
| 504 | udelay(1); |
| 505 | status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT); |
| 506 | if (status == STAT_IDLE) |
| 507 | return 0; |
| 508 | } |
| 509 | dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status); |
| 510 | return -EIO; |
| 511 | } |
| 512 | |
| 513 | static int __devinit octeon_i2c_probe(struct platform_device *pdev) |
| 514 | { |
| 515 | int irq, result = 0; |
| 516 | struct octeon_i2c *i2c; |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 517 | struct resource *res_mem; |
| 518 | |
| 519 | /* All adaptors have an irq. */ |
| 520 | irq = platform_get_irq(pdev, 0); |
| 521 | if (irq < 0) |
| 522 | return irq; |
| 523 | |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 524 | i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 525 | if (!i2c) { |
| 526 | dev_err(&pdev->dev, "kzalloc failed\n"); |
| 527 | result = -ENOMEM; |
| 528 | goto out; |
| 529 | } |
| 530 | i2c->dev = &pdev->dev; |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 531 | |
| 532 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 533 | |
| 534 | if (res_mem == NULL) { |
| 535 | dev_err(i2c->dev, "found no memory resource\n"); |
| 536 | result = -ENXIO; |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 537 | goto out; |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 538 | } |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 539 | i2c->twsi_phys = res_mem->start; |
| 540 | i2c->regsize = resource_size(res_mem); |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 541 | |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 542 | /* |
| 543 | * "clock-rate" is a legacy binding, the official binding is |
| 544 | * "clock-frequency". Try the official one first and then |
| 545 | * fall back if it doesn't exist. |
| 546 | */ |
| 547 | if (of_property_read_u32(pdev->dev.of_node, |
| 548 | "clock-frequency", &i2c->twsi_freq) && |
| 549 | of_property_read_u32(pdev->dev.of_node, |
| 550 | "clock-rate", &i2c->twsi_freq)) { |
| 551 | dev_err(i2c->dev, |
| 552 | "no I2C 'clock-rate' or 'clock-frequency' property\n"); |
| 553 | result = -ENXIO; |
| 554 | goto out; |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 555 | } |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 556 | |
| 557 | i2c->sys_freq = octeon_get_io_clock_rate(); |
| 558 | |
| 559 | if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize, |
| 560 | res_mem->name)) { |
| 561 | dev_err(i2c->dev, "request_mem_region failed\n"); |
| 562 | goto out; |
| 563 | } |
| 564 | i2c->twsi_base = devm_ioremap(&pdev->dev, i2c->twsi_phys, i2c->regsize); |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 565 | |
| 566 | init_waitqueue_head(&i2c->queue); |
| 567 | |
| 568 | i2c->irq = irq; |
| 569 | |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 570 | result = devm_request_irq(&pdev->dev, i2c->irq, |
| 571 | octeon_i2c_isr, 0, DRV_NAME, i2c); |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 572 | if (result < 0) { |
| 573 | dev_err(i2c->dev, "failed to attach interrupt\n"); |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 574 | goto out; |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 575 | } |
| 576 | |
| 577 | result = octeon_i2c_initlowlevel(i2c); |
| 578 | if (result) { |
| 579 | dev_err(i2c->dev, "init low level failed\n"); |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 580 | goto out; |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 581 | } |
| 582 | |
| 583 | result = octeon_i2c_setclock(i2c); |
| 584 | if (result) { |
| 585 | dev_err(i2c->dev, "clock init failed\n"); |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 586 | goto out; |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 587 | } |
| 588 | |
| 589 | i2c->adap = octeon_i2c_ops; |
| 590 | i2c->adap.dev.parent = &pdev->dev; |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 591 | i2c->adap.dev.of_node = pdev->dev.of_node; |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 592 | i2c_set_adapdata(&i2c->adap, i2c); |
| 593 | platform_set_drvdata(pdev, i2c); |
| 594 | |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 595 | result = i2c_add_adapter(&i2c->adap); |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 596 | if (result < 0) { |
| 597 | dev_err(i2c->dev, "failed to add adapter\n"); |
| 598 | goto fail_add; |
| 599 | } |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 600 | dev_info(i2c->dev, "version %s\n", DRV_VERSION); |
| 601 | |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 602 | of_i2c_register_devices(&i2c->adap); |
| 603 | |
| 604 | return 0; |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 605 | |
| 606 | fail_add: |
| 607 | platform_set_drvdata(pdev, NULL); |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 608 | out: |
| 609 | return result; |
| 610 | }; |
| 611 | |
| 612 | static int __devexit octeon_i2c_remove(struct platform_device *pdev) |
| 613 | { |
| 614 | struct octeon_i2c *i2c = platform_get_drvdata(pdev); |
| 615 | |
| 616 | i2c_del_adapter(&i2c->adap); |
| 617 | platform_set_drvdata(pdev, NULL); |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 618 | return 0; |
| 619 | }; |
| 620 | |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 621 | static struct of_device_id octeon_i2c_match[] = { |
| 622 | { |
| 623 | .compatible = "cavium,octeon-3860-twsi", |
| 624 | }, |
| 625 | {}, |
| 626 | }; |
| 627 | MODULE_DEVICE_TABLE(of, octeon_i2c_match); |
| 628 | |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 629 | static struct platform_driver octeon_i2c_driver = { |
| 630 | .probe = octeon_i2c_probe, |
| 631 | .remove = __devexit_p(octeon_i2c_remove), |
| 632 | .driver = { |
| 633 | .owner = THIS_MODULE, |
| 634 | .name = DRV_NAME, |
David Daney | f353a21 | 2012-07-05 18:12:39 +0200 | [diff] [blame] | 635 | .of_match_table = octeon_i2c_match, |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 636 | }, |
| 637 | }; |
| 638 | |
Axel Lin | a3664b5 | 2012-01-12 20:32:04 +0100 | [diff] [blame] | 639 | module_platform_driver(octeon_i2c_driver); |
Rade Bozic | 85660f4 | 2010-01-28 12:47:07 -0800 | [diff] [blame] | 640 | |
| 641 | MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>"); |
| 642 | MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors"); |
| 643 | MODULE_LICENSE("GPL"); |
| 644 | MODULE_VERSION(DRV_VERSION); |