blob: 0056770e83ada176fc091dba50be956dcaf7841f [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* $Id: io.h,v 1.47 2001/12/13 10:36:02 davem Exp $ */
2#ifndef __SPARC64_IO_H
3#define __SPARC64_IO_H
4
5#include <linux/kernel.h>
6#include <linux/compiler.h>
7#include <linux/types.h>
8
9#include <asm/page.h> /* IO address mapping routines need this */
10#include <asm/system.h>
11#include <asm/asi.h>
12
13/* PC crapola... */
14#define __SLOW_DOWN_IO do { } while (0)
15#define SLOW_DOWN_IO do { } while (0)
16
17extern unsigned long virt_to_bus_not_defined_use_pci_map(volatile void *addr);
18#define virt_to_bus virt_to_bus_not_defined_use_pci_map
19extern unsigned long bus_to_virt_not_defined_use_pci_map(volatile void *addr);
20#define bus_to_virt bus_to_virt_not_defined_use_pci_map
21
22/* BIO layer definitions. */
23extern unsigned long kern_base, kern_size;
24#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
25#define BIO_VMERGE_BOUNDARY 8192
26
27/* Different PCI controllers we support have their PCI MEM space
28 * mapped to an either 2GB (Psycho) or 4GB (Sabre) aligned area,
29 * so need to chop off the top 33 or 32 bits.
30 */
31extern unsigned long pci_memspace_mask;
32
33#define bus_dvma_to_mem(__vaddr) ((__vaddr) & pci_memspace_mask)
34
35static __inline__ u8 _inb(unsigned long addr)
36{
37 u8 ret;
38
39 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
40 : "=r" (ret)
41 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
42
43 return ret;
44}
45
46static __inline__ u16 _inw(unsigned long addr)
47{
48 u16 ret;
49
50 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
51 : "=r" (ret)
52 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
53
54 return ret;
55}
56
57static __inline__ u32 _inl(unsigned long addr)
58{
59 u32 ret;
60
61 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
62 : "=r" (ret)
63 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
64
65 return ret;
66}
67
68static __inline__ void _outb(u8 b, unsigned long addr)
69{
70 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
71 : /* no outputs */
72 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
73}
74
75static __inline__ void _outw(u16 w, unsigned long addr)
76{
77 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
78 : /* no outputs */
79 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
80}
81
82static __inline__ void _outl(u32 l, unsigned long addr)
83{
84 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
85 : /* no outputs */
86 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
87}
88
89#define inb(__addr) (_inb((unsigned long)(__addr)))
90#define inw(__addr) (_inw((unsigned long)(__addr)))
91#define inl(__addr) (_inl((unsigned long)(__addr)))
92#define outb(__b, __addr) (_outb((u8)(__b), (unsigned long)(__addr)))
93#define outw(__w, __addr) (_outw((u16)(__w), (unsigned long)(__addr)))
94#define outl(__l, __addr) (_outl((u32)(__l), (unsigned long)(__addr)))
95
96#define inb_p(__addr) inb(__addr)
97#define outb_p(__b, __addr) outb(__b, __addr)
98#define inw_p(__addr) inw(__addr)
99#define outw_p(__w, __addr) outw(__w, __addr)
100#define inl_p(__addr) inl(__addr)
101#define outl_p(__l, __addr) outl(__l, __addr)
102
David S. Miller8a368952005-08-31 15:01:33 -0700103extern void outsb(unsigned long, const void *, unsigned long);
104extern void outsw(unsigned long, const void *, unsigned long);
105extern void outsl(unsigned long, const void *, unsigned long);
106extern void insb(unsigned long, void *, unsigned long);
107extern void insw(unsigned long, void *, unsigned long);
108extern void insl(unsigned long, void *, unsigned long);
109
110static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
111{
112 insb((unsigned long __force)port, buf, count);
113}
114static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
115{
116 insw((unsigned long __force)port, buf, count);
117}
118
119static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
120{
121 insl((unsigned long __force)port, buf, count);
122}
123
124static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
125{
126 outsb((unsigned long __force)port, buf, count);
127}
128
129static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
130{
131 outsw((unsigned long __force)port, buf, count);
132}
133
134static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
135{
136 outsl((unsigned long __force)port, buf, count);
137}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138
139/* Memory functions, same as I/O accesses on Ultra. */
140static inline u8 _readb(const volatile void __iomem *addr)
141{ u8 ret;
142
143 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
144 : "=r" (ret)
145 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
146 return ret;
147}
148
149static inline u16 _readw(const volatile void __iomem *addr)
150{ u16 ret;
151
152 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
153 : "=r" (ret)
154 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
155
156 return ret;
157}
158
159static inline u32 _readl(const volatile void __iomem *addr)
160{ u32 ret;
161
162 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
163 : "=r" (ret)
164 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
165
166 return ret;
167}
168
169static inline u64 _readq(const volatile void __iomem *addr)
170{ u64 ret;
171
172 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
173 : "=r" (ret)
174 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
175
176 return ret;
177}
178
179static inline void _writeb(u8 b, volatile void __iomem *addr)
180{
181 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
182 : /* no outputs */
183 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
184}
185
186static inline void _writew(u16 w, volatile void __iomem *addr)
187{
188 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
189 : /* no outputs */
190 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
191}
192
193static inline void _writel(u32 l, volatile void __iomem *addr)
194{
195 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
196 : /* no outputs */
197 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
198}
199
200static inline void _writeq(u64 q, volatile void __iomem *addr)
201{
202 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
203 : /* no outputs */
204 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
205}
206
207#define readb(__addr) _readb(__addr)
208#define readw(__addr) _readw(__addr)
209#define readl(__addr) _readl(__addr)
210#define readq(__addr) _readq(__addr)
211#define readb_relaxed(__addr) _readb(__addr)
212#define readw_relaxed(__addr) _readw(__addr)
213#define readl_relaxed(__addr) _readl(__addr)
214#define readq_relaxed(__addr) _readq(__addr)
215#define writeb(__b, __addr) _writeb(__b, __addr)
216#define writew(__w, __addr) _writew(__w, __addr)
217#define writel(__l, __addr) _writel(__l, __addr)
218#define writeq(__q, __addr) _writeq(__q, __addr)
219
220/* Now versions without byte-swapping. */
221static __inline__ u8 _raw_readb(unsigned long addr)
222{
223 u8 ret;
224
225 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
226 : "=r" (ret)
227 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
228
229 return ret;
230}
231
232static __inline__ u16 _raw_readw(unsigned long addr)
233{
234 u16 ret;
235
236 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
237 : "=r" (ret)
238 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
239
240 return ret;
241}
242
243static __inline__ u32 _raw_readl(unsigned long addr)
244{
245 u32 ret;
246
247 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
248 : "=r" (ret)
249 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
250
251 return ret;
252}
253
254static __inline__ u64 _raw_readq(unsigned long addr)
255{
256 u64 ret;
257
258 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
259 : "=r" (ret)
260 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
261
262 return ret;
263}
264
265static __inline__ void _raw_writeb(u8 b, unsigned long addr)
266{
267 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
268 : /* no outputs */
269 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
270}
271
272static __inline__ void _raw_writew(u16 w, unsigned long addr)
273{
274 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
275 : /* no outputs */
276 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
277}
278
279static __inline__ void _raw_writel(u32 l, unsigned long addr)
280{
281 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
282 : /* no outputs */
283 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
284}
285
286static __inline__ void _raw_writeq(u64 q, unsigned long addr)
287{
288 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
289 : /* no outputs */
290 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
291}
292
293#define __raw_readb(__addr) (_raw_readb((unsigned long)(__addr)))
294#define __raw_readw(__addr) (_raw_readw((unsigned long)(__addr)))
295#define __raw_readl(__addr) (_raw_readl((unsigned long)(__addr)))
296#define __raw_readq(__addr) (_raw_readq((unsigned long)(__addr)))
297#define __raw_writeb(__b, __addr) (_raw_writeb((u8)(__b), (unsigned long)(__addr)))
298#define __raw_writew(__w, __addr) (_raw_writew((u16)(__w), (unsigned long)(__addr)))
299#define __raw_writel(__l, __addr) (_raw_writel((u32)(__l), (unsigned long)(__addr)))
300#define __raw_writeq(__q, __addr) (_raw_writeq((u64)(__q), (unsigned long)(__addr)))
301
302/* Valid I/O Space regions are anywhere, because each PCI bus supported
303 * can live in an arbitrary area of the physical address range.
304 */
305#define IO_SPACE_LIMIT 0xffffffffffffffffUL
306
307/* Now, SBUS variants, only difference from PCI is that we do
308 * not use little-endian ASIs.
309 */
310static inline u8 _sbus_readb(const volatile void __iomem *addr)
311{
312 u8 ret;
313
314 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
315 : "=r" (ret)
316 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
317
318 return ret;
319}
320
321static inline u16 _sbus_readw(const volatile void __iomem *addr)
322{
323 u16 ret;
324
325 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
326 : "=r" (ret)
327 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
328
329 return ret;
330}
331
332static inline u32 _sbus_readl(const volatile void __iomem *addr)
333{
334 u32 ret;
335
336 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
337 : "=r" (ret)
338 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
339
340 return ret;
341}
342
343static inline u64 _sbus_readq(const volatile void __iomem *addr)
344{
345 u64 ret;
346
347 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
348 : "=r" (ret)
349 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
350
351 return ret;
352}
353
354static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
355{
356 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
357 : /* no outputs */
358 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
359}
360
361static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
362{
363 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
364 : /* no outputs */
365 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
366}
367
368static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
369{
370 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
371 : /* no outputs */
372 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
373}
374
375static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
376{
377 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
378 : /* no outputs */
379 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
380}
381
382#define sbus_readb(__addr) _sbus_readb(__addr)
383#define sbus_readw(__addr) _sbus_readw(__addr)
384#define sbus_readl(__addr) _sbus_readl(__addr)
385#define sbus_readq(__addr) _sbus_readq(__addr)
386#define sbus_writeb(__b, __addr) _sbus_writeb(__b, __addr)
387#define sbus_writew(__w, __addr) _sbus_writew(__w, __addr)
388#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr)
389#define sbus_writeq(__l, __addr) _sbus_writeq(__l, __addr)
390
391static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
392{
393 while(n--) {
394 sbus_writeb(c, dst);
395 dst++;
396 }
397}
398
399#define sbus_memset_io(d,c,sz) _sbus_memset_io(d,c,sz)
400
401static inline void
402_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
403{
404 volatile void __iomem *d = dst;
405
406 while (n--) {
407 writeb(c, d);
408 d++;
409 }
410}
411
412#define memset_io(d,c,sz) _memset_io(d,c,sz)
413
414static inline void
415_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
416{
417 char *d = dst;
418
419 while (n--) {
420 char tmp = readb(src);
421 *d++ = tmp;
422 src++;
423 }
424}
425
426#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz)
427
428static inline void
429_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
430{
431 const char *s = src;
432 volatile void __iomem *d = dst;
433
434 while (n--) {
435 char tmp = *s++;
436 writeb(tmp, d);
437 d++;
438 }
439}
440
441#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
442
443static inline int check_signature(void __iomem *io_addr,
444 const unsigned char *signature,
445 int length)
446{
447 int retval = 0;
448 do {
449 if (readb(io_addr) != *signature++)
450 goto out;
451 io_addr++;
452 } while (--length);
453 retval = 1;
454out:
455 return retval;
456}
457
458#define mmiowb()
459
460#ifdef __KERNEL__
461
462/* On sparc64 we have the whole physical IO address space accessible
463 * using physically addressed loads and stores, so this does nothing.
464 */
465static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
466{
467 return (void __iomem *)offset;
468}
469
470#define ioremap_nocache(X,Y) ioremap((X),(Y))
471
472static inline void iounmap(volatile void __iomem *addr)
473{
474}
475
476#define ioread8(X) readb(X)
477#define ioread16(X) readw(X)
478#define ioread32(X) readl(X)
479#define iowrite8(val,X) writeb(val,X)
480#define iowrite16(val,X) writew(val,X)
481#define iowrite32(val,X) writel(val,X)
482
483/* Create a virtual mapping cookie for an IO port range */
484extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
485extern void ioport_unmap(void __iomem *);
486
487/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
488struct pci_dev;
489extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
490extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
491
492/* Similarly for SBUS. */
493#define sbus_ioremap(__res, __offset, __size, __name) \
494({ unsigned long __ret; \
495 __ret = (__res)->start + (((__res)->flags & 0x1ffUL) << 32UL); \
496 __ret += (unsigned long) (__offset); \
497 if (! request_region((__ret), (__size), (__name))) \
498 __ret = 0UL; \
499 (void __iomem *) __ret; \
500})
501
502#define sbus_iounmap(__addr, __size) \
503 release_region((unsigned long)(__addr), (__size))
504
505/* Nothing to do */
506
507#define dma_cache_inv(_start,_size) do { } while (0)
508#define dma_cache_wback(_start,_size) do { } while (0)
509#define dma_cache_wback_inv(_start,_size) do { } while (0)
510
511/*
512 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
513 * access
514 */
515#define xlate_dev_mem_ptr(p) __va(p)
516
517/*
518 * Convert a virtual cached pointer to an uncached pointer
519 */
520#define xlate_dev_kmem_ptr(p) p
521
522#endif
523
524#endif /* !(__SPARC64_IO_H) */