Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. |
| 3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) |
| 4 | * |
| 5 | * This version of the driver is specific to the FADS implementation, |
| 6 | * since the board contains control registers external to the processor |
| 7 | * for the control of the LevelOne LXT970 transceiver. The MPC860T manual |
| 8 | * describes connections using the internal parallel port I/O, which |
| 9 | * is basically all of Port D. |
| 10 | * |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 11 | * Right now, I am very wasteful with the buffers. I allocate memory |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | * pages and then divide them into 2K frame buffers. This way I know I |
| 13 | * have buffers large enough to hold one frame within one buffer descriptor. |
| 14 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which |
| 15 | * will be much more memory efficient and will easily handle lots of |
| 16 | * small packets. |
| 17 | * |
| 18 | * Much better multiple PHY support by Magnus Damm. |
| 19 | * Copyright (c) 2000 Ericsson Radio Systems AB. |
| 20 | * |
Greg Ungerer | 562d2f8 | 2005-11-07 14:09:50 +1000 | [diff] [blame] | 21 | * Support for FEC controller of ColdFire processors. |
| 22 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 23 | * |
| 24 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) |
Philippe De Muyter | 677177c | 2006-06-27 13:05:33 +1000 | [diff] [blame] | 25 | * Copyright (c) 2004-2006 Macq Electronique SA. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | */ |
| 27 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | #include <linux/module.h> |
| 29 | #include <linux/kernel.h> |
| 30 | #include <linux/string.h> |
| 31 | #include <linux/ptrace.h> |
| 32 | #include <linux/errno.h> |
| 33 | #include <linux/ioport.h> |
| 34 | #include <linux/slab.h> |
| 35 | #include <linux/interrupt.h> |
| 36 | #include <linux/pci.h> |
| 37 | #include <linux/init.h> |
| 38 | #include <linux/delay.h> |
| 39 | #include <linux/netdevice.h> |
| 40 | #include <linux/etherdevice.h> |
| 41 | #include <linux/skbuff.h> |
| 42 | #include <linux/spinlock.h> |
| 43 | #include <linux/workqueue.h> |
| 44 | #include <linux/bitops.h> |
| 45 | |
| 46 | #include <asm/irq.h> |
| 47 | #include <asm/uaccess.h> |
| 48 | #include <asm/io.h> |
| 49 | #include <asm/pgtable.h> |
| 50 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 51 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \ |
Greg Ungerer | 562d2f8 | 2005-11-07 14:09:50 +1000 | [diff] [blame] | 52 | defined(CONFIG_M5272) || defined(CONFIG_M528x) || \ |
Matt Waddel | 6b26529 | 2006-06-27 13:10:56 +1000 | [diff] [blame] | 53 | defined(CONFIG_M520x) || defined(CONFIG_M532x) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | #include <asm/coldfire.h> |
| 55 | #include <asm/mcfsim.h> |
| 56 | #include "fec.h" |
| 57 | #else |
| 58 | #include <asm/8xx_immap.h> |
| 59 | #include <asm/mpc8xx.h> |
| 60 | #include "commproc.h" |
| 61 | #endif |
| 62 | |
| 63 | #if defined(CONFIG_FEC2) |
| 64 | #define FEC_MAX_PORTS 2 |
| 65 | #else |
| 66 | #define FEC_MAX_PORTS 1 |
| 67 | #endif |
| 68 | |
| 69 | /* |
| 70 | * Define the fixed address of the FEC hardware. |
| 71 | */ |
| 72 | static unsigned int fec_hw[] = { |
| 73 | #if defined(CONFIG_M5272) |
| 74 | (MCF_MBAR + 0x840), |
| 75 | #elif defined(CONFIG_M527x) |
| 76 | (MCF_MBAR + 0x1000), |
| 77 | (MCF_MBAR + 0x1800), |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 78 | #elif defined(CONFIG_M523x) || defined(CONFIG_M528x) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | (MCF_MBAR + 0x1000), |
Greg Ungerer | 562d2f8 | 2005-11-07 14:09:50 +1000 | [diff] [blame] | 80 | #elif defined(CONFIG_M520x) |
| 81 | (MCF_MBAR+0x30000), |
Matt Waddel | 6b26529 | 2006-06-27 13:10:56 +1000 | [diff] [blame] | 82 | #elif defined(CONFIG_M532x) |
| 83 | (MCF_MBAR+0xfc030000), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 84 | #else |
| 85 | &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec), |
| 86 | #endif |
| 87 | }; |
| 88 | |
| 89 | static unsigned char fec_mac_default[] = { |
| 90 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 91 | }; |
| 92 | |
| 93 | /* |
| 94 | * Some hardware gets it MAC address out of local flash memory. |
| 95 | * if this is non-zero then assume it is the address to get MAC from. |
| 96 | */ |
| 97 | #if defined(CONFIG_NETtel) |
| 98 | #define FEC_FLASHMAC 0xf0006006 |
| 99 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) |
| 100 | #define FEC_FLASHMAC 0xf0006000 |
| 101 | #elif defined (CONFIG_MTD_KeyTechnology) |
| 102 | #define FEC_FLASHMAC 0xffe04000 |
| 103 | #elif defined(CONFIG_CANCam) |
| 104 | #define FEC_FLASHMAC 0xf0020000 |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 105 | #elif defined (CONFIG_M5272C3) |
| 106 | #define FEC_FLASHMAC (0xffe04000 + 4) |
| 107 | #elif defined(CONFIG_MOD5272) |
| 108 | #define FEC_FLASHMAC 0xffc0406b |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 109 | #else |
| 110 | #define FEC_FLASHMAC 0 |
| 111 | #endif |
| 112 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 113 | /* Forward declarations of some structures to support different PHYs |
| 114 | */ |
| 115 | |
| 116 | typedef struct { |
| 117 | uint mii_data; |
| 118 | void (*funct)(uint mii_reg, struct net_device *dev); |
| 119 | } phy_cmd_t; |
| 120 | |
| 121 | typedef struct { |
| 122 | uint id; |
| 123 | char *name; |
| 124 | |
| 125 | const phy_cmd_t *config; |
| 126 | const phy_cmd_t *startup; |
| 127 | const phy_cmd_t *ack_int; |
| 128 | const phy_cmd_t *shutdown; |
| 129 | } phy_info_t; |
| 130 | |
| 131 | /* The number of Tx and Rx buffers. These are allocated from the page |
| 132 | * pool. The code may assume these are power of two, so it it best |
| 133 | * to keep them that size. |
| 134 | * We don't need to allocate pages for the transmitter. We just use |
| 135 | * the skbuffer directly. |
| 136 | */ |
| 137 | #define FEC_ENET_RX_PAGES 8 |
| 138 | #define FEC_ENET_RX_FRSIZE 2048 |
| 139 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) |
| 140 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) |
| 141 | #define FEC_ENET_TX_FRSIZE 2048 |
| 142 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) |
| 143 | #define TX_RING_SIZE 16 /* Must be power of two */ |
| 144 | #define TX_RING_MOD_MASK 15 /* for this to work */ |
| 145 | |
Greg Ungerer | 562d2f8 | 2005-11-07 14:09:50 +1000 | [diff] [blame] | 146 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
Matt Waddel | 6b26529 | 2006-06-27 13:10:56 +1000 | [diff] [blame] | 147 | #error "FEC: descriptor ring size constants too large" |
Greg Ungerer | 562d2f8 | 2005-11-07 14:09:50 +1000 | [diff] [blame] | 148 | #endif |
| 149 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | /* Interrupt events/masks. |
| 151 | */ |
| 152 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
| 153 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ |
| 154 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ |
| 155 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ |
| 156 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ |
| 157 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ |
| 158 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ |
| 159 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ |
| 160 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ |
| 161 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ |
| 162 | |
| 163 | /* The FEC stores dest/src/type, data, and checksum for receive packets. |
| 164 | */ |
| 165 | #define PKT_MAXBUF_SIZE 1518 |
| 166 | #define PKT_MINBUF_SIZE 64 |
| 167 | #define PKT_MAXBLR_SIZE 1520 |
| 168 | |
| 169 | |
| 170 | /* |
Matt Waddel | 6b26529 | 2006-06-27 13:10:56 +1000 | [diff] [blame] | 171 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 172 | * size bits. Other FEC hardware does not, so we need to take that into |
| 173 | * account when setting it. |
| 174 | */ |
Greg Ungerer | 562d2f8 | 2005-11-07 14:09:50 +1000 | [diff] [blame] | 175 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
Matt Waddel | 6b26529 | 2006-06-27 13:10:56 +1000 | [diff] [blame] | 176 | defined(CONFIG_M520x) || defined(CONFIG_M532x) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
| 178 | #else |
| 179 | #define OPT_FRAME_SIZE 0 |
| 180 | #endif |
| 181 | |
| 182 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and |
| 183 | * tx_bd_base always point to the base of the buffer descriptors. The |
| 184 | * cur_rx and cur_tx point to the currently available buffer. |
| 185 | * The dirty_tx tracks the current buffer that is being sent by the |
| 186 | * controller. The cur_tx and dirty_tx are equal under both completely |
| 187 | * empty and completely full conditions. The empty/ready indicator in |
| 188 | * the buffer descriptor determines the actual condition. |
| 189 | */ |
| 190 | struct fec_enet_private { |
| 191 | /* Hardware registers of the FEC device */ |
| 192 | volatile fec_t *hwp; |
| 193 | |
| 194 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
| 195 | unsigned char *tx_bounce[TX_RING_SIZE]; |
| 196 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; |
| 197 | ushort skb_cur; |
| 198 | ushort skb_dirty; |
| 199 | |
| 200 | /* CPM dual port RAM relative addresses. |
| 201 | */ |
| 202 | cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ |
| 203 | cbd_t *tx_bd_base; |
| 204 | cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ |
| 205 | cbd_t *dirty_tx; /* The ring entries to be free()ed. */ |
| 206 | struct net_device_stats stats; |
| 207 | uint tx_full; |
| 208 | spinlock_t lock; |
| 209 | |
| 210 | uint phy_id; |
| 211 | uint phy_id_done; |
| 212 | uint phy_status; |
| 213 | uint phy_speed; |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 214 | phy_info_t const *phy; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 215 | struct work_struct phy_task; |
| 216 | |
| 217 | uint sequence_done; |
| 218 | uint mii_phy_task_queued; |
| 219 | |
| 220 | uint phy_addr; |
| 221 | |
| 222 | int index; |
| 223 | int opened; |
| 224 | int link; |
| 225 | int old_link; |
| 226 | int full_duplex; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 227 | }; |
| 228 | |
| 229 | static int fec_enet_open(struct net_device *dev); |
| 230 | static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); |
| 231 | static void fec_enet_mii(struct net_device *dev); |
| 232 | static irqreturn_t fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs); |
| 233 | static void fec_enet_tx(struct net_device *dev); |
| 234 | static void fec_enet_rx(struct net_device *dev); |
| 235 | static int fec_enet_close(struct net_device *dev); |
| 236 | static struct net_device_stats *fec_enet_get_stats(struct net_device *dev); |
| 237 | static void set_multicast_list(struct net_device *dev); |
| 238 | static void fec_restart(struct net_device *dev, int duplex); |
| 239 | static void fec_stop(struct net_device *dev); |
| 240 | static void fec_set_mac_address(struct net_device *dev); |
| 241 | |
| 242 | |
| 243 | /* MII processing. We keep this as simple as possible. Requests are |
| 244 | * placed on the list (if there is room). When the request is finished |
| 245 | * by the MII, an optional function may be called. |
| 246 | */ |
| 247 | typedef struct mii_list { |
| 248 | uint mii_regval; |
| 249 | void (*mii_func)(uint val, struct net_device *dev); |
| 250 | struct mii_list *mii_next; |
| 251 | } mii_list_t; |
| 252 | |
| 253 | #define NMII 20 |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 254 | static mii_list_t mii_cmds[NMII]; |
| 255 | static mii_list_t *mii_free; |
| 256 | static mii_list_t *mii_head; |
| 257 | static mii_list_t *mii_tail; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | |
| 259 | static int mii_queue(struct net_device *dev, int request, |
| 260 | void (*func)(uint, struct net_device *)); |
| 261 | |
| 262 | /* Make MII read/write commands for the FEC. |
| 263 | */ |
| 264 | #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) |
| 265 | #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \ |
| 266 | (VAL & 0xffff)) |
| 267 | #define mk_mii_end 0 |
| 268 | |
| 269 | /* Transmitter timeout. |
| 270 | */ |
| 271 | #define TX_TIMEOUT (2*HZ) |
| 272 | |
| 273 | /* Register definitions for the PHY. |
| 274 | */ |
| 275 | |
| 276 | #define MII_REG_CR 0 /* Control Register */ |
| 277 | #define MII_REG_SR 1 /* Status Register */ |
| 278 | #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */ |
| 279 | #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */ |
| 280 | #define MII_REG_ANAR 4 /* A-N Advertisement Register */ |
| 281 | #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */ |
| 282 | #define MII_REG_ANER 6 /* A-N Expansion Register */ |
| 283 | #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */ |
| 284 | #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */ |
| 285 | |
| 286 | /* values for phy_status */ |
| 287 | |
| 288 | #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */ |
| 289 | #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */ |
| 290 | #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */ |
| 291 | #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */ |
| 292 | #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */ |
| 293 | #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */ |
| 294 | #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */ |
| 295 | |
| 296 | #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */ |
| 297 | #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */ |
| 298 | #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */ |
| 299 | #define PHY_STAT_SPMASK 0xf000 /* mask for speed */ |
| 300 | #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */ |
| 301 | #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */ |
| 302 | #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */ |
| 303 | #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */ |
| 304 | |
| 305 | |
| 306 | static int |
| 307 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) |
| 308 | { |
| 309 | struct fec_enet_private *fep; |
| 310 | volatile fec_t *fecp; |
| 311 | volatile cbd_t *bdp; |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 312 | unsigned short status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 313 | |
| 314 | fep = netdev_priv(dev); |
| 315 | fecp = (volatile fec_t*)dev->base_addr; |
| 316 | |
| 317 | if (!fep->link) { |
| 318 | /* Link is down or autonegotiation is in progress. */ |
| 319 | return 1; |
| 320 | } |
| 321 | |
| 322 | /* Fill in a Tx ring entry */ |
| 323 | bdp = fep->cur_tx; |
| 324 | |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 325 | status = bdp->cbd_sc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 326 | #ifndef final_version |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 327 | if (status & BD_ENET_TX_READY) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 328 | /* Ooops. All transmit buffers are full. Bail out. |
| 329 | * This should not happen, since dev->tbusy should be set. |
| 330 | */ |
| 331 | printk("%s: tx queue full!.\n", dev->name); |
| 332 | return 1; |
| 333 | } |
| 334 | #endif |
| 335 | |
| 336 | /* Clear all of the status flags. |
| 337 | */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 338 | status &= ~BD_ENET_TX_STATS; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 339 | |
| 340 | /* Set buffer length and buffer pointer. |
| 341 | */ |
| 342 | bdp->cbd_bufaddr = __pa(skb->data); |
| 343 | bdp->cbd_datlen = skb->len; |
| 344 | |
| 345 | /* |
| 346 | * On some FEC implementations data must be aligned on |
| 347 | * 4-byte boundaries. Use bounce buffers to copy data |
| 348 | * and get it aligned. Ugh. |
| 349 | */ |
| 350 | if (bdp->cbd_bufaddr & 0x3) { |
| 351 | unsigned int index; |
| 352 | index = bdp - fep->tx_bd_base; |
| 353 | memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen); |
| 354 | bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]); |
| 355 | } |
| 356 | |
| 357 | /* Save skb pointer. |
| 358 | */ |
| 359 | fep->tx_skbuff[fep->skb_cur] = skb; |
| 360 | |
| 361 | fep->stats.tx_bytes += skb->len; |
| 362 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
| 363 | |
| 364 | /* Push the data cache so the CPM does not get stale memory |
| 365 | * data. |
| 366 | */ |
| 367 | flush_dcache_range((unsigned long)skb->data, |
| 368 | (unsigned long)skb->data + skb->len); |
| 369 | |
| 370 | spin_lock_irq(&fep->lock); |
| 371 | |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 372 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
| 373 | * it's the last BD of the frame, and to put the CRC on the end. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 374 | */ |
| 375 | |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 376 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 377 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 378 | bdp->cbd_sc = status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 379 | |
| 380 | dev->trans_start = jiffies; |
| 381 | |
| 382 | /* Trigger transmission start */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 383 | fecp->fec_x_des_active = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 384 | |
| 385 | /* If this was the last BD in the ring, start at the beginning again. |
| 386 | */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 387 | if (status & BD_ENET_TX_WRAP) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 388 | bdp = fep->tx_bd_base; |
| 389 | } else { |
| 390 | bdp++; |
| 391 | } |
| 392 | |
| 393 | if (bdp == fep->dirty_tx) { |
| 394 | fep->tx_full = 1; |
| 395 | netif_stop_queue(dev); |
| 396 | } |
| 397 | |
| 398 | fep->cur_tx = (cbd_t *)bdp; |
| 399 | |
| 400 | spin_unlock_irq(&fep->lock); |
| 401 | |
| 402 | return 0; |
| 403 | } |
| 404 | |
| 405 | static void |
| 406 | fec_timeout(struct net_device *dev) |
| 407 | { |
| 408 | struct fec_enet_private *fep = netdev_priv(dev); |
| 409 | |
| 410 | printk("%s: transmit timed out.\n", dev->name); |
| 411 | fep->stats.tx_errors++; |
| 412 | #ifndef final_version |
| 413 | { |
| 414 | int i; |
| 415 | cbd_t *bdp; |
| 416 | |
| 417 | printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n", |
| 418 | (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "", |
| 419 | (unsigned long)fep->dirty_tx, |
| 420 | (unsigned long)fep->cur_rx); |
| 421 | |
| 422 | bdp = fep->tx_bd_base; |
| 423 | printk(" tx: %u buffers\n", TX_RING_SIZE); |
| 424 | for (i = 0 ; i < TX_RING_SIZE; i++) { |
| 425 | printk(" %08x: %04x %04x %08x\n", |
| 426 | (uint) bdp, |
| 427 | bdp->cbd_sc, |
| 428 | bdp->cbd_datlen, |
| 429 | (int) bdp->cbd_bufaddr); |
| 430 | bdp++; |
| 431 | } |
| 432 | |
| 433 | bdp = fep->rx_bd_base; |
| 434 | printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE); |
| 435 | for (i = 0 ; i < RX_RING_SIZE; i++) { |
| 436 | printk(" %08x: %04x %04x %08x\n", |
| 437 | (uint) bdp, |
| 438 | bdp->cbd_sc, |
| 439 | bdp->cbd_datlen, |
| 440 | (int) bdp->cbd_bufaddr); |
| 441 | bdp++; |
| 442 | } |
| 443 | } |
| 444 | #endif |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 445 | fec_restart(dev, fep->full_duplex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 446 | netif_wake_queue(dev); |
| 447 | } |
| 448 | |
| 449 | /* The interrupt handler. |
| 450 | * This is called from the MPC core interrupt. |
| 451 | */ |
| 452 | static irqreturn_t |
| 453 | fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs) |
| 454 | { |
| 455 | struct net_device *dev = dev_id; |
| 456 | volatile fec_t *fecp; |
| 457 | uint int_events; |
| 458 | int handled = 0; |
| 459 | |
| 460 | fecp = (volatile fec_t*)dev->base_addr; |
| 461 | |
| 462 | /* Get the interrupt events that caused us to be here. |
| 463 | */ |
| 464 | while ((int_events = fecp->fec_ievent) != 0) { |
| 465 | fecp->fec_ievent = int_events; |
| 466 | |
| 467 | /* Handle receive event in its own function. |
| 468 | */ |
| 469 | if (int_events & FEC_ENET_RXF) { |
| 470 | handled = 1; |
| 471 | fec_enet_rx(dev); |
| 472 | } |
| 473 | |
| 474 | /* Transmit OK, or non-fatal error. Update the buffer |
| 475 | descriptors. FEC handles all errors, we just discover |
| 476 | them as part of the transmit process. |
| 477 | */ |
| 478 | if (int_events & FEC_ENET_TXF) { |
| 479 | handled = 1; |
| 480 | fec_enet_tx(dev); |
| 481 | } |
| 482 | |
| 483 | if (int_events & FEC_ENET_MII) { |
| 484 | handled = 1; |
| 485 | fec_enet_mii(dev); |
| 486 | } |
| 487 | |
| 488 | } |
| 489 | return IRQ_RETVAL(handled); |
| 490 | } |
| 491 | |
| 492 | |
| 493 | static void |
| 494 | fec_enet_tx(struct net_device *dev) |
| 495 | { |
| 496 | struct fec_enet_private *fep; |
| 497 | volatile cbd_t *bdp; |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 498 | unsigned short status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 499 | struct sk_buff *skb; |
| 500 | |
| 501 | fep = netdev_priv(dev); |
| 502 | spin_lock(&fep->lock); |
| 503 | bdp = fep->dirty_tx; |
| 504 | |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 505 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 506 | if (bdp == fep->cur_tx && fep->tx_full == 0) break; |
| 507 | |
| 508 | skb = fep->tx_skbuff[fep->skb_dirty]; |
| 509 | /* Check for errors. */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 510 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 511 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
| 512 | BD_ENET_TX_CSL)) { |
| 513 | fep->stats.tx_errors++; |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 514 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 515 | fep->stats.tx_heartbeat_errors++; |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 516 | if (status & BD_ENET_TX_LC) /* Late collision */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 517 | fep->stats.tx_window_errors++; |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 518 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 519 | fep->stats.tx_aborted_errors++; |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 520 | if (status & BD_ENET_TX_UN) /* Underrun */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 521 | fep->stats.tx_fifo_errors++; |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 522 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 523 | fep->stats.tx_carrier_errors++; |
| 524 | } else { |
| 525 | fep->stats.tx_packets++; |
| 526 | } |
| 527 | |
| 528 | #ifndef final_version |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 529 | if (status & BD_ENET_TX_READY) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 530 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
| 531 | #endif |
| 532 | /* Deferred means some collisions occurred during transmit, |
| 533 | * but we eventually sent the packet OK. |
| 534 | */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 535 | if (status & BD_ENET_TX_DEF) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 536 | fep->stats.collisions++; |
| 537 | |
| 538 | /* Free the sk buffer associated with this last transmit. |
| 539 | */ |
| 540 | dev_kfree_skb_any(skb); |
| 541 | fep->tx_skbuff[fep->skb_dirty] = NULL; |
| 542 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; |
| 543 | |
| 544 | /* Update pointer to next buffer descriptor to be transmitted. |
| 545 | */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 546 | if (status & BD_ENET_TX_WRAP) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 547 | bdp = fep->tx_bd_base; |
| 548 | else |
| 549 | bdp++; |
| 550 | |
| 551 | /* Since we have freed up a buffer, the ring is no longer |
| 552 | * full. |
| 553 | */ |
| 554 | if (fep->tx_full) { |
| 555 | fep->tx_full = 0; |
| 556 | if (netif_queue_stopped(dev)) |
| 557 | netif_wake_queue(dev); |
| 558 | } |
| 559 | } |
| 560 | fep->dirty_tx = (cbd_t *)bdp; |
| 561 | spin_unlock(&fep->lock); |
| 562 | } |
| 563 | |
| 564 | |
| 565 | /* During a receive, the cur_rx points to the current incoming buffer. |
| 566 | * When we update through the ring, if the next incoming buffer has |
| 567 | * not been given to the system, we just set the empty indicator, |
| 568 | * effectively tossing the packet. |
| 569 | */ |
| 570 | static void |
| 571 | fec_enet_rx(struct net_device *dev) |
| 572 | { |
| 573 | struct fec_enet_private *fep; |
| 574 | volatile fec_t *fecp; |
| 575 | volatile cbd_t *bdp; |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 576 | unsigned short status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 577 | struct sk_buff *skb; |
| 578 | ushort pkt_len; |
| 579 | __u8 *data; |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 580 | |
| 581 | #ifdef CONFIG_M532x |
| 582 | flush_cache_all(); |
| 583 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 584 | |
| 585 | fep = netdev_priv(dev); |
| 586 | fecp = (volatile fec_t*)dev->base_addr; |
| 587 | |
| 588 | /* First, grab all of the stats for the incoming packet. |
| 589 | * These get messed up if we get called due to a busy condition. |
| 590 | */ |
| 591 | bdp = fep->cur_rx; |
| 592 | |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 593 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 594 | |
| 595 | #ifndef final_version |
| 596 | /* Since we have allocated space to hold a complete frame, |
| 597 | * the last indicator should be set. |
| 598 | */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 599 | if ((status & BD_ENET_RX_LAST) == 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 600 | printk("FEC ENET: rcv is not +last\n"); |
| 601 | #endif |
| 602 | |
| 603 | if (!fep->opened) |
| 604 | goto rx_processing_done; |
| 605 | |
| 606 | /* Check for errors. */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 607 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 608 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
| 609 | fep->stats.rx_errors++; |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 610 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 611 | /* Frame too long or too short. */ |
| 612 | fep->stats.rx_length_errors++; |
| 613 | } |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 614 | if (status & BD_ENET_RX_NO) /* Frame alignment */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 615 | fep->stats.rx_frame_errors++; |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 616 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 617 | fep->stats.rx_crc_errors++; |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 618 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
| 619 | fep->stats.rx_fifo_errors++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | } |
| 621 | |
| 622 | /* Report late collisions as a frame error. |
| 623 | * On this error, the BD is closed, but we don't know what we |
| 624 | * have in the buffer. So, just drop this frame on the floor. |
| 625 | */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 626 | if (status & BD_ENET_RX_CL) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 627 | fep->stats.rx_errors++; |
| 628 | fep->stats.rx_frame_errors++; |
| 629 | goto rx_processing_done; |
| 630 | } |
| 631 | |
| 632 | /* Process the incoming frame. |
| 633 | */ |
| 634 | fep->stats.rx_packets++; |
| 635 | pkt_len = bdp->cbd_datlen; |
| 636 | fep->stats.rx_bytes += pkt_len; |
| 637 | data = (__u8*)__va(bdp->cbd_bufaddr); |
| 638 | |
| 639 | /* This does 16 byte alignment, exactly what we need. |
| 640 | * The packet length includes FCS, but we don't want to |
| 641 | * include that when passing upstream as it messes up |
| 642 | * bridging applications. |
| 643 | */ |
| 644 | skb = dev_alloc_skb(pkt_len-4); |
| 645 | |
| 646 | if (skb == NULL) { |
| 647 | printk("%s: Memory squeeze, dropping packet.\n", dev->name); |
| 648 | fep->stats.rx_dropped++; |
| 649 | } else { |
| 650 | skb->dev = dev; |
| 651 | skb_put(skb,pkt_len-4); /* Make room */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 652 | eth_copy_and_sum(skb, data, pkt_len-4, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 653 | skb->protocol=eth_type_trans(skb,dev); |
| 654 | netif_rx(skb); |
| 655 | } |
| 656 | rx_processing_done: |
| 657 | |
| 658 | /* Clear the status flags for this buffer. |
| 659 | */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 660 | status &= ~BD_ENET_RX_STATS; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 661 | |
| 662 | /* Mark the buffer empty. |
| 663 | */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 664 | status |= BD_ENET_RX_EMPTY; |
| 665 | bdp->cbd_sc = status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 666 | |
| 667 | /* Update BD pointer to next entry. |
| 668 | */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 669 | if (status & BD_ENET_RX_WRAP) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 670 | bdp = fep->rx_bd_base; |
| 671 | else |
| 672 | bdp++; |
| 673 | |
| 674 | #if 1 |
| 675 | /* Doing this here will keep the FEC running while we process |
| 676 | * incoming frames. On a heavily loaded network, we should be |
| 677 | * able to keep up at the expense of system resources. |
| 678 | */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 679 | fecp->fec_r_des_active = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 680 | #endif |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 681 | } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 682 | fep->cur_rx = (cbd_t *)bdp; |
| 683 | |
| 684 | #if 0 |
| 685 | /* Doing this here will allow us to process all frames in the |
| 686 | * ring before the FEC is allowed to put more there. On a heavily |
| 687 | * loaded network, some frames may be lost. Unfortunately, this |
| 688 | * increases the interrupt overhead since we can potentially work |
| 689 | * our way back to the interrupt return only to come right back |
| 690 | * here. |
| 691 | */ |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 692 | fecp->fec_r_des_active = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 693 | #endif |
| 694 | } |
| 695 | |
| 696 | |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 697 | /* called from interrupt context */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 698 | static void |
| 699 | fec_enet_mii(struct net_device *dev) |
| 700 | { |
| 701 | struct fec_enet_private *fep; |
| 702 | volatile fec_t *ep; |
| 703 | mii_list_t *mip; |
| 704 | uint mii_reg; |
| 705 | |
| 706 | fep = netdev_priv(dev); |
| 707 | ep = fep->hwp; |
| 708 | mii_reg = ep->fec_mii_data; |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 709 | |
| 710 | spin_lock(&fep->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 711 | |
| 712 | if ((mip = mii_head) == NULL) { |
| 713 | printk("MII and no head!\n"); |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 714 | goto unlock; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 715 | } |
| 716 | |
| 717 | if (mip->mii_func != NULL) |
| 718 | (*(mip->mii_func))(mii_reg, dev); |
| 719 | |
| 720 | mii_head = mip->mii_next; |
| 721 | mip->mii_next = mii_free; |
| 722 | mii_free = mip; |
| 723 | |
| 724 | if ((mip = mii_head) != NULL) |
| 725 | ep->fec_mii_data = mip->mii_regval; |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 726 | |
| 727 | unlock: |
| 728 | spin_unlock(&fep->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 729 | } |
| 730 | |
| 731 | static int |
| 732 | mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *)) |
| 733 | { |
| 734 | struct fec_enet_private *fep; |
| 735 | unsigned long flags; |
| 736 | mii_list_t *mip; |
| 737 | int retval; |
| 738 | |
| 739 | /* Add PHY address to register command. |
| 740 | */ |
| 741 | fep = netdev_priv(dev); |
| 742 | regval |= fep->phy_addr << 23; |
| 743 | |
| 744 | retval = 0; |
| 745 | |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 746 | spin_lock_irqsave(&fep->lock,flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 747 | |
| 748 | if ((mip = mii_free) != NULL) { |
| 749 | mii_free = mip->mii_next; |
| 750 | mip->mii_regval = regval; |
| 751 | mip->mii_func = func; |
| 752 | mip->mii_next = NULL; |
| 753 | if (mii_head) { |
| 754 | mii_tail->mii_next = mip; |
| 755 | mii_tail = mip; |
| 756 | } |
| 757 | else { |
| 758 | mii_head = mii_tail = mip; |
| 759 | fep->hwp->fec_mii_data = regval; |
| 760 | } |
| 761 | } |
| 762 | else { |
| 763 | retval = 1; |
| 764 | } |
| 765 | |
Greg Ungerer | 0e702ab | 2006-06-27 13:19:33 +1000 | [diff] [blame] | 766 | spin_unlock_irqrestore(&fep->lock,flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 767 | |
| 768 | return(retval); |
| 769 | } |
| 770 | |
| 771 | static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c) |
| 772 | { |
| 773 | int k; |
| 774 | |
| 775 | if(!c) |
| 776 | return; |
| 777 | |
| 778 | for(k = 0; (c+k)->mii_data != mk_mii_end; k++) { |
| 779 | mii_queue(dev, (c+k)->mii_data, (c+k)->funct); |
| 780 | } |
| 781 | } |
| 782 | |
| 783 | static void mii_parse_sr(uint mii_reg, struct net_device *dev) |
| 784 | { |
| 785 | struct fec_enet_private *fep = netdev_priv(dev); |
| 786 | volatile uint *s = &(fep->phy_status); |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 787 | uint status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 788 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 789 | status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 790 | |
| 791 | if (mii_reg & 0x0004) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 792 | status |= PHY_STAT_LINK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 793 | if (mii_reg & 0x0010) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 794 | status |= PHY_STAT_FAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 795 | if (mii_reg & 0x0020) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 796 | status |= PHY_STAT_ANC; |
| 797 | |
| 798 | *s = status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 799 | } |
| 800 | |
| 801 | static void mii_parse_cr(uint mii_reg, struct net_device *dev) |
| 802 | { |
| 803 | struct fec_enet_private *fep = netdev_priv(dev); |
| 804 | volatile uint *s = &(fep->phy_status); |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 805 | uint status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 806 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 807 | status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 808 | |
| 809 | if (mii_reg & 0x1000) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 810 | status |= PHY_CONF_ANE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 811 | if (mii_reg & 0x4000) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 812 | status |= PHY_CONF_LOOP; |
| 813 | *s = status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 814 | } |
| 815 | |
| 816 | static void mii_parse_anar(uint mii_reg, struct net_device *dev) |
| 817 | { |
| 818 | struct fec_enet_private *fep = netdev_priv(dev); |
| 819 | volatile uint *s = &(fep->phy_status); |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 820 | uint status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 821 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 822 | status = *s & ~(PHY_CONF_SPMASK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 823 | |
| 824 | if (mii_reg & 0x0020) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 825 | status |= PHY_CONF_10HDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 826 | if (mii_reg & 0x0040) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 827 | status |= PHY_CONF_10FDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 828 | if (mii_reg & 0x0080) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 829 | status |= PHY_CONF_100HDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 830 | if (mii_reg & 0x00100) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 831 | status |= PHY_CONF_100FDX; |
| 832 | *s = status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 833 | } |
| 834 | |
| 835 | /* ------------------------------------------------------------------------- */ |
| 836 | /* The Level one LXT970 is used by many boards */ |
| 837 | |
| 838 | #define MII_LXT970_MIRROR 16 /* Mirror register */ |
| 839 | #define MII_LXT970_IER 17 /* Interrupt Enable Register */ |
| 840 | #define MII_LXT970_ISR 18 /* Interrupt Status Register */ |
| 841 | #define MII_LXT970_CONFIG 19 /* Configuration Register */ |
| 842 | #define MII_LXT970_CSR 20 /* Chip Status Register */ |
| 843 | |
| 844 | static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev) |
| 845 | { |
| 846 | struct fec_enet_private *fep = netdev_priv(dev); |
| 847 | volatile uint *s = &(fep->phy_status); |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 848 | uint status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 849 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 850 | status = *s & ~(PHY_STAT_SPMASK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 851 | if (mii_reg & 0x0800) { |
| 852 | if (mii_reg & 0x1000) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 853 | status |= PHY_STAT_100FDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 854 | else |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 855 | status |= PHY_STAT_100HDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 856 | } else { |
| 857 | if (mii_reg & 0x1000) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 858 | status |= PHY_STAT_10FDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 859 | else |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 860 | status |= PHY_STAT_10HDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 861 | } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 862 | *s = status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 863 | } |
| 864 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 865 | static phy_cmd_t const phy_cmd_lxt970_config[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 866 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
| 867 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, |
| 868 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 869 | }; |
| 870 | static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 871 | { mk_mii_write(MII_LXT970_IER, 0x0002), NULL }, |
| 872 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ |
| 873 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 874 | }; |
| 875 | static phy_cmd_t const phy_cmd_lxt970_ack_int[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 876 | /* read SR and ISR to acknowledge */ |
| 877 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 878 | { mk_mii_read(MII_LXT970_ISR), NULL }, |
| 879 | |
| 880 | /* find out the current status */ |
| 881 | { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr }, |
| 882 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 883 | }; |
| 884 | static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 885 | { mk_mii_write(MII_LXT970_IER, 0x0000), NULL }, |
| 886 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 887 | }; |
| 888 | static phy_info_t const phy_info_lxt970 = { |
| 889 | .id = 0x07810000, |
| 890 | .name = "LXT970", |
| 891 | .config = phy_cmd_lxt970_config, |
| 892 | .startup = phy_cmd_lxt970_startup, |
| 893 | .ack_int = phy_cmd_lxt970_ack_int, |
| 894 | .shutdown = phy_cmd_lxt970_shutdown |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 895 | }; |
| 896 | |
| 897 | /* ------------------------------------------------------------------------- */ |
| 898 | /* The Level one LXT971 is used on some of my custom boards */ |
| 899 | |
| 900 | /* register definitions for the 971 */ |
| 901 | |
| 902 | #define MII_LXT971_PCR 16 /* Port Control Register */ |
| 903 | #define MII_LXT971_SR2 17 /* Status Register 2 */ |
| 904 | #define MII_LXT971_IER 18 /* Interrupt Enable Register */ |
| 905 | #define MII_LXT971_ISR 19 /* Interrupt Status Register */ |
| 906 | #define MII_LXT971_LCR 20 /* LED Control Register */ |
| 907 | #define MII_LXT971_TCR 30 /* Transmit Control Register */ |
| 908 | |
| 909 | /* |
| 910 | * I had some nice ideas of running the MDIO faster... |
| 911 | * The 971 should support 8MHz and I tried it, but things acted really |
| 912 | * weird, so 2.5 MHz ought to be enough for anyone... |
| 913 | */ |
| 914 | |
| 915 | static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev) |
| 916 | { |
| 917 | struct fec_enet_private *fep = netdev_priv(dev); |
| 918 | volatile uint *s = &(fep->phy_status); |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 919 | uint status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 920 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 921 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 922 | |
| 923 | if (mii_reg & 0x0400) { |
| 924 | fep->link = 1; |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 925 | status |= PHY_STAT_LINK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 926 | } else { |
| 927 | fep->link = 0; |
| 928 | } |
| 929 | if (mii_reg & 0x0080) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 930 | status |= PHY_STAT_ANC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 931 | if (mii_reg & 0x4000) { |
| 932 | if (mii_reg & 0x0200) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 933 | status |= PHY_STAT_100FDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 934 | else |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 935 | status |= PHY_STAT_100HDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 936 | } else { |
| 937 | if (mii_reg & 0x0200) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 938 | status |= PHY_STAT_10FDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 939 | else |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 940 | status |= PHY_STAT_10HDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 941 | } |
| 942 | if (mii_reg & 0x0008) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 943 | status |= PHY_STAT_FAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 944 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 945 | *s = status; |
| 946 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 947 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 948 | static phy_cmd_t const phy_cmd_lxt971_config[] = { |
| 949 | /* limit to 10MBit because my prototype board |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 950 | * doesn't work with 100. */ |
| 951 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
| 952 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, |
| 953 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, |
| 954 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 955 | }; |
| 956 | static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 957 | { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL }, |
| 958 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ |
| 959 | { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */ |
| 960 | /* Somehow does the 971 tell me that the link is down |
| 961 | * the first read after power-up. |
| 962 | * read here to get a valid value in ack_int */ |
| 963 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 964 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 965 | }; |
| 966 | static phy_cmd_t const phy_cmd_lxt971_ack_int[] = { |
| 967 | /* acknowledge the int before reading status ! */ |
| 968 | { mk_mii_read(MII_LXT971_ISR), NULL }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 969 | /* find out the current status */ |
| 970 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 971 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 972 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 973 | }; |
| 974 | static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 975 | { mk_mii_write(MII_LXT971_IER, 0x0000), NULL }, |
| 976 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 977 | }; |
| 978 | static phy_info_t const phy_info_lxt971 = { |
| 979 | .id = 0x0001378e, |
| 980 | .name = "LXT971", |
| 981 | .config = phy_cmd_lxt971_config, |
| 982 | .startup = phy_cmd_lxt971_startup, |
| 983 | .ack_int = phy_cmd_lxt971_ack_int, |
| 984 | .shutdown = phy_cmd_lxt971_shutdown |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 985 | }; |
| 986 | |
| 987 | /* ------------------------------------------------------------------------- */ |
| 988 | /* The Quality Semiconductor QS6612 is used on the RPX CLLF */ |
| 989 | |
| 990 | /* register definitions */ |
| 991 | |
| 992 | #define MII_QS6612_MCR 17 /* Mode Control Register */ |
| 993 | #define MII_QS6612_FTR 27 /* Factory Test Register */ |
| 994 | #define MII_QS6612_MCO 28 /* Misc. Control Register */ |
| 995 | #define MII_QS6612_ISR 29 /* Interrupt Source Register */ |
| 996 | #define MII_QS6612_IMR 30 /* Interrupt Mask Register */ |
| 997 | #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ |
| 998 | |
| 999 | static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev) |
| 1000 | { |
| 1001 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1002 | volatile uint *s = &(fep->phy_status); |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1003 | uint status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1004 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1005 | status = *s & ~(PHY_STAT_SPMASK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1006 | |
| 1007 | switch((mii_reg >> 2) & 7) { |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1008 | case 1: status |= PHY_STAT_10HDX; break; |
| 1009 | case 2: status |= PHY_STAT_100HDX; break; |
| 1010 | case 5: status |= PHY_STAT_10FDX; break; |
| 1011 | case 6: status |= PHY_STAT_100FDX; break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1012 | } |
| 1013 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1014 | *s = status; |
| 1015 | } |
| 1016 | |
| 1017 | static phy_cmd_t const phy_cmd_qs6612_config[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1018 | /* The PHY powers up isolated on the RPX, |
| 1019 | * so send a command to allow operation. |
| 1020 | */ |
| 1021 | { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL }, |
| 1022 | |
| 1023 | /* parse cr and anar to get some info */ |
| 1024 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
| 1025 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, |
| 1026 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1027 | }; |
| 1028 | static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1029 | { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL }, |
| 1030 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ |
| 1031 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1032 | }; |
| 1033 | static phy_cmd_t const phy_cmd_qs6612_ack_int[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1034 | /* we need to read ISR, SR and ANER to acknowledge */ |
| 1035 | { mk_mii_read(MII_QS6612_ISR), NULL }, |
| 1036 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 1037 | { mk_mii_read(MII_REG_ANER), NULL }, |
| 1038 | |
| 1039 | /* read pcr to get info */ |
| 1040 | { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr }, |
| 1041 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1042 | }; |
| 1043 | static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1044 | { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL }, |
| 1045 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1046 | }; |
| 1047 | static phy_info_t const phy_info_qs6612 = { |
| 1048 | .id = 0x00181440, |
| 1049 | .name = "QS6612", |
| 1050 | .config = phy_cmd_qs6612_config, |
| 1051 | .startup = phy_cmd_qs6612_startup, |
| 1052 | .ack_int = phy_cmd_qs6612_ack_int, |
| 1053 | .shutdown = phy_cmd_qs6612_shutdown |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1054 | }; |
| 1055 | |
| 1056 | /* ------------------------------------------------------------------------- */ |
| 1057 | /* AMD AM79C874 phy */ |
| 1058 | |
| 1059 | /* register definitions for the 874 */ |
| 1060 | |
| 1061 | #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */ |
| 1062 | #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */ |
| 1063 | #define MII_AM79C874_DR 18 /* Diagnostic Register */ |
| 1064 | #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */ |
| 1065 | #define MII_AM79C874_MCR 21 /* ModeControl Register */ |
| 1066 | #define MII_AM79C874_DC 23 /* Disconnect Counter */ |
| 1067 | #define MII_AM79C874_REC 24 /* Recieve Error Counter */ |
| 1068 | |
| 1069 | static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev) |
| 1070 | { |
| 1071 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1072 | volatile uint *s = &(fep->phy_status); |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1073 | uint status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1074 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1075 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1076 | |
| 1077 | if (mii_reg & 0x0080) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1078 | status |= PHY_STAT_ANC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1079 | if (mii_reg & 0x0400) |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1080 | status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1081 | else |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1082 | status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX); |
| 1083 | |
| 1084 | *s = status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1085 | } |
| 1086 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1087 | static phy_cmd_t const phy_cmd_am79c874_config[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1088 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
| 1089 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, |
| 1090 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, |
| 1091 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1092 | }; |
| 1093 | static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1094 | { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL }, |
| 1095 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ |
| 1096 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 1097 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1098 | }; |
| 1099 | static phy_cmd_t const phy_cmd_am79c874_ack_int[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1100 | /* find out the current status */ |
| 1101 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 1102 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, |
| 1103 | /* we only need to read ISR to acknowledge */ |
| 1104 | { mk_mii_read(MII_AM79C874_ICSR), NULL }, |
| 1105 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1106 | }; |
| 1107 | static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1108 | { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL }, |
| 1109 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1110 | }; |
| 1111 | static phy_info_t const phy_info_am79c874 = { |
| 1112 | .id = 0x00022561, |
| 1113 | .name = "AM79C874", |
| 1114 | .config = phy_cmd_am79c874_config, |
| 1115 | .startup = phy_cmd_am79c874_startup, |
| 1116 | .ack_int = phy_cmd_am79c874_ack_int, |
| 1117 | .shutdown = phy_cmd_am79c874_shutdown |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1118 | }; |
| 1119 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1120 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1121 | /* ------------------------------------------------------------------------- */ |
| 1122 | /* Kendin KS8721BL phy */ |
| 1123 | |
| 1124 | /* register definitions for the 8721 */ |
| 1125 | |
| 1126 | #define MII_KS8721BL_RXERCR 21 |
| 1127 | #define MII_KS8721BL_ICSR 22 |
| 1128 | #define MII_KS8721BL_PHYCR 31 |
| 1129 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1130 | static phy_cmd_t const phy_cmd_ks8721bl_config[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1131 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
| 1132 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, |
| 1133 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1134 | }; |
| 1135 | static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1136 | { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL }, |
| 1137 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ |
| 1138 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 1139 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1140 | }; |
| 1141 | static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1142 | /* find out the current status */ |
| 1143 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 1144 | /* we only need to read ISR to acknowledge */ |
| 1145 | { mk_mii_read(MII_KS8721BL_ICSR), NULL }, |
| 1146 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1147 | }; |
| 1148 | static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1149 | { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL }, |
| 1150 | { mk_mii_end, } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1151 | }; |
| 1152 | static phy_info_t const phy_info_ks8721bl = { |
| 1153 | .id = 0x00022161, |
| 1154 | .name = "KS8721BL", |
| 1155 | .config = phy_cmd_ks8721bl_config, |
| 1156 | .startup = phy_cmd_ks8721bl_startup, |
| 1157 | .ack_int = phy_cmd_ks8721bl_ack_int, |
| 1158 | .shutdown = phy_cmd_ks8721bl_shutdown |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1159 | }; |
| 1160 | |
| 1161 | /* ------------------------------------------------------------------------- */ |
Greg Ungerer | 562d2f8 | 2005-11-07 14:09:50 +1000 | [diff] [blame] | 1162 | /* register definitions for the DP83848 */ |
| 1163 | |
| 1164 | #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */ |
| 1165 | |
| 1166 | static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev) |
| 1167 | { |
| 1168 | struct fec_enet_private *fep = dev->priv; |
| 1169 | volatile uint *s = &(fep->phy_status); |
| 1170 | |
| 1171 | *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); |
| 1172 | |
| 1173 | /* Link up */ |
| 1174 | if (mii_reg & 0x0001) { |
| 1175 | fep->link = 1; |
| 1176 | *s |= PHY_STAT_LINK; |
| 1177 | } else |
| 1178 | fep->link = 0; |
| 1179 | /* Status of link */ |
| 1180 | if (mii_reg & 0x0010) /* Autonegotioation complete */ |
| 1181 | *s |= PHY_STAT_ANC; |
| 1182 | if (mii_reg & 0x0002) { /* 10MBps? */ |
| 1183 | if (mii_reg & 0x0004) /* Full Duplex? */ |
| 1184 | *s |= PHY_STAT_10FDX; |
| 1185 | else |
| 1186 | *s |= PHY_STAT_10HDX; |
| 1187 | } else { /* 100 Mbps? */ |
| 1188 | if (mii_reg & 0x0004) /* Full Duplex? */ |
| 1189 | *s |= PHY_STAT_100FDX; |
| 1190 | else |
| 1191 | *s |= PHY_STAT_100HDX; |
| 1192 | } |
| 1193 | if (mii_reg & 0x0008) |
| 1194 | *s |= PHY_STAT_FAULT; |
| 1195 | } |
| 1196 | |
| 1197 | static phy_info_t phy_info_dp83848= { |
| 1198 | 0x020005c9, |
| 1199 | "DP83848", |
| 1200 | |
| 1201 | (const phy_cmd_t []) { /* config */ |
| 1202 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
| 1203 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, |
| 1204 | { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 }, |
| 1205 | { mk_mii_end, } |
| 1206 | }, |
| 1207 | (const phy_cmd_t []) { /* startup - enable interrupts */ |
| 1208 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ |
| 1209 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
| 1210 | { mk_mii_end, } |
| 1211 | }, |
| 1212 | (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */ |
| 1213 | { mk_mii_end, } |
| 1214 | }, |
| 1215 | (const phy_cmd_t []) { /* shutdown */ |
| 1216 | { mk_mii_end, } |
| 1217 | }, |
| 1218 | }; |
| 1219 | |
| 1220 | /* ------------------------------------------------------------------------- */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1221 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1222 | static phy_info_t const * const phy_info[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1223 | &phy_info_lxt970, |
| 1224 | &phy_info_lxt971, |
| 1225 | &phy_info_qs6612, |
| 1226 | &phy_info_am79c874, |
| 1227 | &phy_info_ks8721bl, |
Greg Ungerer | 562d2f8 | 2005-11-07 14:09:50 +1000 | [diff] [blame] | 1228 | &phy_info_dp83848, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1229 | NULL |
| 1230 | }; |
| 1231 | |
| 1232 | /* ------------------------------------------------------------------------- */ |
Matt Waddel | 6b26529 | 2006-06-27 13:10:56 +1000 | [diff] [blame] | 1233 | #if !defined(CONFIG_M532x) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1234 | #ifdef CONFIG_RPXCLASSIC |
| 1235 | static void |
| 1236 | mii_link_interrupt(void *dev_id); |
| 1237 | #else |
| 1238 | static irqreturn_t |
| 1239 | mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs); |
| 1240 | #endif |
Matt Waddel | 6b26529 | 2006-06-27 13:10:56 +1000 | [diff] [blame] | 1241 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1242 | |
| 1243 | #if defined(CONFIG_M5272) |
| 1244 | |
| 1245 | /* |
| 1246 | * Code specific to Coldfire 5272 setup. |
| 1247 | */ |
| 1248 | static void __inline__ fec_request_intrs(struct net_device *dev) |
| 1249 | { |
| 1250 | volatile unsigned long *icrp; |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1251 | static const struct idesc { |
| 1252 | char *name; |
| 1253 | unsigned short irq; |
| 1254 | irqreturn_t (*handler)(int, void *, struct pt_regs *); |
| 1255 | } *idp, id[] = { |
| 1256 | { "fec(RX)", 86, fec_enet_interrupt }, |
| 1257 | { "fec(TX)", 87, fec_enet_interrupt }, |
| 1258 | { "fec(OTHER)", 88, fec_enet_interrupt }, |
| 1259 | { "fec(MII)", 66, mii_link_interrupt }, |
| 1260 | { NULL }, |
| 1261 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1262 | |
| 1263 | /* Setup interrupt handlers. */ |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1264 | for (idp = id; idp->name; idp++) { |
| 1265 | if (request_irq(idp->irq, idp->handler, 0, idp->name, dev) != 0) |
| 1266 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq); |
| 1267 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1268 | |
| 1269 | /* Unmask interrupt at ColdFire 5272 SIM */ |
| 1270 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3); |
| 1271 | *icrp = 0x00000ddd; |
| 1272 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); |
| 1273 | *icrp = (*icrp & 0x70777777) | 0x0d000000; |
| 1274 | } |
| 1275 | |
| 1276 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) |
| 1277 | { |
| 1278 | volatile fec_t *fecp; |
| 1279 | |
| 1280 | fecp = fep->hwp; |
| 1281 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; |
| 1282 | fecp->fec_x_cntrl = 0x00; |
| 1283 | |
| 1284 | /* |
| 1285 | * Set MII speed to 2.5 MHz |
| 1286 | * See 5272 manual section 11.5.8: MSCR |
| 1287 | */ |
| 1288 | fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2; |
| 1289 | fecp->fec_mii_speed = fep->phy_speed; |
| 1290 | |
| 1291 | fec_restart(dev, 0); |
| 1292 | } |
| 1293 | |
| 1294 | static void __inline__ fec_get_mac(struct net_device *dev) |
| 1295 | { |
| 1296 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1297 | volatile fec_t *fecp; |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1298 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1299 | |
| 1300 | fecp = fep->hwp; |
| 1301 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1302 | if (FEC_FLASHMAC) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1303 | /* |
| 1304 | * Get MAC address from FLASH. |
| 1305 | * If it is all 1's or 0's, use the default. |
| 1306 | */ |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1307 | iap = (unsigned char *)FEC_FLASHMAC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1308 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
| 1309 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) |
| 1310 | iap = fec_mac_default; |
| 1311 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && |
| 1312 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) |
| 1313 | iap = fec_mac_default; |
| 1314 | } else { |
| 1315 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; |
| 1316 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); |
| 1317 | iap = &tmpaddr[0]; |
| 1318 | } |
| 1319 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1320 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1321 | |
| 1322 | /* Adjust MAC if using default MAC address */ |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1323 | if (iap == fec_mac_default) |
| 1324 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1325 | } |
| 1326 | |
| 1327 | static void __inline__ fec_enable_phy_intr(void) |
| 1328 | { |
| 1329 | } |
| 1330 | |
| 1331 | static void __inline__ fec_disable_phy_intr(void) |
| 1332 | { |
| 1333 | volatile unsigned long *icrp; |
| 1334 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); |
| 1335 | *icrp = (*icrp & 0x70777777) | 0x08000000; |
| 1336 | } |
| 1337 | |
| 1338 | static void __inline__ fec_phy_ack_intr(void) |
| 1339 | { |
| 1340 | volatile unsigned long *icrp; |
| 1341 | /* Acknowledge the interrupt */ |
| 1342 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); |
| 1343 | *icrp = (*icrp & 0x77777777) | 0x08000000; |
| 1344 | } |
| 1345 | |
| 1346 | static void __inline__ fec_localhw_setup(void) |
| 1347 | { |
| 1348 | } |
| 1349 | |
| 1350 | /* |
| 1351 | * Do not need to make region uncached on 5272. |
| 1352 | */ |
| 1353 | static void __inline__ fec_uncache(unsigned long addr) |
| 1354 | { |
| 1355 | } |
| 1356 | |
| 1357 | /* ------------------------------------------------------------------------- */ |
| 1358 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1359 | #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1360 | |
| 1361 | /* |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1362 | * Code specific to Coldfire 5230/5231/5232/5234/5235, |
| 1363 | * the 5270/5271/5274/5275 and 5280/5282 setups. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1364 | */ |
| 1365 | static void __inline__ fec_request_intrs(struct net_device *dev) |
| 1366 | { |
| 1367 | struct fec_enet_private *fep; |
| 1368 | int b; |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1369 | static const struct idesc { |
| 1370 | char *name; |
| 1371 | unsigned short irq; |
| 1372 | } *idp, id[] = { |
| 1373 | { "fec(TXF)", 23 }, |
| 1374 | { "fec(TXB)", 24 }, |
| 1375 | { "fec(TXFIFO)", 25 }, |
| 1376 | { "fec(TXCR)", 26 }, |
| 1377 | { "fec(RXF)", 27 }, |
| 1378 | { "fec(RXB)", 28 }, |
| 1379 | { "fec(MII)", 29 }, |
| 1380 | { "fec(LC)", 30 }, |
| 1381 | { "fec(HBERR)", 31 }, |
| 1382 | { "fec(GRA)", 32 }, |
| 1383 | { "fec(EBERR)", 33 }, |
| 1384 | { "fec(BABT)", 34 }, |
| 1385 | { "fec(BABR)", 35 }, |
| 1386 | { NULL }, |
| 1387 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1388 | |
| 1389 | fep = netdev_priv(dev); |
| 1390 | b = (fep->index) ? 128 : 64; |
| 1391 | |
| 1392 | /* Setup interrupt handlers. */ |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1393 | for (idp = id; idp->name; idp++) { |
| 1394 | if (request_irq(b+idp->irq, fec_enet_interrupt, 0, idp->name, dev) != 0) |
| 1395 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq); |
| 1396 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1397 | |
| 1398 | /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */ |
| 1399 | { |
| 1400 | volatile unsigned char *icrp; |
| 1401 | volatile unsigned long *imrp; |
Willson Callan | 83901fc | 2006-06-27 13:13:44 +1000 | [diff] [blame] | 1402 | int i, ilip; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1403 | |
| 1404 | b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0; |
| 1405 | icrp = (volatile unsigned char *) (MCF_IPSBAR + b + |
| 1406 | MCFINTC_ICR0); |
Willson Callan | 83901fc | 2006-06-27 13:13:44 +1000 | [diff] [blame] | 1407 | for (i = 23, ilip = 0x28; (i < 36); i++) |
| 1408 | icrp[i] = ilip--; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1409 | |
| 1410 | imrp = (volatile unsigned long *) (MCF_IPSBAR + b + |
| 1411 | MCFINTC_IMRH); |
| 1412 | *imrp &= ~0x0000000f; |
| 1413 | imrp = (volatile unsigned long *) (MCF_IPSBAR + b + |
| 1414 | MCFINTC_IMRL); |
| 1415 | *imrp &= ~0xff800001; |
| 1416 | } |
| 1417 | |
| 1418 | #if defined(CONFIG_M528x) |
| 1419 | /* Set up gpio outputs for MII lines */ |
| 1420 | { |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1421 | volatile u16 *gpio_paspar; |
| 1422 | volatile u8 *gpio_pehlpar; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1423 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1424 | gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056); |
| 1425 | gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058); |
| 1426 | *gpio_paspar |= 0x0f00; |
| 1427 | *gpio_pehlpar = 0xc0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1428 | } |
| 1429 | #endif |
| 1430 | } |
| 1431 | |
| 1432 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) |
| 1433 | { |
| 1434 | volatile fec_t *fecp; |
| 1435 | |
| 1436 | fecp = fep->hwp; |
| 1437 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; |
| 1438 | fecp->fec_x_cntrl = 0x00; |
| 1439 | |
| 1440 | /* |
| 1441 | * Set MII speed to 2.5 MHz |
| 1442 | * See 5282 manual section 17.5.4.7: MSCR |
| 1443 | */ |
| 1444 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; |
| 1445 | fecp->fec_mii_speed = fep->phy_speed; |
| 1446 | |
| 1447 | fec_restart(dev, 0); |
| 1448 | } |
| 1449 | |
| 1450 | static void __inline__ fec_get_mac(struct net_device *dev) |
| 1451 | { |
| 1452 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1453 | volatile fec_t *fecp; |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1454 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1455 | |
| 1456 | fecp = fep->hwp; |
| 1457 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1458 | if (FEC_FLASHMAC) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1459 | /* |
| 1460 | * Get MAC address from FLASH. |
| 1461 | * If it is all 1's or 0's, use the default. |
| 1462 | */ |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1463 | iap = FEC_FLASHMAC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1464 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
| 1465 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) |
| 1466 | iap = fec_mac_default; |
| 1467 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && |
| 1468 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) |
| 1469 | iap = fec_mac_default; |
| 1470 | } else { |
| 1471 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; |
| 1472 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); |
| 1473 | iap = &tmpaddr[0]; |
| 1474 | } |
| 1475 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1476 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1477 | |
| 1478 | /* Adjust MAC if using default MAC address */ |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1479 | if (iap == fec_mac_default) |
| 1480 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1481 | } |
| 1482 | |
| 1483 | static void __inline__ fec_enable_phy_intr(void) |
| 1484 | { |
| 1485 | } |
| 1486 | |
| 1487 | static void __inline__ fec_disable_phy_intr(void) |
| 1488 | { |
| 1489 | } |
| 1490 | |
| 1491 | static void __inline__ fec_phy_ack_intr(void) |
| 1492 | { |
| 1493 | } |
| 1494 | |
| 1495 | static void __inline__ fec_localhw_setup(void) |
| 1496 | { |
| 1497 | } |
| 1498 | |
| 1499 | /* |
| 1500 | * Do not need to make region uncached on 5272. |
| 1501 | */ |
| 1502 | static void __inline__ fec_uncache(unsigned long addr) |
| 1503 | { |
| 1504 | } |
| 1505 | |
| 1506 | /* ------------------------------------------------------------------------- */ |
| 1507 | |
Greg Ungerer | 562d2f8 | 2005-11-07 14:09:50 +1000 | [diff] [blame] | 1508 | #elif defined(CONFIG_M520x) |
| 1509 | |
| 1510 | /* |
| 1511 | * Code specific to Coldfire 520x |
| 1512 | */ |
| 1513 | static void __inline__ fec_request_intrs(struct net_device *dev) |
| 1514 | { |
| 1515 | struct fec_enet_private *fep; |
| 1516 | int b; |
| 1517 | static const struct idesc { |
| 1518 | char *name; |
| 1519 | unsigned short irq; |
| 1520 | } *idp, id[] = { |
| 1521 | { "fec(TXF)", 23 }, |
| 1522 | { "fec(TXB)", 24 }, |
| 1523 | { "fec(TXFIFO)", 25 }, |
| 1524 | { "fec(TXCR)", 26 }, |
| 1525 | { "fec(RXF)", 27 }, |
| 1526 | { "fec(RXB)", 28 }, |
| 1527 | { "fec(MII)", 29 }, |
| 1528 | { "fec(LC)", 30 }, |
| 1529 | { "fec(HBERR)", 31 }, |
| 1530 | { "fec(GRA)", 32 }, |
| 1531 | { "fec(EBERR)", 33 }, |
| 1532 | { "fec(BABT)", 34 }, |
| 1533 | { "fec(BABR)", 35 }, |
| 1534 | { NULL }, |
| 1535 | }; |
| 1536 | |
| 1537 | fep = netdev_priv(dev); |
| 1538 | b = 64 + 13; |
| 1539 | |
| 1540 | /* Setup interrupt handlers. */ |
| 1541 | for (idp = id; idp->name; idp++) { |
| 1542 | if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0) |
| 1543 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq); |
| 1544 | } |
| 1545 | |
| 1546 | /* Unmask interrupts at ColdFire interrupt controller */ |
| 1547 | { |
| 1548 | volatile unsigned char *icrp; |
| 1549 | volatile unsigned long *imrp; |
| 1550 | |
| 1551 | icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 + |
| 1552 | MCFINTC_ICR0); |
| 1553 | for (b = 36; (b < 49); b++) |
| 1554 | icrp[b] = 0x04; |
| 1555 | imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + |
| 1556 | MCFINTC_IMRH); |
| 1557 | *imrp &= ~0x0001FFF0; |
| 1558 | } |
| 1559 | *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0; |
| 1560 | *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f; |
| 1561 | } |
| 1562 | |
| 1563 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) |
| 1564 | { |
| 1565 | volatile fec_t *fecp; |
| 1566 | |
| 1567 | fecp = fep->hwp; |
| 1568 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; |
| 1569 | fecp->fec_x_cntrl = 0x00; |
| 1570 | |
| 1571 | /* |
| 1572 | * Set MII speed to 2.5 MHz |
| 1573 | * See 5282 manual section 17.5.4.7: MSCR |
| 1574 | */ |
| 1575 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; |
| 1576 | fecp->fec_mii_speed = fep->phy_speed; |
| 1577 | |
| 1578 | fec_restart(dev, 0); |
| 1579 | } |
| 1580 | |
| 1581 | static void __inline__ fec_get_mac(struct net_device *dev) |
| 1582 | { |
| 1583 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1584 | volatile fec_t *fecp; |
| 1585 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
| 1586 | |
| 1587 | fecp = fep->hwp; |
| 1588 | |
| 1589 | if (FEC_FLASHMAC) { |
| 1590 | /* |
| 1591 | * Get MAC address from FLASH. |
| 1592 | * If it is all 1's or 0's, use the default. |
| 1593 | */ |
| 1594 | iap = FEC_FLASHMAC; |
| 1595 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
| 1596 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) |
| 1597 | iap = fec_mac_default; |
| 1598 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && |
| 1599 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) |
| 1600 | iap = fec_mac_default; |
| 1601 | } else { |
| 1602 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; |
| 1603 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); |
| 1604 | iap = &tmpaddr[0]; |
| 1605 | } |
| 1606 | |
| 1607 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
| 1608 | |
| 1609 | /* Adjust MAC if using default MAC address */ |
| 1610 | if (iap == fec_mac_default) |
| 1611 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; |
| 1612 | } |
| 1613 | |
| 1614 | static void __inline__ fec_enable_phy_intr(void) |
| 1615 | { |
| 1616 | } |
| 1617 | |
| 1618 | static void __inline__ fec_disable_phy_intr(void) |
| 1619 | { |
| 1620 | } |
| 1621 | |
| 1622 | static void __inline__ fec_phy_ack_intr(void) |
| 1623 | { |
| 1624 | } |
| 1625 | |
| 1626 | static void __inline__ fec_localhw_setup(void) |
| 1627 | { |
| 1628 | } |
| 1629 | |
| 1630 | static void __inline__ fec_uncache(unsigned long addr) |
| 1631 | { |
| 1632 | } |
| 1633 | |
| 1634 | /* ------------------------------------------------------------------------- */ |
| 1635 | |
Matt Waddel | 6b26529 | 2006-06-27 13:10:56 +1000 | [diff] [blame] | 1636 | #elif defined(CONFIG_M532x) |
| 1637 | /* |
| 1638 | * Code specific for M532x |
| 1639 | */ |
| 1640 | static void __inline__ fec_request_intrs(struct net_device *dev) |
| 1641 | { |
| 1642 | struct fec_enet_private *fep; |
| 1643 | int b; |
| 1644 | static const struct idesc { |
| 1645 | char *name; |
| 1646 | unsigned short irq; |
| 1647 | } *idp, id[] = { |
| 1648 | { "fec(TXF)", 36 }, |
| 1649 | { "fec(TXB)", 37 }, |
| 1650 | { "fec(TXFIFO)", 38 }, |
| 1651 | { "fec(TXCR)", 39 }, |
| 1652 | { "fec(RXF)", 40 }, |
| 1653 | { "fec(RXB)", 41 }, |
| 1654 | { "fec(MII)", 42 }, |
| 1655 | { "fec(LC)", 43 }, |
| 1656 | { "fec(HBERR)", 44 }, |
| 1657 | { "fec(GRA)", 45 }, |
| 1658 | { "fec(EBERR)", 46 }, |
| 1659 | { "fec(BABT)", 47 }, |
| 1660 | { "fec(BABR)", 48 }, |
| 1661 | { NULL }, |
| 1662 | }; |
| 1663 | |
| 1664 | fep = netdev_priv(dev); |
| 1665 | b = (fep->index) ? 128 : 64; |
| 1666 | |
| 1667 | /* Setup interrupt handlers. */ |
| 1668 | for (idp = id; idp->name; idp++) { |
| 1669 | if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0) |
| 1670 | printk("FEC: Could not allocate %s IRQ(%d)!\n", |
| 1671 | idp->name, b+idp->irq); |
| 1672 | } |
| 1673 | |
| 1674 | /* Unmask interrupts */ |
| 1675 | MCF_INTC0_ICR36 = 0x2; |
| 1676 | MCF_INTC0_ICR37 = 0x2; |
| 1677 | MCF_INTC0_ICR38 = 0x2; |
| 1678 | MCF_INTC0_ICR39 = 0x2; |
| 1679 | MCF_INTC0_ICR40 = 0x2; |
| 1680 | MCF_INTC0_ICR41 = 0x2; |
| 1681 | MCF_INTC0_ICR42 = 0x2; |
| 1682 | MCF_INTC0_ICR43 = 0x2; |
| 1683 | MCF_INTC0_ICR44 = 0x2; |
| 1684 | MCF_INTC0_ICR45 = 0x2; |
| 1685 | MCF_INTC0_ICR46 = 0x2; |
| 1686 | MCF_INTC0_ICR47 = 0x2; |
| 1687 | MCF_INTC0_ICR48 = 0x2; |
| 1688 | |
| 1689 | MCF_INTC0_IMRH &= ~( |
| 1690 | MCF_INTC_IMRH_INT_MASK36 | |
| 1691 | MCF_INTC_IMRH_INT_MASK37 | |
| 1692 | MCF_INTC_IMRH_INT_MASK38 | |
| 1693 | MCF_INTC_IMRH_INT_MASK39 | |
| 1694 | MCF_INTC_IMRH_INT_MASK40 | |
| 1695 | MCF_INTC_IMRH_INT_MASK41 | |
| 1696 | MCF_INTC_IMRH_INT_MASK42 | |
| 1697 | MCF_INTC_IMRH_INT_MASK43 | |
| 1698 | MCF_INTC_IMRH_INT_MASK44 | |
| 1699 | MCF_INTC_IMRH_INT_MASK45 | |
| 1700 | MCF_INTC_IMRH_INT_MASK46 | |
| 1701 | MCF_INTC_IMRH_INT_MASK47 | |
| 1702 | MCF_INTC_IMRH_INT_MASK48 ); |
| 1703 | |
| 1704 | /* Set up gpio outputs for MII lines */ |
| 1705 | MCF_GPIO_PAR_FECI2C |= (0 | |
| 1706 | MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC | |
| 1707 | MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO); |
| 1708 | MCF_GPIO_PAR_FEC = (0 | |
| 1709 | MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | |
| 1710 | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC); |
| 1711 | } |
| 1712 | |
| 1713 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) |
| 1714 | { |
| 1715 | volatile fec_t *fecp; |
| 1716 | |
| 1717 | fecp = fep->hwp; |
| 1718 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; |
| 1719 | fecp->fec_x_cntrl = 0x00; |
| 1720 | |
| 1721 | /* |
| 1722 | * Set MII speed to 2.5 MHz |
| 1723 | */ |
| 1724 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; |
| 1725 | fecp->fec_mii_speed = fep->phy_speed; |
| 1726 | |
| 1727 | fec_restart(dev, 0); |
| 1728 | } |
| 1729 | |
| 1730 | static void __inline__ fec_get_mac(struct net_device *dev) |
| 1731 | { |
| 1732 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1733 | volatile fec_t *fecp; |
| 1734 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
| 1735 | |
| 1736 | fecp = fep->hwp; |
| 1737 | |
| 1738 | if (FEC_FLASHMAC) { |
| 1739 | /* |
| 1740 | * Get MAC address from FLASH. |
| 1741 | * If it is all 1's or 0's, use the default. |
| 1742 | */ |
| 1743 | iap = FEC_FLASHMAC; |
| 1744 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
| 1745 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) |
| 1746 | iap = fec_mac_default; |
| 1747 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && |
| 1748 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) |
| 1749 | iap = fec_mac_default; |
| 1750 | } else { |
| 1751 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; |
| 1752 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); |
| 1753 | iap = &tmpaddr[0]; |
| 1754 | } |
| 1755 | |
| 1756 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
| 1757 | |
| 1758 | /* Adjust MAC if using default MAC address */ |
| 1759 | if (iap == fec_mac_default) |
| 1760 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; |
| 1761 | } |
| 1762 | |
| 1763 | static void __inline__ fec_enable_phy_intr(void) |
| 1764 | { |
| 1765 | } |
| 1766 | |
| 1767 | static void __inline__ fec_disable_phy_intr(void) |
| 1768 | { |
| 1769 | } |
| 1770 | |
| 1771 | static void __inline__ fec_phy_ack_intr(void) |
| 1772 | { |
| 1773 | } |
| 1774 | |
| 1775 | static void __inline__ fec_localhw_setup(void) |
| 1776 | { |
| 1777 | } |
| 1778 | |
| 1779 | /* |
| 1780 | * Do not need to make region uncached on 532x. |
| 1781 | */ |
| 1782 | static void __inline__ fec_uncache(unsigned long addr) |
| 1783 | { |
| 1784 | } |
| 1785 | |
| 1786 | /* ------------------------------------------------------------------------- */ |
| 1787 | |
| 1788 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1789 | #else |
| 1790 | |
| 1791 | /* |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1792 | * Code specific to the MPC860T setup. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1793 | */ |
| 1794 | static void __inline__ fec_request_intrs(struct net_device *dev) |
| 1795 | { |
| 1796 | volatile immap_t *immap; |
| 1797 | |
| 1798 | immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */ |
| 1799 | |
| 1800 | if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0) |
| 1801 | panic("Could not allocate FEC IRQ!"); |
| 1802 | |
| 1803 | #ifdef CONFIG_RPXCLASSIC |
| 1804 | /* Make Port C, bit 15 an input that causes interrupts. |
| 1805 | */ |
| 1806 | immap->im_ioport.iop_pcpar &= ~0x0001; |
| 1807 | immap->im_ioport.iop_pcdir &= ~0x0001; |
| 1808 | immap->im_ioport.iop_pcso &= ~0x0001; |
| 1809 | immap->im_ioport.iop_pcint |= 0x0001; |
| 1810 | cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev); |
| 1811 | |
| 1812 | /* Make LEDS reflect Link status. |
| 1813 | */ |
| 1814 | *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE; |
| 1815 | #endif |
| 1816 | #ifdef CONFIG_FADS |
| 1817 | if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0) |
| 1818 | panic("Could not allocate MII IRQ!"); |
| 1819 | #endif |
| 1820 | } |
| 1821 | |
| 1822 | static void __inline__ fec_get_mac(struct net_device *dev) |
| 1823 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1824 | bd_t *bd; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1825 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1826 | bd = (bd_t *)__res; |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1827 | memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1828 | |
| 1829 | #ifdef CONFIG_RPXCLASSIC |
| 1830 | /* The Embedded Planet boards have only one MAC address in |
| 1831 | * the EEPROM, but can have two Ethernet ports. For the |
| 1832 | * FEC port, we create another address by setting one of |
| 1833 | * the address bits above something that would have (up to |
| 1834 | * now) been allocated. |
| 1835 | */ |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1836 | dev->dev_adrd[3] |= 0x80; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1837 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1838 | } |
| 1839 | |
| 1840 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) |
| 1841 | { |
| 1842 | extern uint _get_IMMR(void); |
| 1843 | volatile immap_t *immap; |
| 1844 | volatile fec_t *fecp; |
| 1845 | |
| 1846 | fecp = fep->hwp; |
| 1847 | immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */ |
| 1848 | |
| 1849 | /* Configure all of port D for MII. |
| 1850 | */ |
| 1851 | immap->im_ioport.iop_pdpar = 0x1fff; |
| 1852 | |
| 1853 | /* Bits moved from Rev. D onward. |
| 1854 | */ |
| 1855 | if ((_get_IMMR() & 0xffff) < 0x0501) |
| 1856 | immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ |
| 1857 | else |
| 1858 | immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ |
| 1859 | |
| 1860 | /* Set MII speed to 2.5 MHz |
| 1861 | */ |
| 1862 | fecp->fec_mii_speed = fep->phy_speed = |
| 1863 | ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e; |
| 1864 | } |
| 1865 | |
| 1866 | static void __inline__ fec_enable_phy_intr(void) |
| 1867 | { |
| 1868 | volatile fec_t *fecp; |
| 1869 | |
| 1870 | fecp = fep->hwp; |
| 1871 | |
| 1872 | /* Enable MII command finished interrupt |
| 1873 | */ |
| 1874 | fecp->fec_ivec = (FEC_INTERRUPT/2) << 29; |
| 1875 | } |
| 1876 | |
| 1877 | static void __inline__ fec_disable_phy_intr(void) |
| 1878 | { |
| 1879 | } |
| 1880 | |
| 1881 | static void __inline__ fec_phy_ack_intr(void) |
| 1882 | { |
| 1883 | } |
| 1884 | |
| 1885 | static void __inline__ fec_localhw_setup(void) |
| 1886 | { |
| 1887 | volatile fec_t *fecp; |
| 1888 | |
| 1889 | fecp = fep->hwp; |
| 1890 | fecp->fec_r_hash = PKT_MAXBUF_SIZE; |
| 1891 | /* Enable big endian and don't care about SDMA FC. |
| 1892 | */ |
| 1893 | fecp->fec_fun_code = 0x78000000; |
| 1894 | } |
| 1895 | |
| 1896 | static void __inline__ fec_uncache(unsigned long addr) |
| 1897 | { |
| 1898 | pte_t *pte; |
| 1899 | pte = va_to_pte(mem_addr); |
| 1900 | pte_val(*pte) |= _PAGE_NO_CACHE; |
| 1901 | flush_tlb_page(init_mm.mmap, mem_addr); |
| 1902 | } |
| 1903 | |
| 1904 | #endif |
| 1905 | |
| 1906 | /* ------------------------------------------------------------------------- */ |
| 1907 | |
| 1908 | static void mii_display_status(struct net_device *dev) |
| 1909 | { |
| 1910 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1911 | volatile uint *s = &(fep->phy_status); |
| 1912 | |
| 1913 | if (!fep->link && !fep->old_link) { |
| 1914 | /* Link is still down - don't print anything */ |
| 1915 | return; |
| 1916 | } |
| 1917 | |
| 1918 | printk("%s: status: ", dev->name); |
| 1919 | |
| 1920 | if (!fep->link) { |
| 1921 | printk("link down"); |
| 1922 | } else { |
| 1923 | printk("link up"); |
| 1924 | |
| 1925 | switch(*s & PHY_STAT_SPMASK) { |
| 1926 | case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break; |
| 1927 | case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break; |
| 1928 | case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break; |
| 1929 | case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break; |
| 1930 | default: |
| 1931 | printk(", Unknown speed/duplex"); |
| 1932 | } |
| 1933 | |
| 1934 | if (*s & PHY_STAT_ANC) |
| 1935 | printk(", auto-negotiation complete"); |
| 1936 | } |
| 1937 | |
| 1938 | if (*s & PHY_STAT_FAULT) |
| 1939 | printk(", remote fault"); |
| 1940 | |
| 1941 | printk(".\n"); |
| 1942 | } |
| 1943 | |
| 1944 | static void mii_display_config(struct net_device *dev) |
| 1945 | { |
| 1946 | struct fec_enet_private *fep = netdev_priv(dev); |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1947 | uint status = fep->phy_status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1948 | |
| 1949 | /* |
| 1950 | ** When we get here, phy_task is already removed from |
| 1951 | ** the workqueue. It is thus safe to allow to reuse it. |
| 1952 | */ |
| 1953 | fep->mii_phy_task_queued = 0; |
| 1954 | printk("%s: config: auto-negotiation ", dev->name); |
| 1955 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1956 | if (status & PHY_CONF_ANE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1957 | printk("on"); |
| 1958 | else |
| 1959 | printk("off"); |
| 1960 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1961 | if (status & PHY_CONF_100FDX) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1962 | printk(", 100FDX"); |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1963 | if (status & PHY_CONF_100HDX) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1964 | printk(", 100HDX"); |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1965 | if (status & PHY_CONF_10FDX) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1966 | printk(", 10FDX"); |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1967 | if (status & PHY_CONF_10HDX) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1968 | printk(", 10HDX"); |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1969 | if (!(status & PHY_CONF_SPMASK)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1970 | printk(", No speed/duplex selected?"); |
| 1971 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 1972 | if (status & PHY_CONF_LOOP) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1973 | printk(", loopback enabled"); |
| 1974 | |
| 1975 | printk(".\n"); |
| 1976 | |
| 1977 | fep->sequence_done = 1; |
| 1978 | } |
| 1979 | |
| 1980 | static void mii_relink(struct net_device *dev) |
| 1981 | { |
| 1982 | struct fec_enet_private *fep = netdev_priv(dev); |
| 1983 | int duplex; |
| 1984 | |
| 1985 | /* |
| 1986 | ** When we get here, phy_task is already removed from |
| 1987 | ** the workqueue. It is thus safe to allow to reuse it. |
| 1988 | */ |
| 1989 | fep->mii_phy_task_queued = 0; |
| 1990 | fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0; |
| 1991 | mii_display_status(dev); |
| 1992 | fep->old_link = fep->link; |
| 1993 | |
| 1994 | if (fep->link) { |
| 1995 | duplex = 0; |
| 1996 | if (fep->phy_status |
| 1997 | & (PHY_STAT_100FDX | PHY_STAT_10FDX)) |
| 1998 | duplex = 1; |
| 1999 | fec_restart(dev, duplex); |
| 2000 | } |
| 2001 | else |
| 2002 | fec_stop(dev); |
| 2003 | |
| 2004 | #if 0 |
| 2005 | enable_irq(fep->mii_irq); |
| 2006 | #endif |
| 2007 | |
| 2008 | } |
| 2009 | |
| 2010 | /* mii_queue_relink is called in interrupt context from mii_link_interrupt */ |
| 2011 | static void mii_queue_relink(uint mii_reg, struct net_device *dev) |
| 2012 | { |
| 2013 | struct fec_enet_private *fep = netdev_priv(dev); |
| 2014 | |
| 2015 | /* |
| 2016 | ** We cannot queue phy_task twice in the workqueue. It |
| 2017 | ** would cause an endless loop in the workqueue. |
| 2018 | ** Fortunately, if the last mii_relink entry has not yet been |
| 2019 | ** executed now, it will do the job for the current interrupt, |
| 2020 | ** which is just what we want. |
| 2021 | */ |
| 2022 | if (fep->mii_phy_task_queued) |
| 2023 | return; |
| 2024 | |
| 2025 | fep->mii_phy_task_queued = 1; |
| 2026 | INIT_WORK(&fep->phy_task, (void*)mii_relink, dev); |
| 2027 | schedule_work(&fep->phy_task); |
| 2028 | } |
| 2029 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 2030 | /* mii_queue_config is called in interrupt context from fec_enet_mii */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2031 | static void mii_queue_config(uint mii_reg, struct net_device *dev) |
| 2032 | { |
| 2033 | struct fec_enet_private *fep = netdev_priv(dev); |
| 2034 | |
| 2035 | if (fep->mii_phy_task_queued) |
| 2036 | return; |
| 2037 | |
| 2038 | fep->mii_phy_task_queued = 1; |
| 2039 | INIT_WORK(&fep->phy_task, (void*)mii_display_config, dev); |
| 2040 | schedule_work(&fep->phy_task); |
| 2041 | } |
| 2042 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 2043 | phy_cmd_t const phy_cmd_relink[] = { |
| 2044 | { mk_mii_read(MII_REG_CR), mii_queue_relink }, |
| 2045 | { mk_mii_end, } |
| 2046 | }; |
| 2047 | phy_cmd_t const phy_cmd_config[] = { |
| 2048 | { mk_mii_read(MII_REG_CR), mii_queue_config }, |
| 2049 | { mk_mii_end, } |
| 2050 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2051 | |
| 2052 | /* Read remainder of PHY ID. |
| 2053 | */ |
| 2054 | static void |
| 2055 | mii_discover_phy3(uint mii_reg, struct net_device *dev) |
| 2056 | { |
| 2057 | struct fec_enet_private *fep; |
| 2058 | int i; |
| 2059 | |
| 2060 | fep = netdev_priv(dev); |
| 2061 | fep->phy_id |= (mii_reg & 0xffff); |
| 2062 | printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id); |
| 2063 | |
| 2064 | for(i = 0; phy_info[i]; i++) { |
| 2065 | if(phy_info[i]->id == (fep->phy_id >> 4)) |
| 2066 | break; |
| 2067 | } |
| 2068 | |
| 2069 | if (phy_info[i]) |
| 2070 | printk(" -- %s\n", phy_info[i]->name); |
| 2071 | else |
| 2072 | printk(" -- unknown PHY!\n"); |
| 2073 | |
| 2074 | fep->phy = phy_info[i]; |
| 2075 | fep->phy_id_done = 1; |
| 2076 | } |
| 2077 | |
| 2078 | /* Scan all of the MII PHY addresses looking for someone to respond |
| 2079 | * with a valid ID. This usually happens quickly. |
| 2080 | */ |
| 2081 | static void |
| 2082 | mii_discover_phy(uint mii_reg, struct net_device *dev) |
| 2083 | { |
| 2084 | struct fec_enet_private *fep; |
| 2085 | volatile fec_t *fecp; |
| 2086 | uint phytype; |
| 2087 | |
| 2088 | fep = netdev_priv(dev); |
| 2089 | fecp = fep->hwp; |
| 2090 | |
| 2091 | if (fep->phy_addr < 32) { |
| 2092 | if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) { |
| 2093 | |
| 2094 | /* Got first part of ID, now get remainder. |
| 2095 | */ |
| 2096 | fep->phy_id = phytype << 16; |
| 2097 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), |
| 2098 | mii_discover_phy3); |
| 2099 | } |
| 2100 | else { |
| 2101 | fep->phy_addr++; |
| 2102 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), |
| 2103 | mii_discover_phy); |
| 2104 | } |
| 2105 | } else { |
| 2106 | printk("FEC: No PHY device found.\n"); |
| 2107 | /* Disable external MII interface */ |
| 2108 | fecp->fec_mii_speed = fep->phy_speed = 0; |
| 2109 | fec_disable_phy_intr(); |
| 2110 | } |
| 2111 | } |
| 2112 | |
| 2113 | /* This interrupt occurs when the PHY detects a link change. |
| 2114 | */ |
| 2115 | #ifdef CONFIG_RPXCLASSIC |
| 2116 | static void |
| 2117 | mii_link_interrupt(void *dev_id) |
| 2118 | #else |
| 2119 | static irqreturn_t |
| 2120 | mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs) |
| 2121 | #endif |
| 2122 | { |
| 2123 | struct net_device *dev = dev_id; |
| 2124 | struct fec_enet_private *fep = netdev_priv(dev); |
| 2125 | |
| 2126 | fec_phy_ack_intr(); |
| 2127 | |
| 2128 | #if 0 |
| 2129 | disable_irq(fep->mii_irq); /* disable now, enable later */ |
| 2130 | #endif |
| 2131 | |
| 2132 | mii_do_cmd(dev, fep->phy->ack_int); |
| 2133 | mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */ |
| 2134 | |
| 2135 | return IRQ_HANDLED; |
| 2136 | } |
| 2137 | |
| 2138 | static int |
| 2139 | fec_enet_open(struct net_device *dev) |
| 2140 | { |
| 2141 | struct fec_enet_private *fep = netdev_priv(dev); |
| 2142 | |
| 2143 | /* I should reset the ring buffers here, but I don't yet know |
| 2144 | * a simple way to do that. |
| 2145 | */ |
| 2146 | fec_set_mac_address(dev); |
| 2147 | |
| 2148 | fep->sequence_done = 0; |
| 2149 | fep->link = 0; |
| 2150 | |
| 2151 | if (fep->phy) { |
| 2152 | mii_do_cmd(dev, fep->phy->ack_int); |
| 2153 | mii_do_cmd(dev, fep->phy->config); |
| 2154 | mii_do_cmd(dev, phy_cmd_config); /* display configuration */ |
| 2155 | |
Matt Waddel | 6b26529 | 2006-06-27 13:10:56 +1000 | [diff] [blame] | 2156 | /* Poll until the PHY tells us its configuration |
| 2157 | * (not link state). |
| 2158 | * Request is initiated by mii_do_cmd above, but answer |
| 2159 | * comes by interrupt. |
| 2160 | * This should take about 25 usec per register at 2.5 MHz, |
| 2161 | * and we read approximately 5 registers. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2162 | */ |
| 2163 | while(!fep->sequence_done) |
| 2164 | schedule(); |
| 2165 | |
| 2166 | mii_do_cmd(dev, fep->phy->startup); |
| 2167 | |
| 2168 | /* Set the initial link state to true. A lot of hardware |
| 2169 | * based on this device does not implement a PHY interrupt, |
| 2170 | * so we are never notified of link change. |
| 2171 | */ |
| 2172 | fep->link = 1; |
| 2173 | } else { |
| 2174 | fep->link = 1; /* lets just try it and see */ |
| 2175 | /* no phy, go full duplex, it's most likely a hub chip */ |
| 2176 | fec_restart(dev, 1); |
| 2177 | } |
| 2178 | |
| 2179 | netif_start_queue(dev); |
| 2180 | fep->opened = 1; |
| 2181 | return 0; /* Success */ |
| 2182 | } |
| 2183 | |
| 2184 | static int |
| 2185 | fec_enet_close(struct net_device *dev) |
| 2186 | { |
| 2187 | struct fec_enet_private *fep = netdev_priv(dev); |
| 2188 | |
| 2189 | /* Don't know what to do yet. |
| 2190 | */ |
| 2191 | fep->opened = 0; |
| 2192 | netif_stop_queue(dev); |
| 2193 | fec_stop(dev); |
| 2194 | |
| 2195 | return 0; |
| 2196 | } |
| 2197 | |
| 2198 | static struct net_device_stats *fec_enet_get_stats(struct net_device *dev) |
| 2199 | { |
| 2200 | struct fec_enet_private *fep = netdev_priv(dev); |
| 2201 | |
| 2202 | return &fep->stats; |
| 2203 | } |
| 2204 | |
| 2205 | /* Set or clear the multicast filter for this adaptor. |
| 2206 | * Skeleton taken from sunlance driver. |
| 2207 | * The CPM Ethernet implementation allows Multicast as well as individual |
| 2208 | * MAC address filtering. Some of the drivers check to make sure it is |
| 2209 | * a group multicast address, and discard those that are not. I guess I |
| 2210 | * will do the same for now, but just remove the test if you want |
| 2211 | * individual filtering as well (do the upper net layers want or support |
| 2212 | * this kind of feature?). |
| 2213 | */ |
| 2214 | |
| 2215 | #define HASH_BITS 6 /* #bits in hash */ |
| 2216 | #define CRC32_POLY 0xEDB88320 |
| 2217 | |
| 2218 | static void set_multicast_list(struct net_device *dev) |
| 2219 | { |
| 2220 | struct fec_enet_private *fep; |
| 2221 | volatile fec_t *ep; |
| 2222 | struct dev_mc_list *dmi; |
| 2223 | unsigned int i, j, bit, data, crc; |
| 2224 | unsigned char hash; |
| 2225 | |
| 2226 | fep = netdev_priv(dev); |
| 2227 | ep = fep->hwp; |
| 2228 | |
| 2229 | if (dev->flags&IFF_PROMISC) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2230 | ep->fec_r_cntrl |= 0x0008; |
| 2231 | } else { |
| 2232 | |
| 2233 | ep->fec_r_cntrl &= ~0x0008; |
| 2234 | |
| 2235 | if (dev->flags & IFF_ALLMULTI) { |
| 2236 | /* Catch all multicast addresses, so set the |
| 2237 | * filter to all 1's. |
| 2238 | */ |
| 2239 | ep->fec_hash_table_high = 0xffffffff; |
| 2240 | ep->fec_hash_table_low = 0xffffffff; |
| 2241 | } else { |
| 2242 | /* Clear filter and add the addresses in hash register. |
| 2243 | */ |
| 2244 | ep->fec_hash_table_high = 0; |
| 2245 | ep->fec_hash_table_low = 0; |
| 2246 | |
| 2247 | dmi = dev->mc_list; |
| 2248 | |
| 2249 | for (j = 0; j < dev->mc_count; j++, dmi = dmi->next) |
| 2250 | { |
| 2251 | /* Only support group multicast for now. |
| 2252 | */ |
| 2253 | if (!(dmi->dmi_addr[0] & 1)) |
| 2254 | continue; |
| 2255 | |
| 2256 | /* calculate crc32 value of mac address |
| 2257 | */ |
| 2258 | crc = 0xffffffff; |
| 2259 | |
| 2260 | for (i = 0; i < dmi->dmi_addrlen; i++) |
| 2261 | { |
| 2262 | data = dmi->dmi_addr[i]; |
| 2263 | for (bit = 0; bit < 8; bit++, data >>= 1) |
| 2264 | { |
| 2265 | crc = (crc >> 1) ^ |
| 2266 | (((crc ^ data) & 1) ? CRC32_POLY : 0); |
| 2267 | } |
| 2268 | } |
| 2269 | |
| 2270 | /* only upper 6 bits (HASH_BITS) are used |
| 2271 | which point to specific bit in he hash registers |
| 2272 | */ |
| 2273 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; |
| 2274 | |
| 2275 | if (hash > 31) |
| 2276 | ep->fec_hash_table_high |= 1 << (hash - 32); |
| 2277 | else |
| 2278 | ep->fec_hash_table_low |= 1 << hash; |
| 2279 | } |
| 2280 | } |
| 2281 | } |
| 2282 | } |
| 2283 | |
| 2284 | /* Set a MAC change in hardware. |
| 2285 | */ |
| 2286 | static void |
| 2287 | fec_set_mac_address(struct net_device *dev) |
| 2288 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2289 | volatile fec_t *fecp; |
| 2290 | |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 2291 | fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2292 | |
| 2293 | /* Set station address. */ |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 2294 | fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) | |
| 2295 | (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24); |
| 2296 | fecp->fec_addr_high = (dev->dev_addr[5] << 16) | |
| 2297 | (dev->dev_addr[4] << 24); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2298 | |
| 2299 | } |
| 2300 | |
| 2301 | /* Initialize the FEC Ethernet on 860T (or ColdFire 5272). |
| 2302 | */ |
| 2303 | /* |
| 2304 | * XXX: We need to clean up on failure exits here. |
| 2305 | */ |
| 2306 | int __init fec_enet_init(struct net_device *dev) |
| 2307 | { |
| 2308 | struct fec_enet_private *fep = netdev_priv(dev); |
| 2309 | unsigned long mem_addr; |
| 2310 | volatile cbd_t *bdp; |
| 2311 | cbd_t *cbd_base; |
| 2312 | volatile fec_t *fecp; |
| 2313 | int i, j; |
| 2314 | static int index = 0; |
| 2315 | |
| 2316 | /* Only allow us to be probed once. */ |
| 2317 | if (index >= FEC_MAX_PORTS) |
| 2318 | return -ENXIO; |
| 2319 | |
Greg Ungerer | 562d2f8 | 2005-11-07 14:09:50 +1000 | [diff] [blame] | 2320 | /* Allocate memory for buffer descriptors. |
| 2321 | */ |
| 2322 | mem_addr = __get_free_page(GFP_KERNEL); |
| 2323 | if (mem_addr == 0) { |
| 2324 | printk("FEC: allocate descriptor memory failed?\n"); |
| 2325 | return -ENOMEM; |
| 2326 | } |
| 2327 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2328 | /* Create an Ethernet device instance. |
| 2329 | */ |
| 2330 | fecp = (volatile fec_t *) fec_hw[index]; |
| 2331 | |
| 2332 | fep->index = index; |
| 2333 | fep->hwp = fecp; |
| 2334 | |
| 2335 | /* Whack a reset. We should wait for this. |
| 2336 | */ |
| 2337 | fecp->fec_ecntrl = 1; |
| 2338 | udelay(10); |
| 2339 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2340 | /* Set the Ethernet address. If using multiple Enets on the 8xx, |
| 2341 | * this needs some work to get unique addresses. |
| 2342 | * |
| 2343 | * This is our default MAC address unless the user changes |
| 2344 | * it via eth_mac_addr (our dev->set_mac_addr handler). |
| 2345 | */ |
| 2346 | fec_get_mac(dev); |
| 2347 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2348 | cbd_base = (cbd_t *)mem_addr; |
| 2349 | /* XXX: missing check for allocation failure */ |
| 2350 | |
| 2351 | fec_uncache(mem_addr); |
| 2352 | |
| 2353 | /* Set receive and transmit descriptor base. |
| 2354 | */ |
| 2355 | fep->rx_bd_base = cbd_base; |
| 2356 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; |
| 2357 | |
| 2358 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; |
| 2359 | fep->cur_rx = fep->rx_bd_base; |
| 2360 | |
| 2361 | fep->skb_cur = fep->skb_dirty = 0; |
| 2362 | |
| 2363 | /* Initialize the receive buffer descriptors. |
| 2364 | */ |
| 2365 | bdp = fep->rx_bd_base; |
| 2366 | for (i=0; i<FEC_ENET_RX_PAGES; i++) { |
| 2367 | |
| 2368 | /* Allocate a page. |
| 2369 | */ |
| 2370 | mem_addr = __get_free_page(GFP_KERNEL); |
| 2371 | /* XXX: missing check for allocation failure */ |
| 2372 | |
| 2373 | fec_uncache(mem_addr); |
| 2374 | |
| 2375 | /* Initialize the BD for every fragment in the page. |
| 2376 | */ |
| 2377 | for (j=0; j<FEC_ENET_RX_FRPPG; j++) { |
| 2378 | bdp->cbd_sc = BD_ENET_RX_EMPTY; |
| 2379 | bdp->cbd_bufaddr = __pa(mem_addr); |
| 2380 | mem_addr += FEC_ENET_RX_FRSIZE; |
| 2381 | bdp++; |
| 2382 | } |
| 2383 | } |
| 2384 | |
| 2385 | /* Set the last buffer to wrap. |
| 2386 | */ |
| 2387 | bdp--; |
| 2388 | bdp->cbd_sc |= BD_SC_WRAP; |
| 2389 | |
| 2390 | /* ...and the same for transmmit. |
| 2391 | */ |
| 2392 | bdp = fep->tx_bd_base; |
| 2393 | for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) { |
| 2394 | if (j >= FEC_ENET_TX_FRPPG) { |
| 2395 | mem_addr = __get_free_page(GFP_KERNEL); |
| 2396 | j = 1; |
| 2397 | } else { |
| 2398 | mem_addr += FEC_ENET_TX_FRSIZE; |
| 2399 | j++; |
| 2400 | } |
| 2401 | fep->tx_bounce[i] = (unsigned char *) mem_addr; |
| 2402 | |
| 2403 | /* Initialize the BD for every fragment in the page. |
| 2404 | */ |
| 2405 | bdp->cbd_sc = 0; |
| 2406 | bdp->cbd_bufaddr = 0; |
| 2407 | bdp++; |
| 2408 | } |
| 2409 | |
| 2410 | /* Set the last buffer to wrap. |
| 2411 | */ |
| 2412 | bdp--; |
| 2413 | bdp->cbd_sc |= BD_SC_WRAP; |
| 2414 | |
| 2415 | /* Set receive and transmit descriptor base. |
| 2416 | */ |
| 2417 | fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base)); |
| 2418 | fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base)); |
| 2419 | |
| 2420 | /* Install our interrupt handlers. This varies depending on |
| 2421 | * the architecture. |
| 2422 | */ |
| 2423 | fec_request_intrs(dev); |
| 2424 | |
Greg Ungerer | 562d2f8 | 2005-11-07 14:09:50 +1000 | [diff] [blame] | 2425 | fecp->fec_hash_table_high = 0; |
| 2426 | fecp->fec_hash_table_low = 0; |
| 2427 | fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; |
| 2428 | fecp->fec_ecntrl = 2; |
Matt Waddel | 6b26529 | 2006-06-27 13:10:56 +1000 | [diff] [blame] | 2429 | fecp->fec_r_des_active = 0; |
Greg Ungerer | 562d2f8 | 2005-11-07 14:09:50 +1000 | [diff] [blame] | 2430 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2431 | dev->base_addr = (unsigned long)fecp; |
| 2432 | |
| 2433 | /* The FEC Ethernet specific entries in the device structure. */ |
| 2434 | dev->open = fec_enet_open; |
| 2435 | dev->hard_start_xmit = fec_enet_start_xmit; |
| 2436 | dev->tx_timeout = fec_timeout; |
| 2437 | dev->watchdog_timeo = TX_TIMEOUT; |
| 2438 | dev->stop = fec_enet_close; |
| 2439 | dev->get_stats = fec_enet_get_stats; |
| 2440 | dev->set_multicast_list = set_multicast_list; |
| 2441 | |
| 2442 | for (i=0; i<NMII-1; i++) |
| 2443 | mii_cmds[i].mii_next = &mii_cmds[i+1]; |
| 2444 | mii_free = mii_cmds; |
| 2445 | |
| 2446 | /* setup MII interface */ |
| 2447 | fec_set_mii(dev, fep); |
| 2448 | |
Matt Waddel | 6b26529 | 2006-06-27 13:10:56 +1000 | [diff] [blame] | 2449 | /* Clear and enable interrupts */ |
| 2450 | fecp->fec_ievent = 0xffc00000; |
| 2451 | fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB | |
| 2452 | FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII); |
| 2453 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2454 | /* Queue up command to detect the PHY and initialize the |
| 2455 | * remainder of the interface. |
| 2456 | */ |
| 2457 | fep->phy_id_done = 0; |
| 2458 | fep->phy_addr = 0; |
| 2459 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy); |
| 2460 | |
| 2461 | index++; |
| 2462 | return 0; |
| 2463 | } |
| 2464 | |
| 2465 | /* This function is called to start or restart the FEC during a link |
| 2466 | * change. This only happens when switching between half and full |
| 2467 | * duplex. |
| 2468 | */ |
| 2469 | static void |
| 2470 | fec_restart(struct net_device *dev, int duplex) |
| 2471 | { |
| 2472 | struct fec_enet_private *fep; |
| 2473 | volatile cbd_t *bdp; |
| 2474 | volatile fec_t *fecp; |
| 2475 | int i; |
| 2476 | |
| 2477 | fep = netdev_priv(dev); |
| 2478 | fecp = fep->hwp; |
| 2479 | |
| 2480 | /* Whack a reset. We should wait for this. |
| 2481 | */ |
| 2482 | fecp->fec_ecntrl = 1; |
| 2483 | udelay(10); |
| 2484 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2485 | /* Clear any outstanding interrupt. |
| 2486 | */ |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 2487 | fecp->fec_ievent = 0xffc00000; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2488 | fec_enable_phy_intr(); |
| 2489 | |
| 2490 | /* Set station address. |
| 2491 | */ |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 2492 | fec_set_mac_address(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2493 | |
| 2494 | /* Reset all multicast. |
| 2495 | */ |
| 2496 | fecp->fec_hash_table_high = 0; |
| 2497 | fecp->fec_hash_table_low = 0; |
| 2498 | |
| 2499 | /* Set maximum receive buffer size. |
| 2500 | */ |
| 2501 | fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; |
| 2502 | |
| 2503 | fec_localhw_setup(); |
| 2504 | |
| 2505 | /* Set receive and transmit descriptor base. |
| 2506 | */ |
| 2507 | fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base)); |
| 2508 | fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base)); |
| 2509 | |
| 2510 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; |
| 2511 | fep->cur_rx = fep->rx_bd_base; |
| 2512 | |
| 2513 | /* Reset SKB transmit buffers. |
| 2514 | */ |
| 2515 | fep->skb_cur = fep->skb_dirty = 0; |
| 2516 | for (i=0; i<=TX_RING_MOD_MASK; i++) { |
| 2517 | if (fep->tx_skbuff[i] != NULL) { |
| 2518 | dev_kfree_skb_any(fep->tx_skbuff[i]); |
| 2519 | fep->tx_skbuff[i] = NULL; |
| 2520 | } |
| 2521 | } |
| 2522 | |
| 2523 | /* Initialize the receive buffer descriptors. |
| 2524 | */ |
| 2525 | bdp = fep->rx_bd_base; |
| 2526 | for (i=0; i<RX_RING_SIZE; i++) { |
| 2527 | |
| 2528 | /* Initialize the BD for every fragment in the page. |
| 2529 | */ |
| 2530 | bdp->cbd_sc = BD_ENET_RX_EMPTY; |
| 2531 | bdp++; |
| 2532 | } |
| 2533 | |
| 2534 | /* Set the last buffer to wrap. |
| 2535 | */ |
| 2536 | bdp--; |
| 2537 | bdp->cbd_sc |= BD_SC_WRAP; |
| 2538 | |
| 2539 | /* ...and the same for transmmit. |
| 2540 | */ |
| 2541 | bdp = fep->tx_bd_base; |
| 2542 | for (i=0; i<TX_RING_SIZE; i++) { |
| 2543 | |
| 2544 | /* Initialize the BD for every fragment in the page. |
| 2545 | */ |
| 2546 | bdp->cbd_sc = 0; |
| 2547 | bdp->cbd_bufaddr = 0; |
| 2548 | bdp++; |
| 2549 | } |
| 2550 | |
| 2551 | /* Set the last buffer to wrap. |
| 2552 | */ |
| 2553 | bdp--; |
| 2554 | bdp->cbd_sc |= BD_SC_WRAP; |
| 2555 | |
| 2556 | /* Enable MII mode. |
| 2557 | */ |
| 2558 | if (duplex) { |
| 2559 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */ |
| 2560 | fecp->fec_x_cntrl = 0x04; /* FD enable */ |
| 2561 | } |
| 2562 | else { |
| 2563 | /* MII enable|No Rcv on Xmit */ |
| 2564 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06; |
| 2565 | fecp->fec_x_cntrl = 0x00; |
| 2566 | } |
| 2567 | fep->full_duplex = duplex; |
| 2568 | |
| 2569 | /* Set MII speed. |
| 2570 | */ |
| 2571 | fecp->fec_mii_speed = fep->phy_speed; |
| 2572 | |
| 2573 | /* And last, enable the transmit and receive processing. |
| 2574 | */ |
| 2575 | fecp->fec_ecntrl = 2; |
Matt Waddel | 6b26529 | 2006-06-27 13:10:56 +1000 | [diff] [blame] | 2576 | fecp->fec_r_des_active = 0; |
| 2577 | |
| 2578 | /* Enable interrupts we wish to service. |
| 2579 | */ |
| 2580 | fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB | |
| 2581 | FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2582 | } |
| 2583 | |
| 2584 | static void |
| 2585 | fec_stop(struct net_device *dev) |
| 2586 | { |
| 2587 | volatile fec_t *fecp; |
| 2588 | struct fec_enet_private *fep; |
| 2589 | |
| 2590 | fep = netdev_priv(dev); |
| 2591 | fecp = fep->hwp; |
| 2592 | |
Philippe De Muyter | 677177c | 2006-06-27 13:05:33 +1000 | [diff] [blame] | 2593 | /* |
| 2594 | ** We cannot expect a graceful transmit stop without link !!! |
| 2595 | */ |
| 2596 | if (fep->link) |
| 2597 | { |
| 2598 | fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */ |
| 2599 | udelay(10); |
| 2600 | if (!(fecp->fec_ievent & FEC_ENET_GRA)) |
| 2601 | printk("fec_stop : Graceful transmit stop did not complete !\n"); |
| 2602 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2603 | |
| 2604 | /* Whack a reset. We should wait for this. |
| 2605 | */ |
| 2606 | fecp->fec_ecntrl = 1; |
| 2607 | udelay(10); |
| 2608 | |
| 2609 | /* Clear outstanding MII command interrupts. |
| 2610 | */ |
| 2611 | fecp->fec_ievent = FEC_ENET_MII; |
| 2612 | fec_enable_phy_intr(); |
| 2613 | |
| 2614 | fecp->fec_imask = FEC_ENET_MII; |
| 2615 | fecp->fec_mii_speed = fep->phy_speed; |
| 2616 | } |
| 2617 | |
| 2618 | static int __init fec_enet_module_init(void) |
| 2619 | { |
| 2620 | struct net_device *dev; |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 2621 | int i, j, err; |
| 2622 | |
| 2623 | printk("FEC ENET Version 0.2\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2624 | |
| 2625 | for (i = 0; (i < FEC_MAX_PORTS); i++) { |
| 2626 | dev = alloc_etherdev(sizeof(struct fec_enet_private)); |
| 2627 | if (!dev) |
| 2628 | return -ENOMEM; |
| 2629 | err = fec_enet_init(dev); |
| 2630 | if (err) { |
| 2631 | free_netdev(dev); |
| 2632 | continue; |
| 2633 | } |
| 2634 | if (register_netdev(dev) != 0) { |
| 2635 | /* XXX: missing cleanup here */ |
| 2636 | free_netdev(dev); |
| 2637 | return -EIO; |
| 2638 | } |
Greg Ungerer | 7dd6a2a | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 2639 | |
| 2640 | printk("%s: ethernet ", dev->name); |
| 2641 | for (j = 0; (j < 5); j++) |
| 2642 | printk("%02x:", dev->dev_addr[j]); |
| 2643 | printk("%02x\n", dev->dev_addr[5]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2644 | } |
| 2645 | return 0; |
| 2646 | } |
| 2647 | |
| 2648 | module_init(fec_enet_module_init); |
| 2649 | |
| 2650 | MODULE_LICENSE("GPL"); |