blob: 2bd0511511e4cc78114817311866e48085997c85 [file] [log] [blame]
Ben Skeggs4b223ee2010-08-03 10:00:56 +10001/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26
27#include "nouveau_drv.h"
Ben Skeggsb2b09932010-11-24 10:47:15 +100028#include "nouveau_mm.h"
29
30static void nvc0_fifo_isr(struct drm_device *);
31
32struct nvc0_fifo_priv {
33 struct nouveau_gpuobj *playlist[2];
34 int cur_playlist;
35 struct nouveau_vma user_vma;
Ben Skeggsec9c0882010-12-31 12:10:49 +100036 int spoon_nr;
Ben Skeggsb2b09932010-11-24 10:47:15 +100037};
38
39struct nvc0_fifo_chan {
40 struct nouveau_bo *user;
41 struct nouveau_gpuobj *ramfc;
42};
43
44static void
45nvc0_fifo_playlist_update(struct drm_device *dev)
46{
47 struct drm_nouveau_private *dev_priv = dev->dev_private;
48 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
49 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
50 struct nvc0_fifo_priv *priv = pfifo->priv;
51 struct nouveau_gpuobj *cur;
52 int i, p;
53
54 cur = priv->playlist[priv->cur_playlist];
55 priv->cur_playlist = !priv->cur_playlist;
56
57 for (i = 0, p = 0; i < 128; i++) {
58 if (!(nv_rd32(dev, 0x3004 + (i * 8)) & 1))
59 continue;
60 nv_wo32(cur, p + 0, i);
61 nv_wo32(cur, p + 4, 0x00000004);
62 p += 8;
63 }
64 pinstmem->flush(dev);
65
66 nv_wr32(dev, 0x002270, cur->vinst >> 12);
67 nv_wr32(dev, 0x002274, 0x01f00000 | (p >> 3));
68 if (!nv_wait(dev, 0x00227c, 0x00100000, 0x00000000))
69 NV_ERROR(dev, "PFIFO - playlist update failed\n");
70}
Ben Skeggs4b223ee2010-08-03 10:00:56 +100071
72void
73nvc0_fifo_disable(struct drm_device *dev)
74{
75}
76
77void
78nvc0_fifo_enable(struct drm_device *dev)
79{
80}
81
82bool
83nvc0_fifo_reassign(struct drm_device *dev, bool enable)
84{
85 return false;
86}
87
88bool
Ben Skeggs4b223ee2010-08-03 10:00:56 +100089nvc0_fifo_cache_pull(struct drm_device *dev, bool enable)
90{
91 return false;
92}
93
94int
95nvc0_fifo_channel_id(struct drm_device *dev)
96{
97 return 127;
98}
99
100int
101nvc0_fifo_create_context(struct nouveau_channel *chan)
102{
Ben Skeggsb2b09932010-11-24 10:47:15 +1000103 struct drm_device *dev = chan->dev;
104 struct drm_nouveau_private *dev_priv = dev->dev_private;
105 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
106 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
107 struct nvc0_fifo_priv *priv = pfifo->priv;
108 struct nvc0_fifo_chan *fifoch;
109 u64 ib_virt, user_vinst;
110 int ret;
111
112 chan->fifo_priv = kzalloc(sizeof(*fifoch), GFP_KERNEL);
113 if (!chan->fifo_priv)
114 return -ENOMEM;
115 fifoch = chan->fifo_priv;
116
117 /* allocate vram for control regs, map into polling area */
118 ret = nouveau_bo_new(dev, NULL, 0x1000, 0, TTM_PL_FLAG_VRAM,
Ben Skeggsd550c412011-02-16 08:41:56 +1000119 0, 0, &fifoch->user);
Ben Skeggsb2b09932010-11-24 10:47:15 +1000120 if (ret)
121 goto error;
122
123 ret = nouveau_bo_pin(fifoch->user, TTM_PL_FLAG_VRAM);
124 if (ret) {
125 nouveau_bo_ref(NULL, &fifoch->user);
126 goto error;
127 }
128
129 user_vinst = fifoch->user->bo.mem.start << PAGE_SHIFT;
130
131 ret = nouveau_bo_map(fifoch->user);
132 if (ret) {
133 nouveau_bo_unpin(fifoch->user);
134 nouveau_bo_ref(NULL, &fifoch->user);
135 goto error;
136 }
137
138 nouveau_vm_map_at(&priv->user_vma, chan->id * 0x1000,
139 fifoch->user->bo.mem.mm_node);
140
141 chan->user = ioremap_wc(pci_resource_start(dev->pdev, 1) +
142 priv->user_vma.offset + (chan->id * 0x1000),
143 PAGE_SIZE);
144 if (!chan->user) {
145 ret = -ENOMEM;
146 goto error;
147 }
148
149 ib_virt = chan->pushbuf_base + chan->dma.ib_base * 4;
150
151 /* zero channel regs */
152 nouveau_bo_wr32(fifoch->user, 0x0040/4, 0);
153 nouveau_bo_wr32(fifoch->user, 0x0044/4, 0);
154 nouveau_bo_wr32(fifoch->user, 0x0048/4, 0);
155 nouveau_bo_wr32(fifoch->user, 0x004c/4, 0);
156 nouveau_bo_wr32(fifoch->user, 0x0050/4, 0);
157 nouveau_bo_wr32(fifoch->user, 0x0058/4, 0);
158 nouveau_bo_wr32(fifoch->user, 0x005c/4, 0);
159 nouveau_bo_wr32(fifoch->user, 0x0060/4, 0);
160 nouveau_bo_wr32(fifoch->user, 0x0088/4, 0);
161 nouveau_bo_wr32(fifoch->user, 0x008c/4, 0);
162
163 /* ramfc */
164 ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst,
165 chan->ramin->vinst, 0x100,
166 NVOBJ_FLAG_ZERO_ALLOC, &fifoch->ramfc);
167 if (ret)
168 goto error;
169
170 nv_wo32(fifoch->ramfc, 0x08, lower_32_bits(user_vinst));
171 nv_wo32(fifoch->ramfc, 0x0c, upper_32_bits(user_vinst));
172 nv_wo32(fifoch->ramfc, 0x10, 0x0000face);
173 nv_wo32(fifoch->ramfc, 0x30, 0xfffff902);
174 nv_wo32(fifoch->ramfc, 0x48, lower_32_bits(ib_virt));
175 nv_wo32(fifoch->ramfc, 0x4c, drm_order(chan->dma.ib_max + 1) << 16 |
176 upper_32_bits(ib_virt));
177 nv_wo32(fifoch->ramfc, 0x54, 0x00000002);
178 nv_wo32(fifoch->ramfc, 0x84, 0x20400000);
179 nv_wo32(fifoch->ramfc, 0x94, 0x30000001);
180 nv_wo32(fifoch->ramfc, 0x9c, 0x00000100);
181 nv_wo32(fifoch->ramfc, 0xa4, 0x1f1f1f1f);
182 nv_wo32(fifoch->ramfc, 0xa8, 0x1f1f1f1f);
183 nv_wo32(fifoch->ramfc, 0xac, 0x0000001f);
184 nv_wo32(fifoch->ramfc, 0xb8, 0xf8000000);
185 nv_wo32(fifoch->ramfc, 0xf8, 0x10003080); /* 0x002310 */
186 nv_wo32(fifoch->ramfc, 0xfc, 0x10000010); /* 0x002350 */
187 pinstmem->flush(dev);
188
189 nv_wr32(dev, 0x003000 + (chan->id * 8), 0xc0000000 |
190 (chan->ramin->vinst >> 12));
191 nv_wr32(dev, 0x003004 + (chan->id * 8), 0x001f0001);
192 nvc0_fifo_playlist_update(dev);
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000193 return 0;
Ben Skeggsb2b09932010-11-24 10:47:15 +1000194
195error:
196 pfifo->destroy_context(chan);
197 return ret;
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000198}
199
200void
201nvc0_fifo_destroy_context(struct nouveau_channel *chan)
202{
Ben Skeggsb2b09932010-11-24 10:47:15 +1000203 struct drm_device *dev = chan->dev;
204 struct nvc0_fifo_chan *fifoch;
205
206 nv_mask(dev, 0x003004 + (chan->id * 8), 0x00000001, 0x00000000);
207 nv_wr32(dev, 0x002634, chan->id);
208 if (!nv_wait(dev, 0x0002634, 0xffffffff, chan->id))
209 NV_WARN(dev, "0x2634 != chid: 0x%08x\n", nv_rd32(dev, 0x2634));
210
211 nvc0_fifo_playlist_update(dev);
212
213 nv_wr32(dev, 0x003000 + (chan->id * 8), 0x00000000);
214
215 if (chan->user) {
216 iounmap(chan->user);
217 chan->user = NULL;
218 }
219
220 fifoch = chan->fifo_priv;
221 chan->fifo_priv = NULL;
222 if (!fifoch)
223 return;
224
225 nouveau_gpuobj_ref(NULL, &fifoch->ramfc);
226 if (fifoch->user) {
227 nouveau_bo_unmap(fifoch->user);
228 nouveau_bo_unpin(fifoch->user);
229 nouveau_bo_ref(NULL, &fifoch->user);
230 }
231 kfree(fifoch);
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000232}
233
234int
235nvc0_fifo_load_context(struct nouveau_channel *chan)
236{
237 return 0;
238}
239
240int
241nvc0_fifo_unload_context(struct drm_device *dev)
242{
Ben Skeggs7a5c23d2011-04-12 18:51:39 +1000243 struct drm_nouveau_private *dev_priv = dev->dev_private;
244 int i;
245
246 for (i = 0; i < 128; i++) {
247 if (!(nv_rd32(dev, 0x003004 + (i * 4)) & 1))
248 continue;
249
250 nv_mask(dev, 0x003004 + (i * 4), 0x00000001, 0x00000000);
251 nv_wr32(dev, 0x002634, i);
252 if (!nv_wait(dev, 0x002634, 0xffffffff, i)) {
253 NV_INFO(dev, "PFIFO: kick ch %d failed: 0x%08x\n",
254 i, nv_rd32(dev, 0x002634));
255 return -EBUSY;
256 }
257 }
258
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000259 return 0;
260}
261
Ben Skeggsb2b09932010-11-24 10:47:15 +1000262static void
263nvc0_fifo_destroy(struct drm_device *dev)
264{
265 struct drm_nouveau_private *dev_priv = dev->dev_private;
266 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
267 struct nvc0_fifo_priv *priv;
268
269 priv = pfifo->priv;
270 if (!priv)
271 return;
272
273 nouveau_vm_put(&priv->user_vma);
274 nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
275 nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
276 kfree(priv);
277}
278
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000279void
280nvc0_fifo_takedown(struct drm_device *dev)
281{
Ben Skeggsb2b09932010-11-24 10:47:15 +1000282 nv_wr32(dev, 0x002140, 0x00000000);
283 nvc0_fifo_destroy(dev);
284}
285
286static int
287nvc0_fifo_create(struct drm_device *dev)
288{
289 struct drm_nouveau_private *dev_priv = dev->dev_private;
290 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
291 struct nvc0_fifo_priv *priv;
292 int ret;
293
294 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
295 if (!priv)
296 return -ENOMEM;
297 pfifo->priv = priv;
298
299 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000, 0,
300 &priv->playlist[0]);
301 if (ret)
302 goto error;
303
304 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000, 0,
305 &priv->playlist[1]);
306 if (ret)
307 goto error;
308
309 ret = nouveau_vm_get(dev_priv->bar1_vm, pfifo->channels * 0x1000,
310 12, NV_MEM_ACCESS_RW, &priv->user_vma);
311 if (ret)
312 goto error;
313
314 nouveau_irq_register(dev, 8, nvc0_fifo_isr);
315 NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
316 return 0;
317
318error:
319 nvc0_fifo_destroy(dev);
320 return ret;
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000321}
322
323int
324nvc0_fifo_init(struct drm_device *dev)
325{
Ben Skeggsb2b09932010-11-24 10:47:15 +1000326 struct drm_nouveau_private *dev_priv = dev->dev_private;
327 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
328 struct nvc0_fifo_priv *priv;
329 int ret, i;
330
331 if (!pfifo->priv) {
332 ret = nvc0_fifo_create(dev);
333 if (ret)
334 return ret;
335 }
336 priv = pfifo->priv;
337
338 /* reset PFIFO, enable all available PSUBFIFO areas */
339 nv_mask(dev, 0x000200, 0x00000100, 0x00000000);
340 nv_mask(dev, 0x000200, 0x00000100, 0x00000100);
341 nv_wr32(dev, 0x000204, 0xffffffff);
342 nv_wr32(dev, 0x002204, 0xffffffff);
343
Ben Skeggsec9c0882010-12-31 12:10:49 +1000344 priv->spoon_nr = hweight32(nv_rd32(dev, 0x002204));
345 NV_DEBUG(dev, "PFIFO: %d subfifo(s)\n", priv->spoon_nr);
346
Ben Skeggsb2b09932010-11-24 10:47:15 +1000347 /* assign engines to subfifos */
Ben Skeggsec9c0882010-12-31 12:10:49 +1000348 if (priv->spoon_nr >= 3) {
349 nv_wr32(dev, 0x002208, ~(1 << 0)); /* PGRAPH */
350 nv_wr32(dev, 0x00220c, ~(1 << 1)); /* PVP */
351 nv_wr32(dev, 0x002210, ~(1 << 1)); /* PPP */
352 nv_wr32(dev, 0x002214, ~(1 << 1)); /* PBSP */
353 nv_wr32(dev, 0x002218, ~(1 << 2)); /* PCE0 */
354 nv_wr32(dev, 0x00221c, ~(1 << 1)); /* PCE1 */
355 }
Ben Skeggsb2b09932010-11-24 10:47:15 +1000356
357 /* PSUBFIFO[n] */
358 for (i = 0; i < 3; i++) {
359 nv_mask(dev, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
360 nv_wr32(dev, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
361 nv_wr32(dev, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTR_EN */
362 }
363
364 nv_mask(dev, 0x002200, 0x00000001, 0x00000001);
365 nv_wr32(dev, 0x002254, 0x10000000 | priv->user_vma.offset >> 12);
366
367 nv_wr32(dev, 0x002a00, 0xffffffff); /* clears PFIFO.INTR bit 30 */
368 nv_wr32(dev, 0x002100, 0xffffffff);
369 nv_wr32(dev, 0x002140, 0xbfffffff);
Ben Skeggs4b223ee2010-08-03 10:00:56 +1000370 return 0;
371}
372
Ben Skeggsb2b09932010-11-24 10:47:15 +1000373struct nouveau_enum nvc0_fifo_fault_unit[] = {
Ben Skeggs7a313472011-03-29 00:52:59 +1000374 { 0x00, "PGRAPH" },
375 { 0x03, "PEEPHOLE" },
376 { 0x04, "BAR1" },
377 { 0x05, "BAR3" },
378 { 0x07, "PFIFO" },
379 { 0x10, "PBSP" },
380 { 0x11, "PPPP" },
381 { 0x13, "PCOUNTER" },
382 { 0x14, "PVP" },
383 { 0x15, "PCOPY0" },
384 { 0x16, "PCOPY1" },
385 { 0x17, "PDAEMON" },
Ben Skeggsb2b09932010-11-24 10:47:15 +1000386 {}
387};
388
389struct nouveau_enum nvc0_fifo_fault_reason[] = {
Ben Skeggse2966632011-03-29 08:57:34 +1000390 { 0x00, "PT_NOT_PRESENT" },
391 { 0x01, "PT_TOO_SHORT" },
392 { 0x02, "PAGE_NOT_PRESENT" },
393 { 0x03, "VM_LIMIT_EXCEEDED" },
394 { 0x04, "NO_CHANNEL" },
395 { 0x05, "PAGE_SYSTEM_ONLY" },
396 { 0x06, "PAGE_READ_ONLY" },
397 { 0x0a, "COMPRESSED_SYSRAM" },
398 { 0x0c, "INVALID_STORAGE_TYPE" },
Ben Skeggsb2b09932010-11-24 10:47:15 +1000399 {}
400};
401
Ben Skeggs7795bee2011-03-29 09:28:24 +1000402struct nouveau_enum nvc0_fifo_fault_hubclient[] = {
403 { 0x01, "PCOPY0" },
404 { 0x02, "PCOPY1" },
405 { 0x04, "DISPATCH" },
406 { 0x05, "CTXCTL" },
407 { 0x06, "PFIFO" },
408 { 0x07, "BAR_READ" },
409 { 0x08, "BAR_WRITE" },
410 { 0x0b, "PVP" },
411 { 0x0c, "PPPP" },
412 { 0x0d, "PBSP" },
413 { 0x11, "PCOUNTER" },
414 { 0x12, "PDAEMON" },
415 { 0x14, "CCACHE" },
416 { 0x15, "CCACHE_POST" },
417 {}
418};
419
420struct nouveau_enum nvc0_fifo_fault_gpcclient[] = {
421 { 0x01, "TEX" },
422 { 0x0c, "ESETUP" },
423 { 0x0e, "CTXCTL" },
424 { 0x0f, "PROP" },
425 {}
426};
427
Ben Skeggsb2b09932010-11-24 10:47:15 +1000428struct nouveau_bitfield nvc0_fifo_subfifo_intr[] = {
429/* { 0x00008000, "" } seen with null ib push */
430 { 0x00200000, "ILLEGAL_MTHD" },
431 { 0x00800000, "EMPTY_SUBC" },
432 {}
433};
434
435static void
436nvc0_fifo_isr_vm_fault(struct drm_device *dev, int unit)
437{
438 u32 inst = nv_rd32(dev, 0x2800 + (unit * 0x10));
439 u32 valo = nv_rd32(dev, 0x2804 + (unit * 0x10));
440 u32 vahi = nv_rd32(dev, 0x2808 + (unit * 0x10));
441 u32 stat = nv_rd32(dev, 0x280c + (unit * 0x10));
Ben Skeggs7795bee2011-03-29 09:28:24 +1000442 u32 client = (stat & 0x00001f00) >> 8;
Ben Skeggsb2b09932010-11-24 10:47:15 +1000443
444 NV_INFO(dev, "PFIFO: %s fault at 0x%010llx [",
445 (stat & 0x00000080) ? "write" : "read", (u64)vahi << 32 | valo);
446 nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f);
447 printk("] from ");
448 nouveau_enum_print(nvc0_fifo_fault_unit, unit);
Ben Skeggs7795bee2011-03-29 09:28:24 +1000449 if (stat & 0x00000040) {
450 printk("/");
451 nouveau_enum_print(nvc0_fifo_fault_hubclient, client);
452 } else {
453 printk("/GPC%d/", (stat & 0x1f000000) >> 24);
454 nouveau_enum_print(nvc0_fifo_fault_gpcclient, client);
455 }
Ben Skeggsb2b09932010-11-24 10:47:15 +1000456 printk(" on channel 0x%010llx\n", (u64)inst << 12);
457}
458
459static void
460nvc0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit)
461{
462 u32 stat = nv_rd32(dev, 0x040108 + (unit * 0x2000));
463 u32 addr = nv_rd32(dev, 0x0400c0 + (unit * 0x2000));
464 u32 data = nv_rd32(dev, 0x0400c4 + (unit * 0x2000));
465 u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f;
466 u32 subc = (addr & 0x00070000);
467 u32 mthd = (addr & 0x00003ffc);
468
469 NV_INFO(dev, "PSUBFIFO %d:", unit);
470 nouveau_bitfield_print(nvc0_fifo_subfifo_intr, stat);
471 NV_INFO(dev, "PSUBFIFO %d: ch %d subc %d mthd 0x%04x data 0x%08x\n",
472 unit, chid, subc, mthd, data);
473
474 nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008);
475 nv_wr32(dev, 0x040108 + (unit * 0x2000), stat);
476}
477
478static void
479nvc0_fifo_isr(struct drm_device *dev)
480{
481 u32 stat = nv_rd32(dev, 0x002100);
482
Ben Skeggscc8cd642011-01-28 13:42:16 +1000483 if (stat & 0x00000100) {
484 NV_INFO(dev, "PFIFO: unknown status 0x00000100\n");
485 nv_wr32(dev, 0x002100, 0x00000100);
486 stat &= ~0x00000100;
487 }
488
Ben Skeggsb2b09932010-11-24 10:47:15 +1000489 if (stat & 0x10000000) {
490 u32 units = nv_rd32(dev, 0x00259c);
491 u32 u = units;
492
493 while (u) {
494 int i = ffs(u) - 1;
495 nvc0_fifo_isr_vm_fault(dev, i);
496 u &= ~(1 << i);
497 }
498
499 nv_wr32(dev, 0x00259c, units);
500 stat &= ~0x10000000;
501 }
502
503 if (stat & 0x20000000) {
504 u32 units = nv_rd32(dev, 0x0025a0);
505 u32 u = units;
506
507 while (u) {
508 int i = ffs(u) - 1;
509 nvc0_fifo_isr_subfifo_intr(dev, i);
510 u &= ~(1 << i);
511 }
512
513 nv_wr32(dev, 0x0025a0, units);
514 stat &= ~0x20000000;
515 }
516
Ben Skeggscc8cd642011-01-28 13:42:16 +1000517 if (stat & 0x40000000) {
518 NV_INFO(dev, "PFIFO: unknown status 0x40000000\n");
519 nv_mask(dev, 0x002a00, 0x00000000, 0x00000000);
520 stat &= ~0x40000000;
521 }
522
Ben Skeggsb2b09932010-11-24 10:47:15 +1000523 if (stat) {
524 NV_INFO(dev, "PFIFO: unhandled status 0x%08x\n", stat);
525 nv_wr32(dev, 0x002100, stat);
Ben Skeggscc8cd642011-01-28 13:42:16 +1000526 nv_wr32(dev, 0x002140, 0);
Ben Skeggsb2b09932010-11-24 10:47:15 +1000527 }
Ben Skeggsb2b09932010-11-24 10:47:15 +1000528}