Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-clps711x/core.c |
| 3 | * |
| 4 | * Core support for the CLPS711x-based machines. |
| 5 | * |
| 6 | * Copyright (C) 2001,2011 Deep Blue Solutions Ltd |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | */ |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 22 | #include <linux/io.h> |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 23 | #include <linux/init.h> |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame] | 24 | #include <linux/sizes.h> |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 25 | #include <linux/interrupt.h> |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 26 | #include <linux/irq.h> |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 27 | #include <linux/clk.h> |
| 28 | #include <linux/clkdev.h> |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame] | 29 | #include <linux/clockchips.h> |
Alexander Shiyan | c99f72a | 2013-05-13 21:07:32 +0400 | [diff] [blame] | 30 | #include <linux/clocksource.h> |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 31 | #include <linux/clk-provider.h> |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 32 | |
Alexander Shiyan | 99f04c8 | 2012-11-17 17:57:14 +0400 | [diff] [blame] | 33 | #include <asm/exception.h> |
Alexander Shiyan | 1979261 | 2012-11-17 17:57:15 +0400 | [diff] [blame] | 34 | #include <asm/mach/irq.h> |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 35 | #include <asm/mach/map.h> |
| 36 | #include <asm/mach/time.h> |
Alexander Shiyan | c99f72a | 2013-05-13 21:07:32 +0400 | [diff] [blame] | 37 | #include <asm/sched_clock.h> |
David Howells | 9f97da7 | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 38 | #include <asm/system_misc.h> |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 39 | |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 40 | #include <mach/hardware.h> |
| 41 | |
| 42 | static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh, |
| 43 | *clk_tint, *clk_spi; |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 44 | |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 45 | /* |
| 46 | * This maps the generic CLPS711x registers |
| 47 | */ |
| 48 | static struct map_desc clps711x_io_desc[] __initdata = { |
| 49 | { |
Alexander Shiyan | 304b2c6 | 2012-05-06 09:21:57 +0400 | [diff] [blame] | 50 | .virtual = (unsigned long)CLPS711X_VIRT_BASE, |
| 51 | .pfn = __phys_to_pfn(CLPS711X_PHYS_BASE), |
Alexander Shiyan | 6cb1b14 | 2012-10-10 19:45:31 +0400 | [diff] [blame] | 52 | .length = SZ_64K, |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 53 | .type = MT_DEVICE |
| 54 | } |
| 55 | }; |
| 56 | |
| 57 | void __init clps711x_map_io(void) |
| 58 | { |
| 59 | iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc)); |
| 60 | } |
| 61 | |
| 62 | static void int1_mask(struct irq_data *d) |
| 63 | { |
| 64 | u32 intmr1; |
| 65 | |
| 66 | intmr1 = clps_readl(INTMR1); |
| 67 | intmr1 &= ~(1 << d->irq); |
| 68 | clps_writel(intmr1, INTMR1); |
| 69 | } |
| 70 | |
Alexander Shiyan | 74fde6d | 2012-10-10 19:45:29 +0400 | [diff] [blame] | 71 | static void int1_eoi(struct irq_data *d) |
| 72 | { |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 73 | switch (d->irq) { |
| 74 | case IRQ_CSINT: clps_writel(0, COEOI); break; |
| 75 | case IRQ_TC1OI: clps_writel(0, TC1EOI); break; |
| 76 | case IRQ_TC2OI: clps_writel(0, TC2EOI); break; |
| 77 | case IRQ_RTCMI: clps_writel(0, RTCEOI); break; |
| 78 | case IRQ_TINT: clps_writel(0, TEOI); break; |
| 79 | case IRQ_UMSINT: clps_writel(0, UMSEOI); break; |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | static void int1_unmask(struct irq_data *d) |
| 84 | { |
| 85 | u32 intmr1; |
| 86 | |
| 87 | intmr1 = clps_readl(INTMR1); |
| 88 | intmr1 |= 1 << d->irq; |
| 89 | clps_writel(intmr1, INTMR1); |
| 90 | } |
| 91 | |
| 92 | static struct irq_chip int1_chip = { |
Alexander Shiyan | 1979261 | 2012-11-17 17:57:15 +0400 | [diff] [blame] | 93 | .name = "Interrupt Vector 1", |
Alexander Shiyan | 74fde6d | 2012-10-10 19:45:29 +0400 | [diff] [blame] | 94 | .irq_eoi = int1_eoi, |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 95 | .irq_mask = int1_mask, |
| 96 | .irq_unmask = int1_unmask, |
| 97 | }; |
| 98 | |
| 99 | static void int2_mask(struct irq_data *d) |
| 100 | { |
| 101 | u32 intmr2; |
| 102 | |
| 103 | intmr2 = clps_readl(INTMR2); |
| 104 | intmr2 &= ~(1 << (d->irq - 16)); |
| 105 | clps_writel(intmr2, INTMR2); |
| 106 | } |
| 107 | |
Alexander Shiyan | 74fde6d | 2012-10-10 19:45:29 +0400 | [diff] [blame] | 108 | static void int2_eoi(struct irq_data *d) |
| 109 | { |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 110 | switch (d->irq) { |
| 111 | case IRQ_KBDINT: clps_writel(0, KBDEOI); break; |
| 112 | } |
| 113 | } |
| 114 | |
| 115 | static void int2_unmask(struct irq_data *d) |
| 116 | { |
| 117 | u32 intmr2; |
| 118 | |
| 119 | intmr2 = clps_readl(INTMR2); |
| 120 | intmr2 |= 1 << (d->irq - 16); |
| 121 | clps_writel(intmr2, INTMR2); |
| 122 | } |
| 123 | |
| 124 | static struct irq_chip int2_chip = { |
Alexander Shiyan | 1979261 | 2012-11-17 17:57:15 +0400 | [diff] [blame] | 125 | .name = "Interrupt Vector 2", |
Alexander Shiyan | 74fde6d | 2012-10-10 19:45:29 +0400 | [diff] [blame] | 126 | .irq_eoi = int2_eoi, |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 127 | .irq_mask = int2_mask, |
| 128 | .irq_unmask = int2_unmask, |
| 129 | }; |
| 130 | |
Alexander Shiyan | 1979261 | 2012-11-17 17:57:15 +0400 | [diff] [blame] | 131 | static void int3_mask(struct irq_data *d) |
| 132 | { |
| 133 | u32 intmr3; |
| 134 | |
| 135 | intmr3 = clps_readl(INTMR3); |
| 136 | intmr3 &= ~(1 << (d->irq - 32)); |
| 137 | clps_writel(intmr3, INTMR3); |
| 138 | } |
| 139 | |
| 140 | static void int3_unmask(struct irq_data *d) |
| 141 | { |
| 142 | u32 intmr3; |
| 143 | |
| 144 | intmr3 = clps_readl(INTMR3); |
| 145 | intmr3 |= 1 << (d->irq - 32); |
| 146 | clps_writel(intmr3, INTMR3); |
| 147 | } |
| 148 | |
| 149 | static struct irq_chip int3_chip = { |
| 150 | .name = "Interrupt Vector 3", |
| 151 | .irq_mask = int3_mask, |
| 152 | .irq_unmask = int3_unmask, |
| 153 | }; |
| 154 | |
Alexander Shiyan | 99f04c8 | 2012-11-17 17:57:14 +0400 | [diff] [blame] | 155 | static struct { |
Alexander Shiyan | 74fde6d | 2012-10-10 19:45:29 +0400 | [diff] [blame] | 156 | int nr; |
| 157 | struct irq_chip *chip; |
| 158 | irq_flow_handler_t handle; |
Alexander Shiyan | 99f04c8 | 2012-11-17 17:57:14 +0400 | [diff] [blame] | 159 | } clps711x_irqdescs[] __initdata = { |
Alexander Shiyan | 74fde6d | 2012-10-10 19:45:29 +0400 | [diff] [blame] | 160 | { IRQ_CSINT, &int1_chip, handle_fasteoi_irq, }, |
| 161 | { IRQ_EINT1, &int1_chip, handle_level_irq, }, |
| 162 | { IRQ_EINT2, &int1_chip, handle_level_irq, }, |
| 163 | { IRQ_EINT3, &int1_chip, handle_level_irq, }, |
| 164 | { IRQ_TC1OI, &int1_chip, handle_fasteoi_irq, }, |
| 165 | { IRQ_TC2OI, &int1_chip, handle_fasteoi_irq, }, |
| 166 | { IRQ_RTCMI, &int1_chip, handle_fasteoi_irq, }, |
| 167 | { IRQ_TINT, &int1_chip, handle_fasteoi_irq, }, |
| 168 | { IRQ_UTXINT1, &int1_chip, handle_level_irq, }, |
| 169 | { IRQ_URXINT1, &int1_chip, handle_level_irq, }, |
| 170 | { IRQ_UMSINT, &int1_chip, handle_fasteoi_irq, }, |
| 171 | { IRQ_SSEOTI, &int1_chip, handle_level_irq, }, |
| 172 | { IRQ_KBDINT, &int2_chip, handle_fasteoi_irq, }, |
| 173 | { IRQ_SS2RX, &int2_chip, handle_level_irq, }, |
| 174 | { IRQ_SS2TX, &int2_chip, handle_level_irq, }, |
| 175 | { IRQ_UTXINT2, &int2_chip, handle_level_irq, }, |
| 176 | { IRQ_URXINT2, &int2_chip, handle_level_irq, }, |
| 177 | }; |
| 178 | |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 179 | void __init clps711x_init_irq(void) |
| 180 | { |
| 181 | unsigned int i; |
| 182 | |
Alexander Shiyan | 74fde6d | 2012-10-10 19:45:29 +0400 | [diff] [blame] | 183 | /* Disable interrupts */ |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 184 | clps_writel(0, INTMR1); |
| 185 | clps_writel(0, INTMR2); |
Alexander Shiyan | 74fde6d | 2012-10-10 19:45:29 +0400 | [diff] [blame] | 186 | clps_writel(0, INTMR3); |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 187 | |
Alexander Shiyan | 74fde6d | 2012-10-10 19:45:29 +0400 | [diff] [blame] | 188 | /* Clear down any pending interrupts */ |
| 189 | clps_writel(0, BLEOI); |
| 190 | clps_writel(0, MCEOI); |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 191 | clps_writel(0, COEOI); |
| 192 | clps_writel(0, TC1EOI); |
| 193 | clps_writel(0, TC2EOI); |
| 194 | clps_writel(0, RTCEOI); |
| 195 | clps_writel(0, TEOI); |
| 196 | clps_writel(0, UMSEOI); |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 197 | clps_writel(0, KBDEOI); |
Alexander Shiyan | 74fde6d | 2012-10-10 19:45:29 +0400 | [diff] [blame] | 198 | clps_writel(0, SRXEOF); |
| 199 | clps_writel(0xffffffff, DAISR); |
| 200 | |
| 201 | for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) { |
| 202 | irq_set_chip_and_handler(clps711x_irqdescs[i].nr, |
| 203 | clps711x_irqdescs[i].chip, |
| 204 | clps711x_irqdescs[i].handle); |
| 205 | set_irq_flags(clps711x_irqdescs[i].nr, |
| 206 | IRQF_VALID | IRQF_PROBE); |
| 207 | } |
Alexander Shiyan | 1979261 | 2012-11-17 17:57:15 +0400 | [diff] [blame] | 208 | |
| 209 | if (IS_ENABLED(CONFIG_FIQ)) { |
| 210 | init_FIQ(0); |
| 211 | irq_set_chip_and_handler(IRQ_DAIINT, &int3_chip, |
| 212 | handle_bad_irq); |
| 213 | set_irq_flags(IRQ_DAIINT, |
| 214 | IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); |
| 215 | } |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 216 | } |
| 217 | |
Alexander Shiyan | 7dfbf1b | 2013-05-13 21:07:33 +0400 | [diff] [blame] | 218 | static inline u32 fls16(u32 x) |
Alexander Shiyan | 99f04c8 | 2012-11-17 17:57:14 +0400 | [diff] [blame] | 219 | { |
| 220 | u32 r = 15; |
| 221 | |
| 222 | if (!(x & 0xff00)) { |
| 223 | x <<= 8; |
| 224 | r -= 8; |
| 225 | } |
| 226 | if (!(x & 0xf000)) { |
| 227 | x <<= 4; |
| 228 | r -= 4; |
| 229 | } |
| 230 | if (!(x & 0xc000)) { |
| 231 | x <<= 2; |
| 232 | r -= 2; |
| 233 | } |
| 234 | if (!(x & 0x8000)) |
| 235 | r--; |
| 236 | |
| 237 | return r; |
| 238 | } |
| 239 | |
| 240 | asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs) |
| 241 | { |
Alexander Shiyan | 7dfbf1b | 2013-05-13 21:07:33 +0400 | [diff] [blame] | 242 | do { |
| 243 | u32 irqstat; |
| 244 | void __iomem *base = CLPS711X_VIRT_BASE; |
Alexander Shiyan | 99f04c8 | 2012-11-17 17:57:14 +0400 | [diff] [blame] | 245 | |
Alexander Shiyan | 7dfbf1b | 2013-05-13 21:07:33 +0400 | [diff] [blame] | 246 | irqstat = readw_relaxed(base + INTSR1) & |
| 247 | readw_relaxed(base + INTMR1); |
| 248 | if (irqstat) |
| 249 | handle_IRQ(fls16(irqstat), regs); |
Alexander Shiyan | 99f04c8 | 2012-11-17 17:57:14 +0400 | [diff] [blame] | 250 | |
Alexander Shiyan | 7dfbf1b | 2013-05-13 21:07:33 +0400 | [diff] [blame] | 251 | irqstat = readw_relaxed(base + INTSR2) & |
| 252 | readw_relaxed(base + INTMR2); |
| 253 | if (irqstat) { |
| 254 | handle_IRQ(fls16(irqstat) + 16, regs); |
| 255 | continue; |
| 256 | } |
| 257 | |
| 258 | break; |
| 259 | } while (1); |
Alexander Shiyan | 99f04c8 | 2012-11-17 17:57:14 +0400 | [diff] [blame] | 260 | } |
| 261 | |
Alexander Shiyan | c99f72a | 2013-05-13 21:07:32 +0400 | [diff] [blame] | 262 | static u32 notrace clps711x_sched_clock_read(void) |
| 263 | { |
| 264 | return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D); |
| 265 | } |
| 266 | |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame] | 267 | static void clps711x_clockevent_set_mode(enum clock_event_mode mode, |
| 268 | struct clock_event_device *evt) |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 269 | { |
Alexander Shiyan | c99f72a | 2013-05-13 21:07:32 +0400 | [diff] [blame] | 270 | disable_irq(IRQ_TC2OI); |
| 271 | |
| 272 | switch (mode) { |
| 273 | case CLOCK_EVT_MODE_PERIODIC: |
| 274 | enable_irq(IRQ_TC2OI); |
| 275 | break; |
| 276 | case CLOCK_EVT_MODE_ONESHOT: |
| 277 | /* Not supported */ |
| 278 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 279 | case CLOCK_EVT_MODE_UNUSED: |
| 280 | case CLOCK_EVT_MODE_RESUME: |
| 281 | /* Left event sources disabled, no more interrupts appear */ |
| 282 | break; |
| 283 | } |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 284 | } |
| 285 | |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame] | 286 | static struct clock_event_device clockevent_clps711x = { |
Alexander Shiyan | c99f72a | 2013-05-13 21:07:32 +0400 | [diff] [blame] | 287 | .name = "clps711x-clockevent", |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame] | 288 | .rating = 300, |
| 289 | .features = CLOCK_EVT_FEAT_PERIODIC, |
| 290 | .set_mode = clps711x_clockevent_set_mode, |
| 291 | }; |
| 292 | |
| 293 | static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id) |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 294 | { |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame] | 295 | clockevent_clps711x.event_handler(&clockevent_clps711x); |
| 296 | |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 297 | return IRQ_HANDLED; |
| 298 | } |
| 299 | |
| 300 | static struct irqaction clps711x_timer_irq = { |
Alexander Shiyan | c99f72a | 2013-05-13 21:07:32 +0400 | [diff] [blame] | 301 | .name = "clps711x-timer", |
| 302 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
Alexander Shiyan | 4a8355c | 2012-10-10 19:45:27 +0400 | [diff] [blame] | 303 | .handler = clps711x_timer_interrupt, |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 304 | }; |
| 305 | |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 306 | static void add_fixed_clk(struct clk *clk, const char *name, int rate) |
| 307 | { |
| 308 | clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); |
| 309 | clk_register_clkdev(clk, name, NULL); |
| 310 | } |
| 311 | |
Stephen Warren | 6bb27d7 | 2012-11-08 12:40:59 -0700 | [diff] [blame] | 312 | void __init clps711x_timer_init(void) |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 313 | { |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 314 | int osc, ext, pll, cpu, bus, timl, timh, uart, spi; |
| 315 | u32 tmp; |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 316 | |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 317 | osc = 3686400; |
| 318 | ext = 13000000; |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 319 | |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 320 | tmp = clps_readl(PLLR) >> 24; |
| 321 | if (tmp) |
| 322 | pll = (osc * tmp) / 2; |
| 323 | else |
| 324 | pll = 73728000; /* Default value */ |
| 325 | |
| 326 | tmp = clps_readl(SYSFLG2); |
| 327 | if (tmp & SYSFLG2_CKMODE) { |
| 328 | cpu = ext; |
| 329 | bus = cpu; |
| 330 | spi = 135400; |
Alexander Shiyan | 2a6f061 | 2013-05-13 21:07:23 +0400 | [diff] [blame] | 331 | pll = 0; |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 332 | } else { |
| 333 | cpu = pll; |
| 334 | if (cpu >= 36864000) |
| 335 | bus = cpu / 2; |
| 336 | else |
| 337 | bus = 36864000 / 2; |
| 338 | spi = cpu / 576; |
| 339 | } |
| 340 | |
| 341 | uart = bus / 10; |
| 342 | |
| 343 | if (tmp & SYSFLG2_CKMODE) { |
| 344 | tmp = clps_readl(SYSCON2); |
| 345 | if (tmp & SYSCON2_OSTB) |
| 346 | timh = ext / 26; |
| 347 | else |
| 348 | timh = 541440; |
| 349 | } else |
Alexander Shiyan | c99f72a | 2013-05-13 21:07:32 +0400 | [diff] [blame] | 350 | timh = DIV_ROUND_CLOSEST(cpu, 144); |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 351 | |
Alexander Shiyan | c99f72a | 2013-05-13 21:07:32 +0400 | [diff] [blame] | 352 | timl = DIV_ROUND_CLOSEST(timh, 256); |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 353 | |
| 354 | /* All clocks are fixed */ |
| 355 | add_fixed_clk(clk_pll, "pll", pll); |
| 356 | add_fixed_clk(clk_bus, "bus", bus); |
| 357 | add_fixed_clk(clk_uart, "uart", uart); |
| 358 | add_fixed_clk(clk_timerl, "timer_lf", timl); |
| 359 | add_fixed_clk(clk_timerh, "timer_hf", timh); |
| 360 | add_fixed_clk(clk_tint, "tint", 64); |
| 361 | add_fixed_clk(clk_spi, "spi", spi); |
| 362 | |
| 363 | pr_info("CPU frequency set at %i Hz.\n", cpu); |
| 364 | |
Alexander Shiyan | c99f72a | 2013-05-13 21:07:32 +0400 | [diff] [blame] | 365 | /* Start Timer1 in free running mode (Low frequency) */ |
| 366 | tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M); |
Alexander Shiyan | 61ae48c | 2012-08-21 20:59:35 +0400 | [diff] [blame] | 367 | clps_writel(tmp, SYSCON1); |
| 368 | |
Alexander Shiyan | c99f72a | 2013-05-13 21:07:32 +0400 | [diff] [blame] | 369 | setup_sched_clock(clps711x_sched_clock_read, 16, timl); |
| 370 | |
| 371 | clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D, |
| 372 | "clps711x_clocksource", timl, 300, 16, |
| 373 | clocksource_mmio_readw_down); |
| 374 | |
| 375 | /* Set Timer2 prescaler */ |
| 376 | clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D); |
| 377 | |
| 378 | /* Start Timer2 in prescale mode (High frequency)*/ |
| 379 | tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S; |
| 380 | clps_writel(tmp, SYSCON1); |
| 381 | |
| 382 | clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0); |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 383 | |
| 384 | setup_irq(IRQ_TC2OI, &clps711x_timer_irq); |
Russell King | 3a08322 | 2011-11-05 17:38:32 +0000 | [diff] [blame] | 385 | } |
| 386 | |
Robin Holt | 7b6d864 | 2013-07-08 16:01:40 -0700 | [diff] [blame^] | 387 | void clps711x_restart(enum reboot_mode mode, const char *cmd) |
Russell King | 6c00071 | 2011-11-05 17:41:52 +0000 | [diff] [blame] | 388 | { |
| 389 | soft_restart(0); |
| 390 | } |
Nicolas Pitre | 71e256c | 2011-08-02 12:22:48 -0400 | [diff] [blame] | 391 | |
| 392 | static void clps711x_idle(void) |
| 393 | { |
| 394 | clps_writel(1, HALT); |
Alexander Shiyan | d0ad52a | 2013-05-13 21:07:31 +0400 | [diff] [blame] | 395 | asm("mov r0, r0"); |
| 396 | asm("mov r0, r0"); |
Nicolas Pitre | 71e256c | 2011-08-02 12:22:48 -0400 | [diff] [blame] | 397 | } |
| 398 | |
Alexander Shiyan | d0ad52a | 2013-05-13 21:07:31 +0400 | [diff] [blame] | 399 | void __init clps711x_init_early(void) |
Nicolas Pitre | 71e256c | 2011-08-02 12:22:48 -0400 | [diff] [blame] | 400 | { |
| 401 | arm_pm_idle = clps711x_idle; |
Nicolas Pitre | 71e256c | 2011-08-02 12:22:48 -0400 | [diff] [blame] | 402 | } |