blob: 65b635ce28c8c78da6563f21538d9d6434de23a9 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/i2c.h>
28#include "drmP.h"
29#include "intel_drv.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
32
33#include "drm_crtc_helper.h"
34
35bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
36
37typedef struct {
38 /* given values */
39 int n;
40 int m1, m2;
41 int p1, p2;
42 /* derived values */
43 int dot;
44 int vco;
45 int m;
46 int p;
47} intel_clock_t;
48
49typedef struct {
50 int min, max;
51} intel_range_t;
52
53typedef struct {
54 int dot_limit;
55 int p2_slow, p2_fast;
56} intel_p2_t;
57
58#define INTEL_P2_NUM 2
59
60typedef struct {
61 intel_range_t dot, vco, n, m, m1, m2, p, p1;
62 intel_p2_t p2;
63} intel_limit_t;
64
65#define I8XX_DOT_MIN 25000
66#define I8XX_DOT_MAX 350000
67#define I8XX_VCO_MIN 930000
68#define I8XX_VCO_MAX 1400000
69#define I8XX_N_MIN 3
70#define I8XX_N_MAX 16
71#define I8XX_M_MIN 96
72#define I8XX_M_MAX 140
73#define I8XX_M1_MIN 18
74#define I8XX_M1_MAX 26
75#define I8XX_M2_MIN 6
76#define I8XX_M2_MAX 16
77#define I8XX_P_MIN 4
78#define I8XX_P_MAX 128
79#define I8XX_P1_MIN 2
80#define I8XX_P1_MAX 33
81#define I8XX_P1_LVDS_MIN 1
82#define I8XX_P1_LVDS_MAX 6
83#define I8XX_P2_SLOW 4
84#define I8XX_P2_FAST 2
85#define I8XX_P2_LVDS_SLOW 14
86#define I8XX_P2_LVDS_FAST 14 /* No fast option */
87#define I8XX_P2_SLOW_LIMIT 165000
88
89#define I9XX_DOT_MIN 20000
90#define I9XX_DOT_MAX 400000
91#define I9XX_VCO_MIN 1400000
92#define I9XX_VCO_MAX 2800000
Kristian Høgsbergf3cade52009-02-13 20:56:50 -050093#define I9XX_N_MIN 1
94#define I9XX_N_MAX 6
Jesse Barnes79e53942008-11-07 14:24:08 -080095#define I9XX_M_MIN 70
96#define I9XX_M_MAX 120
97#define I9XX_M1_MIN 10
Kristian Høgsbergf3cade52009-02-13 20:56:50 -050098#define I9XX_M1_MAX 22
Jesse Barnes79e53942008-11-07 14:24:08 -080099#define I9XX_M2_MIN 5
100#define I9XX_M2_MAX 9
101#define I9XX_P_SDVO_DAC_MIN 5
102#define I9XX_P_SDVO_DAC_MAX 80
103#define I9XX_P_LVDS_MIN 7
104#define I9XX_P_LVDS_MAX 98
105#define I9XX_P1_MIN 1
106#define I9XX_P1_MAX 8
107#define I9XX_P2_SDVO_DAC_SLOW 10
108#define I9XX_P2_SDVO_DAC_FAST 5
109#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
110#define I9XX_P2_LVDS_SLOW 14
111#define I9XX_P2_LVDS_FAST 7
112#define I9XX_P2_LVDS_SLOW_LIMIT 112000
113
114#define INTEL_LIMIT_I8XX_DVO_DAC 0
115#define INTEL_LIMIT_I8XX_LVDS 1
116#define INTEL_LIMIT_I9XX_SDVO_DAC 2
117#define INTEL_LIMIT_I9XX_LVDS 3
118
119static const intel_limit_t intel_limits[] = {
120 { /* INTEL_LIMIT_I8XX_DVO_DAC */
121 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
122 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
123 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
124 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
125 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
126 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
127 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
128 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
129 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
130 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
131 },
132 { /* INTEL_LIMIT_I8XX_LVDS */
133 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
134 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
135 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
136 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
137 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
138 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
139 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
140 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
141 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
142 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
143 },
144 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
145 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
146 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
147 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
148 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
149 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
150 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
151 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
152 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
153 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
154 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
155 },
156 { /* INTEL_LIMIT_I9XX_LVDS */
157 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
158 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
159 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
160 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
161 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
162 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
163 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
164 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
165 /* The single-channel range is 25-112Mhz, and dual-channel
166 * is 80-224Mhz. Prefer single channel as much as possible.
167 */
168 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
169 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
170 },
171};
172
173static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
174{
175 struct drm_device *dev = crtc->dev;
176 const intel_limit_t *limit;
177
178 if (IS_I9XX(dev)) {
179 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
180 limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
181 else
182 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
183 } else {
184 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
185 limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
186 else
187 limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC];
188 }
189 return limit;
190}
191
Kristian Høgsberga29f5ca2009-02-13 20:56:51 -0500192static void intel_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800193{
194 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
195 clock->p = clock->p1 * clock->p2;
196 clock->vco = refclk * clock->m / (clock->n + 2);
197 clock->dot = clock->vco / clock->p;
198}
199
Jesse Barnes79e53942008-11-07 14:24:08 -0800200/**
201 * Returns whether any output on the specified pipe is of the specified type
202 */
203bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
204{
205 struct drm_device *dev = crtc->dev;
206 struct drm_mode_config *mode_config = &dev->mode_config;
207 struct drm_connector *l_entry;
208
209 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
210 if (l_entry->encoder &&
211 l_entry->encoder->crtc == crtc) {
212 struct intel_output *intel_output = to_intel_output(l_entry);
213 if (intel_output->type == type)
214 return true;
215 }
216 }
217 return false;
218}
219
Kristian Høgsberg43565a02009-02-13 20:56:52 -0500220#define INTELPllInvalid(s) do { DRM_DEBUG(s); return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800221/**
222 * Returns whether the given set of divisors are valid for a given refclk with
223 * the given connectors.
224 */
225
226static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
227{
228 const intel_limit_t *limit = intel_limit (crtc);
229
230 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
231 INTELPllInvalid ("p1 out of range\n");
232 if (clock->p < limit->p.min || limit->p.max < clock->p)
233 INTELPllInvalid ("p out of range\n");
234 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
235 INTELPllInvalid ("m2 out of range\n");
236 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
237 INTELPllInvalid ("m1 out of range\n");
238 if (clock->m1 <= clock->m2)
239 INTELPllInvalid ("m1 <= m2\n");
240 if (clock->m < limit->m.min || limit->m.max < clock->m)
241 INTELPllInvalid ("m out of range\n");
242 if (clock->n < limit->n.min || limit->n.max < clock->n)
243 INTELPllInvalid ("n out of range\n");
244 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
245 INTELPllInvalid ("vco out of range\n");
246 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
247 * connector, etc., rather than just a single range.
248 */
249 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
250 INTELPllInvalid ("dot out of range\n");
251
252 return true;
253}
254
255/**
256 * Returns a set of divisors for the desired target clock with the given
257 * refclk, or FALSE. The returned values represent the clock equation:
258 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
259 */
260static bool intel_find_best_PLL(struct drm_crtc *crtc, int target,
261 int refclk, intel_clock_t *best_clock)
262{
263 struct drm_device *dev = crtc->dev;
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 intel_clock_t clock;
266 const intel_limit_t *limit = intel_limit(crtc);
267 int err = target;
268
269 if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
270 (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
271 /*
272 * For LVDS, if the panel is on, just rely on its current
273 * settings for dual-channel. We haven't figured out how to
274 * reliably set up different single/dual channel state, if we
275 * even can.
276 */
277 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
278 LVDS_CLKB_POWER_UP)
279 clock.p2 = limit->p2.p2_fast;
280 else
281 clock.p2 = limit->p2.p2_slow;
282 } else {
283 if (target < limit->p2.dot_limit)
284 clock.p2 = limit->p2.p2_slow;
285 else
286 clock.p2 = limit->p2.p2_fast;
287 }
288
289 memset (best_clock, 0, sizeof (*best_clock));
290
291 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
292 for (clock.m2 = limit->m2.min; clock.m2 < clock.m1 &&
293 clock.m2 <= limit->m2.max; clock.m2++) {
294 for (clock.n = limit->n.min; clock.n <= limit->n.max;
295 clock.n++) {
296 for (clock.p1 = limit->p1.min;
297 clock.p1 <= limit->p1.max; clock.p1++) {
298 int this_err;
299
Kristian Høgsberga29f5ca2009-02-13 20:56:51 -0500300 intel_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800301
302 if (!intel_PLL_is_valid(crtc, &clock))
303 continue;
304
305 this_err = abs(clock.dot - target);
306 if (this_err < err) {
307 *best_clock = clock;
308 err = this_err;
309 }
310 }
311 }
312 }
313 }
314
315 return (err != target);
316}
317
318void
319intel_wait_for_vblank(struct drm_device *dev)
320{
321 /* Wait for 20ms, i.e. one cycle at 50hz. */
322 udelay(20000);
323}
324
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000325static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500326intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
327 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -0800328{
329 struct drm_device *dev = crtc->dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 struct drm_i915_master_private *master_priv;
332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
333 struct intel_framebuffer *intel_fb;
334 struct drm_i915_gem_object *obj_priv;
335 struct drm_gem_object *obj;
336 int pipe = intel_crtc->pipe;
337 unsigned long Start, Offset;
338 int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
339 int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
340 int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
341 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500342 u32 dspcntr, alignment;
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000343 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -0800344
345 /* no fb bound */
346 if (!crtc->fb) {
347 DRM_DEBUG("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000348 return 0;
349 }
350
351 switch (pipe) {
352 case 0:
353 case 1:
354 break;
355 default:
356 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
357 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -0800358 }
359
360 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnes79e53942008-11-07 14:24:08 -0800361 obj = intel_fb->obj;
362 obj_priv = obj->driver_private;
363
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500364 switch (obj_priv->tiling_mode) {
365 case I915_TILING_NONE:
366 alignment = 64 * 1024;
367 break;
368 case I915_TILING_X:
Chris Wilson2ebed172009-02-11 14:26:30 +0000369 /* pin() will align the object as required by fence */
370 alignment = 0;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500371 break;
372 case I915_TILING_Y:
373 /* FIXME: Is this true? */
374 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000375 return -EINVAL;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500376 default:
377 BUG();
378 }
379
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000380 mutex_lock(&dev->struct_mutex);
381 ret = i915_gem_object_pin(intel_fb->obj, alignment);
382 if (ret != 0) {
383 mutex_unlock(&dev->struct_mutex);
384 return ret;
385 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500386
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000387 ret = i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1);
388 if (ret != 0) {
389 i915_gem_object_unpin(intel_fb->obj);
390 mutex_unlock(&dev->struct_mutex);
391 return ret;
392 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800393
394 dspcntr = I915_READ(dspcntr_reg);
Jesse Barnes712531b2009-01-09 13:56:14 -0800395 /* Mask out pixel format bits in case we change it */
396 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Jesse Barnes79e53942008-11-07 14:24:08 -0800397 switch (crtc->fb->bits_per_pixel) {
398 case 8:
399 dspcntr |= DISPPLANE_8BPP;
400 break;
401 case 16:
402 if (crtc->fb->depth == 15)
403 dspcntr |= DISPPLANE_15_16BPP;
404 else
405 dspcntr |= DISPPLANE_16BPP;
406 break;
407 case 24:
408 case 32:
409 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
410 break;
411 default:
412 DRM_ERROR("Unknown color depth\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000413 i915_gem_object_unpin(intel_fb->obj);
414 mutex_unlock(&dev->struct_mutex);
415 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -0800416 }
417 I915_WRITE(dspcntr_reg, dspcntr);
418
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000419 Start = obj_priv->gtt_offset;
420 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
421
Jesse Barnes79e53942008-11-07 14:24:08 -0800422 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000423 I915_WRITE(dspstride, crtc->fb->pitch);
Jesse Barnes79e53942008-11-07 14:24:08 -0800424 if (IS_I965G(dev)) {
425 I915_WRITE(dspbase, Offset);
426 I915_READ(dspbase);
427 I915_WRITE(dspsurf, Start);
428 I915_READ(dspsurf);
429 } else {
430 I915_WRITE(dspbase, Start + Offset);
431 I915_READ(dspbase);
432 }
433
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -0500434 intel_wait_for_vblank(dev);
435
436 if (old_fb) {
437 intel_fb = to_intel_framebuffer(old_fb);
438 i915_gem_object_unpin(intel_fb->obj);
439 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000440 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -0800441
442 if (!dev->primary->master)
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000443 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -0800444
445 master_priv = dev->primary->master->driver_priv;
446 if (!master_priv->sarea_priv)
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000447 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -0800448
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000449 if (pipe) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800450 master_priv->sarea_priv->pipeB_x = x;
451 master_priv->sarea_priv->pipeB_y = y;
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000452 } else {
453 master_priv->sarea_priv->pipeA_x = x;
454 master_priv->sarea_priv->pipeA_y = y;
Jesse Barnes79e53942008-11-07 14:24:08 -0800455 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000456
457 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -0800458}
459
460
461
462/**
463 * Sets the power management mode of the pipe and plane.
464 *
465 * This code should probably grow support for turning the cursor off and back
466 * on appropriately at the same time as we're turning the pipe off/on.
467 */
468static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
469{
470 struct drm_device *dev = crtc->dev;
471 struct drm_i915_master_private *master_priv;
472 struct drm_i915_private *dev_priv = dev->dev_private;
473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
474 int pipe = intel_crtc->pipe;
475 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
476 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
477 int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
478 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
479 u32 temp;
480 bool enabled;
481
482 /* XXX: When our outputs are all unaware of DPMS modes other than off
483 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
484 */
485 switch (mode) {
486 case DRM_MODE_DPMS_ON:
487 case DRM_MODE_DPMS_STANDBY:
488 case DRM_MODE_DPMS_SUSPEND:
489 /* Enable the DPLL */
490 temp = I915_READ(dpll_reg);
491 if ((temp & DPLL_VCO_ENABLE) == 0) {
492 I915_WRITE(dpll_reg, temp);
493 I915_READ(dpll_reg);
494 /* Wait for the clocks to stabilize. */
495 udelay(150);
496 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
497 I915_READ(dpll_reg);
498 /* Wait for the clocks to stabilize. */
499 udelay(150);
500 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
501 I915_READ(dpll_reg);
502 /* Wait for the clocks to stabilize. */
503 udelay(150);
504 }
505
506 /* Enable the pipe */
507 temp = I915_READ(pipeconf_reg);
508 if ((temp & PIPEACONF_ENABLE) == 0)
509 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
510
511 /* Enable the plane */
512 temp = I915_READ(dspcntr_reg);
513 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
514 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
515 /* Flush the plane changes */
516 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
517 }
518
519 intel_crtc_load_lut(crtc);
520
521 /* Give the overlay scaler a chance to enable if it's on this pipe */
522 //intel_crtc_dpms_video(crtc, true); TODO
523 break;
524 case DRM_MODE_DPMS_OFF:
525 /* Give the overlay scaler a chance to disable if it's on this pipe */
526 //intel_crtc_dpms_video(crtc, FALSE); TODO
527
528 /* Disable the VGA plane that we never use */
529 I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
530
531 /* Disable display plane */
532 temp = I915_READ(dspcntr_reg);
533 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
534 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
535 /* Flush the plane changes */
536 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
537 I915_READ(dspbase_reg);
538 }
539
540 if (!IS_I9XX(dev)) {
541 /* Wait for vblank for the disable to take effect */
542 intel_wait_for_vblank(dev);
543 }
544
545 /* Next, disable display pipes */
546 temp = I915_READ(pipeconf_reg);
547 if ((temp & PIPEACONF_ENABLE) != 0) {
548 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
549 I915_READ(pipeconf_reg);
550 }
551
552 /* Wait for vblank for the disable to take effect. */
553 intel_wait_for_vblank(dev);
554
555 temp = I915_READ(dpll_reg);
556 if ((temp & DPLL_VCO_ENABLE) != 0) {
557 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
558 I915_READ(dpll_reg);
559 }
560
561 /* Wait for the clocks to turn off. */
562 udelay(150);
563 break;
564 }
565
566 if (!dev->primary->master)
567 return;
568
569 master_priv = dev->primary->master->driver_priv;
570 if (!master_priv->sarea_priv)
571 return;
572
573 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
574
575 switch (pipe) {
576 case 0:
577 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
578 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
579 break;
580 case 1:
581 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
582 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
583 break;
584 default:
585 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
586 break;
587 }
588
589 intel_crtc->dpms_mode = mode;
590}
591
592static void intel_crtc_prepare (struct drm_crtc *crtc)
593{
594 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
595 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
596}
597
598static void intel_crtc_commit (struct drm_crtc *crtc)
599{
600 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
601 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
602}
603
604void intel_encoder_prepare (struct drm_encoder *encoder)
605{
606 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
607 /* lvds has its own version of prepare see intel_lvds_prepare */
608 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
609}
610
611void intel_encoder_commit (struct drm_encoder *encoder)
612{
613 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
614 /* lvds has its own version of commit see intel_lvds_commit */
615 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
616}
617
618static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
619 struct drm_display_mode *mode,
620 struct drm_display_mode *adjusted_mode)
621{
622 return true;
623}
624
625
626/** Returns the core display clock speed for i830 - i945 */
627static int intel_get_core_clock_speed(struct drm_device *dev)
628{
629
630 /* Core clock values taken from the published datasheets.
631 * The 830 may go up to 166 Mhz, which we should check.
632 */
633 if (IS_I945G(dev))
634 return 400000;
635 else if (IS_I915G(dev))
636 return 333000;
637 else if (IS_I945GM(dev) || IS_845G(dev))
638 return 200000;
639 else if (IS_I915GM(dev)) {
640 u16 gcfgc = 0;
641
642 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
643
644 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
645 return 133000;
646 else {
647 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
648 case GC_DISPLAY_CLOCK_333_MHZ:
649 return 333000;
650 default:
651 case GC_DISPLAY_CLOCK_190_200_MHZ:
652 return 190000;
653 }
654 }
655 } else if (IS_I865G(dev))
656 return 266000;
657 else if (IS_I855(dev)) {
658 u16 hpllcc = 0;
659 /* Assume that the hardware is in the high speed state. This
660 * should be the default.
661 */
662 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
663 case GC_CLOCK_133_200:
664 case GC_CLOCK_100_200:
665 return 200000;
666 case GC_CLOCK_166_250:
667 return 250000;
668 case GC_CLOCK_100_133:
669 return 133000;
670 }
671 } else /* 852, 830 */
672 return 133000;
673
674 return 0; /* Silence gcc warning */
675}
676
677
678/**
679 * Return the pipe currently connected to the panel fitter,
680 * or -1 if the panel fitter is not present or not in use
681 */
682static int intel_panel_fitter_pipe (struct drm_device *dev)
683{
684 struct drm_i915_private *dev_priv = dev->dev_private;
685 u32 pfit_control;
686
687 /* i830 doesn't have a panel fitter */
688 if (IS_I830(dev))
689 return -1;
690
691 pfit_control = I915_READ(PFIT_CONTROL);
692
693 /* See if the panel fitter is in use */
694 if ((pfit_control & PFIT_ENABLE) == 0)
695 return -1;
696
697 /* 965 can place panel fitter on either pipe */
698 if (IS_I965G(dev))
699 return (pfit_control >> 29) & 0x3;
700
701 /* older chips can only use pipe 1 */
702 return 1;
703}
704
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000705static int intel_crtc_mode_set(struct drm_crtc *crtc,
706 struct drm_display_mode *mode,
707 struct drm_display_mode *adjusted_mode,
708 int x, int y,
709 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -0800710{
711 struct drm_device *dev = crtc->dev;
712 struct drm_i915_private *dev_priv = dev->dev_private;
713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
714 int pipe = intel_crtc->pipe;
715 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
716 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
717 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
718 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
719 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
720 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
721 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
722 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
723 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
724 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
725 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
726 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
727 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
728 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
Kristian Høgsberg43565a02009-02-13 20:56:52 -0500729 int refclk, num_outputs = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -0800730 intel_clock_t clock;
731 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
732 bool ok, is_sdvo = false, is_dvo = false;
733 bool is_crt = false, is_lvds = false, is_tv = false;
734 struct drm_mode_config *mode_config = &dev->mode_config;
735 struct drm_connector *connector;
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000736 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -0800737
738 drm_vblank_pre_modeset(dev, pipe);
739
740 list_for_each_entry(connector, &mode_config->connector_list, head) {
741 struct intel_output *intel_output = to_intel_output(connector);
742
743 if (!connector->encoder || connector->encoder->crtc != crtc)
744 continue;
745
746 switch (intel_output->type) {
747 case INTEL_OUTPUT_LVDS:
748 is_lvds = true;
749 break;
750 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -0800751 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -0800752 is_sdvo = true;
Jesse Barnese2f0ba92009-02-02 15:11:52 -0800753 if (intel_output->needs_tv_clock)
754 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -0800755 break;
756 case INTEL_OUTPUT_DVO:
757 is_dvo = true;
758 break;
759 case INTEL_OUTPUT_TVOUT:
760 is_tv = true;
761 break;
762 case INTEL_OUTPUT_ANALOG:
763 is_crt = true;
764 break;
765 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -0500766
767 num_outputs++;
Jesse Barnes79e53942008-11-07 14:24:08 -0800768 }
769
Kristian Høgsberg43565a02009-02-13 20:56:52 -0500770 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
771 refclk = dev_priv->lvds_ssc_freq * 1000;
772 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
773 } else if (IS_I9XX(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800774 refclk = 96000;
775 } else {
776 refclk = 48000;
777 }
778
779 ok = intel_find_best_PLL(crtc, adjusted_mode->clock, refclk, &clock);
780 if (!ok) {
781 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000782 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -0800783 }
784
785 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
786
787 dpll = DPLL_VGA_MODE_DIS;
788 if (IS_I9XX(dev)) {
789 if (is_lvds)
790 dpll |= DPLLB_MODE_LVDS;
791 else
792 dpll |= DPLLB_MODE_DAC_SERIAL;
793 if (is_sdvo) {
794 dpll |= DPLL_DVO_HIGH_SPEED;
795 if (IS_I945G(dev) || IS_I945GM(dev)) {
796 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
797 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
798 }
799 }
800
801 /* compute bitmask from p1 value */
802 dpll |= (1 << (clock.p1 - 1)) << 16;
803 switch (clock.p2) {
804 case 5:
805 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
806 break;
807 case 7:
808 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
809 break;
810 case 10:
811 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
812 break;
813 case 14:
814 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
815 break;
816 }
817 if (IS_I965G(dev))
818 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
819 } else {
820 if (is_lvds) {
821 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
822 } else {
823 if (clock.p1 == 2)
824 dpll |= PLL_P1_DIVIDE_BY_TWO;
825 else
826 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
827 if (clock.p2 == 4)
828 dpll |= PLL_P2_DIVIDE_BY_4;
829 }
830 }
831
Kristian Høgsberg43565a02009-02-13 20:56:52 -0500832 if (is_sdvo && is_tv)
833 dpll |= PLL_REF_INPUT_TVCLKINBC;
834 else if (is_tv)
Jesse Barnes79e53942008-11-07 14:24:08 -0800835 /* XXX: just matching BIOS for now */
Kristian Høgsberg43565a02009-02-13 20:56:52 -0500836 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
Jesse Barnes79e53942008-11-07 14:24:08 -0800837 dpll |= 3;
Kristian Høgsberg43565a02009-02-13 20:56:52 -0500838 else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
839 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -0800840 else
841 dpll |= PLL_REF_INPUT_DREFCLK;
842
843 /* setup pipeconf */
844 pipeconf = I915_READ(pipeconf_reg);
845
846 /* Set up the display plane register */
847 dspcntr = DISPPLANE_GAMMA_ENABLE;
848
849 if (pipe == 0)
850 dspcntr |= DISPPLANE_SEL_PIPE_A;
851 else
852 dspcntr |= DISPPLANE_SEL_PIPE_B;
853
854 if (pipe == 0 && !IS_I965G(dev)) {
855 /* Enable pixel doubling when the dot clock is > 90% of the (display)
856 * core speed.
857 *
858 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
859 * pipe == 0 check?
860 */
861 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
862 pipeconf |= PIPEACONF_DOUBLE_WIDE;
863 else
864 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
865 }
866
867 dspcntr |= DISPLAY_PLANE_ENABLE;
868 pipeconf |= PIPEACONF_ENABLE;
869 dpll |= DPLL_VCO_ENABLE;
870
871
872 /* Disable the panel fitter if it was on our pipe */
873 if (intel_panel_fitter_pipe(dev) == pipe)
874 I915_WRITE(PFIT_CONTROL, 0);
875
876 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
877 drm_mode_debug_printmodeline(mode);
878
879
880 if (dpll & DPLL_VCO_ENABLE) {
881 I915_WRITE(fp_reg, fp);
882 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
883 I915_READ(dpll_reg);
884 udelay(150);
885 }
886
887 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
888 * This is an exception to the general rule that mode_set doesn't turn
889 * things on.
890 */
891 if (is_lvds) {
892 u32 lvds = I915_READ(LVDS);
893
894 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
895 /* Set the B0-B3 data pairs corresponding to whether we're going to
896 * set the DPLLs for dual-channel mode or not.
897 */
898 if (clock.p2 == 7)
899 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
900 else
901 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
902
903 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
904 * appropriately here, but we need to look more thoroughly into how
905 * panels behave in the two modes.
906 */
907
908 I915_WRITE(LVDS, lvds);
909 I915_READ(LVDS);
910 }
911
912 I915_WRITE(fp_reg, fp);
913 I915_WRITE(dpll_reg, dpll);
914 I915_READ(dpll_reg);
915 /* Wait for the clocks to stabilize. */
916 udelay(150);
917
918 if (IS_I965G(dev)) {
919 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
920 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
921 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
922 } else {
923 /* write it again -- the BIOS does, after all */
924 I915_WRITE(dpll_reg, dpll);
925 }
926 I915_READ(dpll_reg);
927 /* Wait for the clocks to stabilize. */
928 udelay(150);
929
930 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
931 ((adjusted_mode->crtc_htotal - 1) << 16));
932 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
933 ((adjusted_mode->crtc_hblank_end - 1) << 16));
934 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
935 ((adjusted_mode->crtc_hsync_end - 1) << 16));
936 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
937 ((adjusted_mode->crtc_vtotal - 1) << 16));
938 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
939 ((adjusted_mode->crtc_vblank_end - 1) << 16));
940 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
941 ((adjusted_mode->crtc_vsync_end - 1) << 16));
942 /* pipesrc and dspsize control the size that is scaled from, which should
943 * always be the user's requested size.
944 */
945 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
946 I915_WRITE(dsppos_reg, 0);
947 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
948 I915_WRITE(pipeconf_reg, pipeconf);
949 I915_READ(pipeconf_reg);
950
951 intel_wait_for_vblank(dev);
952
953 I915_WRITE(dspcntr_reg, dspcntr);
954
955 /* Flush the plane changes */
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000956 ret = intel_pipe_set_base(crtc, x, y, old_fb);
957 if (ret != 0)
958 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -0800959
960 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +0000961
962 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -0800963}
964
965/** Loads the palette/gamma unit for the CRTC with the prepared values */
966void intel_crtc_load_lut(struct drm_crtc *crtc)
967{
968 struct drm_device *dev = crtc->dev;
969 struct drm_i915_private *dev_priv = dev->dev_private;
970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
971 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
972 int i;
973
974 /* The clocks have to be on to load the palette. */
975 if (!crtc->enabled)
976 return;
977
978 for (i = 0; i < 256; i++) {
979 I915_WRITE(palreg + 4 * i,
980 (intel_crtc->lut_r[i] << 16) |
981 (intel_crtc->lut_g[i] << 8) |
982 intel_crtc->lut_b[i]);
983 }
984}
985
986static int intel_crtc_cursor_set(struct drm_crtc *crtc,
987 struct drm_file *file_priv,
988 uint32_t handle,
989 uint32_t width, uint32_t height)
990{
991 struct drm_device *dev = crtc->dev;
992 struct drm_i915_private *dev_priv = dev->dev_private;
993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
994 struct drm_gem_object *bo;
995 struct drm_i915_gem_object *obj_priv;
996 int pipe = intel_crtc->pipe;
997 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
998 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
999 uint32_t temp;
1000 size_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05001001 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08001002
1003 DRM_DEBUG("\n");
1004
1005 /* if we want to turn off the cursor ignore width and height */
1006 if (!handle) {
1007 DRM_DEBUG("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05001008 temp = CURSOR_MODE_DISABLE;
1009 addr = 0;
1010 bo = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10001011 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05001012 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08001013 }
1014
1015 /* Currently we only support 64x64 cursors */
1016 if (width != 64 || height != 64) {
1017 DRM_ERROR("we currently only support 64x64 cursors\n");
1018 return -EINVAL;
1019 }
1020
1021 bo = drm_gem_object_lookup(dev, file_priv, handle);
1022 if (!bo)
1023 return -ENOENT;
1024
1025 obj_priv = bo->driver_private;
1026
1027 if (bo->size < width * height * 4) {
1028 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10001029 ret = -ENOMEM;
1030 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08001031 }
1032
Dave Airlie71acb5e2008-12-30 20:31:46 +10001033 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05001034 mutex_lock(&dev->struct_mutex);
Dave Airlie71acb5e2008-12-30 20:31:46 +10001035 if (!dev_priv->cursor_needs_physical) {
1036 ret = i915_gem_object_pin(bo, PAGE_SIZE);
1037 if (ret) {
1038 DRM_ERROR("failed to pin cursor bo\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05001039 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10001040 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001041 addr = obj_priv->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10001042 } else {
1043 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
1044 if (ret) {
1045 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05001046 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10001047 }
1048 addr = obj_priv->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05001049 }
1050
Jesse Barnes79e53942008-11-07 14:24:08 -08001051 temp = 0;
1052 /* set the pipe for the cursor */
1053 temp |= (pipe << 28);
1054 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1055
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05001056 finish:
Jesse Barnes79e53942008-11-07 14:24:08 -08001057 I915_WRITE(control, temp);
1058 I915_WRITE(base, addr);
1059
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05001060 if (intel_crtc->cursor_bo) {
Dave Airlie71acb5e2008-12-30 20:31:46 +10001061 if (dev_priv->cursor_needs_physical) {
1062 if (intel_crtc->cursor_bo != bo)
1063 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
1064 } else
1065 i915_gem_object_unpin(intel_crtc->cursor_bo);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05001066 drm_gem_object_unreference(intel_crtc->cursor_bo);
1067 }
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05001068 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05001069
1070 intel_crtc->cursor_addr = addr;
1071 intel_crtc->cursor_bo = bo;
1072
Jesse Barnes79e53942008-11-07 14:24:08 -08001073 return 0;
Dave Airlie34b8686e2009-01-15 14:03:07 +10001074fail:
1075 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05001076fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10001077 drm_gem_object_unreference(bo);
1078 mutex_unlock(&dev->struct_mutex);
1079 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08001080}
1081
1082static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1083{
1084 struct drm_device *dev = crtc->dev;
1085 struct drm_i915_private *dev_priv = dev->dev_private;
1086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1087 int pipe = intel_crtc->pipe;
1088 uint32_t temp = 0;
1089 uint32_t adder;
1090
1091 if (x < 0) {
1092 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1093 x = -x;
1094 }
1095 if (y < 0) {
1096 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1097 y = -y;
1098 }
1099
1100 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1101 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1102
1103 adder = intel_crtc->cursor_addr;
1104 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1105 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
1106
1107 return 0;
1108}
1109
1110/** Sets the color ramps on behalf of RandR */
1111void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1112 u16 blue, int regno)
1113{
1114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1115
1116 intel_crtc->lut_r[regno] = red >> 8;
1117 intel_crtc->lut_g[regno] = green >> 8;
1118 intel_crtc->lut_b[regno] = blue >> 8;
1119}
1120
1121static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1122 u16 *blue, uint32_t size)
1123{
1124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1125 int i;
1126
1127 if (size != 256)
1128 return;
1129
1130 for (i = 0; i < 256; i++) {
1131 intel_crtc->lut_r[i] = red[i] >> 8;
1132 intel_crtc->lut_g[i] = green[i] >> 8;
1133 intel_crtc->lut_b[i] = blue[i] >> 8;
1134 }
1135
1136 intel_crtc_load_lut(crtc);
1137}
1138
1139/**
1140 * Get a pipe with a simple mode set on it for doing load-based monitor
1141 * detection.
1142 *
1143 * It will be up to the load-detect code to adjust the pipe as appropriate for
1144 * its requirements. The pipe will be connected to no other outputs.
1145 *
1146 * Currently this code will only succeed if there is a pipe with no outputs
1147 * configured for it. In the future, it could choose to temporarily disable
1148 * some outputs to free up a pipe for its use.
1149 *
1150 * \return crtc, or NULL if no pipes are available.
1151 */
1152
1153/* VESA 640x480x72Hz mode to set on the pipe */
1154static struct drm_display_mode load_detect_mode = {
1155 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
1156 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1157};
1158
1159struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
1160 struct drm_display_mode *mode,
1161 int *dpms_mode)
1162{
1163 struct intel_crtc *intel_crtc;
1164 struct drm_crtc *possible_crtc;
1165 struct drm_crtc *supported_crtc =NULL;
1166 struct drm_encoder *encoder = &intel_output->enc;
1167 struct drm_crtc *crtc = NULL;
1168 struct drm_device *dev = encoder->dev;
1169 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1170 struct drm_crtc_helper_funcs *crtc_funcs;
1171 int i = -1;
1172
1173 /*
1174 * Algorithm gets a little messy:
1175 * - if the connector already has an assigned crtc, use it (but make
1176 * sure it's on first)
1177 * - try to find the first unused crtc that can drive this connector,
1178 * and use that if we find one
1179 * - if there are no unused crtcs available, try to use the first
1180 * one we found that supports the connector
1181 */
1182
1183 /* See if we already have a CRTC for this connector */
1184 if (encoder->crtc) {
1185 crtc = encoder->crtc;
1186 /* Make sure the crtc and connector are running */
1187 intel_crtc = to_intel_crtc(crtc);
1188 *dpms_mode = intel_crtc->dpms_mode;
1189 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
1190 crtc_funcs = crtc->helper_private;
1191 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1192 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1193 }
1194 return crtc;
1195 }
1196
1197 /* Find an unused one (if possible) */
1198 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
1199 i++;
1200 if (!(encoder->possible_crtcs & (1 << i)))
1201 continue;
1202 if (!possible_crtc->enabled) {
1203 crtc = possible_crtc;
1204 break;
1205 }
1206 if (!supported_crtc)
1207 supported_crtc = possible_crtc;
1208 }
1209
1210 /*
1211 * If we didn't find an unused CRTC, don't use any.
1212 */
1213 if (!crtc) {
1214 return NULL;
1215 }
1216
1217 encoder->crtc = crtc;
1218 intel_output->load_detect_temp = true;
1219
1220 intel_crtc = to_intel_crtc(crtc);
1221 *dpms_mode = intel_crtc->dpms_mode;
1222
1223 if (!crtc->enabled) {
1224 if (!mode)
1225 mode = &load_detect_mode;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001226 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08001227 } else {
1228 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
1229 crtc_funcs = crtc->helper_private;
1230 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1231 }
1232
1233 /* Add this connector to the crtc */
1234 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
1235 encoder_funcs->commit(encoder);
1236 }
1237 /* let the connector get through one full cycle before testing */
1238 intel_wait_for_vblank(dev);
1239
1240 return crtc;
1241}
1242
1243void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
1244{
1245 struct drm_encoder *encoder = &intel_output->enc;
1246 struct drm_device *dev = encoder->dev;
1247 struct drm_crtc *crtc = encoder->crtc;
1248 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1249 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1250
1251 if (intel_output->load_detect_temp) {
1252 encoder->crtc = NULL;
1253 intel_output->load_detect_temp = false;
1254 crtc->enabled = drm_helper_crtc_in_use(crtc);
1255 drm_helper_disable_unused_functions(dev);
1256 }
1257
1258 /* Switch crtc and output back off if necessary */
1259 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
1260 if (encoder->crtc == crtc)
1261 encoder_funcs->dpms(encoder, dpms_mode);
1262 crtc_funcs->dpms(crtc, dpms_mode);
1263 }
1264}
1265
1266/* Returns the clock of the currently programmed mode of the given pipe. */
1267static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
1268{
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1271 int pipe = intel_crtc->pipe;
1272 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
1273 u32 fp;
1274 intel_clock_t clock;
1275
1276 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1277 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
1278 else
1279 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
1280
1281 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1282 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1283 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1284 if (IS_I9XX(dev)) {
1285 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
1286 DPLL_FPA01_P1_POST_DIV_SHIFT);
1287
1288 switch (dpll & DPLL_MODE_MASK) {
1289 case DPLLB_MODE_DAC_SERIAL:
1290 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
1291 5 : 10;
1292 break;
1293 case DPLLB_MODE_LVDS:
1294 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
1295 7 : 14;
1296 break;
1297 default:
1298 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
1299 "mode\n", (int)(dpll & DPLL_MODE_MASK));
1300 return 0;
1301 }
1302
1303 /* XXX: Handle the 100Mhz refclk */
Kristian Høgsberga29f5ca2009-02-13 20:56:51 -05001304 intel_clock(96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08001305 } else {
1306 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
1307
1308 if (is_lvds) {
1309 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1310 DPLL_FPA01_P1_POST_DIV_SHIFT);
1311 clock.p2 = 14;
1312
1313 if ((dpll & PLL_REF_INPUT_MASK) ==
1314 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1315 /* XXX: might not be 66MHz */
Kristian Høgsberga29f5ca2009-02-13 20:56:51 -05001316 intel_clock(66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08001317 } else
Kristian Høgsberga29f5ca2009-02-13 20:56:51 -05001318 intel_clock(48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08001319 } else {
1320 if (dpll & PLL_P1_DIVIDE_BY_TWO)
1321 clock.p1 = 2;
1322 else {
1323 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1324 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1325 }
1326 if (dpll & PLL_P2_DIVIDE_BY_4)
1327 clock.p2 = 4;
1328 else
1329 clock.p2 = 2;
1330
Kristian Høgsberga29f5ca2009-02-13 20:56:51 -05001331 intel_clock(48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08001332 }
1333 }
1334
1335 /* XXX: It would be nice to validate the clocks, but we can't reuse
1336 * i830PllIsValid() because it relies on the xf86_config connector
1337 * configuration being accurate, which it isn't necessarily.
1338 */
1339
1340 return clock.dot;
1341}
1342
1343/** Returns the currently programmed mode of the given pipe. */
1344struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1345 struct drm_crtc *crtc)
1346{
1347 struct drm_i915_private *dev_priv = dev->dev_private;
1348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1349 int pipe = intel_crtc->pipe;
1350 struct drm_display_mode *mode;
1351 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
1352 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
1353 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
1354 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
1355
1356 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1357 if (!mode)
1358 return NULL;
1359
1360 mode->clock = intel_crtc_clock_get(dev, crtc);
1361 mode->hdisplay = (htot & 0xffff) + 1;
1362 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1363 mode->hsync_start = (hsync & 0xffff) + 1;
1364 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1365 mode->vdisplay = (vtot & 0xffff) + 1;
1366 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1367 mode->vsync_start = (vsync & 0xffff) + 1;
1368 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1369
1370 drm_mode_set_name(mode);
1371 drm_mode_set_crtcinfo(mode, 0);
1372
1373 return mode;
1374}
1375
1376static void intel_crtc_destroy(struct drm_crtc *crtc)
1377{
1378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1379
1380 drm_crtc_cleanup(crtc);
1381 kfree(intel_crtc);
1382}
1383
1384static const struct drm_crtc_helper_funcs intel_helper_funcs = {
1385 .dpms = intel_crtc_dpms,
1386 .mode_fixup = intel_crtc_mode_fixup,
1387 .mode_set = intel_crtc_mode_set,
1388 .mode_set_base = intel_pipe_set_base,
1389 .prepare = intel_crtc_prepare,
1390 .commit = intel_crtc_commit,
1391};
1392
1393static const struct drm_crtc_funcs intel_crtc_funcs = {
1394 .cursor_set = intel_crtc_cursor_set,
1395 .cursor_move = intel_crtc_cursor_move,
1396 .gamma_set = intel_crtc_gamma_set,
1397 .set_config = drm_crtc_helper_set_config,
1398 .destroy = intel_crtc_destroy,
1399};
1400
1401
Hannes Ederb358d0a2008-12-18 21:18:47 +01001402static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08001403{
1404 struct intel_crtc *intel_crtc;
1405 int i;
1406
1407 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
1408 if (intel_crtc == NULL)
1409 return;
1410
1411 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
1412
1413 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
1414 intel_crtc->pipe = pipe;
1415 for (i = 0; i < 256; i++) {
1416 intel_crtc->lut_r[i] = i;
1417 intel_crtc->lut_g[i] = i;
1418 intel_crtc->lut_b[i] = i;
1419 }
1420
1421 intel_crtc->cursor_addr = 0;
1422 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
1423 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
1424
1425 intel_crtc->mode_set.crtc = &intel_crtc->base;
1426 intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
1427 intel_crtc->mode_set.num_connectors = 0;
1428
1429 if (i915_fbpercrtc) {
1430
1431
1432
1433 }
1434}
1435
1436struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
1437{
1438 struct drm_crtc *crtc = NULL;
1439
1440 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1442 if (intel_crtc->pipe == pipe)
1443 break;
1444 }
1445 return crtc;
1446}
1447
Hannes Ederb358d0a2008-12-18 21:18:47 +01001448static int intel_connector_clones(struct drm_device *dev, int type_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08001449{
1450 int index_mask = 0;
1451 struct drm_connector *connector;
1452 int entry = 0;
1453
1454 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1455 struct intel_output *intel_output = to_intel_output(connector);
1456 if (type_mask & (1 << intel_output->type))
1457 index_mask |= (1 << entry);
1458 entry++;
1459 }
1460 return index_mask;
1461}
1462
1463
1464static void intel_setup_outputs(struct drm_device *dev)
1465{
Eric Anholt725e30a2009-01-22 13:01:02 -08001466 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08001467 struct drm_connector *connector;
1468
1469 intel_crt_init(dev);
1470
1471 /* Set up integrated LVDS */
1472 if (IS_MOBILE(dev) && !IS_I830(dev))
1473 intel_lvds_init(dev);
1474
1475 if (IS_I9XX(dev)) {
Eric Anholt7d573822009-01-02 13:33:00 -08001476 int found;
1477
Eric Anholt725e30a2009-01-22 13:01:02 -08001478 if (I915_READ(SDVOB) & SDVO_DETECTED) {
1479 found = intel_sdvo_init(dev, SDVOB);
1480 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1481 intel_hdmi_init(dev, SDVOB);
1482 }
1483 if (!IS_G4X(dev) || (I915_READ(SDVOB) & SDVO_DETECTED)) {
1484 found = intel_sdvo_init(dev, SDVOC);
1485 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
1486 intel_hdmi_init(dev, SDVOC);
1487 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001488 } else
1489 intel_dvo_init(dev);
1490
Eric Anholt1fc45d82009-01-02 15:57:35 -08001491 if (IS_I9XX(dev) && IS_MOBILE(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08001492 intel_tv_init(dev);
1493
1494 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1495 struct intel_output *intel_output = to_intel_output(connector);
1496 struct drm_encoder *encoder = &intel_output->enc;
1497 int crtc_mask = 0, clone_mask = 0;
1498
1499 /* valid crtcs */
1500 switch(intel_output->type) {
Eric Anholt7d573822009-01-02 13:33:00 -08001501 case INTEL_OUTPUT_HDMI:
1502 crtc_mask = ((1 << 0)|
1503 (1 << 1));
1504 clone_mask = ((1 << INTEL_OUTPUT_HDMI));
1505 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08001506 case INTEL_OUTPUT_DVO:
1507 case INTEL_OUTPUT_SDVO:
1508 crtc_mask = ((1 << 0)|
1509 (1 << 1));
1510 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
1511 (1 << INTEL_OUTPUT_DVO) |
1512 (1 << INTEL_OUTPUT_SDVO));
1513 break;
1514 case INTEL_OUTPUT_ANALOG:
1515 crtc_mask = ((1 << 0)|
1516 (1 << 1));
1517 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
1518 (1 << INTEL_OUTPUT_DVO) |
1519 (1 << INTEL_OUTPUT_SDVO));
1520 break;
1521 case INTEL_OUTPUT_LVDS:
1522 crtc_mask = (1 << 1);
1523 clone_mask = (1 << INTEL_OUTPUT_LVDS);
1524 break;
1525 case INTEL_OUTPUT_TVOUT:
1526 crtc_mask = ((1 << 0) |
1527 (1 << 1));
1528 clone_mask = (1 << INTEL_OUTPUT_TVOUT);
1529 break;
1530 }
1531 encoder->possible_crtcs = crtc_mask;
1532 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
1533 }
1534}
1535
1536static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
1537{
1538 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1539 struct drm_device *dev = fb->dev;
1540
1541 if (fb->fbdev)
1542 intelfb_remove(dev, fb);
1543
1544 drm_framebuffer_cleanup(fb);
1545 mutex_lock(&dev->struct_mutex);
1546 drm_gem_object_unreference(intel_fb->obj);
1547 mutex_unlock(&dev->struct_mutex);
1548
1549 kfree(intel_fb);
1550}
1551
1552static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1553 struct drm_file *file_priv,
1554 unsigned int *handle)
1555{
1556 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1557 struct drm_gem_object *object = intel_fb->obj;
1558
1559 return drm_gem_handle_create(file_priv, object, handle);
1560}
1561
1562static const struct drm_framebuffer_funcs intel_fb_funcs = {
1563 .destroy = intel_user_framebuffer_destroy,
1564 .create_handle = intel_user_framebuffer_create_handle,
1565};
1566
1567int intel_framebuffer_create(struct drm_device *dev,
1568 struct drm_mode_fb_cmd *mode_cmd,
1569 struct drm_framebuffer **fb,
1570 struct drm_gem_object *obj)
1571{
1572 struct intel_framebuffer *intel_fb;
1573 int ret;
1574
1575 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1576 if (!intel_fb)
1577 return -ENOMEM;
1578
1579 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
1580 if (ret) {
1581 DRM_ERROR("framebuffer init failed %d\n", ret);
1582 return ret;
1583 }
1584
1585 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
1586
1587 intel_fb->obj = obj;
1588
1589 *fb = &intel_fb->base;
1590
1591 return 0;
1592}
1593
1594
1595static struct drm_framebuffer *
1596intel_user_framebuffer_create(struct drm_device *dev,
1597 struct drm_file *filp,
1598 struct drm_mode_fb_cmd *mode_cmd)
1599{
1600 struct drm_gem_object *obj;
1601 struct drm_framebuffer *fb;
1602 int ret;
1603
1604 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
1605 if (!obj)
1606 return NULL;
1607
1608 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
1609 if (ret) {
Jesse Barnes496818f2009-02-11 13:28:14 -08001610 mutex_lock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08001611 drm_gem_object_unreference(obj);
Jesse Barnes496818f2009-02-11 13:28:14 -08001612 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08001613 return NULL;
1614 }
1615
1616 return fb;
1617}
1618
Jesse Barnes79e53942008-11-07 14:24:08 -08001619static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08001620 .fb_create = intel_user_framebuffer_create,
1621 .fb_changed = intelfb_probe,
1622};
1623
1624void intel_modeset_init(struct drm_device *dev)
1625{
1626 int num_pipe;
1627 int i;
1628
1629 drm_mode_config_init(dev);
1630
1631 dev->mode_config.min_width = 0;
1632 dev->mode_config.min_height = 0;
1633
1634 dev->mode_config.funcs = (void *)&intel_mode_funcs;
1635
1636 if (IS_I965G(dev)) {
1637 dev->mode_config.max_width = 8192;
1638 dev->mode_config.max_height = 8192;
1639 } else {
1640 dev->mode_config.max_width = 2048;
1641 dev->mode_config.max_height = 2048;
1642 }
1643
1644 /* set memory base */
1645 if (IS_I9XX(dev))
1646 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
1647 else
1648 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
1649
1650 if (IS_MOBILE(dev) || IS_I9XX(dev))
1651 num_pipe = 2;
1652 else
1653 num_pipe = 1;
1654 DRM_DEBUG("%d display pipe%s available.\n",
1655 num_pipe, num_pipe > 1 ? "s" : "");
1656
1657 for (i = 0; i < num_pipe; i++) {
1658 intel_crtc_init(dev, i);
1659 }
1660
1661 intel_setup_outputs(dev);
1662}
1663
1664void intel_modeset_cleanup(struct drm_device *dev)
1665{
1666 drm_mode_config_cleanup(dev);
1667}
1668
1669
1670/* current intel driver doesn't take advantage of encoders
1671 always give back the encoder for the connector
1672*/
1673struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
1674{
1675 struct intel_output *intel_output = to_intel_output(connector);
1676
1677 return &intel_output->enc;
1678}