Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Support for the Tundra Universe I/II VME-PCI Bridge Chips |
| 3 | * |
Martyn Welch | 66bd8db | 2010-02-18 15:12:52 +0000 | [diff] [blame] | 4 | * Author: Martyn Welch <martyn.welch@ge.com> |
| 5 | * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 6 | * |
| 7 | * Based on work by Tom Armistead and Ajit Prem |
| 8 | * Copyright 2004 Motorola Inc. |
| 9 | * |
| 10 | * Derived from ca91c042.c by Michael Wyrick |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify it |
| 13 | * under the terms of the GNU General Public License as published by the |
| 14 | * Free Software Foundation; either version 2 of the License, or (at your |
| 15 | * option) any later version. |
| 16 | */ |
| 17 | |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 18 | #include <linux/module.h> |
| 19 | #include <linux/mm.h> |
| 20 | #include <linux/types.h> |
| 21 | #include <linux/errno.h> |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 22 | #include <linux/pci.h> |
| 23 | #include <linux/dma-mapping.h> |
| 24 | #include <linux/poll.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/spinlock.h> |
Greg Kroah-Hartman | 6af783c | 2009-10-12 15:00:08 -0700 | [diff] [blame] | 27 | #include <linux/sched.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 28 | #include <linux/slab.h> |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 29 | #include <linux/time.h> |
| 30 | #include <linux/io.h> |
| 31 | #include <linux/uaccess.h> |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 32 | |
| 33 | #include "../vme.h" |
| 34 | #include "../vme_bridge.h" |
| 35 | #include "vme_ca91cx42.h" |
| 36 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 37 | static int __init ca91cx42_init(void); |
| 38 | static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *); |
| 39 | static void ca91cx42_remove(struct pci_dev *); |
| 40 | static void __exit ca91cx42_exit(void); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 41 | |
Martyn Welch | 12b2d5c | 2009-12-15 08:42:56 +0000 | [diff] [blame] | 42 | /* Module parameters */ |
| 43 | static int geoid; |
| 44 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 45 | static char driver_name[] = "vme_ca91cx42"; |
| 46 | |
Németh Márton | 13ac58d | 2010-01-10 00:18:26 +0100 | [diff] [blame] | 47 | static const struct pci_device_id ca91cx42_ids[] = { |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 48 | { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) }, |
| 49 | { }, |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 50 | }; |
| 51 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 52 | static struct pci_driver ca91cx42_driver = { |
| 53 | .name = driver_name, |
| 54 | .id_table = ca91cx42_ids, |
| 55 | .probe = ca91cx42_probe, |
| 56 | .remove = ca91cx42_remove, |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 57 | }; |
| 58 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 59 | static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge) |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 60 | { |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 61 | wake_up(&(bridge->dma_queue)); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 62 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 63 | return CA91CX42_LINT_DMA; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 64 | } |
| 65 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 66 | static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat) |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 67 | { |
| 68 | int i; |
| 69 | u32 serviced = 0; |
| 70 | |
| 71 | for (i = 0; i < 4; i++) { |
| 72 | if (stat & CA91CX42_LINT_LM[i]) { |
| 73 | /* We only enable interrupts if the callback is set */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 74 | bridge->lm_callback[i](i); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 75 | serviced |= CA91CX42_LINT_LM[i]; |
| 76 | } |
| 77 | } |
| 78 | |
| 79 | return serviced; |
| 80 | } |
| 81 | |
| 82 | /* XXX This needs to be split into 4 queues */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 83 | static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask) |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 84 | { |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 85 | wake_up(&(bridge->mbox_queue)); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 86 | |
| 87 | return CA91CX42_LINT_MBOX; |
| 88 | } |
| 89 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 90 | static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge) |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 91 | { |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 92 | wake_up(&(bridge->iack_queue)); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 93 | |
| 94 | return CA91CX42_LINT_SW_IACK; |
| 95 | } |
| 96 | |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 97 | static u32 ca91cx42_VERR_irqhandler(struct vme_bridge *ca91cx42_bridge) |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 98 | { |
| 99 | int val; |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 100 | struct ca91cx42_driver *bridge; |
| 101 | |
| 102 | bridge = ca91cx42_bridge->driver_priv; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 103 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 104 | val = ioread32(bridge->base + DGCS); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 105 | |
| 106 | if (!(val & 0x00000800)) { |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 107 | dev_err(ca91cx42_bridge->parent, "ca91cx42_VERR_irqhandler DMA " |
| 108 | "Read Error DGCS=%08X\n", val); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 109 | } |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 110 | |
| 111 | return CA91CX42_LINT_VERR; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 112 | } |
| 113 | |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 114 | static u32 ca91cx42_LERR_irqhandler(struct vme_bridge *ca91cx42_bridge) |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 115 | { |
| 116 | int val; |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 117 | struct ca91cx42_driver *bridge; |
| 118 | |
| 119 | bridge = ca91cx42_bridge->driver_priv; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 120 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 121 | val = ioread32(bridge->base + DGCS); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 122 | |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 123 | if (!(val & 0x00000800)) |
| 124 | dev_err(ca91cx42_bridge->parent, "ca91cx42_LERR_irqhandler DMA " |
| 125 | "Read Error DGCS=%08X\n", val); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 126 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 127 | return CA91CX42_LINT_LERR; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 128 | } |
| 129 | |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 130 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 131 | static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge, |
| 132 | int stat) |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 133 | { |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 134 | int vec, i, serviced = 0; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 135 | struct ca91cx42_driver *bridge; |
| 136 | |
| 137 | bridge = ca91cx42_bridge->driver_priv; |
| 138 | |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 139 | |
| 140 | for (i = 7; i > 0; i--) { |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 141 | if (stat & (1 << i)) { |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 142 | vec = ioread32(bridge->base + |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 143 | CA91CX42_V_STATID[i]) & 0xff; |
| 144 | |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 145 | vme_irq_handler(ca91cx42_bridge, i, vec); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 146 | |
| 147 | serviced |= (1 << i); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 148 | } |
| 149 | } |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 150 | |
| 151 | return serviced; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 152 | } |
| 153 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 154 | static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr) |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 155 | { |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 156 | u32 stat, enable, serviced = 0; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 157 | struct vme_bridge *ca91cx42_bridge; |
| 158 | struct ca91cx42_driver *bridge; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 159 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 160 | ca91cx42_bridge = ptr; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 161 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 162 | bridge = ca91cx42_bridge->driver_priv; |
| 163 | |
| 164 | enable = ioread32(bridge->base + LINT_EN); |
| 165 | stat = ioread32(bridge->base + LINT_STAT); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 166 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 167 | /* Only look at unmasked interrupts */ |
| 168 | stat &= enable; |
| 169 | |
| 170 | if (unlikely(!stat)) |
| 171 | return IRQ_NONE; |
| 172 | |
| 173 | if (stat & CA91CX42_LINT_DMA) |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 174 | serviced |= ca91cx42_DMA_irqhandler(bridge); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 175 | if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 | |
| 176 | CA91CX42_LINT_LM3)) |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 177 | serviced |= ca91cx42_LM_irqhandler(bridge, stat); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 178 | if (stat & CA91CX42_LINT_MBOX) |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 179 | serviced |= ca91cx42_MB_irqhandler(bridge, stat); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 180 | if (stat & CA91CX42_LINT_SW_IACK) |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 181 | serviced |= ca91cx42_IACK_irqhandler(bridge); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 182 | if (stat & CA91CX42_LINT_VERR) |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 183 | serviced |= ca91cx42_VERR_irqhandler(ca91cx42_bridge); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 184 | if (stat & CA91CX42_LINT_LERR) |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 185 | serviced |= ca91cx42_LERR_irqhandler(ca91cx42_bridge); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 186 | if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 | |
| 187 | CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 | |
| 188 | CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 | |
| 189 | CA91CX42_LINT_VIRQ7)) |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 190 | serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 191 | |
| 192 | /* Clear serviced interrupts */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 193 | iowrite32(stat, bridge->base + LINT_STAT); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 194 | |
| 195 | return IRQ_HANDLED; |
| 196 | } |
| 197 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 198 | static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge) |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 199 | { |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 200 | int result, tmp; |
| 201 | struct pci_dev *pdev; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 202 | struct ca91cx42_driver *bridge; |
| 203 | |
| 204 | bridge = ca91cx42_bridge->driver_priv; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 205 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 206 | /* Need pdev */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 207 | pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 208 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 209 | /* Initialise list for VME bus errors */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 210 | INIT_LIST_HEAD(&(ca91cx42_bridge->vme_errors)); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 211 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 212 | mutex_init(&(ca91cx42_bridge->irq_mtx)); |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 213 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 214 | /* Disable interrupts from PCI to VME */ |
| 215 | iowrite32(0, bridge->base + VINT_EN); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 216 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 217 | /* Disable PCI interrupts */ |
| 218 | iowrite32(0, bridge->base + LINT_EN); |
| 219 | /* Clear Any Pending PCI Interrupts */ |
| 220 | iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 221 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 222 | result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED, |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 223 | driver_name, ca91cx42_bridge); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 224 | if (result) { |
| 225 | dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n", |
| 226 | pdev->irq); |
| 227 | return result; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 228 | } |
| 229 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 230 | /* Ensure all interrupts are mapped to PCI Interrupt 0 */ |
| 231 | iowrite32(0, bridge->base + LINT_MAP0); |
| 232 | iowrite32(0, bridge->base + LINT_MAP1); |
| 233 | iowrite32(0, bridge->base + LINT_MAP2); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 234 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 235 | /* Enable DMA, mailbox & LM Interrupts */ |
| 236 | tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 | |
| 237 | CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK | |
| 238 | CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA; |
| 239 | |
| 240 | iowrite32(tmp, bridge->base + LINT_EN); |
| 241 | |
| 242 | return 0; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 243 | } |
| 244 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 245 | static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge, |
| 246 | struct pci_dev *pdev) |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 247 | { |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 248 | /* Disable interrupts from PCI to VME */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 249 | iowrite32(0, bridge->base + VINT_EN); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 250 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 251 | /* Disable PCI interrupts */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 252 | iowrite32(0, bridge->base + LINT_EN); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 253 | /* Clear Any Pending PCI Interrupts */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 254 | iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 255 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 256 | free_irq(pdev->irq, pdev); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 257 | } |
| 258 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 259 | /* |
| 260 | * Set up an VME interrupt |
| 261 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 262 | void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level, int state, |
| 263 | int sync) |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 264 | |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 265 | { |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 266 | struct pci_dev *pdev; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 267 | u32 tmp; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 268 | struct ca91cx42_driver *bridge; |
| 269 | |
| 270 | bridge = ca91cx42_bridge->driver_priv; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 271 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 272 | /* Enable IRQ level */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 273 | tmp = ioread32(bridge->base + LINT_EN); |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 274 | |
| 275 | if (state == 0) |
| 276 | tmp &= ~CA91CX42_LINT_VIRQ[level]; |
| 277 | else |
| 278 | tmp |= CA91CX42_LINT_VIRQ[level]; |
| 279 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 280 | iowrite32(tmp, bridge->base + LINT_EN); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 281 | |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 282 | if ((state == 0) && (sync != 0)) { |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 283 | pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, |
| 284 | dev); |
| 285 | |
| 286 | synchronize_irq(pdev->irq); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 287 | } |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 288 | } |
| 289 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 290 | int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level, |
| 291 | int statid) |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 292 | { |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 293 | u32 tmp; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 294 | struct ca91cx42_driver *bridge; |
| 295 | |
| 296 | bridge = ca91cx42_bridge->driver_priv; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 297 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 298 | /* Universe can only generate even vectors */ |
| 299 | if (statid & 1) |
| 300 | return -EINVAL; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 301 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 302 | mutex_lock(&(bridge->vme_int)); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 303 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 304 | tmp = ioread32(bridge->base + VINT_EN); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 305 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 306 | /* Set Status/ID */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 307 | iowrite32(statid << 24, bridge->base + STATID); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 308 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 309 | /* Assert VMEbus IRQ */ |
| 310 | tmp = tmp | (1 << (level + 24)); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 311 | iowrite32(tmp, bridge->base + VINT_EN); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 312 | |
| 313 | /* Wait for IACK */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 314 | wait_event_interruptible(bridge->iack_queue, 0); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 315 | |
| 316 | /* Return interrupt to low state */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 317 | tmp = ioread32(bridge->base + VINT_EN); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 318 | tmp = tmp & ~(1 << (level + 24)); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 319 | iowrite32(tmp, bridge->base + VINT_EN); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 320 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 321 | mutex_unlock(&(bridge->vme_int)); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 322 | |
| 323 | return 0; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 324 | } |
| 325 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 326 | int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, |
| 327 | unsigned long long vme_base, unsigned long long size, |
| 328 | dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle) |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 329 | { |
Martyn Welch | 21e0cf6 | 2010-02-18 15:13:32 +0000 | [diff] [blame] | 330 | unsigned int i, addr = 0, granularity; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 331 | unsigned int temp_ctl = 0; |
| 332 | unsigned int vme_bound, pci_offset; |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 333 | struct vme_bridge *ca91cx42_bridge; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 334 | struct ca91cx42_driver *bridge; |
| 335 | |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 336 | ca91cx42_bridge = image->parent; |
| 337 | |
| 338 | bridge = ca91cx42_bridge->driver_priv; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 339 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 340 | i = image->number; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 341 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 342 | switch (aspace) { |
| 343 | case VME_A16: |
| 344 | addr |= CA91CX42_VSI_CTL_VAS_A16; |
| 345 | break; |
| 346 | case VME_A24: |
| 347 | addr |= CA91CX42_VSI_CTL_VAS_A24; |
| 348 | break; |
| 349 | case VME_A32: |
| 350 | addr |= CA91CX42_VSI_CTL_VAS_A32; |
| 351 | break; |
| 352 | case VME_USER1: |
| 353 | addr |= CA91CX42_VSI_CTL_VAS_USER1; |
| 354 | break; |
| 355 | case VME_USER2: |
| 356 | addr |= CA91CX42_VSI_CTL_VAS_USER2; |
| 357 | break; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 358 | case VME_A64: |
| 359 | case VME_CRCSR: |
| 360 | case VME_USER3: |
| 361 | case VME_USER4: |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 362 | default: |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 363 | dev_err(ca91cx42_bridge->parent, "Invalid address space\n"); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 364 | return -EINVAL; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 365 | break; |
| 366 | } |
| 367 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 368 | /* |
| 369 | * Bound address is a valid address for the window, adjust |
| 370 | * accordingly |
| 371 | */ |
Martyn Welch | 21e0cf6 | 2010-02-18 15:13:32 +0000 | [diff] [blame] | 372 | vme_bound = vme_base + size; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 373 | pci_offset = pci_base - vme_base; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 374 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 375 | if ((i == 0) || (i == 4)) |
| 376 | granularity = 0x1000; |
| 377 | else |
| 378 | granularity = 0x10000; |
| 379 | |
| 380 | if (vme_base & (granularity - 1)) { |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 381 | dev_err(ca91cx42_bridge->parent, "Invalid VME base " |
| 382 | "alignment\n"); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 383 | return -EINVAL; |
| 384 | } |
| 385 | if (vme_bound & (granularity - 1)) { |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 386 | dev_err(ca91cx42_bridge->parent, "Invalid VME bound " |
| 387 | "alignment\n"); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 388 | return -EINVAL; |
| 389 | } |
| 390 | if (pci_offset & (granularity - 1)) { |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 391 | dev_err(ca91cx42_bridge->parent, "Invalid PCI Offset " |
| 392 | "alignment\n"); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 393 | return -EINVAL; |
| 394 | } |
| 395 | |
| 396 | /* Disable while we are mucking around */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 397 | temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 398 | temp_ctl &= ~CA91CX42_VSI_CTL_EN; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 399 | iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 400 | |
| 401 | /* Setup mapping */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 402 | iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]); |
| 403 | iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]); |
| 404 | iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 405 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 406 | /* Setup address space */ |
| 407 | temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M; |
| 408 | temp_ctl |= addr; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 409 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 410 | /* Setup cycle types */ |
| 411 | temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M); |
| 412 | if (cycle & VME_SUPER) |
| 413 | temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR; |
| 414 | if (cycle & VME_USER) |
| 415 | temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV; |
| 416 | if (cycle & VME_PROG) |
| 417 | temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM; |
| 418 | if (cycle & VME_DATA) |
| 419 | temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 420 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 421 | /* Write ctl reg without enable */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 422 | iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 423 | |
| 424 | if (enabled) |
| 425 | temp_ctl |= CA91CX42_VSI_CTL_EN; |
| 426 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 427 | iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 428 | |
| 429 | return 0; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 430 | } |
| 431 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 432 | int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled, |
| 433 | unsigned long long *vme_base, unsigned long long *size, |
| 434 | dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle) |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 435 | { |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 436 | unsigned int i, granularity = 0, ctl = 0; |
| 437 | unsigned long long vme_bound, pci_offset; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 438 | struct ca91cx42_driver *bridge; |
| 439 | |
| 440 | bridge = image->parent->driver_priv; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 441 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 442 | i = image->number; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 443 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 444 | if ((i == 0) || (i == 4)) |
| 445 | granularity = 0x1000; |
| 446 | else |
| 447 | granularity = 0x10000; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 448 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 449 | /* Read Registers */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 450 | ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 451 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 452 | *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]); |
| 453 | vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]); |
| 454 | pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 455 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 456 | *pci_base = (dma_addr_t)vme_base + pci_offset; |
| 457 | *size = (unsigned long long)((vme_bound - *vme_base) + granularity); |
| 458 | |
| 459 | *enabled = 0; |
| 460 | *aspace = 0; |
| 461 | *cycle = 0; |
| 462 | |
| 463 | if (ctl & CA91CX42_VSI_CTL_EN) |
| 464 | *enabled = 1; |
| 465 | |
| 466 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16) |
| 467 | *aspace = VME_A16; |
| 468 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24) |
| 469 | *aspace = VME_A24; |
| 470 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32) |
| 471 | *aspace = VME_A32; |
| 472 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1) |
| 473 | *aspace = VME_USER1; |
| 474 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2) |
| 475 | *aspace = VME_USER2; |
| 476 | |
| 477 | if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR) |
| 478 | *cycle |= VME_SUPER; |
| 479 | if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV) |
| 480 | *cycle |= VME_USER; |
| 481 | if (ctl & CA91CX42_VSI_CTL_PGM_PGM) |
| 482 | *cycle |= VME_PROG; |
| 483 | if (ctl & CA91CX42_VSI_CTL_PGM_DATA) |
| 484 | *cycle |= VME_DATA; |
| 485 | |
| 486 | return 0; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 487 | } |
| 488 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 489 | /* |
| 490 | * Allocate and map PCI Resource |
| 491 | */ |
| 492 | static int ca91cx42_alloc_resource(struct vme_master_resource *image, |
| 493 | unsigned long long size) |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 494 | { |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 495 | unsigned long long existing_size; |
| 496 | int retval = 0; |
| 497 | struct pci_dev *pdev; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 498 | struct vme_bridge *ca91cx42_bridge; |
| 499 | |
| 500 | ca91cx42_bridge = image->parent; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 501 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 502 | /* Find pci_dev container of dev */ |
| 503 | if (ca91cx42_bridge->parent == NULL) { |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 504 | dev_err(ca91cx42_bridge->parent, "Dev entry NULL\n"); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 505 | return -EINVAL; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 506 | } |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 507 | pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev); |
| 508 | |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 509 | existing_size = (unsigned long long)(image->bus_resource.end - |
| 510 | image->bus_resource.start); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 511 | |
| 512 | /* If the existing size is OK, return */ |
| 513 | if (existing_size == (size - 1)) |
| 514 | return 0; |
| 515 | |
| 516 | if (existing_size != 0) { |
| 517 | iounmap(image->kern_base); |
| 518 | image->kern_base = NULL; |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 519 | if (image->bus_resource.name != NULL) |
| 520 | kfree(image->bus_resource.name); |
| 521 | release_resource(&(image->bus_resource)); |
| 522 | memset(&(image->bus_resource), 0, sizeof(struct resource)); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 523 | } |
| 524 | |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 525 | if (image->bus_resource.name == NULL) { |
Julia Lawall | 0aa3f13 | 2010-05-30 22:27:46 +0200 | [diff] [blame] | 526 | image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC); |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 527 | if (image->bus_resource.name == NULL) { |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 528 | dev_err(ca91cx42_bridge->parent, "Unable to allocate " |
| 529 | "memory for resource name\n"); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 530 | retval = -ENOMEM; |
| 531 | goto err_name; |
| 532 | } |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 533 | } |
| 534 | |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 535 | sprintf((char *)image->bus_resource.name, "%s.%d", |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 536 | ca91cx42_bridge->name, image->number); |
| 537 | |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 538 | image->bus_resource.start = 0; |
| 539 | image->bus_resource.end = (unsigned long)size; |
| 540 | image->bus_resource.flags = IORESOURCE_MEM; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 541 | |
| 542 | retval = pci_bus_alloc_resource(pdev->bus, |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 543 | &(image->bus_resource), size, size, PCIBIOS_MIN_MEM, |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 544 | 0, NULL, NULL); |
| 545 | if (retval) { |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 546 | dev_err(ca91cx42_bridge->parent, "Failed to allocate mem " |
| 547 | "resource for window %d size 0x%lx start 0x%lx\n", |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 548 | image->number, (unsigned long)size, |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 549 | (unsigned long)image->bus_resource.start); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 550 | goto err_resource; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 551 | } |
| 552 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 553 | image->kern_base = ioremap_nocache( |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 554 | image->bus_resource.start, size); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 555 | if (image->kern_base == NULL) { |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 556 | dev_err(ca91cx42_bridge->parent, "Failed to remap resource\n"); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 557 | retval = -ENOMEM; |
| 558 | goto err_remap; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 559 | } |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 560 | |
| 561 | return 0; |
| 562 | |
| 563 | iounmap(image->kern_base); |
| 564 | image->kern_base = NULL; |
| 565 | err_remap: |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 566 | release_resource(&(image->bus_resource)); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 567 | err_resource: |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 568 | kfree(image->bus_resource.name); |
| 569 | memset(&(image->bus_resource), 0, sizeof(struct resource)); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 570 | err_name: |
| 571 | return retval; |
| 572 | } |
| 573 | |
| 574 | /* |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 575 | * Free and unmap PCI Resource |
| 576 | */ |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 577 | static void ca91cx42_free_resource(struct vme_master_resource *image) |
| 578 | { |
| 579 | iounmap(image->kern_base); |
| 580 | image->kern_base = NULL; |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 581 | release_resource(&(image->bus_resource)); |
| 582 | kfree(image->bus_resource.name); |
| 583 | memset(&(image->bus_resource), 0, sizeof(struct resource)); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 584 | } |
| 585 | |
| 586 | |
| 587 | int ca91cx42_master_set(struct vme_master_resource *image, int enabled, |
| 588 | unsigned long long vme_base, unsigned long long size, |
| 589 | vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth) |
| 590 | { |
| 591 | int retval = 0; |
Martyn Welch | 21e0cf6 | 2010-02-18 15:13:32 +0000 | [diff] [blame] | 592 | unsigned int i, granularity = 0; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 593 | unsigned int temp_ctl = 0; |
| 594 | unsigned long long pci_bound, vme_offset, pci_base; |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 595 | struct vme_bridge *ca91cx42_bridge; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 596 | struct ca91cx42_driver *bridge; |
| 597 | |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 598 | ca91cx42_bridge = image->parent; |
| 599 | |
| 600 | bridge = ca91cx42_bridge->driver_priv; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 601 | |
Martyn Welch | 21e0cf6 | 2010-02-18 15:13:32 +0000 | [diff] [blame] | 602 | i = image->number; |
| 603 | |
| 604 | if ((i == 0) || (i == 4)) |
| 605 | granularity = 0x1000; |
| 606 | else |
| 607 | granularity = 0x10000; |
| 608 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 609 | /* Verify input data */ |
Martyn Welch | 21e0cf6 | 2010-02-18 15:13:32 +0000 | [diff] [blame] | 610 | if (vme_base & (granularity - 1)) { |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 611 | dev_err(ca91cx42_bridge->parent, "Invalid VME Window " |
| 612 | "alignment\n"); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 613 | retval = -EINVAL; |
| 614 | goto err_window; |
| 615 | } |
Martyn Welch | 21e0cf6 | 2010-02-18 15:13:32 +0000 | [diff] [blame] | 616 | if (size & (granularity - 1)) { |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 617 | dev_err(ca91cx42_bridge->parent, "Invalid VME Window " |
| 618 | "alignment\n"); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 619 | retval = -EINVAL; |
| 620 | goto err_window; |
| 621 | } |
| 622 | |
| 623 | spin_lock(&(image->lock)); |
| 624 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 625 | /* |
| 626 | * Let's allocate the resource here rather than further up the stack as |
| 627 | * it avoids pushing loads of bus dependant stuff up the stack |
| 628 | */ |
| 629 | retval = ca91cx42_alloc_resource(image, size); |
| 630 | if (retval) { |
| 631 | spin_unlock(&(image->lock)); |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 632 | dev_err(ca91cx42_bridge->parent, "Unable to allocate memory " |
| 633 | "for resource name\n"); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 634 | retval = -ENOMEM; |
| 635 | goto err_res; |
| 636 | } |
| 637 | |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 638 | pci_base = (unsigned long long)image->bus_resource.start; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 639 | |
| 640 | /* |
| 641 | * Bound address is a valid address for the window, adjust |
| 642 | * according to window granularity. |
| 643 | */ |
Martyn Welch | 21e0cf6 | 2010-02-18 15:13:32 +0000 | [diff] [blame] | 644 | pci_bound = pci_base + size; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 645 | vme_offset = vme_base - pci_base; |
| 646 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 647 | /* Disable while we are mucking around */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 648 | temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 649 | temp_ctl &= ~CA91CX42_LSI_CTL_EN; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 650 | iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 651 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 652 | /* Setup cycle types */ |
| 653 | temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M; |
| 654 | if (cycle & VME_BLT) |
| 655 | temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT; |
| 656 | if (cycle & VME_MBLT) |
| 657 | temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 658 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 659 | /* Setup data width */ |
| 660 | temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M; |
| 661 | switch (dwidth) { |
| 662 | case VME_D8: |
| 663 | temp_ctl |= CA91CX42_LSI_CTL_VDW_D8; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 664 | break; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 665 | case VME_D16: |
| 666 | temp_ctl |= CA91CX42_LSI_CTL_VDW_D16; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 667 | break; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 668 | case VME_D32: |
| 669 | temp_ctl |= CA91CX42_LSI_CTL_VDW_D32; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 670 | break; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 671 | case VME_D64: |
| 672 | temp_ctl |= CA91CX42_LSI_CTL_VDW_D64; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 673 | break; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 674 | default: |
| 675 | spin_unlock(&(image->lock)); |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 676 | dev_err(ca91cx42_bridge->parent, "Invalid data width\n"); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 677 | retval = -EINVAL; |
| 678 | goto err_dwidth; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 679 | break; |
| 680 | } |
| 681 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 682 | /* Setup address space */ |
| 683 | temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M; |
| 684 | switch (aspace) { |
| 685 | case VME_A16: |
| 686 | temp_ctl |= CA91CX42_LSI_CTL_VAS_A16; |
| 687 | break; |
| 688 | case VME_A24: |
| 689 | temp_ctl |= CA91CX42_LSI_CTL_VAS_A24; |
| 690 | break; |
| 691 | case VME_A32: |
| 692 | temp_ctl |= CA91CX42_LSI_CTL_VAS_A32; |
| 693 | break; |
| 694 | case VME_CRCSR: |
| 695 | temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR; |
| 696 | break; |
| 697 | case VME_USER1: |
| 698 | temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1; |
| 699 | break; |
| 700 | case VME_USER2: |
| 701 | temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2; |
| 702 | break; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 703 | case VME_A64: |
| 704 | case VME_USER3: |
| 705 | case VME_USER4: |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 706 | default: |
| 707 | spin_unlock(&(image->lock)); |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 708 | dev_err(ca91cx42_bridge->parent, "Invalid address space\n"); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 709 | retval = -EINVAL; |
| 710 | goto err_aspace; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 711 | break; |
| 712 | } |
| 713 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 714 | temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M); |
| 715 | if (cycle & VME_SUPER) |
| 716 | temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR; |
| 717 | if (cycle & VME_PROG) |
| 718 | temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 719 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 720 | /* Setup mapping */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 721 | iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]); |
| 722 | iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]); |
| 723 | iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 724 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 725 | /* Write ctl reg without enable */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 726 | iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 727 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 728 | if (enabled) |
| 729 | temp_ctl |= CA91CX42_LSI_CTL_EN; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 730 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 731 | iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 732 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 733 | spin_unlock(&(image->lock)); |
| 734 | return 0; |
| 735 | |
| 736 | err_aspace: |
| 737 | err_dwidth: |
| 738 | ca91cx42_free_resource(image); |
| 739 | err_res: |
| 740 | err_window: |
| 741 | return retval; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 742 | } |
| 743 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 744 | int __ca91cx42_master_get(struct vme_master_resource *image, int *enabled, |
| 745 | unsigned long long *vme_base, unsigned long long *size, |
| 746 | vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth) |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 747 | { |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 748 | unsigned int i, ctl; |
| 749 | unsigned long long pci_base, pci_bound, vme_offset; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 750 | struct ca91cx42_driver *bridge; |
| 751 | |
| 752 | bridge = image->parent->driver_priv; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 753 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 754 | i = image->number; |
| 755 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 756 | ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 757 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 758 | pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]); |
| 759 | vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]); |
| 760 | pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 761 | |
| 762 | *vme_base = pci_base + vme_offset; |
Martyn Welch | 21e0cf6 | 2010-02-18 15:13:32 +0000 | [diff] [blame] | 763 | *size = (unsigned long long)(pci_bound - pci_base); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 764 | |
| 765 | *enabled = 0; |
| 766 | *aspace = 0; |
| 767 | *cycle = 0; |
| 768 | *dwidth = 0; |
| 769 | |
| 770 | if (ctl & CA91CX42_LSI_CTL_EN) |
| 771 | *enabled = 1; |
| 772 | |
| 773 | /* Setup address space */ |
| 774 | switch (ctl & CA91CX42_LSI_CTL_VAS_M) { |
| 775 | case CA91CX42_LSI_CTL_VAS_A16: |
| 776 | *aspace = VME_A16; |
| 777 | break; |
| 778 | case CA91CX42_LSI_CTL_VAS_A24: |
| 779 | *aspace = VME_A24; |
| 780 | break; |
| 781 | case CA91CX42_LSI_CTL_VAS_A32: |
| 782 | *aspace = VME_A32; |
| 783 | break; |
| 784 | case CA91CX42_LSI_CTL_VAS_CRCSR: |
| 785 | *aspace = VME_CRCSR; |
| 786 | break; |
| 787 | case CA91CX42_LSI_CTL_VAS_USER1: |
| 788 | *aspace = VME_USER1; |
| 789 | break; |
| 790 | case CA91CX42_LSI_CTL_VAS_USER2: |
| 791 | *aspace = VME_USER2; |
| 792 | break; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 793 | } |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 794 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 795 | /* XXX Not sure howto check for MBLT */ |
| 796 | /* Setup cycle types */ |
| 797 | if (ctl & CA91CX42_LSI_CTL_VCT_BLT) |
| 798 | *cycle |= VME_BLT; |
| 799 | else |
| 800 | *cycle |= VME_SCT; |
| 801 | |
| 802 | if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR) |
| 803 | *cycle |= VME_SUPER; |
| 804 | else |
| 805 | *cycle |= VME_USER; |
| 806 | |
| 807 | if (ctl & CA91CX42_LSI_CTL_PGM_PGM) |
| 808 | *cycle = VME_PROG; |
| 809 | else |
| 810 | *cycle = VME_DATA; |
| 811 | |
| 812 | /* Setup data width */ |
| 813 | switch (ctl & CA91CX42_LSI_CTL_VDW_M) { |
| 814 | case CA91CX42_LSI_CTL_VDW_D8: |
| 815 | *dwidth = VME_D8; |
| 816 | break; |
| 817 | case CA91CX42_LSI_CTL_VDW_D16: |
| 818 | *dwidth = VME_D16; |
| 819 | break; |
| 820 | case CA91CX42_LSI_CTL_VDW_D32: |
| 821 | *dwidth = VME_D32; |
| 822 | break; |
| 823 | case CA91CX42_LSI_CTL_VDW_D64: |
| 824 | *dwidth = VME_D64; |
| 825 | break; |
| 826 | } |
| 827 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 828 | return 0; |
Martyn Welch | 6047969 | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 829 | } |
| 830 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 831 | int ca91cx42_master_get(struct vme_master_resource *image, int *enabled, |
| 832 | unsigned long long *vme_base, unsigned long long *size, |
| 833 | vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth) |
| 834 | { |
| 835 | int retval; |
| 836 | |
| 837 | spin_lock(&(image->lock)); |
| 838 | |
| 839 | retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace, |
| 840 | cycle, dwidth); |
| 841 | |
| 842 | spin_unlock(&(image->lock)); |
| 843 | |
| 844 | return retval; |
| 845 | } |
| 846 | |
| 847 | ssize_t ca91cx42_master_read(struct vme_master_resource *image, void *buf, |
| 848 | size_t count, loff_t offset) |
| 849 | { |
Martyn Welch | 21e0cf6 | 2010-02-18 15:13:32 +0000 | [diff] [blame] | 850 | ssize_t retval; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 851 | |
| 852 | spin_lock(&(image->lock)); |
| 853 | |
| 854 | memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count); |
| 855 | retval = count; |
| 856 | |
| 857 | spin_unlock(&(image->lock)); |
| 858 | |
| 859 | return retval; |
| 860 | } |
| 861 | |
| 862 | ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf, |
| 863 | size_t count, loff_t offset) |
| 864 | { |
| 865 | int retval = 0; |
| 866 | |
| 867 | spin_lock(&(image->lock)); |
| 868 | |
| 869 | memcpy_toio(image->kern_base + offset, buf, (unsigned int)count); |
| 870 | retval = count; |
| 871 | |
| 872 | spin_unlock(&(image->lock)); |
| 873 | |
| 874 | return retval; |
| 875 | } |
| 876 | |
Martyn Welch | 04e10e1 | 2010-02-18 15:13:38 +0000 | [diff] [blame] | 877 | unsigned int ca91cx42_master_rmw(struct vme_master_resource *image, |
| 878 | unsigned int mask, unsigned int compare, unsigned int swap, |
| 879 | loff_t offset) |
| 880 | { |
| 881 | u32 pci_addr, result; |
| 882 | int i; |
| 883 | struct ca91cx42_driver *bridge; |
| 884 | struct device *dev; |
| 885 | |
| 886 | bridge = image->parent->driver_priv; |
| 887 | dev = image->parent->parent; |
| 888 | |
| 889 | /* Find the PCI address that maps to the desired VME address */ |
| 890 | i = image->number; |
| 891 | |
| 892 | /* Locking as we can only do one of these at a time */ |
| 893 | mutex_lock(&(bridge->vme_rmw)); |
| 894 | |
| 895 | /* Lock image */ |
| 896 | spin_lock(&(image->lock)); |
| 897 | |
| 898 | pci_addr = (u32)image->kern_base + offset; |
| 899 | |
| 900 | /* Address must be 4-byte aligned */ |
| 901 | if (pci_addr & 0x3) { |
| 902 | dev_err(dev, "RMW Address not 4-byte aligned\n"); |
Julia Lawall | 7c0ace5 | 2010-05-26 17:59:11 +0200 | [diff] [blame^] | 903 | result = -EINVAL; |
| 904 | goto out; |
Martyn Welch | 04e10e1 | 2010-02-18 15:13:38 +0000 | [diff] [blame] | 905 | } |
| 906 | |
| 907 | /* Ensure RMW Disabled whilst configuring */ |
| 908 | iowrite32(0, bridge->base + SCYC_CTL); |
| 909 | |
| 910 | /* Configure registers */ |
| 911 | iowrite32(mask, bridge->base + SCYC_EN); |
| 912 | iowrite32(compare, bridge->base + SCYC_CMP); |
| 913 | iowrite32(swap, bridge->base + SCYC_SWP); |
| 914 | iowrite32(pci_addr, bridge->base + SCYC_ADDR); |
| 915 | |
| 916 | /* Enable RMW */ |
| 917 | iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL); |
| 918 | |
| 919 | /* Kick process off with a read to the required address. */ |
| 920 | result = ioread32(image->kern_base + offset); |
| 921 | |
| 922 | /* Disable RMW */ |
| 923 | iowrite32(0, bridge->base + SCYC_CTL); |
| 924 | |
Julia Lawall | 7c0ace5 | 2010-05-26 17:59:11 +0200 | [diff] [blame^] | 925 | out: |
Martyn Welch | 04e10e1 | 2010-02-18 15:13:38 +0000 | [diff] [blame] | 926 | spin_unlock(&(image->lock)); |
| 927 | |
| 928 | mutex_unlock(&(bridge->vme_rmw)); |
| 929 | |
| 930 | return result; |
| 931 | } |
| 932 | |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 933 | int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, |
| 934 | struct vme_dma_attr *dest, size_t count) |
| 935 | { |
| 936 | struct ca91cx42_dma_entry *entry, *prev; |
| 937 | struct vme_dma_pci *pci_attr; |
| 938 | struct vme_dma_vme *vme_attr; |
| 939 | dma_addr_t desc_ptr; |
| 940 | int retval = 0; |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 941 | struct device *dev; |
| 942 | |
| 943 | dev = list->parent->parent->parent; |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 944 | |
| 945 | /* XXX descriptor must be aligned on 64-bit boundaries */ |
Julia Lawall | 3241487 | 2010-05-11 20:26:57 +0200 | [diff] [blame] | 946 | entry = kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL); |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 947 | if (entry == NULL) { |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 948 | dev_err(dev, "Failed to allocate memory for dma resource " |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 949 | "structure\n"); |
| 950 | retval = -ENOMEM; |
| 951 | goto err_mem; |
| 952 | } |
| 953 | |
| 954 | /* Test descriptor alignment */ |
| 955 | if ((unsigned long)&(entry->descriptor) & CA91CX42_DCPP_M) { |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 956 | dev_err(dev, "Descriptor not aligned to 16 byte boundary as " |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 957 | "required: %p\n", &(entry->descriptor)); |
| 958 | retval = -EINVAL; |
| 959 | goto err_align; |
| 960 | } |
| 961 | |
| 962 | memset(&(entry->descriptor), 0, sizeof(struct ca91cx42_dma_descriptor)); |
| 963 | |
| 964 | if (dest->type == VME_DMA_VME) { |
| 965 | entry->descriptor.dctl |= CA91CX42_DCTL_L2V; |
| 966 | vme_attr = (struct vme_dma_vme *)dest->private; |
| 967 | pci_attr = (struct vme_dma_pci *)src->private; |
| 968 | } else { |
| 969 | vme_attr = (struct vme_dma_vme *)src->private; |
| 970 | pci_attr = (struct vme_dma_pci *)dest->private; |
| 971 | } |
| 972 | |
| 973 | /* Check we can do fullfill required attributes */ |
| 974 | if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 | |
| 975 | VME_USER2)) != 0) { |
| 976 | |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 977 | dev_err(dev, "Unsupported cycle type\n"); |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 978 | retval = -EINVAL; |
| 979 | goto err_aspace; |
| 980 | } |
| 981 | |
| 982 | if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER | |
| 983 | VME_PROG | VME_DATA)) != 0) { |
| 984 | |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 985 | dev_err(dev, "Unsupported cycle type\n"); |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 986 | retval = -EINVAL; |
| 987 | goto err_cycle; |
| 988 | } |
| 989 | |
| 990 | /* Check to see if we can fullfill source and destination */ |
| 991 | if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) || |
| 992 | ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) { |
| 993 | |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 994 | dev_err(dev, "Cannot perform transfer with this " |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 995 | "source-destination combination\n"); |
| 996 | retval = -EINVAL; |
| 997 | goto err_direct; |
| 998 | } |
| 999 | |
| 1000 | /* Setup cycle types */ |
| 1001 | if (vme_attr->cycle & VME_BLT) |
| 1002 | entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT; |
| 1003 | |
| 1004 | /* Setup data width */ |
| 1005 | switch (vme_attr->dwidth) { |
| 1006 | case VME_D8: |
| 1007 | entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8; |
| 1008 | break; |
| 1009 | case VME_D16: |
| 1010 | entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16; |
| 1011 | break; |
| 1012 | case VME_D32: |
| 1013 | entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32; |
| 1014 | break; |
| 1015 | case VME_D64: |
| 1016 | entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64; |
| 1017 | break; |
| 1018 | default: |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1019 | dev_err(dev, "Invalid data width\n"); |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 1020 | return -EINVAL; |
| 1021 | } |
| 1022 | |
| 1023 | /* Setup address space */ |
| 1024 | switch (vme_attr->aspace) { |
| 1025 | case VME_A16: |
| 1026 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16; |
| 1027 | break; |
| 1028 | case VME_A24: |
| 1029 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24; |
| 1030 | break; |
| 1031 | case VME_A32: |
| 1032 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32; |
| 1033 | break; |
| 1034 | case VME_USER1: |
| 1035 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1; |
| 1036 | break; |
| 1037 | case VME_USER2: |
| 1038 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2; |
| 1039 | break; |
| 1040 | default: |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1041 | dev_err(dev, "Invalid address space\n"); |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 1042 | return -EINVAL; |
| 1043 | break; |
| 1044 | } |
| 1045 | |
| 1046 | if (vme_attr->cycle & VME_SUPER) |
| 1047 | entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR; |
| 1048 | if (vme_attr->cycle & VME_PROG) |
| 1049 | entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM; |
| 1050 | |
| 1051 | entry->descriptor.dtbc = count; |
| 1052 | entry->descriptor.dla = pci_attr->address; |
| 1053 | entry->descriptor.dva = vme_attr->address; |
| 1054 | entry->descriptor.dcpp = CA91CX42_DCPP_NULL; |
| 1055 | |
| 1056 | /* Add to list */ |
| 1057 | list_add_tail(&(entry->list), &(list->entries)); |
| 1058 | |
| 1059 | /* Fill out previous descriptors "Next Address" */ |
| 1060 | if (entry->list.prev != &(list->entries)) { |
| 1061 | prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry, |
| 1062 | list); |
| 1063 | /* We need the bus address for the pointer */ |
| 1064 | desc_ptr = virt_to_bus(&(entry->descriptor)); |
| 1065 | prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M; |
| 1066 | } |
| 1067 | |
| 1068 | return 0; |
| 1069 | |
| 1070 | err_cycle: |
| 1071 | err_aspace: |
| 1072 | err_direct: |
| 1073 | err_align: |
| 1074 | kfree(entry); |
| 1075 | err_mem: |
| 1076 | return retval; |
| 1077 | } |
| 1078 | |
| 1079 | static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge) |
| 1080 | { |
| 1081 | u32 tmp; |
| 1082 | struct ca91cx42_driver *bridge; |
| 1083 | |
| 1084 | bridge = ca91cx42_bridge->driver_priv; |
| 1085 | |
| 1086 | tmp = ioread32(bridge->base + DGCS); |
| 1087 | |
| 1088 | if (tmp & CA91CX42_DGCS_ACT) |
| 1089 | return 0; |
| 1090 | else |
| 1091 | return 1; |
| 1092 | } |
| 1093 | |
| 1094 | int ca91cx42_dma_list_exec(struct vme_dma_list *list) |
| 1095 | { |
| 1096 | struct vme_dma_resource *ctrlr; |
| 1097 | struct ca91cx42_dma_entry *entry; |
| 1098 | int retval = 0; |
| 1099 | dma_addr_t bus_addr; |
| 1100 | u32 val; |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1101 | struct device *dev; |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 1102 | struct ca91cx42_driver *bridge; |
| 1103 | |
| 1104 | ctrlr = list->parent; |
| 1105 | |
| 1106 | bridge = ctrlr->parent->driver_priv; |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1107 | dev = ctrlr->parent->parent; |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 1108 | |
| 1109 | mutex_lock(&(ctrlr->mtx)); |
| 1110 | |
| 1111 | if (!(list_empty(&(ctrlr->running)))) { |
| 1112 | /* |
| 1113 | * XXX We have an active DMA transfer and currently haven't |
| 1114 | * sorted out the mechanism for "pending" DMA transfers. |
| 1115 | * Return busy. |
| 1116 | */ |
| 1117 | /* Need to add to pending here */ |
| 1118 | mutex_unlock(&(ctrlr->mtx)); |
| 1119 | return -EBUSY; |
| 1120 | } else { |
| 1121 | list_add(&(list->list), &(ctrlr->running)); |
| 1122 | } |
| 1123 | |
| 1124 | /* Get first bus address and write into registers */ |
| 1125 | entry = list_first_entry(&(list->entries), struct ca91cx42_dma_entry, |
| 1126 | list); |
| 1127 | |
| 1128 | bus_addr = virt_to_bus(&(entry->descriptor)); |
| 1129 | |
| 1130 | mutex_unlock(&(ctrlr->mtx)); |
| 1131 | |
| 1132 | iowrite32(0, bridge->base + DTBC); |
| 1133 | iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP); |
| 1134 | |
| 1135 | /* Start the operation */ |
| 1136 | val = ioread32(bridge->base + DGCS); |
| 1137 | |
| 1138 | /* XXX Could set VMEbus On and Off Counters here */ |
| 1139 | val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M); |
| 1140 | |
| 1141 | val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT | |
| 1142 | CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR | |
| 1143 | CA91CX42_DGCS_PERR); |
| 1144 | |
| 1145 | iowrite32(val, bridge->base + DGCS); |
| 1146 | |
| 1147 | val |= CA91CX42_DGCS_GO; |
| 1148 | |
| 1149 | iowrite32(val, bridge->base + DGCS); |
| 1150 | |
| 1151 | wait_event_interruptible(bridge->dma_queue, |
| 1152 | ca91cx42_dma_busy(ctrlr->parent)); |
| 1153 | |
| 1154 | /* |
| 1155 | * Read status register, this register is valid until we kick off a |
| 1156 | * new transfer. |
| 1157 | */ |
| 1158 | val = ioread32(bridge->base + DGCS); |
| 1159 | |
| 1160 | if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR | |
| 1161 | CA91CX42_DGCS_PERR)) { |
| 1162 | |
Martyn Welch | 48d9356e | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1163 | dev_err(dev, "ca91c042: DMA Error. DGCS=%08X\n", val); |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 1164 | val = ioread32(bridge->base + DCTL); |
| 1165 | } |
| 1166 | |
| 1167 | /* Remove list from running list */ |
| 1168 | mutex_lock(&(ctrlr->mtx)); |
| 1169 | list_del(&(list->list)); |
| 1170 | mutex_unlock(&(ctrlr->mtx)); |
| 1171 | |
| 1172 | return retval; |
| 1173 | |
| 1174 | } |
| 1175 | |
| 1176 | int ca91cx42_dma_list_empty(struct vme_dma_list *list) |
| 1177 | { |
| 1178 | struct list_head *pos, *temp; |
| 1179 | struct ca91cx42_dma_entry *entry; |
| 1180 | |
| 1181 | /* detach and free each entry */ |
| 1182 | list_for_each_safe(pos, temp, &(list->entries)) { |
| 1183 | list_del(pos); |
| 1184 | entry = list_entry(pos, struct ca91cx42_dma_entry, list); |
| 1185 | kfree(entry); |
| 1186 | } |
| 1187 | |
| 1188 | return 0; |
| 1189 | } |
| 1190 | |
Martyn Welch | 2b82beb | 2010-02-18 15:13:19 +0000 | [diff] [blame] | 1191 | /* |
| 1192 | * All 4 location monitors reside at the same base - this is therefore a |
| 1193 | * system wide configuration. |
| 1194 | * |
| 1195 | * This does not enable the LM monitor - that should be done when the first |
| 1196 | * callback is attached and disabled when the last callback is removed. |
| 1197 | */ |
| 1198 | int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, |
| 1199 | vme_address_t aspace, vme_cycle_t cycle) |
| 1200 | { |
| 1201 | u32 temp_base, lm_ctl = 0; |
| 1202 | int i; |
| 1203 | struct ca91cx42_driver *bridge; |
| 1204 | struct device *dev; |
| 1205 | |
| 1206 | bridge = lm->parent->driver_priv; |
| 1207 | dev = lm->parent->parent; |
| 1208 | |
| 1209 | /* Check the alignment of the location monitor */ |
| 1210 | temp_base = (u32)lm_base; |
| 1211 | if (temp_base & 0xffff) { |
| 1212 | dev_err(dev, "Location monitor must be aligned to 64KB " |
| 1213 | "boundary"); |
| 1214 | return -EINVAL; |
| 1215 | } |
| 1216 | |
| 1217 | mutex_lock(&(lm->mtx)); |
| 1218 | |
| 1219 | /* If we already have a callback attached, we can't move it! */ |
| 1220 | for (i = 0; i < lm->monitors; i++) { |
| 1221 | if (bridge->lm_callback[i] != NULL) { |
| 1222 | mutex_unlock(&(lm->mtx)); |
| 1223 | dev_err(dev, "Location monitor callback attached, " |
| 1224 | "can't reset\n"); |
| 1225 | return -EBUSY; |
| 1226 | } |
| 1227 | } |
| 1228 | |
| 1229 | switch (aspace) { |
| 1230 | case VME_A16: |
| 1231 | lm_ctl |= CA91CX42_LM_CTL_AS_A16; |
| 1232 | break; |
| 1233 | case VME_A24: |
| 1234 | lm_ctl |= CA91CX42_LM_CTL_AS_A24; |
| 1235 | break; |
| 1236 | case VME_A32: |
| 1237 | lm_ctl |= CA91CX42_LM_CTL_AS_A32; |
| 1238 | break; |
| 1239 | default: |
| 1240 | mutex_unlock(&(lm->mtx)); |
| 1241 | dev_err(dev, "Invalid address space\n"); |
| 1242 | return -EINVAL; |
| 1243 | break; |
| 1244 | } |
| 1245 | |
| 1246 | if (cycle & VME_SUPER) |
| 1247 | lm_ctl |= CA91CX42_LM_CTL_SUPR; |
| 1248 | if (cycle & VME_USER) |
| 1249 | lm_ctl |= CA91CX42_LM_CTL_NPRIV; |
| 1250 | if (cycle & VME_PROG) |
| 1251 | lm_ctl |= CA91CX42_LM_CTL_PGM; |
| 1252 | if (cycle & VME_DATA) |
| 1253 | lm_ctl |= CA91CX42_LM_CTL_DATA; |
| 1254 | |
| 1255 | iowrite32(lm_base, bridge->base + LM_BS); |
| 1256 | iowrite32(lm_ctl, bridge->base + LM_CTL); |
| 1257 | |
| 1258 | mutex_unlock(&(lm->mtx)); |
| 1259 | |
| 1260 | return 0; |
| 1261 | } |
| 1262 | |
| 1263 | /* Get configuration of the callback monitor and return whether it is enabled |
| 1264 | * or disabled. |
| 1265 | */ |
| 1266 | int ca91cx42_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base, |
| 1267 | vme_address_t *aspace, vme_cycle_t *cycle) |
| 1268 | { |
| 1269 | u32 lm_ctl, enabled = 0; |
| 1270 | struct ca91cx42_driver *bridge; |
| 1271 | |
| 1272 | bridge = lm->parent->driver_priv; |
| 1273 | |
| 1274 | mutex_lock(&(lm->mtx)); |
| 1275 | |
| 1276 | *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS); |
| 1277 | lm_ctl = ioread32(bridge->base + LM_CTL); |
| 1278 | |
| 1279 | if (lm_ctl & CA91CX42_LM_CTL_EN) |
| 1280 | enabled = 1; |
| 1281 | |
| 1282 | if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16) |
| 1283 | *aspace = VME_A16; |
| 1284 | if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24) |
| 1285 | *aspace = VME_A24; |
| 1286 | if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32) |
| 1287 | *aspace = VME_A32; |
| 1288 | |
| 1289 | *cycle = 0; |
| 1290 | if (lm_ctl & CA91CX42_LM_CTL_SUPR) |
| 1291 | *cycle |= VME_SUPER; |
| 1292 | if (lm_ctl & CA91CX42_LM_CTL_NPRIV) |
| 1293 | *cycle |= VME_USER; |
| 1294 | if (lm_ctl & CA91CX42_LM_CTL_PGM) |
| 1295 | *cycle |= VME_PROG; |
| 1296 | if (lm_ctl & CA91CX42_LM_CTL_DATA) |
| 1297 | *cycle |= VME_DATA; |
| 1298 | |
| 1299 | mutex_unlock(&(lm->mtx)); |
| 1300 | |
| 1301 | return enabled; |
| 1302 | } |
| 1303 | |
| 1304 | /* |
| 1305 | * Attach a callback to a specific location monitor. |
| 1306 | * |
| 1307 | * Callback will be passed the monitor triggered. |
| 1308 | */ |
| 1309 | int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor, |
| 1310 | void (*callback)(int)) |
| 1311 | { |
| 1312 | u32 lm_ctl, tmp; |
| 1313 | struct ca91cx42_driver *bridge; |
| 1314 | struct device *dev; |
| 1315 | |
| 1316 | bridge = lm->parent->driver_priv; |
| 1317 | dev = lm->parent->parent; |
| 1318 | |
| 1319 | mutex_lock(&(lm->mtx)); |
| 1320 | |
| 1321 | /* Ensure that the location monitor is configured - need PGM or DATA */ |
| 1322 | lm_ctl = ioread32(bridge->base + LM_CTL); |
| 1323 | if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) { |
| 1324 | mutex_unlock(&(lm->mtx)); |
| 1325 | dev_err(dev, "Location monitor not properly configured\n"); |
| 1326 | return -EINVAL; |
| 1327 | } |
| 1328 | |
| 1329 | /* Check that a callback isn't already attached */ |
| 1330 | if (bridge->lm_callback[monitor] != NULL) { |
| 1331 | mutex_unlock(&(lm->mtx)); |
| 1332 | dev_err(dev, "Existing callback attached\n"); |
| 1333 | return -EBUSY; |
| 1334 | } |
| 1335 | |
| 1336 | /* Attach callback */ |
| 1337 | bridge->lm_callback[monitor] = callback; |
| 1338 | |
| 1339 | /* Enable Location Monitor interrupt */ |
| 1340 | tmp = ioread32(bridge->base + LINT_EN); |
| 1341 | tmp |= CA91CX42_LINT_LM[monitor]; |
| 1342 | iowrite32(tmp, bridge->base + LINT_EN); |
| 1343 | |
| 1344 | /* Ensure that global Location Monitor Enable set */ |
| 1345 | if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) { |
| 1346 | lm_ctl |= CA91CX42_LM_CTL_EN; |
| 1347 | iowrite32(lm_ctl, bridge->base + LM_CTL); |
| 1348 | } |
| 1349 | |
| 1350 | mutex_unlock(&(lm->mtx)); |
| 1351 | |
| 1352 | return 0; |
| 1353 | } |
| 1354 | |
| 1355 | /* |
| 1356 | * Detach a callback function forn a specific location monitor. |
| 1357 | */ |
| 1358 | int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor) |
| 1359 | { |
| 1360 | u32 tmp; |
| 1361 | struct ca91cx42_driver *bridge; |
| 1362 | |
| 1363 | bridge = lm->parent->driver_priv; |
| 1364 | |
| 1365 | mutex_lock(&(lm->mtx)); |
| 1366 | |
| 1367 | /* Disable Location Monitor and ensure previous interrupts are clear */ |
| 1368 | tmp = ioread32(bridge->base + LINT_EN); |
| 1369 | tmp &= ~CA91CX42_LINT_LM[monitor]; |
| 1370 | iowrite32(tmp, bridge->base + LINT_EN); |
| 1371 | |
| 1372 | iowrite32(CA91CX42_LINT_LM[monitor], |
| 1373 | bridge->base + LINT_STAT); |
| 1374 | |
| 1375 | /* Detach callback */ |
| 1376 | bridge->lm_callback[monitor] = NULL; |
| 1377 | |
| 1378 | /* If all location monitors disabled, disable global Location Monitor */ |
| 1379 | if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 | |
| 1380 | CA91CX42_LINT_LM3)) == 0) { |
| 1381 | tmp = ioread32(bridge->base + LM_CTL); |
| 1382 | tmp &= ~CA91CX42_LM_CTL_EN; |
| 1383 | iowrite32(tmp, bridge->base + LM_CTL); |
| 1384 | } |
| 1385 | |
| 1386 | mutex_unlock(&(lm->mtx)); |
| 1387 | |
| 1388 | return 0; |
| 1389 | } |
| 1390 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1391 | int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge) |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1392 | { |
| 1393 | u32 slot = 0; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1394 | struct ca91cx42_driver *bridge; |
| 1395 | |
| 1396 | bridge = ca91cx42_bridge->driver_priv; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1397 | |
Martyn Welch | 12b2d5c | 2009-12-15 08:42:56 +0000 | [diff] [blame] | 1398 | if (!geoid) { |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1399 | slot = ioread32(bridge->base + VCSR_BS); |
Martyn Welch | 12b2d5c | 2009-12-15 08:42:56 +0000 | [diff] [blame] | 1400 | slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27); |
| 1401 | } else |
| 1402 | slot = geoid; |
| 1403 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1404 | return (int)slot; |
| 1405 | |
| 1406 | } |
| 1407 | |
| 1408 | static int __init ca91cx42_init(void) |
| 1409 | { |
| 1410 | return pci_register_driver(&ca91cx42_driver); |
| 1411 | } |
| 1412 | |
| 1413 | /* |
| 1414 | * Configure CR/CSR space |
| 1415 | * |
| 1416 | * Access to the CR/CSR can be configured at power-up. The location of the |
| 1417 | * CR/CSR registers in the CR/CSR address space is determined by the boards |
| 1418 | * Auto-ID or Geographic address. This function ensures that the window is |
| 1419 | * enabled at an offset consistent with the boards geopgraphic address. |
| 1420 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1421 | static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge, |
| 1422 | struct pci_dev *pdev) |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1423 | { |
| 1424 | unsigned int crcsr_addr; |
| 1425 | int tmp, slot; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1426 | struct ca91cx42_driver *bridge; |
| 1427 | |
| 1428 | bridge = ca91cx42_bridge->driver_priv; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1429 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1430 | slot = ca91cx42_slot_get(ca91cx42_bridge); |
Martyn Welch | 25331ba | 2010-02-18 15:13:45 +0000 | [diff] [blame] | 1431 | |
| 1432 | /* Write CSR Base Address if slot ID is supplied as a module param */ |
| 1433 | if (geoid) |
| 1434 | iowrite32(geoid << 27, bridge->base + VCSR_BS); |
| 1435 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1436 | dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot); |
| 1437 | if (slot == 0) { |
| 1438 | dev_err(&pdev->dev, "Slot number is unset, not configuring " |
| 1439 | "CR/CSR space\n"); |
| 1440 | return -EINVAL; |
| 1441 | } |
| 1442 | |
| 1443 | /* Allocate mem for CR/CSR image */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1444 | bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, |
| 1445 | &(bridge->crcsr_bus)); |
| 1446 | if (bridge->crcsr_kernel == NULL) { |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1447 | dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR " |
| 1448 | "image\n"); |
| 1449 | return -ENOMEM; |
| 1450 | } |
| 1451 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1452 | memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1453 | |
| 1454 | crcsr_addr = slot * (512 * 1024); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1455 | iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1456 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1457 | tmp = ioread32(bridge->base + VCSR_CTL); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1458 | tmp |= CA91CX42_VCSR_CTL_EN; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1459 | iowrite32(tmp, bridge->base + VCSR_CTL); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1460 | |
| 1461 | return 0; |
| 1462 | } |
| 1463 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1464 | static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge, |
| 1465 | struct pci_dev *pdev) |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1466 | { |
| 1467 | u32 tmp; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1468 | struct ca91cx42_driver *bridge; |
| 1469 | |
| 1470 | bridge = ca91cx42_bridge->driver_priv; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1471 | |
| 1472 | /* Turn off CR/CSR space */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1473 | tmp = ioread32(bridge->base + VCSR_CTL); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1474 | tmp &= ~CA91CX42_VCSR_CTL_EN; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1475 | iowrite32(tmp, bridge->base + VCSR_CTL); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1476 | |
| 1477 | /* Free image */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1478 | iowrite32(0, bridge->base + VCSR_TO); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1479 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1480 | pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel, |
| 1481 | bridge->crcsr_bus); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1482 | } |
| 1483 | |
| 1484 | static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
| 1485 | { |
| 1486 | int retval, i; |
| 1487 | u32 data; |
| 1488 | struct list_head *pos = NULL; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1489 | struct vme_bridge *ca91cx42_bridge; |
| 1490 | struct ca91cx42_driver *ca91cx42_device; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1491 | struct vme_master_resource *master_image; |
| 1492 | struct vme_slave_resource *slave_image; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1493 | struct vme_dma_resource *dma_ctrlr; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1494 | struct vme_lm_resource *lm; |
| 1495 | |
| 1496 | /* We want to support more than one of each bridge so we need to |
| 1497 | * dynamically allocate the bridge structure |
| 1498 | */ |
Julia Lawall | 7a6cb0d | 2010-05-13 22:00:05 +0200 | [diff] [blame] | 1499 | ca91cx42_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1500 | |
| 1501 | if (ca91cx42_bridge == NULL) { |
| 1502 | dev_err(&pdev->dev, "Failed to allocate memory for device " |
| 1503 | "structure\n"); |
| 1504 | retval = -ENOMEM; |
| 1505 | goto err_struct; |
| 1506 | } |
| 1507 | |
Julia Lawall | 7a6cb0d | 2010-05-13 22:00:05 +0200 | [diff] [blame] | 1508 | ca91cx42_device = kzalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1509 | |
| 1510 | if (ca91cx42_device == NULL) { |
| 1511 | dev_err(&pdev->dev, "Failed to allocate memory for device " |
| 1512 | "structure\n"); |
| 1513 | retval = -ENOMEM; |
| 1514 | goto err_driver; |
| 1515 | } |
| 1516 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1517 | ca91cx42_bridge->driver_priv = ca91cx42_device; |
| 1518 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1519 | /* Enable the device */ |
| 1520 | retval = pci_enable_device(pdev); |
| 1521 | if (retval) { |
| 1522 | dev_err(&pdev->dev, "Unable to enable device\n"); |
| 1523 | goto err_enable; |
| 1524 | } |
| 1525 | |
| 1526 | /* Map Registers */ |
| 1527 | retval = pci_request_regions(pdev, driver_name); |
| 1528 | if (retval) { |
| 1529 | dev_err(&pdev->dev, "Unable to reserve resources\n"); |
| 1530 | goto err_resource; |
| 1531 | } |
| 1532 | |
| 1533 | /* map registers in BAR 0 */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1534 | ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0), |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1535 | 4096); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1536 | if (!ca91cx42_device->base) { |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1537 | dev_err(&pdev->dev, "Unable to remap CRG region\n"); |
| 1538 | retval = -EIO; |
| 1539 | goto err_remap; |
| 1540 | } |
| 1541 | |
| 1542 | /* Check to see if the mapping worked out */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1543 | data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1544 | if (data != PCI_VENDOR_ID_TUNDRA) { |
| 1545 | dev_err(&pdev->dev, "PCI_ID check failed\n"); |
| 1546 | retval = -EIO; |
| 1547 | goto err_test; |
| 1548 | } |
| 1549 | |
| 1550 | /* Initialize wait queues & mutual exclusion flags */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1551 | init_waitqueue_head(&(ca91cx42_device->dma_queue)); |
| 1552 | init_waitqueue_head(&(ca91cx42_device->iack_queue)); |
| 1553 | mutex_init(&(ca91cx42_device->vme_int)); |
| 1554 | mutex_init(&(ca91cx42_device->vme_rmw)); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1555 | |
| 1556 | ca91cx42_bridge->parent = &(pdev->dev); |
| 1557 | strcpy(ca91cx42_bridge->name, driver_name); |
| 1558 | |
| 1559 | /* Setup IRQ */ |
| 1560 | retval = ca91cx42_irq_init(ca91cx42_bridge); |
| 1561 | if (retval != 0) { |
| 1562 | dev_err(&pdev->dev, "Chip Initialization failed.\n"); |
| 1563 | goto err_irq; |
| 1564 | } |
| 1565 | |
| 1566 | /* Add master windows to list */ |
| 1567 | INIT_LIST_HEAD(&(ca91cx42_bridge->master_resources)); |
| 1568 | for (i = 0; i < CA91C142_MAX_MASTER; i++) { |
| 1569 | master_image = kmalloc(sizeof(struct vme_master_resource), |
| 1570 | GFP_KERNEL); |
| 1571 | if (master_image == NULL) { |
| 1572 | dev_err(&pdev->dev, "Failed to allocate memory for " |
| 1573 | "master resource structure\n"); |
| 1574 | retval = -ENOMEM; |
| 1575 | goto err_master; |
| 1576 | } |
| 1577 | master_image->parent = ca91cx42_bridge; |
| 1578 | spin_lock_init(&(master_image->lock)); |
| 1579 | master_image->locked = 0; |
| 1580 | master_image->number = i; |
| 1581 | master_image->address_attr = VME_A16 | VME_A24 | VME_A32 | |
| 1582 | VME_CRCSR | VME_USER1 | VME_USER2; |
| 1583 | master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | |
| 1584 | VME_SUPER | VME_USER | VME_PROG | VME_DATA; |
| 1585 | master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64; |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 1586 | memset(&(master_image->bus_resource), 0, |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1587 | sizeof(struct resource)); |
| 1588 | master_image->kern_base = NULL; |
| 1589 | list_add_tail(&(master_image->list), |
| 1590 | &(ca91cx42_bridge->master_resources)); |
| 1591 | } |
| 1592 | |
| 1593 | /* Add slave windows to list */ |
| 1594 | INIT_LIST_HEAD(&(ca91cx42_bridge->slave_resources)); |
| 1595 | for (i = 0; i < CA91C142_MAX_SLAVE; i++) { |
| 1596 | slave_image = kmalloc(sizeof(struct vme_slave_resource), |
| 1597 | GFP_KERNEL); |
| 1598 | if (slave_image == NULL) { |
| 1599 | dev_err(&pdev->dev, "Failed to allocate memory for " |
| 1600 | "slave resource structure\n"); |
| 1601 | retval = -ENOMEM; |
| 1602 | goto err_slave; |
| 1603 | } |
| 1604 | slave_image->parent = ca91cx42_bridge; |
| 1605 | mutex_init(&(slave_image->mtx)); |
| 1606 | slave_image->locked = 0; |
| 1607 | slave_image->number = i; |
| 1608 | slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 | |
| 1609 | VME_USER2; |
| 1610 | |
| 1611 | /* Only windows 0 and 4 support A16 */ |
| 1612 | if (i == 0 || i == 4) |
| 1613 | slave_image->address_attr |= VME_A16; |
| 1614 | |
| 1615 | slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | |
| 1616 | VME_SUPER | VME_USER | VME_PROG | VME_DATA; |
| 1617 | list_add_tail(&(slave_image->list), |
| 1618 | &(ca91cx42_bridge->slave_resources)); |
| 1619 | } |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 1620 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1621 | /* Add dma engines to list */ |
| 1622 | INIT_LIST_HEAD(&(ca91cx42_bridge->dma_resources)); |
| 1623 | for (i = 0; i < CA91C142_MAX_DMA; i++) { |
| 1624 | dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource), |
| 1625 | GFP_KERNEL); |
| 1626 | if (dma_ctrlr == NULL) { |
| 1627 | dev_err(&pdev->dev, "Failed to allocate memory for " |
| 1628 | "dma resource structure\n"); |
| 1629 | retval = -ENOMEM; |
| 1630 | goto err_dma; |
| 1631 | } |
| 1632 | dma_ctrlr->parent = ca91cx42_bridge; |
| 1633 | mutex_init(&(dma_ctrlr->mtx)); |
| 1634 | dma_ctrlr->locked = 0; |
| 1635 | dma_ctrlr->number = i; |
Martyn Welch | 4f723df | 2010-02-18 15:12:58 +0000 | [diff] [blame] | 1636 | dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM | |
| 1637 | VME_DMA_MEM_TO_VME; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1638 | INIT_LIST_HEAD(&(dma_ctrlr->pending)); |
| 1639 | INIT_LIST_HEAD(&(dma_ctrlr->running)); |
| 1640 | list_add_tail(&(dma_ctrlr->list), |
| 1641 | &(ca91cx42_bridge->dma_resources)); |
| 1642 | } |
Martyn Welch | 4860ab7 | 2010-02-18 15:13:25 +0000 | [diff] [blame] | 1643 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1644 | /* Add location monitor to list */ |
| 1645 | INIT_LIST_HEAD(&(ca91cx42_bridge->lm_resources)); |
| 1646 | lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL); |
| 1647 | if (lm == NULL) { |
| 1648 | dev_err(&pdev->dev, "Failed to allocate memory for " |
| 1649 | "location monitor resource structure\n"); |
| 1650 | retval = -ENOMEM; |
| 1651 | goto err_lm; |
| 1652 | } |
| 1653 | lm->parent = ca91cx42_bridge; |
| 1654 | mutex_init(&(lm->mtx)); |
| 1655 | lm->locked = 0; |
| 1656 | lm->number = 1; |
| 1657 | lm->monitors = 4; |
| 1658 | list_add_tail(&(lm->list), &(ca91cx42_bridge->lm_resources)); |
| 1659 | |
| 1660 | ca91cx42_bridge->slave_get = ca91cx42_slave_get; |
| 1661 | ca91cx42_bridge->slave_set = ca91cx42_slave_set; |
| 1662 | ca91cx42_bridge->master_get = ca91cx42_master_get; |
| 1663 | ca91cx42_bridge->master_set = ca91cx42_master_set; |
| 1664 | ca91cx42_bridge->master_read = ca91cx42_master_read; |
| 1665 | ca91cx42_bridge->master_write = ca91cx42_master_write; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1666 | ca91cx42_bridge->master_rmw = ca91cx42_master_rmw; |
| 1667 | ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add; |
| 1668 | ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec; |
| 1669 | ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty; |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 1670 | ca91cx42_bridge->irq_set = ca91cx42_irq_set; |
| 1671 | ca91cx42_bridge->irq_generate = ca91cx42_irq_generate; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1672 | ca91cx42_bridge->lm_set = ca91cx42_lm_set; |
| 1673 | ca91cx42_bridge->lm_get = ca91cx42_lm_get; |
| 1674 | ca91cx42_bridge->lm_attach = ca91cx42_lm_attach; |
| 1675 | ca91cx42_bridge->lm_detach = ca91cx42_lm_detach; |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1676 | ca91cx42_bridge->slot_get = ca91cx42_slot_get; |
| 1677 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1678 | data = ioread32(ca91cx42_device->base + MISC_CTL); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1679 | dev_info(&pdev->dev, "Board is%s the VME system controller\n", |
| 1680 | (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not"); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1681 | dev_info(&pdev->dev, "Slot ID is %d\n", |
| 1682 | ca91cx42_slot_get(ca91cx42_bridge)); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1683 | |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1684 | if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev)) |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1685 | dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1686 | |
| 1687 | /* Need to save ca91cx42_bridge pointer locally in link list for use in |
| 1688 | * ca91cx42_remove() |
| 1689 | */ |
| 1690 | retval = vme_register_bridge(ca91cx42_bridge); |
| 1691 | if (retval != 0) { |
| 1692 | dev_err(&pdev->dev, "Chip Registration failed.\n"); |
| 1693 | goto err_reg; |
| 1694 | } |
| 1695 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1696 | pci_set_drvdata(pdev, ca91cx42_bridge); |
| 1697 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1698 | return 0; |
| 1699 | |
| 1700 | vme_unregister_bridge(ca91cx42_bridge); |
| 1701 | err_reg: |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1702 | ca91cx42_crcsr_exit(ca91cx42_bridge, pdev); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1703 | err_lm: |
| 1704 | /* resources are stored in link list */ |
| 1705 | list_for_each(pos, &(ca91cx42_bridge->lm_resources)) { |
| 1706 | lm = list_entry(pos, struct vme_lm_resource, list); |
| 1707 | list_del(pos); |
| 1708 | kfree(lm); |
| 1709 | } |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1710 | err_dma: |
| 1711 | /* resources are stored in link list */ |
| 1712 | list_for_each(pos, &(ca91cx42_bridge->dma_resources)) { |
| 1713 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); |
| 1714 | list_del(pos); |
| 1715 | kfree(dma_ctrlr); |
| 1716 | } |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1717 | err_slave: |
| 1718 | /* resources are stored in link list */ |
| 1719 | list_for_each(pos, &(ca91cx42_bridge->slave_resources)) { |
| 1720 | slave_image = list_entry(pos, struct vme_slave_resource, list); |
| 1721 | list_del(pos); |
| 1722 | kfree(slave_image); |
| 1723 | } |
| 1724 | err_master: |
| 1725 | /* resources are stored in link list */ |
| 1726 | list_for_each(pos, &(ca91cx42_bridge->master_resources)) { |
| 1727 | master_image = list_entry(pos, struct vme_master_resource, |
| 1728 | list); |
| 1729 | list_del(pos); |
| 1730 | kfree(master_image); |
| 1731 | } |
| 1732 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1733 | ca91cx42_irq_exit(ca91cx42_device, pdev); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1734 | err_irq: |
| 1735 | err_test: |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1736 | iounmap(ca91cx42_device->base); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1737 | err_remap: |
| 1738 | pci_release_regions(pdev); |
| 1739 | err_resource: |
| 1740 | pci_disable_device(pdev); |
| 1741 | err_enable: |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1742 | kfree(ca91cx42_device); |
| 1743 | err_driver: |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1744 | kfree(ca91cx42_bridge); |
| 1745 | err_struct: |
| 1746 | return retval; |
| 1747 | |
| 1748 | } |
| 1749 | |
| 1750 | void ca91cx42_remove(struct pci_dev *pdev) |
| 1751 | { |
| 1752 | struct list_head *pos = NULL; |
| 1753 | struct vme_master_resource *master_image; |
| 1754 | struct vme_slave_resource *slave_image; |
| 1755 | struct vme_dma_resource *dma_ctrlr; |
| 1756 | struct vme_lm_resource *lm; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1757 | struct ca91cx42_driver *bridge; |
| 1758 | struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev); |
| 1759 | |
| 1760 | bridge = ca91cx42_bridge->driver_priv; |
| 1761 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1762 | |
| 1763 | /* Turn off Ints */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1764 | iowrite32(0, bridge->base + LINT_EN); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1765 | |
| 1766 | /* Turn off the windows */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1767 | iowrite32(0x00800000, bridge->base + LSI0_CTL); |
| 1768 | iowrite32(0x00800000, bridge->base + LSI1_CTL); |
| 1769 | iowrite32(0x00800000, bridge->base + LSI2_CTL); |
| 1770 | iowrite32(0x00800000, bridge->base + LSI3_CTL); |
| 1771 | iowrite32(0x00800000, bridge->base + LSI4_CTL); |
| 1772 | iowrite32(0x00800000, bridge->base + LSI5_CTL); |
| 1773 | iowrite32(0x00800000, bridge->base + LSI6_CTL); |
| 1774 | iowrite32(0x00800000, bridge->base + LSI7_CTL); |
| 1775 | iowrite32(0x00F00000, bridge->base + VSI0_CTL); |
| 1776 | iowrite32(0x00F00000, bridge->base + VSI1_CTL); |
| 1777 | iowrite32(0x00F00000, bridge->base + VSI2_CTL); |
| 1778 | iowrite32(0x00F00000, bridge->base + VSI3_CTL); |
| 1779 | iowrite32(0x00F00000, bridge->base + VSI4_CTL); |
| 1780 | iowrite32(0x00F00000, bridge->base + VSI5_CTL); |
| 1781 | iowrite32(0x00F00000, bridge->base + VSI6_CTL); |
| 1782 | iowrite32(0x00F00000, bridge->base + VSI7_CTL); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1783 | |
| 1784 | vme_unregister_bridge(ca91cx42_bridge); |
Martyn Welch | bb9ea89 | 2010-02-18 16:22:13 +0000 | [diff] [blame] | 1785 | |
| 1786 | ca91cx42_crcsr_exit(ca91cx42_bridge, pdev); |
| 1787 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1788 | /* resources are stored in link list */ |
| 1789 | list_for_each(pos, &(ca91cx42_bridge->lm_resources)) { |
| 1790 | lm = list_entry(pos, struct vme_lm_resource, list); |
| 1791 | list_del(pos); |
| 1792 | kfree(lm); |
| 1793 | } |
| 1794 | |
| 1795 | /* resources are stored in link list */ |
| 1796 | list_for_each(pos, &(ca91cx42_bridge->dma_resources)) { |
| 1797 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); |
| 1798 | list_del(pos); |
| 1799 | kfree(dma_ctrlr); |
| 1800 | } |
| 1801 | |
| 1802 | /* resources are stored in link list */ |
| 1803 | list_for_each(pos, &(ca91cx42_bridge->slave_resources)) { |
| 1804 | slave_image = list_entry(pos, struct vme_slave_resource, list); |
| 1805 | list_del(pos); |
| 1806 | kfree(slave_image); |
| 1807 | } |
| 1808 | |
| 1809 | /* resources are stored in link list */ |
| 1810 | list_for_each(pos, &(ca91cx42_bridge->master_resources)) { |
| 1811 | master_image = list_entry(pos, struct vme_master_resource, |
| 1812 | list); |
| 1813 | list_del(pos); |
| 1814 | kfree(master_image); |
| 1815 | } |
| 1816 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1817 | ca91cx42_irq_exit(bridge, pdev); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1818 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1819 | iounmap(bridge->base); |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1820 | |
| 1821 | pci_release_regions(pdev); |
| 1822 | |
| 1823 | pci_disable_device(pdev); |
| 1824 | |
| 1825 | kfree(ca91cx42_bridge); |
| 1826 | } |
| 1827 | |
| 1828 | static void __exit ca91cx42_exit(void) |
| 1829 | { |
| 1830 | pci_unregister_driver(&ca91cx42_driver); |
| 1831 | } |
| 1832 | |
Martyn Welch | 12b2d5c | 2009-12-15 08:42:56 +0000 | [diff] [blame] | 1833 | MODULE_PARM_DESC(geoid, "Override geographical addressing"); |
| 1834 | module_param(geoid, int, 0); |
| 1835 | |
Martyn Welch | 3d0f8bc | 2009-08-27 17:00:40 +0100 | [diff] [blame] | 1836 | MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge"); |
| 1837 | MODULE_LICENSE("GPL"); |
| 1838 | |
| 1839 | module_init(ca91cx42_init); |
| 1840 | module_exit(ca91cx42_exit); |