Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | * Driver for Solarflare Solarstorm network controllers and boards |
| 3 | * Copyright 2005-2006 Fen Systems Ltd. |
Ben Hutchings | 0a6f40c | 2011-02-25 00:01:34 +0000 | [diff] [blame] | 4 | * Copyright 2006-2010 Solarflare Communications Inc. |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation, incorporated herein by reference. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/bitops.h> |
| 12 | #include <linux/delay.h> |
| 13 | #include <linux/pci.h> |
| 14 | #include <linux/module.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 15 | #include <linux/slab.h> |
Ben Hutchings | d614cfb | 2010-04-28 09:29:02 +0000 | [diff] [blame] | 16 | #include <linux/random.h> |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 17 | #include "net_driver.h" |
| 18 | #include "bitfield.h" |
| 19 | #include "efx.h" |
| 20 | #include "nic.h" |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 21 | #include "spi.h" |
| 22 | #include "regs.h" |
| 23 | #include "io.h" |
| 24 | #include "phy.h" |
| 25 | #include "workarounds.h" |
| 26 | #include "mcdi.h" |
| 27 | #include "mcdi_pcol.h" |
Ben Hutchings | d4f2cec | 2012-07-04 03:58:33 +0100 | [diff] [blame] | 28 | #include "selftest.h" |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 29 | |
| 30 | /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */ |
| 31 | |
| 32 | static void siena_init_wol(struct efx_nic *efx); |
Ben Hutchings | d4f2cec | 2012-07-04 03:58:33 +0100 | [diff] [blame] | 33 | static int siena_reset_hw(struct efx_nic *efx, enum reset_type method); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 34 | |
| 35 | |
| 36 | static void siena_push_irq_moderation(struct efx_channel *channel) |
| 37 | { |
| 38 | efx_dword_t timer_cmd; |
| 39 | |
| 40 | if (channel->irq_moderation) |
| 41 | EFX_POPULATE_DWORD_2(timer_cmd, |
| 42 | FRF_CZ_TC_TIMER_MODE, |
| 43 | FFE_CZ_TIMER_MODE_INT_HLDOFF, |
| 44 | FRF_CZ_TC_TIMER_VAL, |
| 45 | channel->irq_moderation - 1); |
| 46 | else |
| 47 | EFX_POPULATE_DWORD_2(timer_cmd, |
| 48 | FRF_CZ_TC_TIMER_MODE, |
| 49 | FFE_CZ_TIMER_MODE_DIS, |
| 50 | FRF_CZ_TC_TIMER_VAL, 0); |
| 51 | efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, |
| 52 | channel->channel); |
| 53 | } |
| 54 | |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 55 | static int siena_mdio_write(struct net_device *net_dev, |
| 56 | int prtad, int devad, u16 addr, u16 value) |
| 57 | { |
| 58 | struct efx_nic *efx = netdev_priv(net_dev); |
| 59 | uint32_t status; |
| 60 | int rc; |
| 61 | |
| 62 | rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad, |
| 63 | addr, value, &status); |
| 64 | if (rc) |
| 65 | return rc; |
| 66 | if (status != MC_CMD_MDIO_STATUS_GOOD) |
| 67 | return -EIO; |
| 68 | |
| 69 | return 0; |
| 70 | } |
| 71 | |
| 72 | static int siena_mdio_read(struct net_device *net_dev, |
| 73 | int prtad, int devad, u16 addr) |
| 74 | { |
| 75 | struct efx_nic *efx = netdev_priv(net_dev); |
| 76 | uint16_t value; |
| 77 | uint32_t status; |
| 78 | int rc; |
| 79 | |
| 80 | rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad, |
| 81 | addr, &value, &status); |
| 82 | if (rc) |
| 83 | return rc; |
| 84 | if (status != MC_CMD_MDIO_STATUS_GOOD) |
| 85 | return -EIO; |
| 86 | |
| 87 | return (int)value; |
| 88 | } |
| 89 | |
| 90 | /* This call is responsible for hooking in the MAC and PHY operations */ |
| 91 | static int siena_probe_port(struct efx_nic *efx) |
| 92 | { |
| 93 | int rc; |
| 94 | |
| 95 | /* Hook in PHY operations table */ |
| 96 | efx->phy_op = &efx_mcdi_phy_ops; |
| 97 | |
| 98 | /* Set up MDIO structure for PHY */ |
| 99 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; |
| 100 | efx->mdio.mdio_read = siena_mdio_read; |
| 101 | efx->mdio.mdio_write = siena_mdio_write; |
| 102 | |
Steve Hodgson | 7a6b8f6 | 2010-02-03 09:30:38 +0000 | [diff] [blame] | 103 | /* Fill out MDIO structure, loopback modes, and initial link state */ |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 104 | rc = efx->phy_op->probe(efx); |
| 105 | if (rc != 0) |
| 106 | return rc; |
| 107 | |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 108 | /* Allocate buffer for stats */ |
| 109 | rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer, |
| 110 | MC_CMD_MAC_NSTATS * sizeof(u64)); |
| 111 | if (rc) |
| 112 | return rc; |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 113 | netif_dbg(efx, probe, efx->net_dev, |
| 114 | "stats buffer at %llx (virt %p phys %llx)\n", |
| 115 | (u64)efx->stats_buffer.dma_addr, |
| 116 | efx->stats_buffer.addr, |
| 117 | (u64)virt_to_phys(efx->stats_buffer.addr)); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 118 | |
| 119 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1); |
| 120 | |
| 121 | return 0; |
| 122 | } |
| 123 | |
stephen hemminger | d215697 | 2010-10-18 05:27:31 +0000 | [diff] [blame] | 124 | static void siena_remove_port(struct efx_nic *efx) |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 125 | { |
Steve Hodgson | ff3b00a | 2009-12-23 13:46:36 +0000 | [diff] [blame] | 126 | efx->phy_op->remove(efx); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 127 | efx_nic_free_buffer(efx, &efx->stats_buffer); |
| 128 | } |
| 129 | |
| 130 | static const struct efx_nic_register_test siena_register_tests[] = { |
| 131 | { FR_AZ_ADR_REGION, |
Steve Hodgson | 4cddca5 | 2010-02-03 09:31:40 +0000 | [diff] [blame] | 132 | EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) }, |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 133 | { FR_CZ_USR_EV_CFG, |
| 134 | EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) }, |
| 135 | { FR_AZ_RX_CFG, |
| 136 | EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) }, |
| 137 | { FR_AZ_TX_CFG, |
| 138 | EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) }, |
| 139 | { FR_AZ_TX_RESERVED, |
| 140 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, |
| 141 | { FR_AZ_SRM_TX_DC_CFG, |
| 142 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
| 143 | { FR_AZ_RX_DC_CFG, |
| 144 | EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) }, |
| 145 | { FR_AZ_RX_DC_PF_WM, |
| 146 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, |
| 147 | { FR_BZ_DP_CTRL, |
| 148 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, |
| 149 | { FR_BZ_RX_RSS_TKEY, |
| 150 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, |
| 151 | { FR_CZ_RX_RSS_IPV6_REG1, |
| 152 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, |
| 153 | { FR_CZ_RX_RSS_IPV6_REG2, |
| 154 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, |
| 155 | { FR_CZ_RX_RSS_IPV6_REG3, |
| 156 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) }, |
| 157 | }; |
| 158 | |
Ben Hutchings | d4f2cec | 2012-07-04 03:58:33 +0100 | [diff] [blame] | 159 | static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 160 | { |
Ben Hutchings | d4f2cec | 2012-07-04 03:58:33 +0100 | [diff] [blame] | 161 | enum reset_type reset_method = reset_method; |
| 162 | int rc, rc2; |
| 163 | |
| 164 | efx_reset_down(efx, reset_method); |
| 165 | |
| 166 | /* Reset the chip immediately so that it is completely |
| 167 | * quiescent regardless of what any VF driver does. |
| 168 | */ |
| 169 | rc = siena_reset_hw(efx, reset_method); |
| 170 | if (rc) |
| 171 | goto out; |
| 172 | |
| 173 | tests->registers = |
| 174 | efx_nic_test_registers(efx, siena_register_tests, |
| 175 | ARRAY_SIZE(siena_register_tests)) |
| 176 | ? -1 : 1; |
| 177 | |
| 178 | rc = siena_reset_hw(efx, reset_method); |
| 179 | out: |
| 180 | rc2 = efx_reset_up(efx, reset_method, rc == 0); |
| 181 | return rc ? rc : rc2; |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 182 | } |
| 183 | |
| 184 | /************************************************************************** |
| 185 | * |
| 186 | * Device reset |
| 187 | * |
| 188 | ************************************************************************** |
| 189 | */ |
| 190 | |
Ben Hutchings | 0e2a9c7 | 2011-06-24 20:50:07 +0100 | [diff] [blame] | 191 | static enum reset_type siena_map_reset_reason(enum reset_type reason) |
| 192 | { |
| 193 | return RESET_TYPE_ALL; |
| 194 | } |
| 195 | |
| 196 | static int siena_map_reset_flags(u32 *flags) |
| 197 | { |
| 198 | enum { |
| 199 | SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER | |
| 200 | ETH_RESET_OFFLOAD | ETH_RESET_MAC | |
| 201 | ETH_RESET_PHY), |
| 202 | SIENA_RESET_MC = (SIENA_RESET_PORT | |
| 203 | ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT), |
| 204 | }; |
| 205 | |
| 206 | if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) { |
| 207 | *flags &= ~SIENA_RESET_MC; |
| 208 | return RESET_TYPE_WORLD; |
| 209 | } |
| 210 | |
| 211 | if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) { |
| 212 | *flags &= ~SIENA_RESET_PORT; |
| 213 | return RESET_TYPE_ALL; |
| 214 | } |
| 215 | |
| 216 | /* no invisible reset implemented */ |
| 217 | |
| 218 | return -EINVAL; |
| 219 | } |
| 220 | |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 221 | static int siena_reset_hw(struct efx_nic *efx, enum reset_type method) |
| 222 | { |
Steve Hodgson | 8b2103a | 2010-02-03 09:30:17 +0000 | [diff] [blame] | 223 | int rc; |
| 224 | |
| 225 | /* Recover from a failed assertion pre-reset */ |
| 226 | rc = efx_mcdi_handle_assertion(efx); |
| 227 | if (rc) |
| 228 | return rc; |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 229 | |
| 230 | if (method == RESET_TYPE_WORLD) |
| 231 | return efx_mcdi_reset_mc(efx); |
| 232 | else |
| 233 | return efx_mcdi_reset_port(efx); |
| 234 | } |
| 235 | |
| 236 | static int siena_probe_nvconfig(struct efx_nic *efx) |
| 237 | { |
Ben Hutchings | cc180b6 | 2011-12-08 19:51:47 +0000 | [diff] [blame] | 238 | u32 caps = 0; |
| 239 | int rc; |
| 240 | |
| 241 | rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps); |
| 242 | |
| 243 | efx->timer_quantum_ns = |
| 244 | (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ? |
| 245 | 3072 : 6144; /* 768 cycles */ |
| 246 | return rc; |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 247 | } |
| 248 | |
Ben Hutchings | 28e47c4 | 2012-02-15 01:58:49 +0000 | [diff] [blame] | 249 | static void siena_dimension_resources(struct efx_nic *efx) |
| 250 | { |
| 251 | /* Each port has a small block of internal SRAM dedicated to |
| 252 | * the buffer table and descriptor caches. In theory we can |
| 253 | * map both blocks to one port, but we don't. |
| 254 | */ |
| 255 | efx_nic_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2); |
| 256 | } |
| 257 | |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 258 | static int siena_probe_nic(struct efx_nic *efx) |
| 259 | { |
| 260 | struct siena_nic_data *nic_data; |
Rusty Russell | 3db1cd5 | 2011-12-19 13:56:45 +0000 | [diff] [blame] | 261 | bool already_attached = false; |
Ben Hutchings | d42a8f4 | 2010-06-01 11:32:43 +0000 | [diff] [blame] | 262 | efx_oword_t reg; |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 263 | int rc; |
| 264 | |
| 265 | /* Allocate storage for hardware specific data */ |
| 266 | nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL); |
| 267 | if (!nic_data) |
| 268 | return -ENOMEM; |
| 269 | efx->nic_data = nic_data; |
| 270 | |
| 271 | if (efx_nic_fpga_ver(efx) != 0) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 272 | netif_err(efx, probe, efx->net_dev, |
| 273 | "Siena FPGA not supported\n"); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 274 | rc = -ENODEV; |
| 275 | goto fail1; |
| 276 | } |
| 277 | |
Ben Hutchings | d42a8f4 | 2010-06-01 11:32:43 +0000 | [diff] [blame] | 278 | efx_reado(efx, ®, FR_AZ_CS_DEBUG); |
Ben Hutchings | 3df95ce | 2010-06-02 10:39:56 +0000 | [diff] [blame] | 279 | efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1; |
Ben Hutchings | d42a8f4 | 2010-06-01 11:32:43 +0000 | [diff] [blame] | 280 | |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 281 | efx_mcdi_init(efx); |
| 282 | |
| 283 | /* Recover from a failed assertion before probing */ |
| 284 | rc = efx_mcdi_handle_assertion(efx); |
| 285 | if (rc) |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 286 | goto fail1; |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 287 | |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 288 | /* Let the BMC know that the driver is now in charge of link and |
| 289 | * filter settings. We must do this before we reset the NIC */ |
| 290 | rc = efx_mcdi_drv_attach(efx, true, &already_attached); |
| 291 | if (rc) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 292 | netif_err(efx, probe, efx->net_dev, |
| 293 | "Unable to register driver with MCPU\n"); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 294 | goto fail2; |
| 295 | } |
| 296 | if (already_attached) |
| 297 | /* Not a fatal error */ |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 298 | netif_err(efx, probe, efx->net_dev, |
| 299 | "Host already registered with MCPU\n"); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 300 | |
| 301 | /* Now we can reset the NIC */ |
| 302 | rc = siena_reset_hw(efx, RESET_TYPE_ALL); |
| 303 | if (rc) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 304 | netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n"); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 305 | goto fail3; |
| 306 | } |
| 307 | |
| 308 | siena_init_wol(efx); |
| 309 | |
| 310 | /* Allocate memory for INT_KER */ |
| 311 | rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); |
| 312 | if (rc) |
| 313 | goto fail4; |
| 314 | BUG_ON(efx->irq_status.dma_addr & 0x0f); |
| 315 | |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 316 | netif_dbg(efx, probe, efx->net_dev, |
| 317 | "INT_KER at %llx (virt %p phys %llx)\n", |
| 318 | (unsigned long long)efx->irq_status.dma_addr, |
| 319 | efx->irq_status.addr, |
| 320 | (unsigned long long)virt_to_phys(efx->irq_status.addr)); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 321 | |
| 322 | /* Read in the non-volatile configuration */ |
| 323 | rc = siena_probe_nvconfig(efx); |
| 324 | if (rc == -EINVAL) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 325 | netif_err(efx, probe, efx->net_dev, |
| 326 | "NVRAM is invalid therefore using defaults\n"); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 327 | efx->phy_type = PHY_TYPE_NONE; |
| 328 | efx->mdio.prtad = MDIO_PRTAD_NONE; |
| 329 | } else if (rc) { |
| 330 | goto fail5; |
| 331 | } |
| 332 | |
Ben Hutchings | 55c5e0f | 2012-01-06 20:25:39 +0000 | [diff] [blame] | 333 | rc = efx_mcdi_mon_probe(efx); |
| 334 | if (rc) |
| 335 | goto fail5; |
| 336 | |
Ben Hutchings | cd2d5b5 | 2012-02-14 00:48:07 +0000 | [diff] [blame] | 337 | efx_sriov_probe(efx); |
Stuart Hodgson | 7c236c4 | 2012-09-03 11:09:36 +0100 | [diff] [blame^] | 338 | efx_ptp_probe(efx); |
Ben Hutchings | cd2d5b5 | 2012-02-14 00:48:07 +0000 | [diff] [blame] | 339 | |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 340 | return 0; |
| 341 | |
| 342 | fail5: |
| 343 | efx_nic_free_buffer(efx, &efx->irq_status); |
| 344 | fail4: |
| 345 | fail3: |
| 346 | efx_mcdi_drv_attach(efx, false, NULL); |
| 347 | fail2: |
| 348 | fail1: |
| 349 | kfree(efx->nic_data); |
| 350 | return rc; |
| 351 | } |
| 352 | |
| 353 | /* This call performs hardware-specific global initialisation, such as |
| 354 | * defining the descriptor cache sizes and number of RSS channels. |
| 355 | * It does not set up any buffers, descriptor rings or event queues. |
| 356 | */ |
| 357 | static int siena_init_nic(struct efx_nic *efx) |
| 358 | { |
| 359 | efx_oword_t temp; |
| 360 | int rc; |
| 361 | |
| 362 | /* Recover from a failed assertion post-reset */ |
| 363 | rc = efx_mcdi_handle_assertion(efx); |
| 364 | if (rc) |
| 365 | return rc; |
| 366 | |
| 367 | /* Squash TX of packets of 16 bytes or less */ |
| 368 | efx_reado(efx, &temp, FR_AZ_TX_RESERVED); |
| 369 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); |
| 370 | efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); |
| 371 | |
| 372 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 |
| 373 | * descriptors (which is bad). |
| 374 | */ |
| 375 | efx_reado(efx, &temp, FR_AZ_TX_CFG); |
| 376 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); |
| 377 | EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1); |
| 378 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); |
| 379 | |
| 380 | efx_reado(efx, &temp, FR_AZ_RX_CFG); |
| 381 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0); |
| 382 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1); |
Ben Hutchings | 477e54e | 2010-06-25 07:05:56 +0000 | [diff] [blame] | 383 | /* Enable hash insertion. This is broken for the 'Falcon' hash |
| 384 | * if IPv6 hashing is also enabled, so also select Toeplitz |
| 385 | * TCP/IPv4 and IPv4 hashes. */ |
| 386 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1); |
| 387 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1); |
| 388 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 389 | efx_writeo(efx, &temp, FR_AZ_RX_CFG); |
| 390 | |
Ben Hutchings | 477e54e | 2010-06-25 07:05:56 +0000 | [diff] [blame] | 391 | /* Set hash key for IPv4 */ |
| 392 | memcpy(&temp, efx->rx_hash_key, sizeof(temp)); |
| 393 | efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY); |
| 394 | |
Ben Hutchings | d614cfb | 2010-04-28 09:29:02 +0000 | [diff] [blame] | 395 | /* Enable IPv6 RSS */ |
Ben Hutchings | 5d3a6fc | 2010-06-25 07:05:43 +0000 | [diff] [blame] | 396 | BUILD_BUG_ON(sizeof(efx->rx_hash_key) < |
Ben Hutchings | d614cfb | 2010-04-28 09:29:02 +0000 | [diff] [blame] | 397 | 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 || |
| 398 | FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0); |
Ben Hutchings | 5d3a6fc | 2010-06-25 07:05:43 +0000 | [diff] [blame] | 399 | memcpy(&temp, efx->rx_hash_key, sizeof(temp)); |
Ben Hutchings | d614cfb | 2010-04-28 09:29:02 +0000 | [diff] [blame] | 400 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1); |
Ben Hutchings | 5d3a6fc | 2010-06-25 07:05:43 +0000 | [diff] [blame] | 401 | memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp)); |
Ben Hutchings | d614cfb | 2010-04-28 09:29:02 +0000 | [diff] [blame] | 402 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2); |
| 403 | EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1, |
| 404 | FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1); |
Ben Hutchings | 5d3a6fc | 2010-06-25 07:05:43 +0000 | [diff] [blame] | 405 | memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp), |
Ben Hutchings | d614cfb | 2010-04-28 09:29:02 +0000 | [diff] [blame] | 406 | FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8); |
| 407 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3); |
| 408 | |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 409 | /* Enable event logging */ |
| 410 | rc = efx_mcdi_log_ctrl(efx, true, false, 0); |
| 411 | if (rc) |
| 412 | return rc; |
| 413 | |
| 414 | /* Set destination of both TX and RX Flush events */ |
| 415 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); |
| 416 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); |
| 417 | |
| 418 | EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1); |
| 419 | efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG); |
| 420 | |
| 421 | efx_nic_init_common(efx); |
| 422 | return 0; |
| 423 | } |
| 424 | |
| 425 | static void siena_remove_nic(struct efx_nic *efx) |
| 426 | { |
Ben Hutchings | 55c5e0f | 2012-01-06 20:25:39 +0000 | [diff] [blame] | 427 | efx_mcdi_mon_remove(efx); |
| 428 | |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 429 | efx_nic_free_buffer(efx, &efx->irq_status); |
| 430 | |
| 431 | siena_reset_hw(efx, RESET_TYPE_ALL); |
| 432 | |
| 433 | /* Relinquish the device back to the BMC */ |
Ben Hutchings | bdca71e | 2012-02-24 21:29:40 +0000 | [diff] [blame] | 434 | efx_mcdi_drv_attach(efx, false, NULL); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 435 | |
| 436 | /* Tear down the private nic state */ |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 437 | kfree(efx->nic_data); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 438 | efx->nic_data = NULL; |
| 439 | } |
| 440 | |
Steve Hodgson | a659b2a | 2011-06-22 12:11:33 +0100 | [diff] [blame] | 441 | #define STATS_GENERATION_INVALID ((__force __le64)(-1)) |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 442 | |
| 443 | static int siena_try_update_nic_stats(struct efx_nic *efx) |
| 444 | { |
Steve Hodgson | a659b2a | 2011-06-22 12:11:33 +0100 | [diff] [blame] | 445 | __le64 *dma_stats; |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 446 | struct efx_mac_stats *mac_stats; |
Steve Hodgson | a659b2a | 2011-06-22 12:11:33 +0100 | [diff] [blame] | 447 | __le64 generation_start, generation_end; |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 448 | |
| 449 | mac_stats = &efx->mac_stats; |
Joe Perches | 43d620c | 2011-06-16 19:08:06 +0000 | [diff] [blame] | 450 | dma_stats = efx->stats_buffer.addr; |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 451 | |
| 452 | generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; |
| 453 | if (generation_end == STATS_GENERATION_INVALID) |
| 454 | return 0; |
| 455 | rmb(); |
| 456 | |
| 457 | #define MAC_STAT(M, D) \ |
Steve Hodgson | a659b2a | 2011-06-22 12:11:33 +0100 | [diff] [blame] | 458 | mac_stats->M = le64_to_cpu(dma_stats[MC_CMD_MAC_ ## D]) |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 459 | |
| 460 | MAC_STAT(tx_bytes, TX_BYTES); |
| 461 | MAC_STAT(tx_bad_bytes, TX_BAD_BYTES); |
Ben Hutchings | b7f514a | 2012-07-04 22:25:07 +0100 | [diff] [blame] | 462 | efx_update_diff_stat(&mac_stats->tx_good_bytes, |
| 463 | mac_stats->tx_bytes - mac_stats->tx_bad_bytes); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 464 | MAC_STAT(tx_packets, TX_PKTS); |
| 465 | MAC_STAT(tx_bad, TX_BAD_FCS_PKTS); |
| 466 | MAC_STAT(tx_pause, TX_PAUSE_PKTS); |
| 467 | MAC_STAT(tx_control, TX_CONTROL_PKTS); |
| 468 | MAC_STAT(tx_unicast, TX_UNICAST_PKTS); |
| 469 | MAC_STAT(tx_multicast, TX_MULTICAST_PKTS); |
| 470 | MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS); |
| 471 | MAC_STAT(tx_lt64, TX_LT64_PKTS); |
| 472 | MAC_STAT(tx_64, TX_64_PKTS); |
| 473 | MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS); |
| 474 | MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS); |
| 475 | MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS); |
| 476 | MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS); |
| 477 | MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS); |
| 478 | MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS); |
| 479 | MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS); |
| 480 | mac_stats->tx_collision = 0; |
| 481 | MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS); |
| 482 | MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS); |
| 483 | MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS); |
| 484 | MAC_STAT(tx_deferred, TX_DEFERRED_PKTS); |
| 485 | MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS); |
| 486 | mac_stats->tx_collision = (mac_stats->tx_single_collision + |
| 487 | mac_stats->tx_multiple_collision + |
| 488 | mac_stats->tx_excessive_collision + |
| 489 | mac_stats->tx_late_collision); |
| 490 | MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS); |
| 491 | MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS); |
| 492 | MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS); |
| 493 | MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS); |
| 494 | MAC_STAT(rx_bytes, RX_BYTES); |
| 495 | MAC_STAT(rx_bad_bytes, RX_BAD_BYTES); |
Ben Hutchings | b7f514a | 2012-07-04 22:25:07 +0100 | [diff] [blame] | 496 | efx_update_diff_stat(&mac_stats->rx_good_bytes, |
| 497 | mac_stats->rx_bytes - mac_stats->rx_bad_bytes); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 498 | MAC_STAT(rx_packets, RX_PKTS); |
| 499 | MAC_STAT(rx_good, RX_GOOD_PKTS); |
Ben Hutchings | 1cdc2cf | 2010-09-10 06:41:00 +0000 | [diff] [blame] | 500 | MAC_STAT(rx_bad, RX_BAD_FCS_PKTS); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 501 | MAC_STAT(rx_pause, RX_PAUSE_PKTS); |
| 502 | MAC_STAT(rx_control, RX_CONTROL_PKTS); |
| 503 | MAC_STAT(rx_unicast, RX_UNICAST_PKTS); |
| 504 | MAC_STAT(rx_multicast, RX_MULTICAST_PKTS); |
| 505 | MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS); |
| 506 | MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS); |
| 507 | MAC_STAT(rx_64, RX_64_PKTS); |
| 508 | MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS); |
| 509 | MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS); |
| 510 | MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS); |
| 511 | MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS); |
| 512 | MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS); |
| 513 | MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS); |
| 514 | MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS); |
| 515 | mac_stats->rx_bad_lt64 = 0; |
| 516 | mac_stats->rx_bad_64_to_15xx = 0; |
| 517 | mac_stats->rx_bad_15xx_to_jumbo = 0; |
| 518 | MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS); |
| 519 | MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS); |
| 520 | mac_stats->rx_missed = 0; |
| 521 | MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS); |
| 522 | MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS); |
| 523 | MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS); |
| 524 | MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS); |
| 525 | MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS); |
| 526 | mac_stats->rx_good_lt64 = 0; |
| 527 | |
Steve Hodgson | a659b2a | 2011-06-22 12:11:33 +0100 | [diff] [blame] | 528 | efx->n_rx_nodesc_drop_cnt = |
| 529 | le64_to_cpu(dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 530 | |
| 531 | #undef MAC_STAT |
| 532 | |
| 533 | rmb(); |
| 534 | generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; |
| 535 | if (generation_end != generation_start) |
| 536 | return -EAGAIN; |
| 537 | |
| 538 | return 0; |
| 539 | } |
| 540 | |
| 541 | static void siena_update_nic_stats(struct efx_nic *efx) |
| 542 | { |
Ben Hutchings | aabc564 | 2010-04-28 09:00:35 +0000 | [diff] [blame] | 543 | int retry; |
| 544 | |
| 545 | /* If we're unlucky enough to read statistics wduring the DMA, wait |
| 546 | * up to 10ms for it to finish (typically takes <500us) */ |
| 547 | for (retry = 0; retry < 100; ++retry) { |
| 548 | if (siena_try_update_nic_stats(efx) == 0) |
| 549 | return; |
| 550 | udelay(100); |
| 551 | } |
| 552 | |
| 553 | /* Use the old values instead */ |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 554 | } |
| 555 | |
| 556 | static void siena_start_nic_stats(struct efx_nic *efx) |
| 557 | { |
Steve Hodgson | a659b2a | 2011-06-22 12:11:33 +0100 | [diff] [blame] | 558 | __le64 *dma_stats = efx->stats_buffer.addr; |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 559 | |
| 560 | dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID; |
| 561 | |
| 562 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, |
| 563 | MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0); |
| 564 | } |
| 565 | |
| 566 | static void siena_stop_nic_stats(struct efx_nic *efx) |
| 567 | { |
| 568 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0); |
| 569 | } |
| 570 | |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 571 | /************************************************************************** |
| 572 | * |
| 573 | * Wake on LAN |
| 574 | * |
| 575 | ************************************************************************** |
| 576 | */ |
| 577 | |
| 578 | static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) |
| 579 | { |
| 580 | struct siena_nic_data *nic_data = efx->nic_data; |
| 581 | |
| 582 | wol->supported = WAKE_MAGIC; |
| 583 | if (nic_data->wol_filter_id != -1) |
| 584 | wol->wolopts = WAKE_MAGIC; |
| 585 | else |
| 586 | wol->wolopts = 0; |
| 587 | memset(&wol->sopass, 0, sizeof(wol->sopass)); |
| 588 | } |
| 589 | |
| 590 | |
| 591 | static int siena_set_wol(struct efx_nic *efx, u32 type) |
| 592 | { |
| 593 | struct siena_nic_data *nic_data = efx->nic_data; |
| 594 | int rc; |
| 595 | |
| 596 | if (type & ~WAKE_MAGIC) |
| 597 | return -EINVAL; |
| 598 | |
| 599 | if (type & WAKE_MAGIC) { |
| 600 | if (nic_data->wol_filter_id != -1) |
| 601 | efx_mcdi_wol_filter_remove(efx, |
| 602 | nic_data->wol_filter_id); |
Ben Hutchings | 02ebc26 | 2010-12-02 13:48:20 +0000 | [diff] [blame] | 603 | rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr, |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 604 | &nic_data->wol_filter_id); |
| 605 | if (rc) |
| 606 | goto fail; |
| 607 | |
| 608 | pci_wake_from_d3(efx->pci_dev, true); |
| 609 | } else { |
| 610 | rc = efx_mcdi_wol_filter_reset(efx); |
| 611 | nic_data->wol_filter_id = -1; |
| 612 | pci_wake_from_d3(efx->pci_dev, false); |
| 613 | if (rc) |
| 614 | goto fail; |
| 615 | } |
| 616 | |
| 617 | return 0; |
| 618 | fail: |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 619 | netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n", |
| 620 | __func__, type, rc); |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 621 | return rc; |
| 622 | } |
| 623 | |
| 624 | |
| 625 | static void siena_init_wol(struct efx_nic *efx) |
| 626 | { |
| 627 | struct siena_nic_data *nic_data = efx->nic_data; |
| 628 | int rc; |
| 629 | |
| 630 | rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id); |
| 631 | |
| 632 | if (rc != 0) { |
| 633 | /* If it failed, attempt to get into a synchronised |
| 634 | * state with MC by resetting any set WoL filters */ |
| 635 | efx_mcdi_wol_filter_reset(efx); |
| 636 | nic_data->wol_filter_id = -1; |
| 637 | } else if (nic_data->wol_filter_id != -1) { |
| 638 | pci_wake_from_d3(efx->pci_dev, true); |
| 639 | } |
| 640 | } |
| 641 | |
| 642 | |
| 643 | /************************************************************************** |
| 644 | * |
| 645 | * Revision-dependent attributes used by efx.c and nic.c |
| 646 | * |
| 647 | ************************************************************************** |
| 648 | */ |
| 649 | |
stephen hemminger | 6c8c251 | 2011-04-14 05:50:12 +0000 | [diff] [blame] | 650 | const struct efx_nic_type siena_a0_nic_type = { |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 651 | .probe = siena_probe_nic, |
| 652 | .remove = siena_remove_nic, |
| 653 | .init = siena_init_nic, |
Ben Hutchings | 28e47c4 | 2012-02-15 01:58:49 +0000 | [diff] [blame] | 654 | .dimension_resources = siena_dimension_resources, |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 655 | .fini = efx_port_dummy_op_void, |
| 656 | .monitor = NULL, |
Ben Hutchings | 0e2a9c7 | 2011-06-24 20:50:07 +0100 | [diff] [blame] | 657 | .map_reset_reason = siena_map_reset_reason, |
| 658 | .map_reset_flags = siena_map_reset_flags, |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 659 | .reset = siena_reset_hw, |
| 660 | .probe_port = siena_probe_port, |
| 661 | .remove_port = siena_remove_port, |
| 662 | .prepare_flush = efx_port_dummy_op_void, |
| 663 | .update_stats = siena_update_nic_stats, |
| 664 | .start_stats = siena_start_nic_stats, |
| 665 | .stop_stats = siena_stop_nic_stats, |
| 666 | .set_id_led = efx_mcdi_set_id_led, |
| 667 | .push_irq_moderation = siena_push_irq_moderation, |
Ben Hutchings | 710b208 | 2011-09-03 00:15:00 +0100 | [diff] [blame] | 668 | .reconfigure_mac = efx_mcdi_mac_reconfigure, |
| 669 | .check_mac_fault = efx_mcdi_mac_check_fault, |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 670 | .reconfigure_port = efx_mcdi_phy_reconfigure, |
| 671 | .get_wol = siena_get_wol, |
| 672 | .set_wol = siena_set_wol, |
| 673 | .resume_wol = siena_init_wol, |
Ben Hutchings | d4f2cec | 2012-07-04 03:58:33 +0100 | [diff] [blame] | 674 | .test_chip = siena_test_chip, |
Ben Hutchings | 2e80340 | 2010-02-03 09:31:01 +0000 | [diff] [blame] | 675 | .test_nvram = efx_mcdi_nvram_test_all, |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 676 | |
| 677 | .revision = EFX_REV_SIENA_A0, |
David S. Miller | 8decf86 | 2011-09-22 03:23:13 -0400 | [diff] [blame] | 678 | .mem_map_size = (FR_CZ_MC_TREG_SMEM + |
| 679 | FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS), |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 680 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, |
| 681 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, |
| 682 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, |
| 683 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, |
| 684 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, |
| 685 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
Ben Hutchings | 39c9cf0 | 2010-06-23 11:31:28 +0000 | [diff] [blame] | 686 | .rx_buffer_hash_size = 0x10, |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 687 | .rx_buffer_padding = 0, |
| 688 | .max_interrupt_mode = EFX_INT_MODE_MSIX, |
| 689 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy |
| 690 | * interrupt handler only supports 32 |
| 691 | * channels */ |
Ben Hutchings | cc180b6 | 2011-12-08 19:51:47 +0000 | [diff] [blame] | 692 | .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH, |
Ben Hutchings | 39c9cf0 | 2010-06-23 11:31:28 +0000 | [diff] [blame] | 693 | .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
Ben Hutchings | b4187e4 | 2010-09-20 08:43:42 +0000 | [diff] [blame] | 694 | NETIF_F_RXHASH | NETIF_F_NTUPLE), |
Ben Hutchings | afd4aea | 2009-11-29 15:15:25 +0000 | [diff] [blame] | 695 | }; |