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Mark Brownc9fbf7e2010-03-26 16:49:15 +00001/*
2 * wm8994-irq.c -- Interrupt controller support for Wolfson WM8994
3 *
4 * Copyright 2010 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/i2c.h>
18#include <linux/irq.h>
19#include <linux/mfd/core.h>
20#include <linux/interrupt.h>
Mark Brown8ab30692011-10-25 10:19:04 +020021#include <linux/regmap.h>
Mark Brownc9fbf7e2010-03-26 16:49:15 +000022
23#include <linux/mfd/wm8994/core.h>
Mark Brownb0ab9072012-06-01 16:33:19 +010024#include <linux/mfd/wm8994/pdata.h>
Mark Brownc9fbf7e2010-03-26 16:49:15 +000025#include <linux/mfd/wm8994/registers.h>
26
27#include <linux/delay.h>
28
Mark Brown8ab30692011-10-25 10:19:04 +020029static struct regmap_irq wm8994_irqs[] = {
Mark Brownc9fbf7e2010-03-26 16:49:15 +000030 [WM8994_IRQ_TEMP_SHUT] = {
Mark Brown8ab30692011-10-25 10:19:04 +020031 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000032 .mask = WM8994_TEMP_SHUT_EINT,
33 },
34 [WM8994_IRQ_MIC1_DET] = {
Mark Brown8ab30692011-10-25 10:19:04 +020035 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000036 .mask = WM8994_MIC1_DET_EINT,
37 },
38 [WM8994_IRQ_MIC1_SHRT] = {
Mark Brown8ab30692011-10-25 10:19:04 +020039 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000040 .mask = WM8994_MIC1_SHRT_EINT,
41 },
42 [WM8994_IRQ_MIC2_DET] = {
Mark Brown8ab30692011-10-25 10:19:04 +020043 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000044 .mask = WM8994_MIC2_DET_EINT,
45 },
46 [WM8994_IRQ_MIC2_SHRT] = {
Mark Brown8ab30692011-10-25 10:19:04 +020047 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000048 .mask = WM8994_MIC2_SHRT_EINT,
49 },
50 [WM8994_IRQ_FLL1_LOCK] = {
Mark Brown8ab30692011-10-25 10:19:04 +020051 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000052 .mask = WM8994_FLL1_LOCK_EINT,
53 },
54 [WM8994_IRQ_FLL2_LOCK] = {
Mark Brown8ab30692011-10-25 10:19:04 +020055 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000056 .mask = WM8994_FLL2_LOCK_EINT,
57 },
58 [WM8994_IRQ_SRC1_LOCK] = {
Mark Brown8ab30692011-10-25 10:19:04 +020059 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000060 .mask = WM8994_SRC1_LOCK_EINT,
61 },
62 [WM8994_IRQ_SRC2_LOCK] = {
Mark Brown8ab30692011-10-25 10:19:04 +020063 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000064 .mask = WM8994_SRC2_LOCK_EINT,
65 },
66 [WM8994_IRQ_AIF1DRC1_SIG_DET] = {
Mark Brown8ab30692011-10-25 10:19:04 +020067 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000068 .mask = WM8994_AIF1DRC1_SIG_DET,
69 },
70 [WM8994_IRQ_AIF1DRC2_SIG_DET] = {
Mark Brown8ab30692011-10-25 10:19:04 +020071 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000072 .mask = WM8994_AIF1DRC2_SIG_DET_EINT,
73 },
74 [WM8994_IRQ_AIF2DRC_SIG_DET] = {
Mark Brown8ab30692011-10-25 10:19:04 +020075 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000076 .mask = WM8994_AIF2DRC_SIG_DET_EINT,
77 },
78 [WM8994_IRQ_FIFOS_ERR] = {
Mark Brown8ab30692011-10-25 10:19:04 +020079 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000080 .mask = WM8994_FIFOS_ERR_EINT,
81 },
82 [WM8994_IRQ_WSEQ_DONE] = {
Mark Brown8ab30692011-10-25 10:19:04 +020083 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000084 .mask = WM8994_WSEQ_DONE_EINT,
85 },
86 [WM8994_IRQ_DCS_DONE] = {
Mark Brown8ab30692011-10-25 10:19:04 +020087 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000088 .mask = WM8994_DCS_DONE_EINT,
89 },
90 [WM8994_IRQ_TEMP_WARN] = {
Mark Brown8ab30692011-10-25 10:19:04 +020091 .reg_offset = 1,
Mark Brownc9fbf7e2010-03-26 16:49:15 +000092 .mask = WM8994_TEMP_WARN_EINT,
93 },
94 [WM8994_IRQ_GPIO(1)] = {
Mark Brownc9fbf7e2010-03-26 16:49:15 +000095 .mask = WM8994_GP1_EINT,
96 },
97 [WM8994_IRQ_GPIO(2)] = {
Mark Brownc9fbf7e2010-03-26 16:49:15 +000098 .mask = WM8994_GP2_EINT,
99 },
100 [WM8994_IRQ_GPIO(3)] = {
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000101 .mask = WM8994_GP3_EINT,
102 },
103 [WM8994_IRQ_GPIO(4)] = {
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000104 .mask = WM8994_GP4_EINT,
105 },
106 [WM8994_IRQ_GPIO(5)] = {
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000107 .mask = WM8994_GP5_EINT,
108 },
109 [WM8994_IRQ_GPIO(6)] = {
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000110 .mask = WM8994_GP6_EINT,
111 },
112 [WM8994_IRQ_GPIO(7)] = {
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000113 .mask = WM8994_GP7_EINT,
114 },
115 [WM8994_IRQ_GPIO(8)] = {
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000116 .mask = WM8994_GP8_EINT,
117 },
118 [WM8994_IRQ_GPIO(9)] = {
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000119 .mask = WM8994_GP8_EINT,
120 },
121 [WM8994_IRQ_GPIO(10)] = {
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000122 .mask = WM8994_GP10_EINT,
123 },
124 [WM8994_IRQ_GPIO(11)] = {
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000125 .mask = WM8994_GP11_EINT,
126 },
127};
128
Mark Brown8ab30692011-10-25 10:19:04 +0200129static struct regmap_irq_chip wm8994_irq_chip = {
130 .name = "wm8994",
131 .irqs = wm8994_irqs,
132 .num_irqs = ARRAY_SIZE(wm8994_irqs),
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000133
Mark Brown8ab30692011-10-25 10:19:04 +0200134 .num_regs = 2,
135 .status_base = WM8994_INTERRUPT_STATUS_1,
136 .mask_base = WM8994_INTERRUPT_STATUS_1_MASK,
137 .ack_base = WM8994_INTERRUPT_STATUS_1,
Mark Brown7a976372012-07-24 15:41:53 +0100138 .runtime_pm = true,
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000139};
140
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000141int wm8994_irq_init(struct wm8994 *wm8994)
142{
Mark Brown8ab30692011-10-25 10:19:04 +0200143 int ret;
Mark Brownb0ab9072012-06-01 16:33:19 +0100144 unsigned long irqflags;
145 struct wm8994_pdata *pdata = wm8994->dev->platform_data;
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000146
147 if (!wm8994->irq) {
148 dev_warn(wm8994->dev,
149 "No interrupt specified, no interrupts\n");
150 wm8994->irq_base = 0;
151 return 0;
152 }
153
Mark Brownb0ab9072012-06-01 16:33:19 +0100154 /* select user or default irq flags */
155 irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT;
156 if (pdata->irq_flags)
157 irqflags = pdata->irq_flags;
158
Mark Brown8ab30692011-10-25 10:19:04 +0200159 ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq,
Mark Brownb0ab9072012-06-01 16:33:19 +0100160 irqflags,
Mark Brown8ab30692011-10-25 10:19:04 +0200161 wm8994->irq_base, &wm8994_irq_chip,
162 &wm8994->irq_data);
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000163 if (ret != 0) {
Mark Brown8ab30692011-10-25 10:19:04 +0200164 dev_err(wm8994->dev, "Failed to register IRQ chip: %d\n", ret);
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000165 return ret;
166 }
167
168 /* Enable top level interrupt if it was masked */
169 wm8994_reg_write(wm8994, WM8994_INTERRUPT_CONTROL, 0);
170
171 return 0;
172}
173
174void wm8994_irq_exit(struct wm8994 *wm8994)
175{
Mark Brown8ab30692011-10-25 10:19:04 +0200176 regmap_del_irq_chip(wm8994->irq, wm8994->irq_data);
Mark Brownc9fbf7e2010-03-26 16:49:15 +0000177}