Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 1 | /* |
| 2 | * wm8994-irq.c -- Interrupt controller support for Wolfson WM8994 |
| 3 | * |
| 4 | * Copyright 2010 Wolfson Microelectronics PLC. |
| 5 | * |
| 6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | * option) any later version. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/i2c.h> |
| 18 | #include <linux/irq.h> |
| 19 | #include <linux/mfd/core.h> |
| 20 | #include <linux/interrupt.h> |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 21 | #include <linux/regmap.h> |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 22 | |
| 23 | #include <linux/mfd/wm8994/core.h> |
Mark Brown | b0ab907 | 2012-06-01 16:33:19 +0100 | [diff] [blame] | 24 | #include <linux/mfd/wm8994/pdata.h> |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 25 | #include <linux/mfd/wm8994/registers.h> |
| 26 | |
| 27 | #include <linux/delay.h> |
| 28 | |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 29 | static struct regmap_irq wm8994_irqs[] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 30 | [WM8994_IRQ_TEMP_SHUT] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 31 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 32 | .mask = WM8994_TEMP_SHUT_EINT, |
| 33 | }, |
| 34 | [WM8994_IRQ_MIC1_DET] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 35 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 36 | .mask = WM8994_MIC1_DET_EINT, |
| 37 | }, |
| 38 | [WM8994_IRQ_MIC1_SHRT] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 39 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 40 | .mask = WM8994_MIC1_SHRT_EINT, |
| 41 | }, |
| 42 | [WM8994_IRQ_MIC2_DET] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 43 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 44 | .mask = WM8994_MIC2_DET_EINT, |
| 45 | }, |
| 46 | [WM8994_IRQ_MIC2_SHRT] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 47 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 48 | .mask = WM8994_MIC2_SHRT_EINT, |
| 49 | }, |
| 50 | [WM8994_IRQ_FLL1_LOCK] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 51 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 52 | .mask = WM8994_FLL1_LOCK_EINT, |
| 53 | }, |
| 54 | [WM8994_IRQ_FLL2_LOCK] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 55 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 56 | .mask = WM8994_FLL2_LOCK_EINT, |
| 57 | }, |
| 58 | [WM8994_IRQ_SRC1_LOCK] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 59 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 60 | .mask = WM8994_SRC1_LOCK_EINT, |
| 61 | }, |
| 62 | [WM8994_IRQ_SRC2_LOCK] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 63 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 64 | .mask = WM8994_SRC2_LOCK_EINT, |
| 65 | }, |
| 66 | [WM8994_IRQ_AIF1DRC1_SIG_DET] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 67 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 68 | .mask = WM8994_AIF1DRC1_SIG_DET, |
| 69 | }, |
| 70 | [WM8994_IRQ_AIF1DRC2_SIG_DET] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 71 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 72 | .mask = WM8994_AIF1DRC2_SIG_DET_EINT, |
| 73 | }, |
| 74 | [WM8994_IRQ_AIF2DRC_SIG_DET] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 75 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 76 | .mask = WM8994_AIF2DRC_SIG_DET_EINT, |
| 77 | }, |
| 78 | [WM8994_IRQ_FIFOS_ERR] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 79 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 80 | .mask = WM8994_FIFOS_ERR_EINT, |
| 81 | }, |
| 82 | [WM8994_IRQ_WSEQ_DONE] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 83 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 84 | .mask = WM8994_WSEQ_DONE_EINT, |
| 85 | }, |
| 86 | [WM8994_IRQ_DCS_DONE] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 87 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 88 | .mask = WM8994_DCS_DONE_EINT, |
| 89 | }, |
| 90 | [WM8994_IRQ_TEMP_WARN] = { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 91 | .reg_offset = 1, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 92 | .mask = WM8994_TEMP_WARN_EINT, |
| 93 | }, |
| 94 | [WM8994_IRQ_GPIO(1)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 95 | .mask = WM8994_GP1_EINT, |
| 96 | }, |
| 97 | [WM8994_IRQ_GPIO(2)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 98 | .mask = WM8994_GP2_EINT, |
| 99 | }, |
| 100 | [WM8994_IRQ_GPIO(3)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 101 | .mask = WM8994_GP3_EINT, |
| 102 | }, |
| 103 | [WM8994_IRQ_GPIO(4)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 104 | .mask = WM8994_GP4_EINT, |
| 105 | }, |
| 106 | [WM8994_IRQ_GPIO(5)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 107 | .mask = WM8994_GP5_EINT, |
| 108 | }, |
| 109 | [WM8994_IRQ_GPIO(6)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 110 | .mask = WM8994_GP6_EINT, |
| 111 | }, |
| 112 | [WM8994_IRQ_GPIO(7)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 113 | .mask = WM8994_GP7_EINT, |
| 114 | }, |
| 115 | [WM8994_IRQ_GPIO(8)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 116 | .mask = WM8994_GP8_EINT, |
| 117 | }, |
| 118 | [WM8994_IRQ_GPIO(9)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 119 | .mask = WM8994_GP8_EINT, |
| 120 | }, |
| 121 | [WM8994_IRQ_GPIO(10)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 122 | .mask = WM8994_GP10_EINT, |
| 123 | }, |
| 124 | [WM8994_IRQ_GPIO(11)] = { |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 125 | .mask = WM8994_GP11_EINT, |
| 126 | }, |
| 127 | }; |
| 128 | |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 129 | static struct regmap_irq_chip wm8994_irq_chip = { |
| 130 | .name = "wm8994", |
| 131 | .irqs = wm8994_irqs, |
| 132 | .num_irqs = ARRAY_SIZE(wm8994_irqs), |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 133 | |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 134 | .num_regs = 2, |
| 135 | .status_base = WM8994_INTERRUPT_STATUS_1, |
| 136 | .mask_base = WM8994_INTERRUPT_STATUS_1_MASK, |
| 137 | .ack_base = WM8994_INTERRUPT_STATUS_1, |
Mark Brown | 7a97637 | 2012-07-24 15:41:53 +0100 | [diff] [blame] | 138 | .runtime_pm = true, |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 139 | }; |
| 140 | |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 141 | int wm8994_irq_init(struct wm8994 *wm8994) |
| 142 | { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 143 | int ret; |
Mark Brown | b0ab907 | 2012-06-01 16:33:19 +0100 | [diff] [blame] | 144 | unsigned long irqflags; |
| 145 | struct wm8994_pdata *pdata = wm8994->dev->platform_data; |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 146 | |
| 147 | if (!wm8994->irq) { |
| 148 | dev_warn(wm8994->dev, |
| 149 | "No interrupt specified, no interrupts\n"); |
| 150 | wm8994->irq_base = 0; |
| 151 | return 0; |
| 152 | } |
| 153 | |
Mark Brown | b0ab907 | 2012-06-01 16:33:19 +0100 | [diff] [blame] | 154 | /* select user or default irq flags */ |
| 155 | irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT; |
| 156 | if (pdata->irq_flags) |
| 157 | irqflags = pdata->irq_flags; |
| 158 | |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 159 | ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq, |
Mark Brown | b0ab907 | 2012-06-01 16:33:19 +0100 | [diff] [blame] | 160 | irqflags, |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 161 | wm8994->irq_base, &wm8994_irq_chip, |
| 162 | &wm8994->irq_data); |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 163 | if (ret != 0) { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 164 | dev_err(wm8994->dev, "Failed to register IRQ chip: %d\n", ret); |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 165 | return ret; |
| 166 | } |
| 167 | |
| 168 | /* Enable top level interrupt if it was masked */ |
| 169 | wm8994_reg_write(wm8994, WM8994_INTERRUPT_CONTROL, 0); |
| 170 | |
| 171 | return 0; |
| 172 | } |
| 173 | |
| 174 | void wm8994_irq_exit(struct wm8994 *wm8994) |
| 175 | { |
Mark Brown | 8ab3069 | 2011-10-25 10:19:04 +0200 | [diff] [blame] | 176 | regmap_del_irq_chip(wm8994->irq, wm8994->irq_data); |
Mark Brown | c9fbf7e | 2010-03-26 16:49:15 +0000 | [diff] [blame] | 177 | } |