Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de> |
| 3 | * Copyright (C) 2005-2009 Freescale Semiconductor, Inc. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2 of the License, or (at your |
| 8 | * option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, but |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 12 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 13 | * for more details. |
| 14 | */ |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/export.h> |
| 17 | #include <linux/types.h> |
| 18 | #include <linux/init.h> |
Philipp Zabel | 6c64155 | 2013-03-28 17:35:21 +0100 | [diff] [blame] | 19 | #include <linux/reset.h> |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/err.h> |
| 22 | #include <linux/spinlock.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/io.h> |
| 26 | #include <linux/clk.h> |
| 27 | #include <linux/list.h> |
| 28 | #include <linux/irq.h> |
Catalin Marinas | de88cbb | 2013-01-18 15:31:37 +0000 | [diff] [blame] | 29 | #include <linux/irqchip/chained_irq.h> |
Philipp Zabel | b728766 | 2013-06-21 10:27:39 +0200 | [diff] [blame] | 30 | #include <linux/irqdomain.h> |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 31 | #include <linux/of_device.h> |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 32 | |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 33 | #include <drm/drm_fourcc.h> |
| 34 | |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 35 | #include "imx-ipu-v3.h" |
| 36 | #include "ipu-prv.h" |
| 37 | |
| 38 | static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset) |
| 39 | { |
| 40 | return readl(ipu->cm_reg + offset); |
| 41 | } |
| 42 | |
| 43 | static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset) |
| 44 | { |
| 45 | writel(value, ipu->cm_reg + offset); |
| 46 | } |
| 47 | |
| 48 | static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset) |
| 49 | { |
| 50 | return readl(ipu->idmac_reg + offset); |
| 51 | } |
| 52 | |
| 53 | static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value, |
| 54 | unsigned offset) |
| 55 | { |
| 56 | writel(value, ipu->idmac_reg + offset); |
| 57 | } |
| 58 | |
| 59 | void ipu_srm_dp_sync_update(struct ipu_soc *ipu) |
| 60 | { |
| 61 | u32 val; |
| 62 | |
| 63 | val = ipu_cm_read(ipu, IPU_SRM_PRI2); |
| 64 | val |= 0x8; |
| 65 | ipu_cm_write(ipu, val, IPU_SRM_PRI2); |
| 66 | } |
| 67 | EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update); |
| 68 | |
| 69 | struct ipu_ch_param __iomem *ipu_get_cpmem(struct ipuv3_channel *channel) |
| 70 | { |
| 71 | struct ipu_soc *ipu = channel->ipu; |
| 72 | |
| 73 | return ipu->cpmem_base + channel->num; |
| 74 | } |
| 75 | EXPORT_SYMBOL_GPL(ipu_get_cpmem); |
| 76 | |
| 77 | void ipu_cpmem_set_high_priority(struct ipuv3_channel *channel) |
| 78 | { |
| 79 | struct ipu_soc *ipu = channel->ipu; |
| 80 | struct ipu_ch_param __iomem *p = ipu_get_cpmem(channel); |
| 81 | u32 val; |
| 82 | |
| 83 | if (ipu->ipu_type == IPUV3EX) |
| 84 | ipu_ch_param_write_field(p, IPU_FIELD_ID, 1); |
| 85 | |
| 86 | val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(channel->num)); |
| 87 | val |= 1 << (channel->num % 32); |
| 88 | ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(channel->num)); |
| 89 | }; |
| 90 | EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority); |
| 91 | |
| 92 | void ipu_ch_param_write_field(struct ipu_ch_param __iomem *base, u32 wbs, u32 v) |
| 93 | { |
| 94 | u32 bit = (wbs >> 8) % 160; |
| 95 | u32 size = wbs & 0xff; |
| 96 | u32 word = (wbs >> 8) / 160; |
| 97 | u32 i = bit / 32; |
| 98 | u32 ofs = bit % 32; |
| 99 | u32 mask = (1 << size) - 1; |
| 100 | u32 val; |
| 101 | |
| 102 | pr_debug("%s %d %d %d\n", __func__, word, bit , size); |
| 103 | |
| 104 | val = readl(&base->word[word].data[i]); |
| 105 | val &= ~(mask << ofs); |
| 106 | val |= v << ofs; |
| 107 | writel(val, &base->word[word].data[i]); |
| 108 | |
| 109 | if ((bit + size - 1) / 32 > i) { |
| 110 | val = readl(&base->word[word].data[i + 1]); |
| 111 | val &= ~(mask >> (ofs ? (32 - ofs) : 0)); |
| 112 | val |= v >> (ofs ? (32 - ofs) : 0); |
| 113 | writel(val, &base->word[word].data[i + 1]); |
| 114 | } |
| 115 | } |
| 116 | EXPORT_SYMBOL_GPL(ipu_ch_param_write_field); |
| 117 | |
| 118 | u32 ipu_ch_param_read_field(struct ipu_ch_param __iomem *base, u32 wbs) |
| 119 | { |
| 120 | u32 bit = (wbs >> 8) % 160; |
| 121 | u32 size = wbs & 0xff; |
| 122 | u32 word = (wbs >> 8) / 160; |
| 123 | u32 i = bit / 32; |
| 124 | u32 ofs = bit % 32; |
| 125 | u32 mask = (1 << size) - 1; |
| 126 | u32 val = 0; |
| 127 | |
| 128 | pr_debug("%s %d %d %d\n", __func__, word, bit , size); |
| 129 | |
| 130 | val = (readl(&base->word[word].data[i]) >> ofs) & mask; |
| 131 | |
| 132 | if ((bit + size - 1) / 32 > i) { |
| 133 | u32 tmp; |
| 134 | tmp = readl(&base->word[word].data[i + 1]); |
| 135 | tmp &= mask >> (ofs ? (32 - ofs) : 0); |
| 136 | val |= tmp << (ofs ? (32 - ofs) : 0); |
| 137 | } |
| 138 | |
| 139 | return val; |
| 140 | } |
| 141 | EXPORT_SYMBOL_GPL(ipu_ch_param_read_field); |
| 142 | |
| 143 | int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem *p, |
Philipp Zabel | e56af86 | 2013-10-10 16:18:37 +0200 | [diff] [blame] | 144 | const struct ipu_rgb *rgb) |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 145 | { |
| 146 | int bpp = 0, npb = 0, ro, go, bo, to; |
| 147 | |
| 148 | ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset; |
| 149 | go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset; |
| 150 | bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset; |
| 151 | to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset; |
| 152 | |
| 153 | ipu_ch_param_write_field(p, IPU_FIELD_WID0, rgb->red.length - 1); |
| 154 | ipu_ch_param_write_field(p, IPU_FIELD_OFS0, ro); |
| 155 | ipu_ch_param_write_field(p, IPU_FIELD_WID1, rgb->green.length - 1); |
| 156 | ipu_ch_param_write_field(p, IPU_FIELD_OFS1, go); |
| 157 | ipu_ch_param_write_field(p, IPU_FIELD_WID2, rgb->blue.length - 1); |
| 158 | ipu_ch_param_write_field(p, IPU_FIELD_OFS2, bo); |
| 159 | |
| 160 | if (rgb->transp.length) { |
| 161 | ipu_ch_param_write_field(p, IPU_FIELD_WID3, |
| 162 | rgb->transp.length - 1); |
| 163 | ipu_ch_param_write_field(p, IPU_FIELD_OFS3, to); |
| 164 | } else { |
| 165 | ipu_ch_param_write_field(p, IPU_FIELD_WID3, 7); |
| 166 | ipu_ch_param_write_field(p, IPU_FIELD_OFS3, |
| 167 | rgb->bits_per_pixel); |
| 168 | } |
| 169 | |
| 170 | switch (rgb->bits_per_pixel) { |
| 171 | case 32: |
| 172 | bpp = 0; |
| 173 | npb = 15; |
| 174 | break; |
| 175 | case 24: |
| 176 | bpp = 1; |
| 177 | npb = 19; |
| 178 | break; |
| 179 | case 16: |
| 180 | bpp = 3; |
| 181 | npb = 31; |
| 182 | break; |
| 183 | case 8: |
| 184 | bpp = 5; |
| 185 | npb = 63; |
| 186 | break; |
| 187 | default: |
| 188 | return -EINVAL; |
| 189 | } |
| 190 | ipu_ch_param_write_field(p, IPU_FIELD_BPP, bpp); |
| 191 | ipu_ch_param_write_field(p, IPU_FIELD_NPB, npb); |
| 192 | ipu_ch_param_write_field(p, IPU_FIELD_PFS, 7); /* rgb mode */ |
| 193 | |
| 194 | return 0; |
| 195 | } |
| 196 | EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb); |
| 197 | |
| 198 | int ipu_cpmem_set_format_passthrough(struct ipu_ch_param __iomem *p, |
| 199 | int width) |
| 200 | { |
| 201 | int bpp = 0, npb = 0; |
| 202 | |
| 203 | switch (width) { |
| 204 | case 32: |
| 205 | bpp = 0; |
| 206 | npb = 15; |
| 207 | break; |
| 208 | case 24: |
| 209 | bpp = 1; |
| 210 | npb = 19; |
| 211 | break; |
| 212 | case 16: |
| 213 | bpp = 3; |
| 214 | npb = 31; |
| 215 | break; |
| 216 | case 8: |
| 217 | bpp = 5; |
| 218 | npb = 63; |
| 219 | break; |
| 220 | default: |
| 221 | return -EINVAL; |
| 222 | } |
| 223 | |
| 224 | ipu_ch_param_write_field(p, IPU_FIELD_BPP, bpp); |
| 225 | ipu_ch_param_write_field(p, IPU_FIELD_NPB, npb); |
| 226 | ipu_ch_param_write_field(p, IPU_FIELD_PFS, 6); /* raw mode */ |
| 227 | |
| 228 | return 0; |
| 229 | } |
| 230 | EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough); |
| 231 | |
Fabio Estevam | 6cadd88 | 2013-03-23 19:43:32 -0300 | [diff] [blame] | 232 | void ipu_cpmem_set_yuv_interleaved(struct ipu_ch_param __iomem *p, |
| 233 | u32 pixel_format) |
Philipp Zabel | 0125f21 | 2012-11-12 16:29:02 +0100 | [diff] [blame] | 234 | { |
| 235 | switch (pixel_format) { |
| 236 | case V4L2_PIX_FMT_UYVY: |
| 237 | ipu_ch_param_write_field(p, IPU_FIELD_BPP, 3); /* bits/pixel */ |
| 238 | ipu_ch_param_write_field(p, IPU_FIELD_PFS, 0xA); /* pix format */ |
| 239 | ipu_ch_param_write_field(p, IPU_FIELD_NPB, 31); /* burst size */ |
| 240 | break; |
| 241 | case V4L2_PIX_FMT_YUYV: |
| 242 | ipu_ch_param_write_field(p, IPU_FIELD_BPP, 3); /* bits/pixel */ |
| 243 | ipu_ch_param_write_field(p, IPU_FIELD_PFS, 0x8); /* pix format */ |
| 244 | ipu_ch_param_write_field(p, IPU_FIELD_NPB, 31); /* burst size */ |
| 245 | break; |
| 246 | } |
| 247 | } |
| 248 | EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved); |
| 249 | |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 250 | void ipu_cpmem_set_yuv_planar_full(struct ipu_ch_param __iomem *p, |
| 251 | u32 pixel_format, int stride, int u_offset, int v_offset) |
| 252 | { |
| 253 | switch (pixel_format) { |
| 254 | case V4L2_PIX_FMT_YUV420: |
| 255 | ipu_ch_param_write_field(p, IPU_FIELD_SLUV, (stride / 2) - 1); |
| 256 | ipu_ch_param_write_field(p, IPU_FIELD_UBO, u_offset / 8); |
| 257 | ipu_ch_param_write_field(p, IPU_FIELD_VBO, v_offset / 8); |
| 258 | break; |
Philipp Zabel | d3e4e61 | 2012-11-12 16:29:00 +0100 | [diff] [blame] | 259 | case V4L2_PIX_FMT_YVU420: |
| 260 | ipu_ch_param_write_field(p, IPU_FIELD_SLUV, (stride / 2) - 1); |
| 261 | ipu_ch_param_write_field(p, IPU_FIELD_UBO, v_offset / 8); |
| 262 | ipu_ch_param_write_field(p, IPU_FIELD_VBO, u_offset / 8); |
| 263 | break; |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 264 | } |
| 265 | } |
| 266 | EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full); |
| 267 | |
| 268 | void ipu_cpmem_set_yuv_planar(struct ipu_ch_param __iomem *p, u32 pixel_format, |
| 269 | int stride, int height) |
| 270 | { |
| 271 | int u_offset, v_offset; |
| 272 | int uv_stride = 0; |
| 273 | |
| 274 | switch (pixel_format) { |
| 275 | case V4L2_PIX_FMT_YUV420: |
Philipp Zabel | d3e4e61 | 2012-11-12 16:29:00 +0100 | [diff] [blame] | 276 | case V4L2_PIX_FMT_YVU420: |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 277 | uv_stride = stride / 2; |
| 278 | u_offset = stride * height; |
| 279 | v_offset = u_offset + (uv_stride * height / 2); |
Philipp Zabel | d3e4e61 | 2012-11-12 16:29:00 +0100 | [diff] [blame] | 280 | ipu_cpmem_set_yuv_planar_full(p, pixel_format, stride, |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 281 | u_offset, v_offset); |
| 282 | break; |
| 283 | } |
| 284 | } |
| 285 | EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar); |
| 286 | |
Philipp Zabel | e56af86 | 2013-10-10 16:18:37 +0200 | [diff] [blame] | 287 | static const struct ipu_rgb def_rgb_32 = { |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 288 | .red = { .offset = 16, .length = 8, }, |
| 289 | .green = { .offset = 8, .length = 8, }, |
| 290 | .blue = { .offset = 0, .length = 8, }, |
| 291 | .transp = { .offset = 24, .length = 8, }, |
| 292 | .bits_per_pixel = 32, |
| 293 | }; |
| 294 | |
Philipp Zabel | e56af86 | 2013-10-10 16:18:37 +0200 | [diff] [blame] | 295 | static const struct ipu_rgb def_bgr_32 = { |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 296 | .red = { .offset = 0, .length = 8, }, |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 297 | .green = { .offset = 8, .length = 8, }, |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 298 | .blue = { .offset = 16, .length = 8, }, |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 299 | .transp = { .offset = 24, .length = 8, }, |
| 300 | .bits_per_pixel = 32, |
| 301 | }; |
| 302 | |
Philipp Zabel | e56af86 | 2013-10-10 16:18:37 +0200 | [diff] [blame] | 303 | static const struct ipu_rgb def_rgb_24 = { |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 304 | .red = { .offset = 16, .length = 8, }, |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 305 | .green = { .offset = 8, .length = 8, }, |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 306 | .blue = { .offset = 0, .length = 8, }, |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 307 | .transp = { .offset = 0, .length = 0, }, |
| 308 | .bits_per_pixel = 24, |
| 309 | }; |
| 310 | |
Philipp Zabel | e56af86 | 2013-10-10 16:18:37 +0200 | [diff] [blame] | 311 | static const struct ipu_rgb def_bgr_24 = { |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 312 | .red = { .offset = 0, .length = 8, }, |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 313 | .green = { .offset = 8, .length = 8, }, |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 314 | .blue = { .offset = 16, .length = 8, }, |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 315 | .transp = { .offset = 0, .length = 0, }, |
| 316 | .bits_per_pixel = 24, |
| 317 | }; |
| 318 | |
Philipp Zabel | e56af86 | 2013-10-10 16:18:37 +0200 | [diff] [blame] | 319 | static const struct ipu_rgb def_rgb_16 = { |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 320 | .red = { .offset = 11, .length = 5, }, |
| 321 | .green = { .offset = 5, .length = 6, }, |
| 322 | .blue = { .offset = 0, .length = 5, }, |
| 323 | .transp = { .offset = 0, .length = 0, }, |
| 324 | .bits_per_pixel = 16, |
| 325 | }; |
| 326 | |
| 327 | #define Y_OFFSET(pix, x, y) ((x) + pix->width * (y)) |
| 328 | #define U_OFFSET(pix, x, y) ((pix->width * pix->height) + \ |
| 329 | (pix->width * (y) / 4) + (x) / 2) |
| 330 | #define V_OFFSET(pix, x, y) ((pix->width * pix->height) + \ |
| 331 | (pix->width * pix->height / 4) + \ |
| 332 | (pix->width * (y) / 4) + (x) / 2) |
| 333 | |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 334 | int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem *cpmem, u32 drm_fourcc) |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 335 | { |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 336 | switch (drm_fourcc) { |
| 337 | case DRM_FORMAT_YUV420: |
| 338 | case DRM_FORMAT_YVU420: |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 339 | /* pix format */ |
| 340 | ipu_ch_param_write_field(cpmem, IPU_FIELD_PFS, 2); |
| 341 | /* burst size */ |
| 342 | ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 63); |
| 343 | break; |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 344 | case DRM_FORMAT_UYVY: |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 345 | /* bits/pixel */ |
| 346 | ipu_ch_param_write_field(cpmem, IPU_FIELD_BPP, 3); |
| 347 | /* pix format */ |
| 348 | ipu_ch_param_write_field(cpmem, IPU_FIELD_PFS, 0xA); |
| 349 | /* burst size */ |
| 350 | ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 31); |
| 351 | break; |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 352 | case DRM_FORMAT_YUYV: |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 353 | /* bits/pixel */ |
| 354 | ipu_ch_param_write_field(cpmem, IPU_FIELD_BPP, 3); |
| 355 | /* pix format */ |
| 356 | ipu_ch_param_write_field(cpmem, IPU_FIELD_PFS, 0x8); |
| 357 | /* burst size */ |
| 358 | ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 31); |
| 359 | break; |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 360 | case DRM_FORMAT_ABGR8888: |
| 361 | case DRM_FORMAT_XBGR8888: |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 362 | ipu_cpmem_set_format_rgb(cpmem, &def_bgr_32); |
| 363 | break; |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 364 | case DRM_FORMAT_ARGB8888: |
| 365 | case DRM_FORMAT_XRGB8888: |
| 366 | ipu_cpmem_set_format_rgb(cpmem, &def_rgb_32); |
| 367 | break; |
| 368 | case DRM_FORMAT_BGR888: |
| 369 | ipu_cpmem_set_format_rgb(cpmem, &def_bgr_24); |
| 370 | break; |
| 371 | case DRM_FORMAT_RGB888: |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 372 | ipu_cpmem_set_format_rgb(cpmem, &def_rgb_24); |
| 373 | break; |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 374 | case DRM_FORMAT_RGB565: |
| 375 | ipu_cpmem_set_format_rgb(cpmem, &def_rgb_16); |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 376 | break; |
| 377 | default: |
| 378 | return -EINVAL; |
| 379 | } |
| 380 | |
| 381 | return 0; |
| 382 | } |
| 383 | EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt); |
| 384 | |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 385 | /* |
| 386 | * The V4L2 spec defines packed RGB formats in memory byte order, which from |
| 387 | * point of view of the IPU corresponds to little-endian words with the first |
| 388 | * component in the least significant bits. |
| 389 | * The DRM pixel formats and IPU internal representation are ordered the other |
| 390 | * way around, with the first named component ordered at the most significant |
| 391 | * bits. Further, V4L2 formats are not well defined: |
| 392 | * http://linuxtv.org/downloads/v4l-dvb-apis/packed-rgb.html |
| 393 | * We choose the interpretation which matches GStreamer behavior. |
| 394 | */ |
| 395 | static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat) |
| 396 | { |
| 397 | switch (pixelformat) { |
| 398 | case V4L2_PIX_FMT_RGB565: |
| 399 | /* |
| 400 | * Here we choose the 'corrected' interpretation of RGBP, a |
| 401 | * little-endian 16-bit word with the red component at the most |
| 402 | * significant bits: |
| 403 | * g[2:0]b[4:0] r[4:0]g[5:3] <=> [16:0] R:G:B |
| 404 | */ |
| 405 | return DRM_FORMAT_RGB565; |
| 406 | case V4L2_PIX_FMT_BGR24: |
| 407 | /* B G R <=> [24:0] R:G:B */ |
| 408 | return DRM_FORMAT_RGB888; |
| 409 | case V4L2_PIX_FMT_RGB24: |
| 410 | /* R G B <=> [24:0] B:G:R */ |
| 411 | return DRM_FORMAT_BGR888; |
| 412 | case V4L2_PIX_FMT_BGR32: |
| 413 | /* B G R A <=> [32:0] A:B:G:R */ |
| 414 | return DRM_FORMAT_XRGB8888; |
| 415 | case V4L2_PIX_FMT_RGB32: |
| 416 | /* R G B A <=> [32:0] A:B:G:R */ |
| 417 | return DRM_FORMAT_XBGR8888; |
| 418 | case V4L2_PIX_FMT_UYVY: |
| 419 | return DRM_FORMAT_UYVY; |
| 420 | case V4L2_PIX_FMT_YUYV: |
| 421 | return DRM_FORMAT_YUYV; |
| 422 | case V4L2_PIX_FMT_YUV420: |
| 423 | return DRM_FORMAT_YUV420; |
| 424 | case V4L2_PIX_FMT_YVU420: |
| 425 | return DRM_FORMAT_YVU420; |
| 426 | } |
| 427 | |
| 428 | return -EINVAL; |
| 429 | } |
| 430 | |
| 431 | enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc) |
| 432 | { |
| 433 | switch (drm_fourcc) { |
| 434 | case DRM_FORMAT_RGB565: |
| 435 | case DRM_FORMAT_BGR565: |
| 436 | case DRM_FORMAT_RGB888: |
| 437 | case DRM_FORMAT_BGR888: |
| 438 | case DRM_FORMAT_XRGB8888: |
| 439 | case DRM_FORMAT_XBGR8888: |
| 440 | case DRM_FORMAT_RGBX8888: |
| 441 | case DRM_FORMAT_BGRX8888: |
| 442 | case DRM_FORMAT_ARGB8888: |
| 443 | case DRM_FORMAT_ABGR8888: |
| 444 | case DRM_FORMAT_RGBA8888: |
| 445 | case DRM_FORMAT_BGRA8888: |
| 446 | return IPUV3_COLORSPACE_RGB; |
| 447 | case DRM_FORMAT_YUYV: |
| 448 | case DRM_FORMAT_UYVY: |
| 449 | case DRM_FORMAT_YUV420: |
| 450 | case DRM_FORMAT_YVU420: |
| 451 | return IPUV3_COLORSPACE_YUV; |
| 452 | default: |
| 453 | return IPUV3_COLORSPACE_UNKNOWN; |
| 454 | } |
| 455 | } |
| 456 | EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace); |
| 457 | |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 458 | int ipu_cpmem_set_image(struct ipu_ch_param __iomem *cpmem, |
| 459 | struct ipu_image *image) |
| 460 | { |
| 461 | struct v4l2_pix_format *pix = &image->pix; |
| 462 | int y_offset, u_offset, v_offset; |
| 463 | |
| 464 | pr_debug("%s: resolution: %dx%d stride: %d\n", |
| 465 | __func__, pix->width, pix->height, |
| 466 | pix->bytesperline); |
| 467 | |
| 468 | ipu_cpmem_set_resolution(cpmem, image->rect.width, |
| 469 | image->rect.height); |
| 470 | ipu_cpmem_set_stride(cpmem, pix->bytesperline); |
| 471 | |
Philipp Zabel | 7cb1779 | 2013-10-10 16:18:38 +0200 | [diff] [blame^] | 472 | ipu_cpmem_set_fmt(cpmem, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat)); |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 473 | |
| 474 | switch (pix->pixelformat) { |
| 475 | case V4L2_PIX_FMT_YUV420: |
Philipp Zabel | d3e4e61 | 2012-11-12 16:29:00 +0100 | [diff] [blame] | 476 | case V4L2_PIX_FMT_YVU420: |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 477 | y_offset = Y_OFFSET(pix, image->rect.left, image->rect.top); |
| 478 | u_offset = U_OFFSET(pix, image->rect.left, |
| 479 | image->rect.top) - y_offset; |
| 480 | v_offset = V_OFFSET(pix, image->rect.left, |
| 481 | image->rect.top) - y_offset; |
| 482 | |
| 483 | ipu_cpmem_set_yuv_planar_full(cpmem, pix->pixelformat, |
| 484 | pix->bytesperline, u_offset, v_offset); |
| 485 | ipu_cpmem_set_buffer(cpmem, 0, image->phys + y_offset); |
| 486 | break; |
| 487 | case V4L2_PIX_FMT_UYVY: |
Michael Olbrich | c096ae1 | 2012-11-12 16:28:59 +0100 | [diff] [blame] | 488 | case V4L2_PIX_FMT_YUYV: |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 489 | ipu_cpmem_set_buffer(cpmem, 0, image->phys + |
| 490 | image->rect.left * 2 + |
| 491 | image->rect.top * image->pix.bytesperline); |
| 492 | break; |
| 493 | case V4L2_PIX_FMT_RGB32: |
| 494 | case V4L2_PIX_FMT_BGR32: |
| 495 | ipu_cpmem_set_buffer(cpmem, 0, image->phys + |
| 496 | image->rect.left * 4 + |
| 497 | image->rect.top * image->pix.bytesperline); |
| 498 | break; |
| 499 | case V4L2_PIX_FMT_RGB565: |
| 500 | ipu_cpmem_set_buffer(cpmem, 0, image->phys + |
| 501 | image->rect.left * 2 + |
| 502 | image->rect.top * image->pix.bytesperline); |
| 503 | break; |
| 504 | case V4L2_PIX_FMT_RGB24: |
| 505 | case V4L2_PIX_FMT_BGR24: |
| 506 | ipu_cpmem_set_buffer(cpmem, 0, image->phys + |
| 507 | image->rect.left * 3 + |
| 508 | image->rect.top * image->pix.bytesperline); |
| 509 | break; |
| 510 | default: |
| 511 | return -EINVAL; |
| 512 | } |
| 513 | |
| 514 | return 0; |
| 515 | } |
| 516 | EXPORT_SYMBOL_GPL(ipu_cpmem_set_image); |
| 517 | |
| 518 | enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat) |
| 519 | { |
| 520 | switch (pixelformat) { |
| 521 | case V4L2_PIX_FMT_YUV420: |
Philipp Zabel | d3e4e61 | 2012-11-12 16:29:00 +0100 | [diff] [blame] | 522 | case V4L2_PIX_FMT_YVU420: |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 523 | case V4L2_PIX_FMT_UYVY: |
Michael Olbrich | c096ae1 | 2012-11-12 16:28:59 +0100 | [diff] [blame] | 524 | case V4L2_PIX_FMT_YUYV: |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 525 | return IPUV3_COLORSPACE_YUV; |
| 526 | case V4L2_PIX_FMT_RGB32: |
| 527 | case V4L2_PIX_FMT_BGR32: |
| 528 | case V4L2_PIX_FMT_RGB24: |
| 529 | case V4L2_PIX_FMT_BGR24: |
| 530 | case V4L2_PIX_FMT_RGB565: |
| 531 | return IPUV3_COLORSPACE_RGB; |
| 532 | default: |
| 533 | return IPUV3_COLORSPACE_UNKNOWN; |
| 534 | } |
| 535 | } |
| 536 | EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace); |
| 537 | |
| 538 | struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num) |
| 539 | { |
| 540 | struct ipuv3_channel *channel; |
| 541 | |
| 542 | dev_dbg(ipu->dev, "%s %d\n", __func__, num); |
| 543 | |
| 544 | if (num > 63) |
| 545 | return ERR_PTR(-ENODEV); |
| 546 | |
| 547 | mutex_lock(&ipu->channel_lock); |
| 548 | |
| 549 | channel = &ipu->channel[num]; |
| 550 | |
| 551 | if (channel->busy) { |
| 552 | channel = ERR_PTR(-EBUSY); |
| 553 | goto out; |
| 554 | } |
| 555 | |
| 556 | channel->busy = 1; |
| 557 | channel->num = num; |
| 558 | |
| 559 | out: |
| 560 | mutex_unlock(&ipu->channel_lock); |
| 561 | |
| 562 | return channel; |
| 563 | } |
| 564 | EXPORT_SYMBOL_GPL(ipu_idmac_get); |
| 565 | |
| 566 | void ipu_idmac_put(struct ipuv3_channel *channel) |
| 567 | { |
| 568 | struct ipu_soc *ipu = channel->ipu; |
| 569 | |
| 570 | dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num); |
| 571 | |
| 572 | mutex_lock(&ipu->channel_lock); |
| 573 | |
| 574 | channel->busy = 0; |
| 575 | |
| 576 | mutex_unlock(&ipu->channel_lock); |
| 577 | } |
| 578 | EXPORT_SYMBOL_GPL(ipu_idmac_put); |
| 579 | |
| 580 | #define idma_mask(ch) (1 << (ch & 0x1f)) |
| 581 | |
| 582 | void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, |
| 583 | bool doublebuffer) |
| 584 | { |
| 585 | struct ipu_soc *ipu = channel->ipu; |
| 586 | unsigned long flags; |
| 587 | u32 reg; |
| 588 | |
| 589 | spin_lock_irqsave(&ipu->lock, flags); |
| 590 | |
| 591 | reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); |
| 592 | if (doublebuffer) |
| 593 | reg |= idma_mask(channel->num); |
| 594 | else |
| 595 | reg &= ~idma_mask(channel->num); |
| 596 | ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); |
| 597 | |
| 598 | spin_unlock_irqrestore(&ipu->lock, flags); |
| 599 | } |
| 600 | EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer); |
| 601 | |
| 602 | int ipu_module_enable(struct ipu_soc *ipu, u32 mask) |
| 603 | { |
| 604 | unsigned long lock_flags; |
| 605 | u32 val; |
| 606 | |
| 607 | spin_lock_irqsave(&ipu->lock, lock_flags); |
| 608 | |
| 609 | val = ipu_cm_read(ipu, IPU_DISP_GEN); |
| 610 | |
| 611 | if (mask & IPU_CONF_DI0_EN) |
| 612 | val |= IPU_DI0_COUNTER_RELEASE; |
| 613 | if (mask & IPU_CONF_DI1_EN) |
| 614 | val |= IPU_DI1_COUNTER_RELEASE; |
| 615 | |
| 616 | ipu_cm_write(ipu, val, IPU_DISP_GEN); |
| 617 | |
| 618 | val = ipu_cm_read(ipu, IPU_CONF); |
| 619 | val |= mask; |
| 620 | ipu_cm_write(ipu, val, IPU_CONF); |
| 621 | |
| 622 | spin_unlock_irqrestore(&ipu->lock, lock_flags); |
| 623 | |
| 624 | return 0; |
| 625 | } |
| 626 | EXPORT_SYMBOL_GPL(ipu_module_enable); |
| 627 | |
| 628 | int ipu_module_disable(struct ipu_soc *ipu, u32 mask) |
| 629 | { |
| 630 | unsigned long lock_flags; |
| 631 | u32 val; |
| 632 | |
| 633 | spin_lock_irqsave(&ipu->lock, lock_flags); |
| 634 | |
| 635 | val = ipu_cm_read(ipu, IPU_CONF); |
| 636 | val &= ~mask; |
| 637 | ipu_cm_write(ipu, val, IPU_CONF); |
| 638 | |
| 639 | val = ipu_cm_read(ipu, IPU_DISP_GEN); |
| 640 | |
| 641 | if (mask & IPU_CONF_DI0_EN) |
| 642 | val &= ~IPU_DI0_COUNTER_RELEASE; |
| 643 | if (mask & IPU_CONF_DI1_EN) |
| 644 | val &= ~IPU_DI1_COUNTER_RELEASE; |
| 645 | |
| 646 | ipu_cm_write(ipu, val, IPU_DISP_GEN); |
| 647 | |
| 648 | spin_unlock_irqrestore(&ipu->lock, lock_flags); |
| 649 | |
| 650 | return 0; |
| 651 | } |
| 652 | EXPORT_SYMBOL_GPL(ipu_module_disable); |
| 653 | |
| 654 | void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num) |
| 655 | { |
| 656 | struct ipu_soc *ipu = channel->ipu; |
| 657 | unsigned int chno = channel->num; |
| 658 | unsigned long flags; |
| 659 | |
| 660 | spin_lock_irqsave(&ipu->lock, flags); |
| 661 | |
| 662 | /* Mark buffer as ready. */ |
| 663 | if (buf_num == 0) |
| 664 | ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); |
| 665 | else |
| 666 | ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); |
| 667 | |
| 668 | spin_unlock_irqrestore(&ipu->lock, flags); |
| 669 | } |
| 670 | EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer); |
| 671 | |
| 672 | int ipu_idmac_enable_channel(struct ipuv3_channel *channel) |
| 673 | { |
| 674 | struct ipu_soc *ipu = channel->ipu; |
| 675 | u32 val; |
| 676 | unsigned long flags; |
| 677 | |
| 678 | spin_lock_irqsave(&ipu->lock, flags); |
| 679 | |
| 680 | val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); |
| 681 | val |= idma_mask(channel->num); |
| 682 | ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); |
| 683 | |
| 684 | spin_unlock_irqrestore(&ipu->lock, flags); |
| 685 | |
| 686 | return 0; |
| 687 | } |
| 688 | EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel); |
| 689 | |
| 690 | int ipu_idmac_disable_channel(struct ipuv3_channel *channel) |
| 691 | { |
| 692 | struct ipu_soc *ipu = channel->ipu; |
| 693 | u32 val; |
| 694 | unsigned long flags; |
| 695 | unsigned long timeout; |
| 696 | |
| 697 | timeout = jiffies + msecs_to_jiffies(50); |
| 698 | while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) & |
| 699 | idma_mask(channel->num)) { |
| 700 | if (time_after(jiffies, timeout)) { |
| 701 | dev_warn(ipu->dev, "disabling busy idmac channel %d\n", |
| 702 | channel->num); |
| 703 | break; |
| 704 | } |
| 705 | cpu_relax(); |
| 706 | } |
| 707 | |
| 708 | spin_lock_irqsave(&ipu->lock, flags); |
| 709 | |
| 710 | /* Disable DMA channel(s) */ |
| 711 | val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); |
| 712 | val &= ~idma_mask(channel->num); |
| 713 | ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); |
| 714 | |
| 715 | /* Set channel buffers NOT to be ready */ |
| 716 | ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */ |
| 717 | |
| 718 | if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) & |
| 719 | idma_mask(channel->num)) { |
| 720 | ipu_cm_write(ipu, idma_mask(channel->num), |
| 721 | IPU_CHA_BUF0_RDY(channel->num)); |
| 722 | } |
| 723 | |
| 724 | if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) & |
| 725 | idma_mask(channel->num)) { |
| 726 | ipu_cm_write(ipu, idma_mask(channel->num), |
| 727 | IPU_CHA_BUF1_RDY(channel->num)); |
| 728 | } |
| 729 | |
| 730 | ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ |
| 731 | |
| 732 | /* Reset the double buffer */ |
| 733 | val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); |
| 734 | val &= ~idma_mask(channel->num); |
| 735 | ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); |
| 736 | |
| 737 | spin_unlock_irqrestore(&ipu->lock, flags); |
| 738 | |
| 739 | return 0; |
| 740 | } |
| 741 | EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel); |
| 742 | |
Philipp Zabel | 6c64155 | 2013-03-28 17:35:21 +0100 | [diff] [blame] | 743 | static int ipu_memory_reset(struct ipu_soc *ipu) |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 744 | { |
| 745 | unsigned long timeout; |
| 746 | |
| 747 | ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST); |
| 748 | |
| 749 | timeout = jiffies + msecs_to_jiffies(1000); |
| 750 | while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) { |
| 751 | if (time_after(jiffies, timeout)) |
| 752 | return -ETIME; |
| 753 | cpu_relax(); |
| 754 | } |
| 755 | |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 756 | return 0; |
| 757 | } |
| 758 | |
| 759 | struct ipu_devtype { |
| 760 | const char *name; |
| 761 | unsigned long cm_ofs; |
| 762 | unsigned long cpmem_ofs; |
| 763 | unsigned long srm_ofs; |
| 764 | unsigned long tpm_ofs; |
| 765 | unsigned long disp0_ofs; |
| 766 | unsigned long disp1_ofs; |
| 767 | unsigned long dc_tmpl_ofs; |
| 768 | unsigned long vdi_ofs; |
| 769 | enum ipuv3_type type; |
| 770 | }; |
| 771 | |
| 772 | static struct ipu_devtype ipu_type_imx51 = { |
| 773 | .name = "IPUv3EX", |
| 774 | .cm_ofs = 0x1e000000, |
| 775 | .cpmem_ofs = 0x1f000000, |
| 776 | .srm_ofs = 0x1f040000, |
| 777 | .tpm_ofs = 0x1f060000, |
| 778 | .disp0_ofs = 0x1e040000, |
| 779 | .disp1_ofs = 0x1e048000, |
| 780 | .dc_tmpl_ofs = 0x1f080000, |
| 781 | .vdi_ofs = 0x1e068000, |
| 782 | .type = IPUV3EX, |
| 783 | }; |
| 784 | |
| 785 | static struct ipu_devtype ipu_type_imx53 = { |
| 786 | .name = "IPUv3M", |
| 787 | .cm_ofs = 0x06000000, |
| 788 | .cpmem_ofs = 0x07000000, |
| 789 | .srm_ofs = 0x07040000, |
| 790 | .tpm_ofs = 0x07060000, |
| 791 | .disp0_ofs = 0x06040000, |
| 792 | .disp1_ofs = 0x06048000, |
| 793 | .dc_tmpl_ofs = 0x07080000, |
| 794 | .vdi_ofs = 0x06068000, |
| 795 | .type = IPUV3M, |
| 796 | }; |
| 797 | |
| 798 | static struct ipu_devtype ipu_type_imx6q = { |
| 799 | .name = "IPUv3H", |
| 800 | .cm_ofs = 0x00200000, |
| 801 | .cpmem_ofs = 0x00300000, |
| 802 | .srm_ofs = 0x00340000, |
| 803 | .tpm_ofs = 0x00360000, |
| 804 | .disp0_ofs = 0x00240000, |
| 805 | .disp1_ofs = 0x00248000, |
| 806 | .dc_tmpl_ofs = 0x00380000, |
| 807 | .vdi_ofs = 0x00268000, |
| 808 | .type = IPUV3H, |
| 809 | }; |
| 810 | |
| 811 | static const struct of_device_id imx_ipu_dt_ids[] = { |
| 812 | { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, }, |
| 813 | { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, }, |
| 814 | { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, }, |
| 815 | { /* sentinel */ } |
| 816 | }; |
| 817 | MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids); |
| 818 | |
| 819 | static int ipu_submodules_init(struct ipu_soc *ipu, |
| 820 | struct platform_device *pdev, unsigned long ipu_base, |
| 821 | struct clk *ipu_clk) |
| 822 | { |
| 823 | char *unit; |
| 824 | int ret; |
| 825 | struct device *dev = &pdev->dev; |
| 826 | const struct ipu_devtype *devtype = ipu->devtype; |
| 827 | |
| 828 | ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, |
| 829 | IPU_CONF_DI0_EN, ipu_clk); |
| 830 | if (ret) { |
| 831 | unit = "di0"; |
| 832 | goto err_di_0; |
| 833 | } |
| 834 | |
| 835 | ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs, |
| 836 | IPU_CONF_DI1_EN, ipu_clk); |
| 837 | if (ret) { |
| 838 | unit = "di1"; |
| 839 | goto err_di_1; |
| 840 | } |
| 841 | |
| 842 | ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs + |
| 843 | IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs); |
| 844 | if (ret) { |
| 845 | unit = "dc_template"; |
| 846 | goto err_dc; |
| 847 | } |
| 848 | |
| 849 | ret = ipu_dmfc_init(ipu, dev, ipu_base + |
| 850 | devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk); |
| 851 | if (ret) { |
| 852 | unit = "dmfc"; |
| 853 | goto err_dmfc; |
| 854 | } |
| 855 | |
| 856 | ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs); |
| 857 | if (ret) { |
| 858 | unit = "dp"; |
| 859 | goto err_dp; |
| 860 | } |
| 861 | |
| 862 | return 0; |
| 863 | |
| 864 | err_dp: |
| 865 | ipu_dmfc_exit(ipu); |
| 866 | err_dmfc: |
| 867 | ipu_dc_exit(ipu); |
| 868 | err_dc: |
| 869 | ipu_di_exit(ipu, 1); |
| 870 | err_di_1: |
| 871 | ipu_di_exit(ipu, 0); |
| 872 | err_di_0: |
| 873 | dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret); |
| 874 | return ret; |
| 875 | } |
| 876 | |
| 877 | static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs) |
| 878 | { |
| 879 | unsigned long status; |
Philipp Zabel | b728766 | 2013-06-21 10:27:39 +0200 | [diff] [blame] | 880 | int i, bit, irq; |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 881 | |
| 882 | for (i = 0; i < num_regs; i++) { |
| 883 | |
| 884 | status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i])); |
| 885 | status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i])); |
| 886 | |
Philipp Zabel | b728766 | 2013-06-21 10:27:39 +0200 | [diff] [blame] | 887 | for_each_set_bit(bit, &status, 32) { |
| 888 | irq = irq_linear_revmap(ipu->domain, regs[i] * 32 + bit); |
| 889 | if (irq) |
| 890 | generic_handle_irq(irq); |
| 891 | } |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 892 | } |
| 893 | } |
| 894 | |
| 895 | static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc) |
| 896 | { |
| 897 | struct ipu_soc *ipu = irq_desc_get_handler_data(desc); |
| 898 | const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14}; |
| 899 | struct irq_chip *chip = irq_get_chip(irq); |
| 900 | |
| 901 | chained_irq_enter(chip, desc); |
| 902 | |
| 903 | ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); |
| 904 | |
| 905 | chained_irq_exit(chip, desc); |
| 906 | } |
| 907 | |
| 908 | static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc) |
| 909 | { |
| 910 | struct ipu_soc *ipu = irq_desc_get_handler_data(desc); |
| 911 | const int int_reg[] = { 4, 5, 8, 9}; |
| 912 | struct irq_chip *chip = irq_get_chip(irq); |
| 913 | |
| 914 | chained_irq_enter(chip, desc); |
| 915 | |
| 916 | ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); |
| 917 | |
| 918 | chained_irq_exit(chip, desc); |
| 919 | } |
| 920 | |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 921 | int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, |
| 922 | enum ipu_channel_irq irq_type) |
| 923 | { |
Philipp Zabel | b728766 | 2013-06-21 10:27:39 +0200 | [diff] [blame] | 924 | int irq = irq_linear_revmap(ipu->domain, irq_type + channel->num); |
| 925 | |
| 926 | if (!irq) |
| 927 | irq = irq_create_mapping(ipu->domain, irq_type + channel->num); |
| 928 | |
| 929 | return irq; |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 930 | } |
| 931 | EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq); |
| 932 | |
| 933 | static void ipu_submodules_exit(struct ipu_soc *ipu) |
| 934 | { |
| 935 | ipu_dp_exit(ipu); |
| 936 | ipu_dmfc_exit(ipu); |
| 937 | ipu_dc_exit(ipu); |
| 938 | ipu_di_exit(ipu, 1); |
| 939 | ipu_di_exit(ipu, 0); |
| 940 | } |
| 941 | |
| 942 | static int platform_remove_devices_fn(struct device *dev, void *unused) |
| 943 | { |
| 944 | struct platform_device *pdev = to_platform_device(dev); |
| 945 | |
| 946 | platform_device_unregister(pdev); |
| 947 | |
| 948 | return 0; |
| 949 | } |
| 950 | |
| 951 | static void platform_device_unregister_children(struct platform_device *pdev) |
| 952 | { |
| 953 | device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn); |
| 954 | } |
| 955 | |
| 956 | struct ipu_platform_reg { |
| 957 | struct ipu_client_platformdata pdata; |
| 958 | const char *name; |
| 959 | }; |
| 960 | |
| 961 | static const struct ipu_platform_reg client_reg[] = { |
| 962 | { |
| 963 | .pdata = { |
| 964 | .di = 0, |
| 965 | .dc = 5, |
| 966 | .dp = IPU_DP_FLOW_SYNC_BG, |
| 967 | .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC, |
| 968 | .dma[1] = -EINVAL, |
| 969 | }, |
| 970 | .name = "imx-ipuv3-crtc", |
| 971 | }, { |
| 972 | .pdata = { |
| 973 | .di = 1, |
| 974 | .dc = 1, |
| 975 | .dp = -EINVAL, |
| 976 | .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC, |
| 977 | .dma[1] = -EINVAL, |
| 978 | }, |
| 979 | .name = "imx-ipuv3-crtc", |
| 980 | }, |
| 981 | }; |
| 982 | |
| 983 | static int ipu_client_id; |
| 984 | |
| 985 | static int ipu_add_subdevice_pdata(struct device *dev, |
| 986 | const struct ipu_platform_reg *reg) |
| 987 | { |
| 988 | struct platform_device *pdev; |
| 989 | |
| 990 | pdev = platform_device_register_data(dev, reg->name, ipu_client_id++, |
| 991 | ®->pdata, sizeof(struct ipu_platform_reg)); |
| 992 | |
| 993 | return pdev ? 0 : -EINVAL; |
| 994 | } |
| 995 | |
| 996 | static int ipu_add_client_devices(struct ipu_soc *ipu) |
| 997 | { |
| 998 | int ret; |
| 999 | int i; |
| 1000 | |
| 1001 | for (i = 0; i < ARRAY_SIZE(client_reg); i++) { |
| 1002 | const struct ipu_platform_reg *reg = &client_reg[i]; |
| 1003 | ret = ipu_add_subdevice_pdata(ipu->dev, reg); |
| 1004 | if (ret) |
| 1005 | goto err_register; |
| 1006 | } |
| 1007 | |
| 1008 | return 0; |
| 1009 | |
| 1010 | err_register: |
| 1011 | platform_device_unregister_children(to_platform_device(ipu->dev)); |
| 1012 | |
| 1013 | return ret; |
| 1014 | } |
| 1015 | |
Philipp Zabel | b728766 | 2013-06-21 10:27:39 +0200 | [diff] [blame] | 1016 | |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1017 | static int ipu_irq_init(struct ipu_soc *ipu) |
| 1018 | { |
Philipp Zabel | 379cdec | 2013-06-21 14:52:17 +0200 | [diff] [blame] | 1019 | struct irq_chip_generic *gc; |
| 1020 | struct irq_chip_type *ct; |
Philipp Zabel | 37f85b26 | 2013-06-21 14:52:18 +0200 | [diff] [blame] | 1021 | unsigned long unused[IPU_NUM_IRQS / 32] = { |
| 1022 | 0x400100d0, 0xffe000fd, |
| 1023 | 0x400100d0, 0xffe000fd, |
| 1024 | 0x400100d0, 0xffe000fd, |
| 1025 | 0x4077ffff, 0xffe7e1fd, |
| 1026 | 0x23fffffe, 0x8880fff0, |
| 1027 | 0xf98fe7d0, 0xfff81fff, |
| 1028 | 0x400100d0, 0xffe000fd, |
| 1029 | 0x00000000, |
| 1030 | }; |
Philipp Zabel | 379cdec | 2013-06-21 14:52:17 +0200 | [diff] [blame] | 1031 | int ret, i; |
| 1032 | |
Philipp Zabel | b728766 | 2013-06-21 10:27:39 +0200 | [diff] [blame] | 1033 | ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS, |
Philipp Zabel | 379cdec | 2013-06-21 14:52:17 +0200 | [diff] [blame] | 1034 | &irq_generic_chip_ops, ipu); |
Philipp Zabel | b728766 | 2013-06-21 10:27:39 +0200 | [diff] [blame] | 1035 | if (!ipu->domain) { |
| 1036 | dev_err(ipu->dev, "failed to add irq domain\n"); |
| 1037 | return -ENODEV; |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1038 | } |
| 1039 | |
Philipp Zabel | 379cdec | 2013-06-21 14:52:17 +0200 | [diff] [blame] | 1040 | ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU", |
| 1041 | handle_level_irq, 0, IRQF_VALID, 0); |
| 1042 | if (ret < 0) { |
| 1043 | dev_err(ipu->dev, "failed to alloc generic irq chips\n"); |
| 1044 | irq_domain_remove(ipu->domain); |
| 1045 | return ret; |
| 1046 | } |
| 1047 | |
| 1048 | for (i = 0; i < IPU_NUM_IRQS; i += 32) { |
| 1049 | gc = irq_get_domain_generic_chip(ipu->domain, i); |
| 1050 | gc->reg_base = ipu->cm_reg; |
Philipp Zabel | 37f85b26 | 2013-06-21 14:52:18 +0200 | [diff] [blame] | 1051 | gc->unused = unused[i / 32]; |
Philipp Zabel | 379cdec | 2013-06-21 14:52:17 +0200 | [diff] [blame] | 1052 | ct = gc->chip_types; |
| 1053 | ct->chip.irq_ack = irq_gc_ack_set_bit; |
| 1054 | ct->chip.irq_mask = irq_gc_mask_clr_bit; |
| 1055 | ct->chip.irq_unmask = irq_gc_mask_set_bit; |
| 1056 | ct->regs.ack = IPU_INT_STAT(i / 32); |
| 1057 | ct->regs.mask = IPU_INT_CTRL(i / 32); |
| 1058 | } |
| 1059 | |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1060 | irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler); |
| 1061 | irq_set_handler_data(ipu->irq_sync, ipu); |
| 1062 | irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler); |
| 1063 | irq_set_handler_data(ipu->irq_err, ipu); |
| 1064 | |
| 1065 | return 0; |
| 1066 | } |
| 1067 | |
| 1068 | static void ipu_irq_exit(struct ipu_soc *ipu) |
| 1069 | { |
Philipp Zabel | b728766 | 2013-06-21 10:27:39 +0200 | [diff] [blame] | 1070 | int i, irq; |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1071 | |
| 1072 | irq_set_chained_handler(ipu->irq_err, NULL); |
| 1073 | irq_set_handler_data(ipu->irq_err, NULL); |
| 1074 | irq_set_chained_handler(ipu->irq_sync, NULL); |
| 1075 | irq_set_handler_data(ipu->irq_sync, NULL); |
| 1076 | |
Philipp Zabel | 379cdec | 2013-06-21 14:52:17 +0200 | [diff] [blame] | 1077 | /* TODO: remove irq_domain_generic_chips */ |
| 1078 | |
Philipp Zabel | b728766 | 2013-06-21 10:27:39 +0200 | [diff] [blame] | 1079 | for (i = 0; i < IPU_NUM_IRQS; i++) { |
| 1080 | irq = irq_linear_revmap(ipu->domain, i); |
| 1081 | if (irq) |
| 1082 | irq_dispose_mapping(irq); |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1083 | } |
| 1084 | |
Philipp Zabel | b728766 | 2013-06-21 10:27:39 +0200 | [diff] [blame] | 1085 | irq_domain_remove(ipu->domain); |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1086 | } |
| 1087 | |
Bill Pemberton | c4aabf8 | 2012-11-19 13:22:11 -0500 | [diff] [blame] | 1088 | static int ipu_probe(struct platform_device *pdev) |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1089 | { |
| 1090 | const struct of_device_id *of_id = |
| 1091 | of_match_device(imx_ipu_dt_ids, &pdev->dev); |
| 1092 | struct ipu_soc *ipu; |
| 1093 | struct resource *res; |
| 1094 | unsigned long ipu_base; |
| 1095 | int i, ret, irq_sync, irq_err; |
| 1096 | const struct ipu_devtype *devtype; |
| 1097 | |
| 1098 | devtype = of_id->data; |
| 1099 | |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1100 | irq_sync = platform_get_irq(pdev, 0); |
| 1101 | irq_err = platform_get_irq(pdev, 1); |
| 1102 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1103 | |
Fabio Estevam | fd563db | 2012-10-24 21:36:46 -0200 | [diff] [blame] | 1104 | dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n", |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1105 | irq_sync, irq_err); |
| 1106 | |
| 1107 | if (!res || irq_sync < 0 || irq_err < 0) |
| 1108 | return -ENODEV; |
| 1109 | |
| 1110 | ipu_base = res->start; |
| 1111 | |
| 1112 | ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL); |
| 1113 | if (!ipu) |
| 1114 | return -ENODEV; |
| 1115 | |
| 1116 | for (i = 0; i < 64; i++) |
| 1117 | ipu->channel[i].ipu = ipu; |
| 1118 | ipu->devtype = devtype; |
| 1119 | ipu->ipu_type = devtype->type; |
| 1120 | |
| 1121 | spin_lock_init(&ipu->lock); |
| 1122 | mutex_init(&ipu->channel_lock); |
| 1123 | |
Fabio Estevam | fd563db | 2012-10-24 21:36:46 -0200 | [diff] [blame] | 1124 | dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n", |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1125 | ipu_base + devtype->cm_ofs); |
Fabio Estevam | fd563db | 2012-10-24 21:36:46 -0200 | [diff] [blame] | 1126 | dev_dbg(&pdev->dev, "idmac: 0x%08lx\n", |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1127 | ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS); |
Fabio Estevam | fd563db | 2012-10-24 21:36:46 -0200 | [diff] [blame] | 1128 | dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n", |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1129 | ipu_base + devtype->cpmem_ofs); |
Fabio Estevam | fd563db | 2012-10-24 21:36:46 -0200 | [diff] [blame] | 1130 | dev_dbg(&pdev->dev, "disp0: 0x%08lx\n", |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1131 | ipu_base + devtype->disp0_ofs); |
Fabio Estevam | fd563db | 2012-10-24 21:36:46 -0200 | [diff] [blame] | 1132 | dev_dbg(&pdev->dev, "disp1: 0x%08lx\n", |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1133 | ipu_base + devtype->disp1_ofs); |
Fabio Estevam | fd563db | 2012-10-24 21:36:46 -0200 | [diff] [blame] | 1134 | dev_dbg(&pdev->dev, "srm: 0x%08lx\n", |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1135 | ipu_base + devtype->srm_ofs); |
Fabio Estevam | fd563db | 2012-10-24 21:36:46 -0200 | [diff] [blame] | 1136 | dev_dbg(&pdev->dev, "tpm: 0x%08lx\n", |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1137 | ipu_base + devtype->tpm_ofs); |
Fabio Estevam | fd563db | 2012-10-24 21:36:46 -0200 | [diff] [blame] | 1138 | dev_dbg(&pdev->dev, "dc: 0x%08lx\n", |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1139 | ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS); |
Fabio Estevam | fd563db | 2012-10-24 21:36:46 -0200 | [diff] [blame] | 1140 | dev_dbg(&pdev->dev, "ic: 0x%08lx\n", |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1141 | ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS); |
Fabio Estevam | fd563db | 2012-10-24 21:36:46 -0200 | [diff] [blame] | 1142 | dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n", |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1143 | ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS); |
Fabio Estevam | fd563db | 2012-10-24 21:36:46 -0200 | [diff] [blame] | 1144 | dev_dbg(&pdev->dev, "vdi: 0x%08lx\n", |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1145 | ipu_base + devtype->vdi_ofs); |
| 1146 | |
| 1147 | ipu->cm_reg = devm_ioremap(&pdev->dev, |
| 1148 | ipu_base + devtype->cm_ofs, PAGE_SIZE); |
| 1149 | ipu->idmac_reg = devm_ioremap(&pdev->dev, |
| 1150 | ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS, |
| 1151 | PAGE_SIZE); |
| 1152 | ipu->cpmem_base = devm_ioremap(&pdev->dev, |
| 1153 | ipu_base + devtype->cpmem_ofs, PAGE_SIZE); |
| 1154 | |
Fabio Estevam | be798b2 | 2013-07-20 18:22:09 -0300 | [diff] [blame] | 1155 | if (!ipu->cm_reg || !ipu->idmac_reg || !ipu->cpmem_base) |
| 1156 | return -ENOMEM; |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1157 | |
| 1158 | ipu->clk = devm_clk_get(&pdev->dev, "bus"); |
| 1159 | if (IS_ERR(ipu->clk)) { |
| 1160 | ret = PTR_ERR(ipu->clk); |
| 1161 | dev_err(&pdev->dev, "clk_get failed with %d", ret); |
Fabio Estevam | be798b2 | 2013-07-20 18:22:09 -0300 | [diff] [blame] | 1162 | return ret; |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1163 | } |
| 1164 | |
| 1165 | platform_set_drvdata(pdev, ipu); |
| 1166 | |
Fabio Estevam | 62645a2 | 2013-07-20 18:22:10 -0300 | [diff] [blame] | 1167 | ret = clk_prepare_enable(ipu->clk); |
| 1168 | if (ret) { |
| 1169 | dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); |
| 1170 | return ret; |
| 1171 | } |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1172 | |
| 1173 | ipu->dev = &pdev->dev; |
| 1174 | ipu->irq_sync = irq_sync; |
| 1175 | ipu->irq_err = irq_err; |
| 1176 | |
| 1177 | ret = ipu_irq_init(ipu); |
| 1178 | if (ret) |
| 1179 | goto out_failed_irq; |
| 1180 | |
Philipp Zabel | 6c64155 | 2013-03-28 17:35:21 +0100 | [diff] [blame] | 1181 | ret = device_reset(&pdev->dev); |
| 1182 | if (ret) { |
| 1183 | dev_err(&pdev->dev, "failed to reset: %d\n", ret); |
| 1184 | goto out_failed_reset; |
| 1185 | } |
| 1186 | ret = ipu_memory_reset(ipu); |
Lothar Waßmann | 4d27b2c | 2012-12-25 15:58:37 +0100 | [diff] [blame] | 1187 | if (ret) |
| 1188 | goto out_failed_reset; |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1189 | |
| 1190 | /* Set MCU_T to divide MCU access window into 2 */ |
| 1191 | ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), |
| 1192 | IPU_DISP_GEN); |
| 1193 | |
| 1194 | ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk); |
| 1195 | if (ret) |
| 1196 | goto failed_submodules_init; |
| 1197 | |
| 1198 | ret = ipu_add_client_devices(ipu); |
| 1199 | if (ret) { |
| 1200 | dev_err(&pdev->dev, "adding client devices failed with %d\n", |
| 1201 | ret); |
| 1202 | goto failed_add_clients; |
| 1203 | } |
| 1204 | |
Fabio Estevam | 9c2c438 | 2012-10-24 21:36:47 -0200 | [diff] [blame] | 1205 | dev_info(&pdev->dev, "%s probed\n", devtype->name); |
| 1206 | |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1207 | return 0; |
| 1208 | |
| 1209 | failed_add_clients: |
| 1210 | ipu_submodules_exit(ipu); |
| 1211 | failed_submodules_init: |
Lothar Waßmann | 4d27b2c | 2012-12-25 15:58:37 +0100 | [diff] [blame] | 1212 | out_failed_reset: |
Philipp Zabel | 6c64155 | 2013-03-28 17:35:21 +0100 | [diff] [blame] | 1213 | ipu_irq_exit(ipu); |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1214 | out_failed_irq: |
| 1215 | clk_disable_unprepare(ipu->clk); |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1216 | return ret; |
| 1217 | } |
| 1218 | |
Bill Pemberton | 8aa1be4 | 2012-11-19 13:26:38 -0500 | [diff] [blame] | 1219 | static int ipu_remove(struct platform_device *pdev) |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1220 | { |
| 1221 | struct ipu_soc *ipu = platform_get_drvdata(pdev); |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1222 | |
| 1223 | platform_device_unregister_children(pdev); |
| 1224 | ipu_submodules_exit(ipu); |
| 1225 | ipu_irq_exit(ipu); |
| 1226 | |
| 1227 | clk_disable_unprepare(ipu->clk); |
| 1228 | |
| 1229 | return 0; |
| 1230 | } |
| 1231 | |
| 1232 | static struct platform_driver imx_ipu_driver = { |
| 1233 | .driver = { |
| 1234 | .name = "imx-ipuv3", |
| 1235 | .of_match_table = imx_ipu_dt_ids, |
| 1236 | }, |
| 1237 | .probe = ipu_probe, |
Bill Pemberton | 99c28f1 | 2012-11-19 13:20:51 -0500 | [diff] [blame] | 1238 | .remove = ipu_remove, |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1239 | }; |
| 1240 | |
| 1241 | module_platform_driver(imx_ipu_driver); |
| 1242 | |
Fabio Estevam | 10f2268 | 2013-07-20 18:22:11 -0300 | [diff] [blame] | 1243 | MODULE_ALIAS("platform:imx-ipuv3"); |
Sascha Hauer | aecfbdb | 2012-09-21 10:07:49 +0200 | [diff] [blame] | 1244 | MODULE_DESCRIPTION("i.MX IPU v3 driver"); |
| 1245 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |
| 1246 | MODULE_LICENSE("GPL"); |