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Lennert Buytenhekabc848c2008-03-27 14:51:39 -04001/*
2 * Marvell MBUS common definitions.
3 *
4 * Copyright (C) 2008 Marvell Semiconductor
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __LINUX_MBUS_H
12#define __LINUX_MBUS_H
13
Ezequiel Garcia79d94682013-07-26 10:17:47 -030014struct resource;
15
Lennert Buytenhekabc848c2008-03-27 14:51:39 -040016struct mbus_dram_target_info
17{
18 /*
19 * The 4-bit MBUS target ID of the DRAM controller.
20 */
21 u8 mbus_dram_target_id;
22
23 /*
24 * The base address, size, and MBUS attribute ID for each
25 * of the possible DRAM chip selects. Peripherals are
26 * required to support at least 4 decode windows.
27 */
28 int num_cs;
29 struct mbus_dram_window {
30 u8 cs_index;
31 u8 mbus_attr;
32 u32 base;
33 u32 size;
34 } cs[4];
35};
36
Thomas Petazzonifddddb52013-03-21 17:59:14 +010037/* Flags for PCI/PCIe address decoding regions */
38#define MVEBU_MBUS_PCI_IO 0x1
39#define MVEBU_MBUS_PCI_MEM 0x2
40#define MVEBU_MBUS_PCI_WA 0x3
41
42/*
43 * Magic value that explicits that we don't need a remapping-capable
44 * address decoding window.
45 */
46#define MVEBU_MBUS_NO_REMAP (0xffffffff)
47
Thomas Petazzoni95b80e02013-03-21 17:59:19 +010048/* Maximum size of a mbus window name */
49#define MVEBU_MBUS_MAX_WINNAME_SZ 32
50
Andrew Lunn63a93322011-12-07 21:48:07 +010051/*
52 * The Marvell mbus is to be found only on SOCs from the Orion family
53 * at the moment. Provide a dummy stub for other architectures.
54 */
55#ifdef CONFIG_PLAT_ORION
56extern const struct mbus_dram_target_info *mv_mbus_dram_info(void);
Thomas Petazzonibfa1ce52015-05-28 11:40:54 +020057extern const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void);
Andrew Lunn63a93322011-12-07 21:48:07 +010058#else
59static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
60{
61 return NULL;
62}
Thomas Petazzonibfa1ce52015-05-28 11:40:54 +020063static inline const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
64{
65 return NULL;
66}
Andrew Lunn63a93322011-12-07 21:48:07 +010067#endif
Thomas Petazzonifddddb52013-03-21 17:59:14 +010068
Thomas Petazzoni4749c022014-11-21 17:00:04 +010069int mvebu_mbus_save_cpu_target(u32 *store_addr);
Ezequiel Garcia79d94682013-07-26 10:17:47 -030070void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
71void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
Marcin Wojtasf2900ac2016-03-14 09:39:02 +010072int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr);
73int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
74 u8 *attr);
Thomas Petazzoni6a63b092013-07-26 10:17:39 -030075int mvebu_mbus_add_window_remap_by_id(unsigned int target,
76 unsigned int attribute,
77 phys_addr_t base, size_t size,
78 phys_addr_t remap);
Thomas Petazzoni6a63b092013-07-26 10:17:39 -030079int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
80 phys_addr_t base, size_t size);
Thomas Petazzonifddddb52013-03-21 17:59:14 +010081int mvebu_mbus_del_window(phys_addr_t base, size_t size);
82int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
83 size_t mbus_size, phys_addr_t sdram_phys_base,
84 size_t sdram_size);
Thomas Petazzoni5686a1e2014-04-14 15:47:01 +020085int mvebu_mbus_dt_init(bool is_coherent);
Thomas Petazzonifddddb52013-03-21 17:59:14 +010086
87#endif /* __LINUX_MBUS_H */