Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Ethernet driver for the Atmel AT91RM9200 (Thunder) |
| 3 | * |
| 4 | * Copyright (C) 2003 SAN People (Pty) Ltd |
| 5 | * |
| 6 | * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc. |
| 7 | * Initial version by Rick Bronson 01/11/2003 |
| 8 | * |
| 9 | * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker |
| 10 | * (Polaroid Corporation) |
| 11 | * |
| 12 | * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru> |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or |
| 15 | * modify it under the terms of the GNU General Public License |
| 16 | * as published by the Free Software Foundation; either version |
| 17 | * 2 of the License, or (at your option) any later version. |
| 18 | */ |
| 19 | |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/init.h> |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 22 | #include <linux/mii.h> |
| 23 | #include <linux/netdevice.h> |
| 24 | #include <linux/etherdevice.h> |
| 25 | #include <linux/skbuff.h> |
| 26 | #include <linux/dma-mapping.h> |
| 27 | #include <linux/ethtool.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/clk.h> |
| 30 | |
| 31 | #include <asm/io.h> |
| 32 | #include <asm/uaccess.h> |
| 33 | #include <asm/mach-types.h> |
| 34 | |
| 35 | #include <asm/arch/at91rm9200_emac.h> |
| 36 | #include <asm/arch/gpio.h> |
| 37 | #include <asm/arch/board.h> |
| 38 | |
| 39 | #include "at91_ether.h" |
| 40 | |
| 41 | #define DRV_NAME "at91_ether" |
| 42 | #define DRV_VERSION "1.0" |
| 43 | |
| 44 | static struct net_device *at91_dev; |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 45 | |
Andrew Victor | 775637d | 2006-06-20 11:50:23 +0200 | [diff] [blame] | 46 | static struct timer_list check_timer; |
| 47 | #define LINK_POLL_INTERVAL (HZ) |
| 48 | |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 49 | /* ..................................................................... */ |
| 50 | |
| 51 | /* |
| 52 | * Read from a EMAC register. |
| 53 | */ |
| 54 | static inline unsigned long at91_emac_read(unsigned int reg) |
| 55 | { |
| 56 | void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC; |
| 57 | |
| 58 | return __raw_readl(emac_base + reg); |
| 59 | } |
| 60 | |
| 61 | /* |
| 62 | * Write to a EMAC register. |
| 63 | */ |
| 64 | static inline void at91_emac_write(unsigned int reg, unsigned long value) |
| 65 | { |
| 66 | void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC; |
| 67 | |
| 68 | __raw_writel(value, emac_base + reg); |
| 69 | } |
| 70 | |
| 71 | /* ........................... PHY INTERFACE ........................... */ |
| 72 | |
| 73 | /* |
| 74 | * Enable the MDIO bit in MAC control register |
| 75 | * When not called from an interrupt-handler, access to the PHY must be |
| 76 | * protected by a spinlock. |
| 77 | */ |
| 78 | static void enable_mdi(void) |
| 79 | { |
| 80 | unsigned long ctl; |
| 81 | |
| 82 | ctl = at91_emac_read(AT91_EMAC_CTL); |
| 83 | at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */ |
| 84 | } |
| 85 | |
| 86 | /* |
| 87 | * Disable the MDIO bit in the MAC control register |
| 88 | */ |
| 89 | static void disable_mdi(void) |
| 90 | { |
| 91 | unsigned long ctl; |
| 92 | |
| 93 | ctl = at91_emac_read(AT91_EMAC_CTL); |
| 94 | at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */ |
| 95 | } |
| 96 | |
| 97 | /* |
| 98 | * Wait until the PHY operation is complete. |
| 99 | */ |
| 100 | static inline void at91_phy_wait(void) { |
| 101 | unsigned long timeout = jiffies + 2; |
| 102 | |
| 103 | while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) { |
| 104 | if (time_after(jiffies, timeout)) { |
| 105 | printk("at91_ether: MIO timeout\n"); |
| 106 | break; |
| 107 | } |
| 108 | cpu_relax(); |
| 109 | } |
| 110 | } |
| 111 | |
| 112 | /* |
| 113 | * Write value to the a PHY register |
| 114 | * Note: MDI interface is assumed to already have been enabled. |
| 115 | */ |
| 116 | static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value) |
| 117 | { |
| 118 | at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W |
| 119 | | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA)); |
| 120 | |
| 121 | /* Wait until IDLE bit in Network Status register is cleared */ |
| 122 | at91_phy_wait(); |
| 123 | } |
| 124 | |
| 125 | /* |
| 126 | * Read value stored in a PHY register. |
| 127 | * Note: MDI interface is assumed to already have been enabled. |
| 128 | */ |
| 129 | static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value) |
| 130 | { |
| 131 | at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R |
| 132 | | ((phy_addr & 0x1f) << 23) | (address << 18)); |
| 133 | |
| 134 | /* Wait until IDLE bit in Network Status register is cleared */ |
| 135 | at91_phy_wait(); |
| 136 | |
| 137 | *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA; |
| 138 | } |
| 139 | |
| 140 | /* ........................... PHY MANAGEMENT .......................... */ |
| 141 | |
| 142 | /* |
| 143 | * Access the PHY to determine the current link speed and mode, and update the |
| 144 | * MAC accordingly. |
| 145 | * If no link or auto-negotiation is busy, then no changes are made. |
| 146 | */ |
Andrew Victor | 775637d | 2006-06-20 11:50:23 +0200 | [diff] [blame] | 147 | static void update_linkspeed(struct net_device *dev, int silent) |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 148 | { |
| 149 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 150 | unsigned int bmsr, bmcr, lpa, mac_cfg; |
| 151 | unsigned int speed, duplex; |
| 152 | |
| 153 | if (!mii_link_ok(&lp->mii)) { /* no link */ |
| 154 | netif_carrier_off(dev); |
Andrew Victor | 775637d | 2006-06-20 11:50:23 +0200 | [diff] [blame] | 155 | if (!silent) |
| 156 | printk(KERN_INFO "%s: Link down.\n", dev->name); |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 157 | return; |
| 158 | } |
| 159 | |
| 160 | /* Link up, or auto-negotiation still in progress */ |
| 161 | read_phy(lp->phy_address, MII_BMSR, &bmsr); |
| 162 | read_phy(lp->phy_address, MII_BMCR, &bmcr); |
| 163 | if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */ |
| 164 | if (!(bmsr & BMSR_ANEGCOMPLETE)) |
| 165 | return; /* Do nothing - another interrupt generated when negotiation complete */ |
| 166 | |
| 167 | read_phy(lp->phy_address, MII_LPA, &lpa); |
| 168 | if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100; |
| 169 | else speed = SPEED_10; |
| 170 | if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL; |
| 171 | else duplex = DUPLEX_HALF; |
| 172 | } else { |
| 173 | speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; |
| 174 | duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; |
| 175 | } |
| 176 | |
| 177 | /* Update the MAC */ |
| 178 | mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD); |
| 179 | if (speed == SPEED_100) { |
| 180 | if (duplex == DUPLEX_FULL) /* 100 Full Duplex */ |
| 181 | mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD; |
| 182 | else /* 100 Half Duplex */ |
| 183 | mac_cfg |= AT91_EMAC_SPD; |
| 184 | } else { |
| 185 | if (duplex == DUPLEX_FULL) /* 10 Full Duplex */ |
| 186 | mac_cfg |= AT91_EMAC_FD; |
| 187 | else {} /* 10 Half Duplex */ |
| 188 | } |
| 189 | at91_emac_write(AT91_EMAC_CFG, mac_cfg); |
| 190 | |
Andrew Victor | 775637d | 2006-06-20 11:50:23 +0200 | [diff] [blame] | 191 | if (!silent) |
| 192 | printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex"); |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 193 | netif_carrier_on(dev); |
| 194 | } |
| 195 | |
| 196 | /* |
| 197 | * Handle interrupts from the PHY |
| 198 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame^] | 199 | static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id) |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 200 | { |
| 201 | struct net_device *dev = (struct net_device *) dev_id; |
| 202 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 203 | unsigned int phy; |
| 204 | |
| 205 | /* |
| 206 | * This hander is triggered on both edges, but the PHY chips expect |
| 207 | * level-triggering. We therefore have to check if the PHY actually has |
| 208 | * an IRQ pending. |
| 209 | */ |
| 210 | enable_mdi(); |
| 211 | if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { |
| 212 | read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */ |
| 213 | if (!(phy & (1 << 0))) |
| 214 | goto done; |
| 215 | } |
| 216 | else if (lp->phy_type == MII_LXT971A_ID) { |
| 217 | read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */ |
| 218 | if (!(phy & (1 << 2))) |
| 219 | goto done; |
| 220 | } |
| 221 | else if (lp->phy_type == MII_BCM5221_ID) { |
| 222 | read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */ |
| 223 | if (!(phy & (1 << 0))) |
| 224 | goto done; |
| 225 | } |
| 226 | else if (lp->phy_type == MII_KS8721_ID) { |
| 227 | read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */ |
| 228 | if (!(phy & ((1 << 2) | 1))) |
| 229 | goto done; |
| 230 | } |
| 231 | |
Andrew Victor | 775637d | 2006-06-20 11:50:23 +0200 | [diff] [blame] | 232 | update_linkspeed(dev, 0); |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 233 | |
| 234 | done: |
| 235 | disable_mdi(); |
| 236 | |
| 237 | return IRQ_HANDLED; |
| 238 | } |
| 239 | |
| 240 | /* |
| 241 | * Initialize and enable the PHY interrupt for link-state changes |
| 242 | */ |
| 243 | static void enable_phyirq(struct net_device *dev) |
| 244 | { |
| 245 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 246 | unsigned int dsintr, irq_number; |
| 247 | int status; |
| 248 | |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 249 | irq_number = lp->board_data.phy_irq_pin; |
Andrew Victor | 775637d | 2006-06-20 11:50:23 +0200 | [diff] [blame] | 250 | if (!irq_number) { |
| 251 | /* |
| 252 | * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L), |
| 253 | * or board does not have it connected. |
| 254 | */ |
| 255 | check_timer.expires = jiffies + LINK_POLL_INTERVAL; |
| 256 | add_timer(&check_timer); |
| 257 | return; |
| 258 | } |
| 259 | |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 260 | status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev); |
| 261 | if (status) { |
| 262 | printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status); |
| 263 | return; |
| 264 | } |
| 265 | |
| 266 | spin_lock_irq(&lp->lock); |
| 267 | enable_mdi(); |
| 268 | |
| 269 | if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ |
| 270 | read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); |
| 271 | dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ |
| 272 | write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); |
| 273 | } |
| 274 | else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ |
| 275 | read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); |
| 276 | dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */ |
| 277 | write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); |
| 278 | } |
| 279 | else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ |
| 280 | dsintr = (1 << 15) | ( 1 << 14); |
| 281 | write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); |
| 282 | } |
| 283 | else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ |
| 284 | dsintr = (1 << 10) | ( 1 << 8); |
| 285 | write_phy(lp->phy_address, MII_TPISTATUS, dsintr); |
| 286 | } |
| 287 | |
| 288 | disable_mdi(); |
| 289 | spin_unlock_irq(&lp->lock); |
| 290 | } |
| 291 | |
| 292 | /* |
| 293 | * Disable the PHY interrupt |
| 294 | */ |
| 295 | static void disable_phyirq(struct net_device *dev) |
| 296 | { |
| 297 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 298 | unsigned int dsintr; |
| 299 | unsigned int irq_number; |
| 300 | |
Andrew Victor | 775637d | 2006-06-20 11:50:23 +0200 | [diff] [blame] | 301 | irq_number = lp->board_data.phy_irq_pin; |
| 302 | if (!irq_number) { |
| 303 | del_timer_sync(&check_timer); |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 304 | return; |
Andrew Victor | 775637d | 2006-06-20 11:50:23 +0200 | [diff] [blame] | 305 | } |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 306 | |
| 307 | spin_lock_irq(&lp->lock); |
| 308 | enable_mdi(); |
| 309 | |
| 310 | if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ |
| 311 | read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); |
| 312 | dsintr = dsintr | 0xf00; /* set bits 8..11 */ |
| 313 | write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); |
| 314 | } |
| 315 | else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ |
| 316 | read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); |
| 317 | dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */ |
| 318 | write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); |
| 319 | } |
| 320 | else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ |
| 321 | read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr); |
| 322 | dsintr = ~(1 << 14); |
| 323 | write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); |
| 324 | } |
| 325 | else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ |
| 326 | read_phy(lp->phy_address, MII_TPISTATUS, &dsintr); |
| 327 | dsintr = ~((1 << 10) | (1 << 8)); |
| 328 | write_phy(lp->phy_address, MII_TPISTATUS, dsintr); |
| 329 | } |
| 330 | |
| 331 | disable_mdi(); |
| 332 | spin_unlock_irq(&lp->lock); |
| 333 | |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 334 | free_irq(irq_number, dev); /* Free interrupt handler */ |
| 335 | } |
| 336 | |
| 337 | /* |
| 338 | * Perform a software reset of the PHY. |
| 339 | */ |
| 340 | #if 0 |
| 341 | static void reset_phy(struct net_device *dev) |
| 342 | { |
| 343 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 344 | unsigned int bmcr; |
| 345 | |
| 346 | spin_lock_irq(&lp->lock); |
| 347 | enable_mdi(); |
| 348 | |
| 349 | /* Perform PHY reset */ |
| 350 | write_phy(lp->phy_address, MII_BMCR, BMCR_RESET); |
| 351 | |
| 352 | /* Wait until PHY reset is complete */ |
| 353 | do { |
| 354 | read_phy(lp->phy_address, MII_BMCR, &bmcr); |
| 355 | } while (!(bmcr && BMCR_RESET)); |
| 356 | |
| 357 | disable_mdi(); |
| 358 | spin_unlock_irq(&lp->lock); |
| 359 | } |
| 360 | #endif |
| 361 | |
Andrew Victor | 775637d | 2006-06-20 11:50:23 +0200 | [diff] [blame] | 362 | static void at91ether_check_link(unsigned long dev_id) |
| 363 | { |
| 364 | struct net_device *dev = (struct net_device *) dev_id; |
| 365 | |
| 366 | enable_mdi(); |
| 367 | update_linkspeed(dev, 1); |
| 368 | disable_mdi(); |
| 369 | |
| 370 | check_timer.expires = jiffies + LINK_POLL_INTERVAL; |
| 371 | add_timer(&check_timer); |
| 372 | } |
| 373 | |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 374 | /* ......................... ADDRESS MANAGEMENT ........................ */ |
| 375 | |
| 376 | /* |
| 377 | * NOTE: Your bootloader must always set the MAC address correctly before |
| 378 | * booting into Linux. |
| 379 | * |
| 380 | * - It must always set the MAC address after reset, even if it doesn't |
| 381 | * happen to access the Ethernet while it's booting. Some versions of |
| 382 | * U-Boot on the AT91RM9200-DK do not do this. |
| 383 | * |
| 384 | * - Likewise it must store the addresses in the correct byte order. |
| 385 | * MicroMonitor (uMon) on the CSB337 does this incorrectly (and |
| 386 | * continues to do so, for bug-compatibility). |
| 387 | */ |
| 388 | |
| 389 | static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo) |
| 390 | { |
| 391 | char addr[6]; |
| 392 | |
| 393 | if (machine_is_csb337()) { |
| 394 | addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */ |
| 395 | addr[4] = (lo & 0xff00) >> 8; |
| 396 | addr[3] = (lo & 0xff0000) >> 16; |
| 397 | addr[2] = (lo & 0xff000000) >> 24; |
| 398 | addr[1] = (hi & 0xff); |
| 399 | addr[0] = (hi & 0xff00) >> 8; |
| 400 | } |
| 401 | else { |
| 402 | addr[0] = (lo & 0xff); |
| 403 | addr[1] = (lo & 0xff00) >> 8; |
| 404 | addr[2] = (lo & 0xff0000) >> 16; |
| 405 | addr[3] = (lo & 0xff000000) >> 24; |
| 406 | addr[4] = (hi & 0xff); |
| 407 | addr[5] = (hi & 0xff00) >> 8; |
| 408 | } |
| 409 | |
| 410 | if (is_valid_ether_addr(addr)) { |
| 411 | memcpy(dev->dev_addr, &addr, 6); |
| 412 | return 1; |
| 413 | } |
| 414 | return 0; |
| 415 | } |
| 416 | |
| 417 | /* |
| 418 | * Set the ethernet MAC address in dev->dev_addr |
| 419 | */ |
| 420 | static void __init get_mac_address(struct net_device *dev) |
| 421 | { |
| 422 | /* Check Specific-Address 1 */ |
| 423 | if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L))) |
| 424 | return; |
| 425 | /* Check Specific-Address 2 */ |
| 426 | if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L))) |
| 427 | return; |
| 428 | /* Check Specific-Address 3 */ |
| 429 | if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L))) |
| 430 | return; |
| 431 | /* Check Specific-Address 4 */ |
| 432 | if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L))) |
| 433 | return; |
| 434 | |
| 435 | printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n"); |
| 436 | } |
| 437 | |
| 438 | /* |
| 439 | * Program the hardware MAC address from dev->dev_addr. |
| 440 | */ |
| 441 | static void update_mac_address(struct net_device *dev) |
| 442 | { |
| 443 | at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0])); |
| 444 | at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4])); |
| 445 | |
| 446 | at91_emac_write(AT91_EMAC_SA2L, 0); |
| 447 | at91_emac_write(AT91_EMAC_SA2H, 0); |
| 448 | } |
| 449 | |
| 450 | /* |
| 451 | * Store the new hardware address in dev->dev_addr, and update the MAC. |
| 452 | */ |
| 453 | static int set_mac_address(struct net_device *dev, void* addr) |
| 454 | { |
| 455 | struct sockaddr *address = addr; |
| 456 | |
| 457 | if (!is_valid_ether_addr(address->sa_data)) |
| 458 | return -EADDRNOTAVAIL; |
| 459 | |
| 460 | memcpy(dev->dev_addr, address->sa_data, dev->addr_len); |
| 461 | update_mac_address(dev); |
| 462 | |
| 463 | printk("%s: Setting MAC address to %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name, |
| 464 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], |
| 465 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); |
| 466 | |
| 467 | return 0; |
| 468 | } |
| 469 | |
| 470 | static int inline hash_bit_value(int bitnr, __u8 *addr) |
| 471 | { |
| 472 | if (addr[bitnr / 8] & (1 << (bitnr % 8))) |
| 473 | return 1; |
| 474 | return 0; |
| 475 | } |
| 476 | |
| 477 | /* |
| 478 | * The hash address register is 64 bits long and takes up two locations in the memory map. |
| 479 | * The least significant bits are stored in EMAC_HSL and the most significant |
| 480 | * bits in EMAC_HSH. |
| 481 | * |
| 482 | * The unicast hash enable and the multicast hash enable bits in the network configuration |
| 483 | * register enable the reception of hash matched frames. The destination address is |
| 484 | * reduced to a 6 bit index into the 64 bit hash register using the following hash function. |
| 485 | * The hash function is an exclusive or of every sixth bit of the destination address. |
| 486 | * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] |
| 487 | * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] |
| 488 | * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] |
| 489 | * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] |
| 490 | * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] |
| 491 | * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] |
| 492 | * da[0] represents the least significant bit of the first byte received, that is, the multicast/ |
| 493 | * unicast indicator, and da[47] represents the most significant bit of the last byte |
| 494 | * received. |
| 495 | * If the hash index points to a bit that is set in the hash register then the frame will be |
| 496 | * matched according to whether the frame is multicast or unicast. |
| 497 | * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and |
| 498 | * the hash index points to a bit set in the hash register. |
| 499 | * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the |
| 500 | * hash index points to a bit set in the hash register. |
| 501 | * To receive all multicast frames, the hash register should be set with all ones and the |
| 502 | * multicast hash enable bit should be set in the network configuration register. |
| 503 | */ |
| 504 | |
| 505 | /* |
| 506 | * Return the hash index value for the specified address. |
| 507 | */ |
| 508 | static int hash_get_index(__u8 *addr) |
| 509 | { |
| 510 | int i, j, bitval; |
| 511 | int hash_index = 0; |
| 512 | |
| 513 | for (j = 0; j < 6; j++) { |
| 514 | for (i = 0, bitval = 0; i < 8; i++) |
| 515 | bitval ^= hash_bit_value(i*6 + j, addr); |
| 516 | |
| 517 | hash_index |= (bitval << j); |
| 518 | } |
| 519 | |
Andrew Victor | 427d269 | 2006-06-20 12:10:57 +0200 | [diff] [blame] | 520 | return hash_index; |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 521 | } |
| 522 | |
| 523 | /* |
| 524 | * Add multicast addresses to the internal multicast-hash table. |
| 525 | */ |
| 526 | static void at91ether_sethashtable(struct net_device *dev) |
| 527 | { |
| 528 | struct dev_mc_list *curr; |
| 529 | unsigned long mc_filter[2]; |
| 530 | unsigned int i, bitnr; |
| 531 | |
| 532 | mc_filter[0] = mc_filter[1] = 0; |
| 533 | |
| 534 | curr = dev->mc_list; |
| 535 | for (i = 0; i < dev->mc_count; i++, curr = curr->next) { |
| 536 | if (!curr) break; /* unexpected end of list */ |
| 537 | |
| 538 | bitnr = hash_get_index(curr->dmi_addr); |
| 539 | mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); |
| 540 | } |
| 541 | |
| 542 | at91_emac_write(AT91_EMAC_HSH, mc_filter[0]); |
| 543 | at91_emac_write(AT91_EMAC_HSL, mc_filter[1]); |
| 544 | } |
| 545 | |
| 546 | /* |
| 547 | * Enable/Disable promiscuous and multicast modes. |
| 548 | */ |
| 549 | static void at91ether_set_rx_mode(struct net_device *dev) |
| 550 | { |
| 551 | unsigned long cfg; |
| 552 | |
| 553 | cfg = at91_emac_read(AT91_EMAC_CFG); |
| 554 | |
| 555 | if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */ |
| 556 | cfg |= AT91_EMAC_CAF; |
| 557 | else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */ |
| 558 | cfg &= ~AT91_EMAC_CAF; |
| 559 | |
| 560 | if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */ |
| 561 | at91_emac_write(AT91_EMAC_HSH, -1); |
| 562 | at91_emac_write(AT91_EMAC_HSL, -1); |
| 563 | cfg |= AT91_EMAC_MTI; |
| 564 | } else if (dev->mc_count > 0) { /* Enable specific multicasts */ |
| 565 | at91ether_sethashtable(dev); |
| 566 | cfg |= AT91_EMAC_MTI; |
| 567 | } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */ |
| 568 | at91_emac_write(AT91_EMAC_HSH, 0); |
| 569 | at91_emac_write(AT91_EMAC_HSL, 0); |
| 570 | cfg &= ~AT91_EMAC_MTI; |
| 571 | } |
| 572 | |
| 573 | at91_emac_write(AT91_EMAC_CFG, cfg); |
| 574 | } |
| 575 | |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 576 | /* ......................... ETHTOOL SUPPORT ........................... */ |
| 577 | |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 578 | static int mdio_read(struct net_device *dev, int phy_id, int location) |
| 579 | { |
| 580 | unsigned int value; |
| 581 | |
| 582 | read_phy(phy_id, location, &value); |
| 583 | return value; |
| 584 | } |
| 585 | |
| 586 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value) |
| 587 | { |
| 588 | write_phy(phy_id, location, value); |
| 589 | } |
| 590 | |
| 591 | static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 592 | { |
| 593 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 594 | int ret; |
| 595 | |
| 596 | spin_lock_irq(&lp->lock); |
| 597 | enable_mdi(); |
| 598 | |
| 599 | ret = mii_ethtool_gset(&lp->mii, cmd); |
| 600 | |
| 601 | disable_mdi(); |
| 602 | spin_unlock_irq(&lp->lock); |
| 603 | |
| 604 | if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */ |
| 605 | cmd->supported = SUPPORTED_FIBRE; |
| 606 | cmd->port = PORT_FIBRE; |
| 607 | } |
| 608 | |
| 609 | return ret; |
| 610 | } |
| 611 | |
| 612 | static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
| 613 | { |
| 614 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 615 | int ret; |
| 616 | |
| 617 | spin_lock_irq(&lp->lock); |
| 618 | enable_mdi(); |
| 619 | |
| 620 | ret = mii_ethtool_sset(&lp->mii, cmd); |
| 621 | |
| 622 | disable_mdi(); |
| 623 | spin_unlock_irq(&lp->lock); |
| 624 | |
| 625 | return ret; |
| 626 | } |
| 627 | |
| 628 | static int at91ether_nwayreset(struct net_device *dev) |
| 629 | { |
| 630 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 631 | int ret; |
| 632 | |
| 633 | spin_lock_irq(&lp->lock); |
| 634 | enable_mdi(); |
| 635 | |
| 636 | ret = mii_nway_restart(&lp->mii); |
| 637 | |
| 638 | disable_mdi(); |
| 639 | spin_unlock_irq(&lp->lock); |
| 640 | |
| 641 | return ret; |
| 642 | } |
| 643 | |
| 644 | static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
| 645 | { |
| 646 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
| 647 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); |
| 648 | strlcpy(info->bus_info, dev->class_dev.dev->bus_id, sizeof(info->bus_info)); |
| 649 | } |
| 650 | |
Jeff Garzik | 7282d49 | 2006-09-13 14:30:00 -0400 | [diff] [blame] | 651 | static const struct ethtool_ops at91ether_ethtool_ops = { |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 652 | .get_settings = at91ether_get_settings, |
| 653 | .set_settings = at91ether_set_settings, |
| 654 | .get_drvinfo = at91ether_get_drvinfo, |
| 655 | .nway_reset = at91ether_nwayreset, |
| 656 | .get_link = ethtool_op_get_link, |
| 657 | }; |
| 658 | |
Andrew Victor | ca5585e | 2006-06-20 11:59:05 +0200 | [diff] [blame] | 659 | static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
| 660 | { |
| 661 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 662 | int res; |
| 663 | |
| 664 | if (!netif_running(dev)) |
| 665 | return -EINVAL; |
| 666 | |
| 667 | spin_lock_irq(&lp->lock); |
| 668 | enable_mdi(); |
| 669 | res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL); |
| 670 | disable_mdi(); |
| 671 | spin_unlock_irq(&lp->lock); |
| 672 | |
| 673 | return res; |
| 674 | } |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 675 | |
| 676 | /* ................................ MAC ................................ */ |
| 677 | |
| 678 | /* |
| 679 | * Initialize and start the Receiver and Transmit subsystems |
| 680 | */ |
| 681 | static void at91ether_start(struct net_device *dev) |
| 682 | { |
| 683 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 684 | struct recv_desc_bufs *dlist, *dlist_phys; |
| 685 | int i; |
| 686 | unsigned long ctl; |
| 687 | |
| 688 | dlist = lp->dlist; |
| 689 | dlist_phys = lp->dlist_phys; |
| 690 | |
| 691 | for (i = 0; i < MAX_RX_DESCR; i++) { |
| 692 | dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0]; |
| 693 | dlist->descriptors[i].size = 0; |
| 694 | } |
| 695 | |
| 696 | /* Set the Wrap bit on the last descriptor */ |
| 697 | dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP; |
| 698 | |
| 699 | /* Reset buffer index */ |
| 700 | lp->rxBuffIndex = 0; |
| 701 | |
| 702 | /* Program address of descriptor list in Rx Buffer Queue register */ |
| 703 | at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys); |
| 704 | |
| 705 | /* Enable Receive and Transmit */ |
| 706 | ctl = at91_emac_read(AT91_EMAC_CTL); |
| 707 | at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE); |
| 708 | } |
| 709 | |
| 710 | /* |
| 711 | * Open the ethernet interface |
| 712 | */ |
| 713 | static int at91ether_open(struct net_device *dev) |
| 714 | { |
| 715 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 716 | unsigned long ctl; |
| 717 | |
Andrew Victor | 427d269 | 2006-06-20 12:10:57 +0200 | [diff] [blame] | 718 | if (!is_valid_ether_addr(dev->dev_addr)) |
| 719 | return -EADDRNOTAVAIL; |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 720 | |
Andrew Victor | 427d269 | 2006-06-20 12:10:57 +0200 | [diff] [blame] | 721 | clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */ |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 722 | |
| 723 | /* Clear internal statistics */ |
| 724 | ctl = at91_emac_read(AT91_EMAC_CTL); |
| 725 | at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR); |
| 726 | |
| 727 | /* Update the MAC address (incase user has changed it) */ |
| 728 | update_mac_address(dev); |
| 729 | |
| 730 | /* Enable PHY interrupt */ |
| 731 | enable_phyirq(dev); |
| 732 | |
| 733 | /* Enable MAC interrupts */ |
| 734 | at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA |
| 735 | | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM |
| 736 | | AT91_EMAC_ROVR | AT91_EMAC_ABT); |
| 737 | |
| 738 | /* Determine current link speed */ |
| 739 | spin_lock_irq(&lp->lock); |
| 740 | enable_mdi(); |
Andrew Victor | 775637d | 2006-06-20 11:50:23 +0200 | [diff] [blame] | 741 | update_linkspeed(dev, 0); |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 742 | disable_mdi(); |
| 743 | spin_unlock_irq(&lp->lock); |
| 744 | |
| 745 | at91ether_start(dev); |
| 746 | netif_start_queue(dev); |
| 747 | return 0; |
| 748 | } |
| 749 | |
| 750 | /* |
| 751 | * Close the interface |
| 752 | */ |
| 753 | static int at91ether_close(struct net_device *dev) |
| 754 | { |
Andrew Victor | 427d269 | 2006-06-20 12:10:57 +0200 | [diff] [blame] | 755 | struct at91_private *lp = (struct at91_private *) dev->priv; |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 756 | unsigned long ctl; |
| 757 | |
| 758 | /* Disable Receiver and Transmitter */ |
| 759 | ctl = at91_emac_read(AT91_EMAC_CTL); |
| 760 | at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE)); |
| 761 | |
| 762 | /* Disable PHY interrupt */ |
| 763 | disable_phyirq(dev); |
| 764 | |
| 765 | /* Disable MAC interrupts */ |
| 766 | at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA |
| 767 | | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM |
| 768 | | AT91_EMAC_ROVR | AT91_EMAC_ABT); |
| 769 | |
| 770 | netif_stop_queue(dev); |
| 771 | |
Andrew Victor | 427d269 | 2006-06-20 12:10:57 +0200 | [diff] [blame] | 772 | clk_disable(lp->ether_clk); /* Disable Peripheral clock */ |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 773 | |
| 774 | return 0; |
| 775 | } |
| 776 | |
| 777 | /* |
| 778 | * Transmit packet. |
| 779 | */ |
| 780 | static int at91ether_tx(struct sk_buff *skb, struct net_device *dev) |
| 781 | { |
| 782 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 783 | |
| 784 | if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) { |
| 785 | netif_stop_queue(dev); |
| 786 | |
| 787 | /* Store packet information (to free when Tx completed) */ |
| 788 | lp->skb = skb; |
| 789 | lp->skb_length = skb->len; |
| 790 | lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); |
| 791 | lp->stats.tx_bytes += skb->len; |
| 792 | |
| 793 | /* Set address of the data in the Transmit Address register */ |
| 794 | at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr); |
| 795 | /* Set length of the packet in the Transmit Control register */ |
| 796 | at91_emac_write(AT91_EMAC_TCR, skb->len); |
| 797 | |
| 798 | dev->trans_start = jiffies; |
| 799 | } else { |
| 800 | printk(KERN_ERR "at91_ether.c: at91ether_tx() called, but device is busy!\n"); |
| 801 | return 1; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb) |
| 802 | on this skb, he also reports -ENETDOWN and printk's, so either |
| 803 | we free and return(0) or don't free and return 1 */ |
| 804 | } |
| 805 | |
| 806 | return 0; |
| 807 | } |
| 808 | |
| 809 | /* |
| 810 | * Update the current statistics from the internal statistics registers. |
| 811 | */ |
| 812 | static struct net_device_stats *at91ether_stats(struct net_device *dev) |
| 813 | { |
| 814 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 815 | int ale, lenerr, seqe, lcol, ecol; |
| 816 | |
| 817 | if (netif_running(dev)) { |
| 818 | lp->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */ |
| 819 | ale = at91_emac_read(AT91_EMAC_ALE); |
| 820 | lp->stats.rx_frame_errors += ale; /* Alignment errors */ |
| 821 | lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF); |
| 822 | lp->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */ |
| 823 | seqe = at91_emac_read(AT91_EMAC_SEQE); |
| 824 | lp->stats.rx_crc_errors += seqe; /* CRC error */ |
| 825 | lp->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */ |
| 826 | lp->stats.rx_errors += (ale + lenerr + seqe |
| 827 | + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB)); |
| 828 | |
| 829 | lp->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */ |
| 830 | lp->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */ |
| 831 | lp->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */ |
| 832 | lp->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */ |
| 833 | |
| 834 | lcol = at91_emac_read(AT91_EMAC_LCOL); |
| 835 | ecol = at91_emac_read(AT91_EMAC_ECOL); |
| 836 | lp->stats.tx_window_errors += lcol; /* Late collisions */ |
| 837 | lp->stats.tx_aborted_errors += ecol; /* 16 collisions */ |
| 838 | |
| 839 | lp->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol); |
| 840 | } |
| 841 | return &lp->stats; |
| 842 | } |
| 843 | |
| 844 | /* |
| 845 | * Extract received frame from buffer descriptors and sent to upper layers. |
| 846 | * (Called from interrupt context) |
| 847 | */ |
| 848 | static void at91ether_rx(struct net_device *dev) |
| 849 | { |
| 850 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 851 | struct recv_desc_bufs *dlist; |
| 852 | unsigned char *p_recv; |
| 853 | struct sk_buff *skb; |
| 854 | unsigned int pktlen; |
| 855 | |
| 856 | dlist = lp->dlist; |
| 857 | while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) { |
| 858 | p_recv = dlist->recv_buf[lp->rxBuffIndex]; |
| 859 | pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */ |
| 860 | skb = alloc_skb(pktlen + 2, GFP_ATOMIC); |
| 861 | if (skb != NULL) { |
| 862 | skb_reserve(skb, 2); |
| 863 | memcpy(skb_put(skb, pktlen), p_recv, pktlen); |
| 864 | |
| 865 | skb->dev = dev; |
| 866 | skb->protocol = eth_type_trans(skb, dev); |
| 867 | skb->len = pktlen; |
| 868 | dev->last_rx = jiffies; |
| 869 | lp->stats.rx_bytes += pktlen; |
| 870 | netif_rx(skb); |
| 871 | } |
| 872 | else { |
| 873 | lp->stats.rx_dropped += 1; |
| 874 | printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name); |
| 875 | } |
| 876 | |
| 877 | if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST) |
| 878 | lp->stats.multicast++; |
| 879 | |
| 880 | dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */ |
| 881 | if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */ |
| 882 | lp->rxBuffIndex = 0; |
| 883 | else |
| 884 | lp->rxBuffIndex++; |
| 885 | } |
| 886 | } |
| 887 | |
| 888 | /* |
| 889 | * MAC interrupt handler |
| 890 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame^] | 891 | static irqreturn_t at91ether_interrupt(int irq, void *dev_id) |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 892 | { |
| 893 | struct net_device *dev = (struct net_device *) dev_id; |
| 894 | struct at91_private *lp = (struct at91_private *) dev->priv; |
| 895 | unsigned long intstatus, ctl; |
| 896 | |
| 897 | /* MAC Interrupt Status register indicates what interrupts are pending. |
| 898 | It is automatically cleared once read. */ |
| 899 | intstatus = at91_emac_read(AT91_EMAC_ISR); |
| 900 | |
| 901 | if (intstatus & AT91_EMAC_RCOM) /* Receive complete */ |
| 902 | at91ether_rx(dev); |
| 903 | |
Andrew Victor | 427d269 | 2006-06-20 12:10:57 +0200 | [diff] [blame] | 904 | if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */ |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 905 | /* The TCOM bit is set even if the transmission failed. */ |
| 906 | if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY)) |
| 907 | lp->stats.tx_errors += 1; |
| 908 | |
| 909 | if (lp->skb) { |
| 910 | dev_kfree_skb_irq(lp->skb); |
| 911 | lp->skb = NULL; |
| 912 | dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE); |
| 913 | } |
| 914 | netif_wake_queue(dev); |
| 915 | } |
| 916 | |
| 917 | /* Work-around for Errata #11 */ |
| 918 | if (intstatus & AT91_EMAC_RBNA) { |
| 919 | ctl = at91_emac_read(AT91_EMAC_CTL); |
| 920 | at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE); |
| 921 | at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE); |
| 922 | } |
| 923 | |
| 924 | if (intstatus & AT91_EMAC_ROVR) |
| 925 | printk("%s: ROVR error\n", dev->name); |
| 926 | |
| 927 | return IRQ_HANDLED; |
| 928 | } |
| 929 | |
| 930 | /* |
| 931 | * Initialize the ethernet interface |
| 932 | */ |
Andrew Victor | 427d269 | 2006-06-20 12:10:57 +0200 | [diff] [blame] | 933 | static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address, |
| 934 | struct platform_device *pdev, struct clk *ether_clk) |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 935 | { |
| 936 | struct at91_eth_data *board_data = pdev->dev.platform_data; |
| 937 | struct net_device *dev; |
| 938 | struct at91_private *lp; |
| 939 | unsigned int val; |
| 940 | int res; |
| 941 | |
| 942 | if (at91_dev) /* already initialized */ |
| 943 | return 0; |
| 944 | |
| 945 | dev = alloc_etherdev(sizeof(struct at91_private)); |
| 946 | if (!dev) |
| 947 | return -ENOMEM; |
| 948 | |
| 949 | dev->base_addr = AT91_VA_BASE_EMAC; |
Andrew Victor | 7272991 | 2006-09-27 09:44:11 +0100 | [diff] [blame] | 950 | dev->irq = AT91RM9200_ID_EMAC; |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 951 | SET_MODULE_OWNER(dev); |
| 952 | |
| 953 | /* Install the interrupt handler */ |
| 954 | if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) { |
| 955 | free_netdev(dev); |
| 956 | return -EBUSY; |
| 957 | } |
| 958 | |
| 959 | /* Allocate memory for DMA Receive descriptors */ |
| 960 | lp = (struct at91_private *)dev->priv; |
| 961 | lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL); |
| 962 | if (lp->dlist == NULL) { |
| 963 | free_irq(dev->irq, dev); |
| 964 | free_netdev(dev); |
| 965 | return -ENOMEM; |
| 966 | } |
| 967 | lp->board_data = *board_data; |
Andrew Victor | 427d269 | 2006-06-20 12:10:57 +0200 | [diff] [blame] | 968 | lp->ether_clk = ether_clk; |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 969 | platform_set_drvdata(pdev, dev); |
| 970 | |
| 971 | spin_lock_init(&lp->lock); |
| 972 | |
| 973 | ether_setup(dev); |
| 974 | dev->open = at91ether_open; |
| 975 | dev->stop = at91ether_close; |
| 976 | dev->hard_start_xmit = at91ether_tx; |
| 977 | dev->get_stats = at91ether_stats; |
| 978 | dev->set_multicast_list = at91ether_set_rx_mode; |
| 979 | dev->set_mac_address = set_mac_address; |
| 980 | dev->ethtool_ops = &at91ether_ethtool_ops; |
Andrew Victor | ca5585e | 2006-06-20 11:59:05 +0200 | [diff] [blame] | 981 | dev->do_ioctl = at91ether_ioctl; |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 982 | |
| 983 | SET_NETDEV_DEV(dev, &pdev->dev); |
| 984 | |
| 985 | get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */ |
| 986 | update_mac_address(dev); /* Program ethernet address into MAC */ |
| 987 | |
| 988 | at91_emac_write(AT91_EMAC_CTL, 0); |
| 989 | |
| 990 | if (lp->board_data.is_rmii) |
| 991 | at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII); |
| 992 | else |
| 993 | at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG); |
| 994 | |
| 995 | /* Perform PHY-specific initialization */ |
| 996 | spin_lock_irq(&lp->lock); |
| 997 | enable_mdi(); |
| 998 | if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { |
| 999 | read_phy(phy_address, MII_DSCR_REG, &val); |
| 1000 | if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */ |
| 1001 | lp->phy_media = PORT_FIBRE; |
| 1002 | } else if (machine_is_csb337()) { |
| 1003 | /* mix link activity status into LED2 link state */ |
| 1004 | write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22); |
| 1005 | } |
| 1006 | disable_mdi(); |
| 1007 | spin_unlock_irq(&lp->lock); |
| 1008 | |
| 1009 | lp->mii.dev = dev; /* Support for ethtool */ |
| 1010 | lp->mii.mdio_read = mdio_read; |
| 1011 | lp->mii.mdio_write = mdio_write; |
Andrew Victor | ca5585e | 2006-06-20 11:59:05 +0200 | [diff] [blame] | 1012 | lp->mii.phy_id = phy_address; |
| 1013 | lp->mii.phy_id_mask = 0x1f; |
| 1014 | lp->mii.reg_num_mask = 0x1f; |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 1015 | |
| 1016 | lp->phy_type = phy_type; /* Type of PHY connected */ |
| 1017 | lp->phy_address = phy_address; /* MDI address of PHY */ |
| 1018 | |
| 1019 | /* Register the network interface */ |
| 1020 | res = register_netdev(dev); |
| 1021 | if (res) { |
| 1022 | free_irq(dev->irq, dev); |
| 1023 | free_netdev(dev); |
| 1024 | dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); |
| 1025 | return res; |
| 1026 | } |
| 1027 | at91_dev = dev; |
| 1028 | |
| 1029 | /* Determine current link speed */ |
| 1030 | spin_lock_irq(&lp->lock); |
| 1031 | enable_mdi(); |
Andrew Victor | 775637d | 2006-06-20 11:50:23 +0200 | [diff] [blame] | 1032 | update_linkspeed(dev, 0); |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 1033 | disable_mdi(); |
| 1034 | spin_unlock_irq(&lp->lock); |
| 1035 | netif_carrier_off(dev); /* will be enabled in open() */ |
| 1036 | |
Andrew Victor | 775637d | 2006-06-20 11:50:23 +0200 | [diff] [blame] | 1037 | /* If board has no PHY IRQ, use a timer to poll the PHY */ |
| 1038 | if (!lp->board_data.phy_irq_pin) { |
| 1039 | init_timer(&check_timer); |
| 1040 | check_timer.data = (unsigned long)dev; |
| 1041 | check_timer.function = at91ether_check_link; |
| 1042 | } |
| 1043 | |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 1044 | /* Display ethernet banner */ |
| 1045 | printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%02x:%02x:%02x:%02x:%02x:%02x)\n", |
| 1046 | dev->name, (uint) dev->base_addr, dev->irq, |
| 1047 | at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-", |
| 1048 | at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex", |
| 1049 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], |
| 1050 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); |
| 1051 | if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) |
Andrew Victor | 427d269 | 2006-06-20 12:10:57 +0200 | [diff] [blame] | 1052 | printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)"); |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 1053 | else if (phy_type == MII_LXT971A_ID) |
| 1054 | printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name); |
| 1055 | else if (phy_type == MII_RTL8201_ID) |
| 1056 | printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name); |
| 1057 | else if (phy_type == MII_BCM5221_ID) |
| 1058 | printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name); |
| 1059 | else if (phy_type == MII_DP83847_ID) |
| 1060 | printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name); |
| 1061 | else if (phy_type == MII_AC101L_ID) |
| 1062 | printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name); |
| 1063 | else if (phy_type == MII_KS8721_ID) |
| 1064 | printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name); |
| 1065 | |
| 1066 | return 0; |
| 1067 | } |
| 1068 | |
| 1069 | /* |
| 1070 | * Detect MAC and PHY and perform initialization |
| 1071 | */ |
| 1072 | static int __init at91ether_probe(struct platform_device *pdev) |
| 1073 | { |
| 1074 | unsigned int phyid1, phyid2; |
| 1075 | int detected = -1; |
| 1076 | unsigned long phy_id; |
| 1077 | unsigned short phy_address = 0; |
Andrew Victor | 427d269 | 2006-06-20 12:10:57 +0200 | [diff] [blame] | 1078 | struct clk *ether_clk; |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 1079 | |
| 1080 | ether_clk = clk_get(&pdev->dev, "ether_clk"); |
Andrew Victor | 427d269 | 2006-06-20 12:10:57 +0200 | [diff] [blame] | 1081 | if (IS_ERR(ether_clk)) { |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 1082 | printk(KERN_ERR "at91_ether: no clock defined\n"); |
| 1083 | return -ENODEV; |
| 1084 | } |
| 1085 | clk_enable(ether_clk); /* Enable Peripheral clock */ |
| 1086 | |
| 1087 | while ((detected != 0) && (phy_address < 32)) { |
| 1088 | /* Read the PHY ID registers */ |
| 1089 | enable_mdi(); |
| 1090 | read_phy(phy_address, MII_PHYSID1, &phyid1); |
| 1091 | read_phy(phy_address, MII_PHYSID2, &phyid2); |
| 1092 | disable_mdi(); |
| 1093 | |
| 1094 | phy_id = (phyid1 << 16) | (phyid2 & 0xfff0); |
| 1095 | switch (phy_id) { |
| 1096 | case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */ |
| 1097 | case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */ |
| 1098 | case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */ |
| 1099 | case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ |
| 1100 | case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ |
| 1101 | case MII_DP83847_ID: /* National Semiconductor DP83847: */ |
| 1102 | case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ |
| 1103 | case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ |
Andrew Victor | 427d269 | 2006-06-20 12:10:57 +0200 | [diff] [blame] | 1104 | detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk); |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 1105 | break; |
| 1106 | } |
| 1107 | |
| 1108 | phy_address++; |
| 1109 | } |
| 1110 | |
| 1111 | clk_disable(ether_clk); /* Disable Peripheral clock */ |
| 1112 | |
| 1113 | return detected; |
| 1114 | } |
| 1115 | |
| 1116 | static int __devexit at91ether_remove(struct platform_device *pdev) |
| 1117 | { |
| 1118 | struct at91_private *lp = (struct at91_private *) at91_dev->priv; |
| 1119 | |
| 1120 | unregister_netdev(at91_dev); |
| 1121 | free_irq(at91_dev->irq, at91_dev); |
| 1122 | dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); |
Andrew Victor | 427d269 | 2006-06-20 12:10:57 +0200 | [diff] [blame] | 1123 | clk_put(lp->ether_clk); |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 1124 | |
| 1125 | free_netdev(at91_dev); |
| 1126 | at91_dev = NULL; |
| 1127 | return 0; |
| 1128 | } |
| 1129 | |
Andrew Victor | 00e5edc | 2006-06-20 12:19:13 +0200 | [diff] [blame] | 1130 | #ifdef CONFIG_PM |
| 1131 | |
| 1132 | static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg) |
| 1133 | { |
| 1134 | struct at91_private *lp = (struct at91_private *) at91_dev->priv; |
| 1135 | struct net_device *net_dev = platform_get_drvdata(pdev); |
| 1136 | int phy_irq = lp->board_data.phy_irq_pin; |
| 1137 | |
| 1138 | if (netif_running(net_dev)) { |
| 1139 | if (phy_irq) |
| 1140 | disable_irq(phy_irq); |
| 1141 | |
| 1142 | netif_stop_queue(net_dev); |
| 1143 | netif_device_detach(net_dev); |
| 1144 | |
| 1145 | clk_disable(lp->ether_clk); |
| 1146 | } |
| 1147 | return 0; |
| 1148 | } |
| 1149 | |
| 1150 | static int at91ether_resume(struct platform_device *pdev) |
| 1151 | { |
| 1152 | struct at91_private *lp = (struct at91_private *) at91_dev->priv; |
| 1153 | struct net_device *net_dev = platform_get_drvdata(pdev); |
| 1154 | int phy_irq = lp->board_data.phy_irq_pin; |
| 1155 | |
| 1156 | if (netif_running(net_dev)) { |
| 1157 | clk_enable(lp->ether_clk); |
| 1158 | |
| 1159 | netif_device_attach(net_dev); |
| 1160 | netif_start_queue(net_dev); |
| 1161 | |
| 1162 | if (phy_irq) |
| 1163 | enable_irq(phy_irq); |
| 1164 | } |
| 1165 | return 0; |
| 1166 | } |
| 1167 | |
| 1168 | #else |
| 1169 | #define at91ether_suspend NULL |
| 1170 | #define at91ether_resume NULL |
| 1171 | #endif |
| 1172 | |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 1173 | static struct platform_driver at91ether_driver = { |
| 1174 | .probe = at91ether_probe, |
| 1175 | .remove = __devexit_p(at91ether_remove), |
Andrew Victor | 00e5edc | 2006-06-20 12:19:13 +0200 | [diff] [blame] | 1176 | .suspend = at91ether_suspend, |
| 1177 | .resume = at91ether_resume, |
Andrew Victor | d4b7780 | 2006-03-24 11:50:17 +0200 | [diff] [blame] | 1178 | .driver = { |
| 1179 | .name = DRV_NAME, |
| 1180 | .owner = THIS_MODULE, |
| 1181 | }, |
| 1182 | }; |
| 1183 | |
| 1184 | static int __init at91ether_init(void) |
| 1185 | { |
| 1186 | return platform_driver_register(&at91ether_driver); |
| 1187 | } |
| 1188 | |
| 1189 | static void __exit at91ether_exit(void) |
| 1190 | { |
| 1191 | platform_driver_unregister(&at91ether_driver); |
| 1192 | } |
| 1193 | |
| 1194 | module_init(at91ether_init) |
| 1195 | module_exit(at91ether_exit) |
| 1196 | |
| 1197 | MODULE_LICENSE("GPL"); |
| 1198 | MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver"); |
| 1199 | MODULE_AUTHOR("Andrew Victor"); |