| Kukjin Kim | 7d30e8b | 2011-02-14 16:33:10 +0900 | [diff] [blame^] | 1 | /* linux/arch/arm/mach-exynos4/include/mach/map.h |
| 2 | * |
| 3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com/ |
| 5 | * |
| 6 | * EXYNOS4 - Memory map definitions |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __ASM_ARCH_MAP_H |
| 14 | #define __ASM_ARCH_MAP_H __FILE__ |
| 15 | |
| 16 | #include <plat/map-base.h> |
| 17 | |
| 18 | /* |
| 19 | * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400. |
| 20 | * So need to define it, and here is to avoid redefinition warning. |
| 21 | */ |
| 22 | #define S3C_UART_OFFSET (0x10000) |
| 23 | |
| 24 | #include <plat/map-s5p.h> |
| 25 | |
| 26 | #define EXYNOS4_PA_SYSRAM 0x02020000 |
| 27 | |
| 28 | #define EXYNOS4_PA_I2S0 0x03830000 |
| 29 | #define EXYNOS4_PA_I2S1 0xE3100000 |
| 30 | #define EXYNOS4_PA_I2S2 0xE2A00000 |
| 31 | |
| 32 | #define EXYNOS4_PA_PCM0 0x03840000 |
| 33 | #define EXYNOS4_PA_PCM1 0x13980000 |
| 34 | #define EXYNOS4_PA_PCM2 0x13990000 |
| 35 | |
| 36 | #define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000)) |
| 37 | |
| 38 | #define EXYNOS4_PA_ONENAND 0x0C000000 |
| 39 | #define EXYNOS4_PA_ONENAND_DMA 0x0C600000 |
| 40 | |
| 41 | #define EXYNOS4_PA_CHIPID 0x10000000 |
| 42 | |
| 43 | #define EXYNOS4_PA_SYSCON 0x10010000 |
| 44 | #define EXYNOS4_PA_PMU 0x10020000 |
| 45 | #define EXYNOS4_PA_CMU 0x10030000 |
| 46 | |
| 47 | #define EXYNOS4_PA_WATCHDOG 0x10060000 |
| 48 | #define EXYNOS4_PA_RTC 0x10070000 |
| 49 | |
| 50 | #define EXYNOS4_PA_DMC0 0x10400000 |
| 51 | |
| 52 | #define EXYNOS4_PA_COMBINER 0x10448000 |
| 53 | |
| 54 | #define EXYNOS4_PA_COREPERI 0x10500000 |
| 55 | #define EXYNOS4_PA_GIC_CPU 0x10500100 |
| 56 | #define EXYNOS4_PA_TWD 0x10500600 |
| 57 | #define EXYNOS4_PA_GIC_DIST 0x10501000 |
| 58 | #define EXYNOS4_PA_L2CC 0x10502000 |
| 59 | |
| 60 | #define EXYNOS4_PA_MDMA 0x10810000 |
| 61 | #define EXYNOS4_PA_PDMA0 0x12680000 |
| 62 | #define EXYNOS4_PA_PDMA1 0x12690000 |
| 63 | |
| 64 | #define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000 |
| 65 | #define EXYNOS4_PA_SYSMMU_SSS 0x10A50000 |
| 66 | #define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000 |
| 67 | #define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000 |
| 68 | #define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000 |
| 69 | #define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000 |
| 70 | #define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000 |
| 71 | #define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000 |
| 72 | #define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000 |
| 73 | #define EXYNOS4_PA_SYSMMU_PCIe 0x12620000 |
| 74 | #define EXYNOS4_PA_SYSMMU_G2D 0x12A20000 |
| 75 | #define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000 |
| 76 | #define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000 |
| 77 | #define EXYNOS4_PA_SYSMMU_TV 0x12E20000 |
| 78 | #define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000 |
| 79 | #define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000 |
| 80 | |
| 81 | #define EXYNOS4_PA_GPIO1 0x11400000 |
| 82 | #define EXYNOS4_PA_GPIO2 0x11000000 |
| 83 | #define EXYNOS4_PA_GPIO3 0x03860000 |
| 84 | |
| 85 | #define EXYNOS4_PA_MIPI_CSIS0 0x11880000 |
| 86 | #define EXYNOS4_PA_MIPI_CSIS1 0x11890000 |
| 87 | |
| 88 | #define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) |
| 89 | |
| 90 | #define EXYNOS4_PA_SROMC 0x12570000 |
| 91 | |
| 92 | #define EXYNOS4_PA_UART 0x13800000 |
| 93 | |
| 94 | #define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) |
| 95 | |
| 96 | #define EXYNOS4_PA_AC97 0x139A0000 |
| 97 | |
| 98 | #define EXYNOS4_PA_TIMER 0x139D0000 |
| 99 | |
| 100 | #define EXYNOS4_PA_SDRAM 0x40000000 |
| 101 | |
| 102 | #define EXYNOS4_PA_SPDIF 0xE1100000 |
| 103 | |
| 104 | /* Compatibiltiy Defines */ |
| 105 | |
| 106 | #define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0) |
| 107 | #define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1) |
| 108 | #define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2) |
| 109 | #define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3) |
| 110 | #define S3C_PA_IIC EXYNOS4_PA_IIC(0) |
| 111 | #define S3C_PA_IIC1 EXYNOS4_PA_IIC(1) |
| 112 | #define S3C_PA_IIC2 EXYNOS4_PA_IIC(2) |
| 113 | #define S3C_PA_IIC3 EXYNOS4_PA_IIC(3) |
| 114 | #define S3C_PA_IIC4 EXYNOS4_PA_IIC(4) |
| 115 | #define S3C_PA_IIC5 EXYNOS4_PA_IIC(5) |
| 116 | #define S3C_PA_IIC6 EXYNOS4_PA_IIC(6) |
| 117 | #define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) |
| 118 | #define S3C_PA_RTC EXYNOS4_PA_RTC |
| 119 | #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG |
| 120 | |
| 121 | #define S5P_PA_CHIPID EXYNOS4_PA_CHIPID |
| 122 | #define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 |
| 123 | #define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 |
| 124 | #define S5P_PA_ONENAND EXYNOS4_PA_ONENAND |
| 125 | #define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA |
| 126 | #define S5P_PA_SDRAM EXYNOS4_PA_SDRAM |
| 127 | #define S5P_PA_SROMC EXYNOS4_PA_SROMC |
| 128 | #define S5P_PA_SYSCON EXYNOS4_PA_SYSCON |
| 129 | #define S5P_PA_TIMER EXYNOS4_PA_TIMER |
| 130 | |
| 131 | /* UART */ |
| 132 | |
| 133 | #define S3C_PA_UART EXYNOS4_PA_UART |
| 134 | |
| 135 | #define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) |
| 136 | #define S5P_PA_UART0 S5P_PA_UART(0) |
| 137 | #define S5P_PA_UART1 S5P_PA_UART(1) |
| 138 | #define S5P_PA_UART2 S5P_PA_UART(2) |
| 139 | #define S5P_PA_UART3 S5P_PA_UART(3) |
| 140 | #define S5P_PA_UART4 S5P_PA_UART(4) |
| 141 | |
| 142 | #define S5P_SZ_UART SZ_256 |
| 143 | |
| 144 | #endif /* __ASM_ARCH_MAP_H */ |