Andrzej Hajda | 7d459937 | 2013-12-05 08:38:39 -0300 | [diff] [blame^] | 1 | /* |
| 2 | * Driver for Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor |
| 3 | * with embedded SoC ISP. |
| 4 | * |
| 5 | * Copyright (C) 2013, Samsung Electronics Co., Ltd. |
| 6 | * Andrzej Hajda <a.hajda@samsung.com> |
| 7 | * |
| 8 | * Based on S5K6AA driver authored by Sylwester Nawrocki |
| 9 | * Copyright (C) 2013, Samsung Electronics Co., Ltd. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/clk.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/firmware.h> |
| 19 | #include <linux/gpio.h> |
| 20 | #include <linux/i2c.h> |
| 21 | #include <linux/media.h> |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/of_gpio.h> |
| 24 | #include <linux/regulator/consumer.h> |
| 25 | #include <linux/slab.h> |
| 26 | |
| 27 | #include <media/media-entity.h> |
| 28 | #include <media/v4l2-ctrls.h> |
| 29 | #include <media/v4l2-device.h> |
| 30 | #include <media/v4l2-subdev.h> |
| 31 | #include <media/v4l2-mediabus.h> |
| 32 | #include <media/v4l2-of.h> |
| 33 | |
| 34 | static int debug; |
| 35 | module_param(debug, int, 0644); |
| 36 | |
| 37 | #define S5K5BAF_DRIVER_NAME "s5k5baf" |
| 38 | #define S5K5BAF_DEFAULT_MCLK_FREQ 24000000U |
| 39 | #define S5K5BAF_CLK_NAME "mclk" |
| 40 | |
| 41 | #define S5K5BAF_FW_FILENAME "s5k5baf-cfg.bin" |
| 42 | #define S5K5BAF_FW_TAG "SF00" |
| 43 | #define S5K5BAG_FW_TAG_LEN 2 |
| 44 | #define S5K5BAG_FW_MAX_COUNT 16 |
| 45 | |
| 46 | #define S5K5BAF_CIS_WIDTH 1600 |
| 47 | #define S5K5BAF_CIS_HEIGHT 1200 |
| 48 | #define S5K5BAF_WIN_WIDTH_MIN 8 |
| 49 | #define S5K5BAF_WIN_HEIGHT_MIN 8 |
| 50 | #define S5K5BAF_GAIN_RED_DEF 127 |
| 51 | #define S5K5BAF_GAIN_GREEN_DEF 95 |
| 52 | #define S5K5BAF_GAIN_BLUE_DEF 180 |
| 53 | /* Default number of MIPI CSI-2 data lanes used */ |
| 54 | #define S5K5BAF_DEF_NUM_LANES 1 |
| 55 | |
| 56 | #define AHB_MSB_ADDR_PTR 0xfcfc |
| 57 | |
| 58 | /* |
| 59 | * Register interface pages (the most significant word of the address) |
| 60 | */ |
| 61 | #define PAGE_IF_HW 0xd000 |
| 62 | #define PAGE_IF_SW 0x7000 |
| 63 | |
| 64 | /* |
| 65 | * H/W register Interface (PAGE_IF_HW) |
| 66 | */ |
| 67 | #define REG_SW_LOAD_COMPLETE 0x0014 |
| 68 | #define REG_CMDWR_PAGE 0x0028 |
| 69 | #define REG_CMDWR_ADDR 0x002a |
| 70 | #define REG_CMDRD_PAGE 0x002c |
| 71 | #define REG_CMDRD_ADDR 0x002e |
| 72 | #define REG_CMD_BUF 0x0f12 |
| 73 | #define REG_SET_HOST_INT 0x1000 |
| 74 | #define REG_CLEAR_HOST_INT 0x1030 |
| 75 | #define REG_PATTERN_SET 0x3100 |
| 76 | #define REG_PATTERN_WIDTH 0x3118 |
| 77 | #define REG_PATTERN_HEIGHT 0x311a |
| 78 | #define REG_PATTERN_PARAM 0x311c |
| 79 | |
| 80 | /* |
| 81 | * S/W register interface (PAGE_IF_SW) |
| 82 | */ |
| 83 | |
| 84 | /* Firmware revision information */ |
| 85 | #define REG_FW_APIVER 0x012e |
| 86 | #define S5K5BAF_FW_APIVER 0x0001 |
| 87 | #define REG_FW_REVISION 0x0130 |
| 88 | #define REG_FW_SENSOR_ID 0x0152 |
| 89 | |
| 90 | /* Initialization parameters */ |
| 91 | /* Master clock frequency in KHz */ |
| 92 | #define REG_I_INCLK_FREQ_L 0x01b8 |
| 93 | #define REG_I_INCLK_FREQ_H 0x01ba |
| 94 | #define MIN_MCLK_FREQ_KHZ 6000U |
| 95 | #define MAX_MCLK_FREQ_KHZ 48000U |
| 96 | #define REG_I_USE_NPVI_CLOCKS 0x01c6 |
| 97 | #define NPVI_CLOCKS 1 |
| 98 | #define REG_I_USE_NMIPI_CLOCKS 0x01c8 |
| 99 | #define NMIPI_CLOCKS 1 |
| 100 | #define REG_I_BLOCK_INTERNAL_PLL_CALC 0x01ca |
| 101 | |
| 102 | /* Clock configurations, n = 0..2. REG_I_* frequency unit is 4 kHz. */ |
| 103 | #define REG_I_OPCLK_4KHZ(n) ((n) * 6 + 0x01cc) |
| 104 | #define REG_I_MIN_OUTRATE_4KHZ(n) ((n) * 6 + 0x01ce) |
| 105 | #define REG_I_MAX_OUTRATE_4KHZ(n) ((n) * 6 + 0x01d0) |
| 106 | #define SCLK_PVI_FREQ 24000 |
| 107 | #define SCLK_MIPI_FREQ 48000 |
| 108 | #define PCLK_MIN_FREQ 6000 |
| 109 | #define PCLK_MAX_FREQ 48000 |
| 110 | #define REG_I_USE_REGS_API 0x01de |
| 111 | #define REG_I_INIT_PARAMS_UPDATED 0x01e0 |
| 112 | #define REG_I_ERROR_INFO 0x01e2 |
| 113 | |
| 114 | /* General purpose parameters */ |
| 115 | #define REG_USER_BRIGHTNESS 0x01e4 |
| 116 | #define REG_USER_CONTRAST 0x01e6 |
| 117 | #define REG_USER_SATURATION 0x01e8 |
| 118 | #define REG_USER_SHARPBLUR 0x01ea |
| 119 | |
| 120 | #define REG_G_SPEC_EFFECTS 0x01ee |
| 121 | #define REG_G_ENABLE_PREV 0x01f0 |
| 122 | #define REG_G_ENABLE_PREV_CHG 0x01f2 |
| 123 | #define REG_G_NEW_CFG_SYNC 0x01f8 |
| 124 | #define REG_G_PREVREQ_IN_WIDTH 0x01fa |
| 125 | #define REG_G_PREVREQ_IN_HEIGHT 0x01fc |
| 126 | #define REG_G_PREVREQ_IN_XOFFS 0x01fe |
| 127 | #define REG_G_PREVREQ_IN_YOFFS 0x0200 |
| 128 | #define REG_G_PREVZOOM_IN_WIDTH 0x020a |
| 129 | #define REG_G_PREVZOOM_IN_HEIGHT 0x020c |
| 130 | #define REG_G_PREVZOOM_IN_XOFFS 0x020e |
| 131 | #define REG_G_PREVZOOM_IN_YOFFS 0x0210 |
| 132 | #define REG_G_INPUTS_CHANGE_REQ 0x021a |
| 133 | #define REG_G_ACTIVE_PREV_CFG 0x021c |
| 134 | #define REG_G_PREV_CFG_CHG 0x021e |
| 135 | #define REG_G_PREV_OPEN_AFTER_CH 0x0220 |
| 136 | #define REG_G_PREV_CFG_ERROR 0x0222 |
| 137 | #define CFG_ERROR_RANGE 0x0b |
| 138 | #define REG_G_PREV_CFG_BYPASS_CHANGED 0x022a |
| 139 | #define REG_G_ACTUAL_P_FR_TIME 0x023a |
| 140 | #define REG_G_ACTUAL_P_OUT_RATE 0x023c |
| 141 | #define REG_G_ACTUAL_C_FR_TIME 0x023e |
| 142 | #define REG_G_ACTUAL_C_OUT_RATE 0x0240 |
| 143 | |
| 144 | /* Preview control section. n = 0...4. */ |
| 145 | #define PREG(n, x) ((n) * 0x26 + x) |
| 146 | #define REG_P_OUT_WIDTH(n) PREG(n, 0x0242) |
| 147 | #define REG_P_OUT_HEIGHT(n) PREG(n, 0x0244) |
| 148 | #define REG_P_FMT(n) PREG(n, 0x0246) |
| 149 | #define REG_P_MAX_OUT_RATE(n) PREG(n, 0x0248) |
| 150 | #define REG_P_MIN_OUT_RATE(n) PREG(n, 0x024a) |
| 151 | #define REG_P_PVI_MASK(n) PREG(n, 0x024c) |
| 152 | #define PVI_MASK_MIPI 0x52 |
| 153 | #define REG_P_CLK_INDEX(n) PREG(n, 0x024e) |
| 154 | #define CLK_PVI_INDEX 0 |
| 155 | #define CLK_MIPI_INDEX NPVI_CLOCKS |
| 156 | #define REG_P_FR_RATE_TYPE(n) PREG(n, 0x0250) |
| 157 | #define FR_RATE_DYNAMIC 0 |
| 158 | #define FR_RATE_FIXED 1 |
| 159 | #define FR_RATE_FIXED_ACCURATE 2 |
| 160 | #define REG_P_FR_RATE_Q_TYPE(n) PREG(n, 0x0252) |
| 161 | #define FR_RATE_Q_DYNAMIC 0 |
| 162 | #define FR_RATE_Q_BEST_FRRATE 1 /* Binning enabled */ |
| 163 | #define FR_RATE_Q_BEST_QUALITY 2 /* Binning disabled */ |
| 164 | /* Frame period in 0.1 ms units */ |
| 165 | #define REG_P_MAX_FR_TIME(n) PREG(n, 0x0254) |
| 166 | #define REG_P_MIN_FR_TIME(n) PREG(n, 0x0256) |
| 167 | #define S5K5BAF_MIN_FR_TIME 333 /* x100 us */ |
| 168 | #define S5K5BAF_MAX_FR_TIME 6500 /* x100 us */ |
| 169 | /* The below 5 registers are for "device correction" values */ |
| 170 | #define REG_P_SATURATION(n) PREG(n, 0x0258) |
| 171 | #define REG_P_SHARP_BLUR(n) PREG(n, 0x025a) |
| 172 | #define REG_P_GLAMOUR(n) PREG(n, 0x025c) |
| 173 | #define REG_P_COLORTEMP(n) PREG(n, 0x025e) |
| 174 | #define REG_P_GAMMA_INDEX(n) PREG(n, 0x0260) |
| 175 | #define REG_P_PREV_MIRROR(n) PREG(n, 0x0262) |
| 176 | #define REG_P_CAP_MIRROR(n) PREG(n, 0x0264) |
| 177 | #define REG_P_CAP_ROTATION(n) PREG(n, 0x0266) |
| 178 | |
| 179 | /* Extended image property controls */ |
| 180 | /* Exposure time in 10 us units */ |
| 181 | #define REG_SF_USR_EXPOSURE_L 0x03bc |
| 182 | #define REG_SF_USR_EXPOSURE_H 0x03be |
| 183 | #define REG_SF_USR_EXPOSURE_CHG 0x03c0 |
| 184 | #define REG_SF_USR_TOT_GAIN 0x03c2 |
| 185 | #define REG_SF_USR_TOT_GAIN_CHG 0x03c4 |
| 186 | #define REG_SF_RGAIN 0x03c6 |
| 187 | #define REG_SF_RGAIN_CHG 0x03c8 |
| 188 | #define REG_SF_GGAIN 0x03ca |
| 189 | #define REG_SF_GGAIN_CHG 0x03cc |
| 190 | #define REG_SF_BGAIN 0x03ce |
| 191 | #define REG_SF_BGAIN_CHG 0x03d0 |
| 192 | #define REG_SF_WBGAIN_CHG 0x03d2 |
| 193 | #define REG_SF_FLICKER_QUANT 0x03d4 |
| 194 | #define REG_SF_FLICKER_QUANT_CHG 0x03d6 |
| 195 | |
| 196 | /* Output interface (parallel/MIPI) setup */ |
| 197 | #define REG_OIF_EN_MIPI_LANES 0x03f2 |
| 198 | #define REG_OIF_EN_PACKETS 0x03f4 |
| 199 | #define EN_PACKETS_CSI2 0xc3 |
| 200 | #define REG_OIF_CFG_CHG 0x03f6 |
| 201 | |
| 202 | /* Auto-algorithms enable mask */ |
| 203 | #define REG_DBG_AUTOALG_EN 0x03f8 |
| 204 | #define AALG_ALL_EN BIT(0) |
| 205 | #define AALG_AE_EN BIT(1) |
| 206 | #define AALG_DIVLEI_EN BIT(2) |
| 207 | #define AALG_WB_EN BIT(3) |
| 208 | #define AALG_USE_WB_FOR_ISP BIT(4) |
| 209 | #define AALG_FLICKER_EN BIT(5) |
| 210 | #define AALG_FIT_EN BIT(6) |
| 211 | #define AALG_WRHW_EN BIT(7) |
| 212 | |
| 213 | /* Pointers to color correction matrices */ |
| 214 | #define REG_PTR_CCM_HORIZON 0x06d0 |
| 215 | #define REG_PTR_CCM_INCANDESCENT 0x06d4 |
| 216 | #define REG_PTR_CCM_WARM_WHITE 0x06d8 |
| 217 | #define REG_PTR_CCM_COOL_WHITE 0x06dc |
| 218 | #define REG_PTR_CCM_DL50 0x06e0 |
| 219 | #define REG_PTR_CCM_DL65 0x06e4 |
| 220 | #define REG_PTR_CCM_OUTDOOR 0x06ec |
| 221 | |
| 222 | #define REG_ARR_CCM(n) (0x2800 + 36 * (n)) |
| 223 | |
| 224 | static const char * const s5k5baf_supply_names[] = { |
| 225 | "vdda", /* Analog power supply 2.8V (2.6V to 3.0V) */ |
| 226 | "vddreg", /* Regulator input power supply 1.8V (1.7V to 1.9V) |
| 227 | or 2.8V (2.6V to 3.0) */ |
| 228 | "vddio", /* I/O power supply 1.8V (1.65V to 1.95V) |
| 229 | or 2.8V (2.5V to 3.1V) */ |
| 230 | }; |
| 231 | #define S5K5BAF_NUM_SUPPLIES ARRAY_SIZE(s5k5baf_supply_names) |
| 232 | |
| 233 | struct s5k5baf_gpio { |
| 234 | int gpio; |
| 235 | int level; |
| 236 | }; |
| 237 | |
| 238 | enum s5k5baf_gpio_id { |
| 239 | STBY, |
| 240 | RST, |
| 241 | NUM_GPIOS, |
| 242 | }; |
| 243 | |
| 244 | #define PAD_CIS 0 |
| 245 | #define PAD_OUT 1 |
| 246 | #define NUM_CIS_PADS 1 |
| 247 | #define NUM_ISP_PADS 2 |
| 248 | |
| 249 | struct s5k5baf_pixfmt { |
| 250 | enum v4l2_mbus_pixelcode code; |
| 251 | u32 colorspace; |
| 252 | /* REG_P_FMT(x) register value */ |
| 253 | u16 reg_p_fmt; |
| 254 | }; |
| 255 | |
| 256 | struct s5k5baf_ctrls { |
| 257 | struct v4l2_ctrl_handler handler; |
| 258 | struct { /* Auto / manual white balance cluster */ |
| 259 | struct v4l2_ctrl *awb; |
| 260 | struct v4l2_ctrl *gain_red; |
| 261 | struct v4l2_ctrl *gain_blue; |
| 262 | }; |
| 263 | struct { /* Mirror cluster */ |
| 264 | struct v4l2_ctrl *hflip; |
| 265 | struct v4l2_ctrl *vflip; |
| 266 | }; |
| 267 | struct { /* Auto exposure / manual exposure and gain cluster */ |
| 268 | struct v4l2_ctrl *auto_exp; |
| 269 | struct v4l2_ctrl *exposure; |
| 270 | struct v4l2_ctrl *gain; |
| 271 | }; |
| 272 | }; |
| 273 | |
| 274 | enum { |
| 275 | S5K5BAF_FW_ID_PATCH, |
| 276 | S5K5BAF_FW_ID_CCM, |
| 277 | S5K5BAF_FW_ID_CIS, |
| 278 | }; |
| 279 | |
| 280 | struct s5k5baf_fw { |
| 281 | u16 count; |
| 282 | struct { |
| 283 | u16 id; |
| 284 | u16 offset; |
| 285 | } seq[0]; |
| 286 | u16 data[0]; |
| 287 | }; |
| 288 | |
| 289 | struct s5k5baf { |
| 290 | struct s5k5baf_gpio gpios[NUM_GPIOS]; |
| 291 | enum v4l2_mbus_type bus_type; |
| 292 | u8 nlanes; |
| 293 | struct regulator_bulk_data supplies[S5K5BAF_NUM_SUPPLIES]; |
| 294 | |
| 295 | struct clk *clock; |
| 296 | u32 mclk_frequency; |
| 297 | |
| 298 | struct s5k5baf_fw *fw; |
| 299 | |
| 300 | struct v4l2_subdev cis_sd; |
| 301 | struct media_pad cis_pad; |
| 302 | |
| 303 | struct v4l2_subdev sd; |
| 304 | struct media_pad pads[NUM_ISP_PADS]; |
| 305 | |
| 306 | /* protects the struct members below */ |
| 307 | struct mutex lock; |
| 308 | |
| 309 | int error; |
| 310 | |
| 311 | struct v4l2_rect crop_sink; |
| 312 | struct v4l2_rect compose; |
| 313 | struct v4l2_rect crop_source; |
| 314 | /* index to s5k5baf_formats array */ |
| 315 | int pixfmt; |
| 316 | /* actual frame interval in 100us */ |
| 317 | u16 fiv; |
| 318 | /* requested frame interval in 100us */ |
| 319 | u16 req_fiv; |
| 320 | /* cache for REG_DBG_AUTOALG_EN register */ |
| 321 | u16 auto_alg; |
| 322 | |
| 323 | struct s5k5baf_ctrls ctrls; |
| 324 | |
| 325 | unsigned int streaming:1; |
| 326 | unsigned int apply_cfg:1; |
| 327 | unsigned int apply_crop:1; |
| 328 | unsigned int valid_auto_alg:1; |
| 329 | unsigned int power; |
| 330 | }; |
| 331 | |
| 332 | static const struct s5k5baf_pixfmt s5k5baf_formats[] = { |
| 333 | { V4L2_MBUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG, 5 }, |
| 334 | /* range 16-240 */ |
| 335 | { V4L2_MBUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_REC709, 6 }, |
| 336 | { V4L2_MBUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_JPEG, 0 }, |
| 337 | }; |
| 338 | |
| 339 | static struct v4l2_rect s5k5baf_cis_rect = { |
| 340 | 0, 0, S5K5BAF_CIS_WIDTH, S5K5BAF_CIS_HEIGHT |
| 341 | }; |
| 342 | |
| 343 | /* Setfile contains set of I2C command sequences. Each sequence has its ID. |
| 344 | * setfile format: |
| 345 | * u8 magic[4]; |
| 346 | * u16 count; number of sequences |
| 347 | * struct { |
| 348 | * u16 id; sequence id |
| 349 | * u16 offset; sequence offset in data array |
| 350 | * } seq[count]; |
| 351 | * u16 data[*]; array containing sequences |
| 352 | * |
| 353 | */ |
| 354 | static int s5k5baf_fw_parse(struct device *dev, struct s5k5baf_fw **fw, |
| 355 | size_t count, const u16 *data) |
| 356 | { |
| 357 | struct s5k5baf_fw *f; |
| 358 | u16 *d, i, *end; |
| 359 | int ret; |
| 360 | |
| 361 | if (count < S5K5BAG_FW_TAG_LEN + 1) { |
| 362 | dev_err(dev, "firmware file too short (%d)\n", count); |
| 363 | return -EINVAL; |
| 364 | } |
| 365 | |
| 366 | ret = memcmp(data, S5K5BAF_FW_TAG, S5K5BAG_FW_TAG_LEN * sizeof(u16)); |
| 367 | if (ret != 0) { |
| 368 | dev_err(dev, "invalid firmware magic number\n"); |
| 369 | return -EINVAL; |
| 370 | } |
| 371 | |
| 372 | data += S5K5BAG_FW_TAG_LEN; |
| 373 | count -= S5K5BAG_FW_TAG_LEN; |
| 374 | |
| 375 | d = devm_kzalloc(dev, count * sizeof(u16), GFP_KERNEL); |
| 376 | |
| 377 | for (i = 0; i < count; ++i) |
| 378 | d[i] = le16_to_cpu(data[i]); |
| 379 | |
| 380 | f = (struct s5k5baf_fw *)d; |
| 381 | if (count < 1 + 2 * f->count) { |
| 382 | dev_err(dev, "invalid firmware header (count=%d size=%d)\n", |
| 383 | f->count, 2 * (count + S5K5BAG_FW_TAG_LEN)); |
| 384 | return -EINVAL; |
| 385 | } |
| 386 | end = d + count; |
| 387 | d += 1 + 2 * f->count; |
| 388 | |
| 389 | for (i = 0; i < f->count; ++i) { |
| 390 | if (f->seq[i].offset + d <= end) |
| 391 | continue; |
| 392 | dev_err(dev, "invalid firmware header (seq=%d)\n", i); |
| 393 | return -EINVAL; |
| 394 | } |
| 395 | |
| 396 | *fw = f; |
| 397 | |
| 398 | return 0; |
| 399 | } |
| 400 | |
| 401 | static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl) |
| 402 | { |
| 403 | return &container_of(ctrl->handler, struct s5k5baf, ctrls.handler)->sd; |
| 404 | } |
| 405 | |
| 406 | static inline bool s5k5baf_is_cis_subdev(struct v4l2_subdev *sd) |
| 407 | { |
| 408 | return sd->entity.type == MEDIA_ENT_T_V4L2_SUBDEV_SENSOR; |
| 409 | } |
| 410 | |
| 411 | static inline struct s5k5baf *to_s5k5baf(struct v4l2_subdev *sd) |
| 412 | { |
| 413 | if (s5k5baf_is_cis_subdev(sd)) |
| 414 | return container_of(sd, struct s5k5baf, cis_sd); |
| 415 | else |
| 416 | return container_of(sd, struct s5k5baf, sd); |
| 417 | } |
| 418 | |
| 419 | static u16 s5k5baf_i2c_read(struct s5k5baf *state, u16 addr) |
| 420 | { |
| 421 | struct i2c_client *c = v4l2_get_subdevdata(&state->sd); |
| 422 | __be16 w, r; |
| 423 | struct i2c_msg msg[] = { |
| 424 | { .addr = c->addr, .flags = 0, |
| 425 | .len = 2, .buf = (u8 *)&w }, |
| 426 | { .addr = c->addr, .flags = I2C_M_RD, |
| 427 | .len = 2, .buf = (u8 *)&r }, |
| 428 | }; |
| 429 | int ret; |
| 430 | |
| 431 | if (state->error) |
| 432 | return 0; |
| 433 | |
| 434 | w = cpu_to_be16(addr); |
| 435 | ret = i2c_transfer(c->adapter, msg, 2); |
| 436 | r = be16_to_cpu(r); |
| 437 | |
| 438 | v4l2_dbg(3, debug, c, "i2c_read: 0x%04x : 0x%04x\n", addr, r); |
| 439 | |
| 440 | if (ret != 2) { |
| 441 | v4l2_err(c, "i2c_read: error during transfer (%d)\n", ret); |
| 442 | state->error = ret; |
| 443 | } |
| 444 | return r; |
| 445 | } |
| 446 | |
| 447 | static void s5k5baf_i2c_write(struct s5k5baf *state, u16 addr, u16 val) |
| 448 | { |
| 449 | u8 buf[4] = { addr >> 8, addr & 0xFF, val >> 8, val & 0xFF }; |
| 450 | struct i2c_client *c = v4l2_get_subdevdata(&state->sd); |
| 451 | int ret; |
| 452 | |
| 453 | if (state->error) |
| 454 | return; |
| 455 | |
| 456 | ret = i2c_master_send(c, buf, 4); |
| 457 | v4l2_dbg(3, debug, c, "i2c_write: 0x%04x : 0x%04x\n", addr, val); |
| 458 | |
| 459 | if (ret != 4) { |
| 460 | v4l2_err(c, "i2c_write: error during transfer (%d)\n", ret); |
| 461 | state->error = ret; |
| 462 | } |
| 463 | } |
| 464 | |
| 465 | static u16 s5k5baf_read(struct s5k5baf *state, u16 addr) |
| 466 | { |
| 467 | s5k5baf_i2c_write(state, REG_CMDRD_ADDR, addr); |
| 468 | return s5k5baf_i2c_read(state, REG_CMD_BUF); |
| 469 | } |
| 470 | |
| 471 | static void s5k5baf_write(struct s5k5baf *state, u16 addr, u16 val) |
| 472 | { |
| 473 | s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr); |
| 474 | s5k5baf_i2c_write(state, REG_CMD_BUF, val); |
| 475 | } |
| 476 | |
| 477 | static void s5k5baf_write_arr_seq(struct s5k5baf *state, u16 addr, |
| 478 | u16 count, const u16 *seq) |
| 479 | { |
| 480 | struct i2c_client *c = v4l2_get_subdevdata(&state->sd); |
| 481 | __be16 buf[count + 1]; |
| 482 | int ret, n; |
| 483 | |
| 484 | s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr); |
| 485 | if (state->error) |
| 486 | return; |
| 487 | |
| 488 | buf[0] = __constant_cpu_to_be16(REG_CMD_BUF); |
| 489 | for (n = 1; n <= count; ++n) |
| 490 | buf[n] = cpu_to_be16(*seq++); |
| 491 | |
| 492 | n *= 2; |
| 493 | ret = i2c_master_send(c, (char *)buf, n); |
| 494 | v4l2_dbg(3, debug, c, "i2c_write_seq(count=%d): %*ph\n", count, |
| 495 | min(2 * count, 64), seq - count); |
| 496 | |
| 497 | if (ret != n) { |
| 498 | v4l2_err(c, "i2c_write_seq: error during transfer (%d)\n", ret); |
| 499 | state->error = ret; |
| 500 | } |
| 501 | } |
| 502 | |
| 503 | #define s5k5baf_write_seq(state, addr, seq...) \ |
| 504 | s5k5baf_write_arr_seq(state, addr, sizeof((char[]){ seq }), \ |
| 505 | (const u16 []){ seq }); |
| 506 | |
| 507 | /* add items count at the beginning of the list */ |
| 508 | #define NSEQ(seq...) sizeof((char[]){ seq }), seq |
| 509 | |
| 510 | /* |
| 511 | * s5k5baf_write_nseq() - Writes sequences of values to sensor memory via i2c |
| 512 | * @nseq: sequence of u16 words in format: |
| 513 | * (N, address, value[1]...value[N-1])*,0 |
| 514 | * Ex.: |
| 515 | * u16 seq[] = { NSEQ(0x4000, 1, 1), NSEQ(0x4010, 640, 480), 0 }; |
| 516 | * ret = s5k5baf_write_nseq(c, seq); |
| 517 | */ |
| 518 | static void s5k5baf_write_nseq(struct s5k5baf *state, const u16 *nseq) |
| 519 | { |
| 520 | int count; |
| 521 | |
| 522 | while ((count = *nseq++)) { |
| 523 | u16 addr = *nseq++; |
| 524 | --count; |
| 525 | |
| 526 | s5k5baf_write_arr_seq(state, addr, count, nseq); |
| 527 | nseq += count; |
| 528 | } |
| 529 | } |
| 530 | |
| 531 | static void s5k5baf_synchronize(struct s5k5baf *state, int timeout, u16 addr) |
| 532 | { |
| 533 | unsigned long end = jiffies + msecs_to_jiffies(timeout); |
| 534 | u16 reg; |
| 535 | |
| 536 | s5k5baf_write(state, addr, 1); |
| 537 | do { |
| 538 | reg = s5k5baf_read(state, addr); |
| 539 | if (state->error || !reg) |
| 540 | return; |
| 541 | usleep_range(5000, 10000); |
| 542 | } while (time_is_after_jiffies(end)); |
| 543 | |
| 544 | v4l2_err(&state->sd, "timeout on register synchronize (%#x)\n", addr); |
| 545 | state->error = -ETIMEDOUT; |
| 546 | } |
| 547 | |
| 548 | static u16 *s5k5baf_fw_get_seq(struct s5k5baf *state, u16 seq_id) |
| 549 | { |
| 550 | struct s5k5baf_fw *fw = state->fw; |
| 551 | u16 *data = fw->data + 2 * fw->count; |
| 552 | int i; |
| 553 | |
| 554 | if (fw == NULL) |
| 555 | return NULL; |
| 556 | |
| 557 | for (i = 0; i < fw->count; ++i) { |
| 558 | if (fw->seq[i].id == seq_id) |
| 559 | return data + fw->seq[i].offset; |
| 560 | } |
| 561 | |
| 562 | return NULL; |
| 563 | } |
| 564 | |
| 565 | static void s5k5baf_hw_patch(struct s5k5baf *state) |
| 566 | { |
| 567 | u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_PATCH); |
| 568 | |
| 569 | if (seq) |
| 570 | s5k5baf_write_nseq(state, seq); |
| 571 | } |
| 572 | |
| 573 | static void s5k5baf_hw_set_clocks(struct s5k5baf *state) |
| 574 | { |
| 575 | unsigned long mclk = state->mclk_frequency / 1000; |
| 576 | u16 status; |
| 577 | static const u16 nseq_clk_cfg[] = { |
| 578 | NSEQ(REG_I_USE_NPVI_CLOCKS, |
| 579 | NPVI_CLOCKS, NMIPI_CLOCKS, 0, |
| 580 | SCLK_PVI_FREQ / 4, PCLK_MIN_FREQ / 4, PCLK_MAX_FREQ / 4, |
| 581 | SCLK_MIPI_FREQ / 4, PCLK_MIN_FREQ / 4, PCLK_MAX_FREQ / 4), |
| 582 | NSEQ(REG_I_USE_REGS_API, 1), |
| 583 | 0 |
| 584 | }; |
| 585 | |
| 586 | s5k5baf_write_seq(state, REG_I_INCLK_FREQ_L, mclk & 0xffff, mclk >> 16); |
| 587 | s5k5baf_write_nseq(state, nseq_clk_cfg); |
| 588 | |
| 589 | s5k5baf_synchronize(state, 250, REG_I_INIT_PARAMS_UPDATED); |
| 590 | status = s5k5baf_read(state, REG_I_ERROR_INFO); |
| 591 | if (!state->error && status) { |
| 592 | v4l2_err(&state->sd, "error configuring PLL (%d)\n", status); |
| 593 | state->error = -EINVAL; |
| 594 | } |
| 595 | } |
| 596 | |
| 597 | /* set custom color correction matrices for various illuminations */ |
| 598 | static void s5k5baf_hw_set_ccm(struct s5k5baf *state) |
| 599 | { |
| 600 | u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CCM); |
| 601 | |
| 602 | if (seq) |
| 603 | s5k5baf_write_nseq(state, seq); |
| 604 | } |
| 605 | |
| 606 | /* CIS sensor tuning, based on undocumented android driver code */ |
| 607 | static void s5k5baf_hw_set_cis(struct s5k5baf *state) |
| 608 | { |
| 609 | u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CIS); |
| 610 | |
| 611 | if (!seq) |
| 612 | return; |
| 613 | |
| 614 | s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_HW); |
| 615 | s5k5baf_write_nseq(state, seq); |
| 616 | s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW); |
| 617 | } |
| 618 | |
| 619 | static void s5k5baf_hw_sync_cfg(struct s5k5baf *state) |
| 620 | { |
| 621 | s5k5baf_write(state, REG_G_PREV_CFG_CHG, 1); |
| 622 | if (state->apply_crop) { |
| 623 | s5k5baf_write(state, REG_G_INPUTS_CHANGE_REQ, 1); |
| 624 | s5k5baf_write(state, REG_G_PREV_CFG_BYPASS_CHANGED, 1); |
| 625 | } |
| 626 | s5k5baf_synchronize(state, 500, REG_G_NEW_CFG_SYNC); |
| 627 | } |
| 628 | /* Set horizontal and vertical image flipping */ |
| 629 | static void s5k5baf_hw_set_mirror(struct s5k5baf *state) |
| 630 | { |
| 631 | u16 flip = state->ctrls.vflip->val | (state->ctrls.vflip->val << 1); |
| 632 | |
| 633 | s5k5baf_write(state, REG_P_PREV_MIRROR(0), flip); |
| 634 | if (state->streaming) |
| 635 | s5k5baf_hw_sync_cfg(state); |
| 636 | } |
| 637 | |
| 638 | static void s5k5baf_hw_set_alg(struct s5k5baf *state, u16 alg, bool enable) |
| 639 | { |
| 640 | u16 cur_alg, new_alg; |
| 641 | |
| 642 | if (!state->valid_auto_alg) |
| 643 | cur_alg = s5k5baf_read(state, REG_DBG_AUTOALG_EN); |
| 644 | else |
| 645 | cur_alg = state->auto_alg; |
| 646 | |
| 647 | new_alg = enable ? (cur_alg | alg) : (cur_alg & ~alg); |
| 648 | |
| 649 | if (new_alg != cur_alg) |
| 650 | s5k5baf_write(state, REG_DBG_AUTOALG_EN, new_alg); |
| 651 | |
| 652 | if (state->error) |
| 653 | return; |
| 654 | |
| 655 | state->valid_auto_alg = 1; |
| 656 | state->auto_alg = new_alg; |
| 657 | } |
| 658 | |
| 659 | /* Configure auto/manual white balance and R/G/B gains */ |
| 660 | static void s5k5baf_hw_set_awb(struct s5k5baf *state, int awb) |
| 661 | { |
| 662 | struct s5k5baf_ctrls *ctrls = &state->ctrls; |
| 663 | |
| 664 | if (!awb) |
| 665 | s5k5baf_write_seq(state, REG_SF_RGAIN, |
| 666 | ctrls->gain_red->val, 1, |
| 667 | S5K5BAF_GAIN_GREEN_DEF, 1, |
| 668 | ctrls->gain_blue->val, 1, |
| 669 | 1); |
| 670 | |
| 671 | s5k5baf_hw_set_alg(state, AALG_WB_EN, awb); |
| 672 | } |
| 673 | |
| 674 | /* Program FW with exposure time, 'exposure' in us units */ |
| 675 | static void s5k5baf_hw_set_user_exposure(struct s5k5baf *state, int exposure) |
| 676 | { |
| 677 | unsigned int time = exposure / 10; |
| 678 | |
| 679 | s5k5baf_write_seq(state, REG_SF_USR_EXPOSURE_L, |
| 680 | time & 0xffff, time >> 16, 1); |
| 681 | } |
| 682 | |
| 683 | static void s5k5baf_hw_set_user_gain(struct s5k5baf *state, int gain) |
| 684 | { |
| 685 | s5k5baf_write_seq(state, REG_SF_USR_TOT_GAIN, gain, 1); |
| 686 | } |
| 687 | |
| 688 | /* Set auto/manual exposure and total gain */ |
| 689 | static void s5k5baf_hw_set_auto_exposure(struct s5k5baf *state, int value) |
| 690 | { |
| 691 | if (value == V4L2_EXPOSURE_AUTO) { |
| 692 | s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, true); |
| 693 | } else { |
| 694 | unsigned int exp_time = state->ctrls.exposure->val; |
| 695 | |
| 696 | s5k5baf_hw_set_user_exposure(state, exp_time); |
| 697 | s5k5baf_hw_set_user_gain(state, state->ctrls.gain->val); |
| 698 | s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, false); |
| 699 | } |
| 700 | } |
| 701 | |
| 702 | static void s5k5baf_hw_set_anti_flicker(struct s5k5baf *state, int v) |
| 703 | { |
| 704 | if (v == V4L2_CID_POWER_LINE_FREQUENCY_AUTO) { |
| 705 | s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, true); |
| 706 | } else { |
| 707 | /* The V4L2_CID_LINE_FREQUENCY control values match |
| 708 | * the register values */ |
| 709 | s5k5baf_write_seq(state, REG_SF_FLICKER_QUANT, v, 1); |
| 710 | s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, false); |
| 711 | } |
| 712 | } |
| 713 | |
| 714 | static void s5k5baf_hw_set_colorfx(struct s5k5baf *state, int val) |
| 715 | { |
| 716 | static const u16 colorfx[] = { |
| 717 | [V4L2_COLORFX_NONE] = 0, |
| 718 | [V4L2_COLORFX_BW] = 1, |
| 719 | [V4L2_COLORFX_NEGATIVE] = 2, |
| 720 | [V4L2_COLORFX_SEPIA] = 3, |
| 721 | [V4L2_COLORFX_SKY_BLUE] = 4, |
| 722 | [V4L2_COLORFX_SKETCH] = 5, |
| 723 | }; |
| 724 | |
| 725 | s5k5baf_write(state, REG_G_SPEC_EFFECTS, colorfx[val]); |
| 726 | } |
| 727 | |
| 728 | static int s5k5baf_find_pixfmt(struct v4l2_mbus_framefmt *mf) |
| 729 | { |
| 730 | int i, c = -1; |
| 731 | |
| 732 | for (i = 0; i < ARRAY_SIZE(s5k5baf_formats); i++) { |
| 733 | if (mf->colorspace != s5k5baf_formats[i].colorspace) |
| 734 | continue; |
| 735 | if (mf->code == s5k5baf_formats[i].code) |
| 736 | return i; |
| 737 | if (c < 0) |
| 738 | c = i; |
| 739 | } |
| 740 | return (c < 0) ? 0 : c; |
| 741 | } |
| 742 | |
| 743 | static int s5k5baf_clear_error(struct s5k5baf *state) |
| 744 | { |
| 745 | int ret = state->error; |
| 746 | |
| 747 | state->error = 0; |
| 748 | return ret; |
| 749 | } |
| 750 | |
| 751 | static int s5k5baf_hw_set_video_bus(struct s5k5baf *state) |
| 752 | { |
| 753 | u16 en_pkts; |
| 754 | |
| 755 | if (state->bus_type == V4L2_MBUS_CSI2) |
| 756 | en_pkts = EN_PACKETS_CSI2; |
| 757 | else |
| 758 | en_pkts = 0; |
| 759 | |
| 760 | s5k5baf_write_seq(state, REG_OIF_EN_MIPI_LANES, |
| 761 | state->nlanes, en_pkts, 1); |
| 762 | |
| 763 | return s5k5baf_clear_error(state); |
| 764 | } |
| 765 | |
| 766 | static u16 s5k5baf_get_cfg_error(struct s5k5baf *state) |
| 767 | { |
| 768 | u16 err = s5k5baf_read(state, REG_G_PREV_CFG_ERROR); |
| 769 | if (err) |
| 770 | s5k5baf_write(state, REG_G_PREV_CFG_ERROR, 0); |
| 771 | return err; |
| 772 | } |
| 773 | |
| 774 | static void s5k5baf_hw_set_fiv(struct s5k5baf *state, u16 fiv) |
| 775 | { |
| 776 | s5k5baf_write(state, REG_P_MAX_FR_TIME(0), fiv); |
| 777 | s5k5baf_hw_sync_cfg(state); |
| 778 | } |
| 779 | |
| 780 | static void s5k5baf_hw_find_min_fiv(struct s5k5baf *state) |
| 781 | { |
| 782 | u16 err, fiv; |
| 783 | int n; |
| 784 | |
| 785 | fiv = s5k5baf_read(state, REG_G_ACTUAL_P_FR_TIME); |
| 786 | if (state->error) |
| 787 | return; |
| 788 | |
| 789 | for (n = 5; n > 0; --n) { |
| 790 | s5k5baf_hw_set_fiv(state, fiv); |
| 791 | err = s5k5baf_get_cfg_error(state); |
| 792 | if (state->error) |
| 793 | return; |
| 794 | switch (err) { |
| 795 | case CFG_ERROR_RANGE: |
| 796 | ++fiv; |
| 797 | break; |
| 798 | case 0: |
| 799 | state->fiv = fiv; |
| 800 | v4l2_info(&state->sd, |
| 801 | "found valid frame interval: %d00us\n", fiv); |
| 802 | return; |
| 803 | default: |
| 804 | v4l2_err(&state->sd, |
| 805 | "error setting frame interval: %d\n", err); |
| 806 | state->error = -EINVAL; |
| 807 | } |
| 808 | }; |
| 809 | v4l2_err(&state->sd, "cannot find correct frame interval\n"); |
| 810 | state->error = -ERANGE; |
| 811 | } |
| 812 | |
| 813 | static void s5k5baf_hw_validate_cfg(struct s5k5baf *state) |
| 814 | { |
| 815 | u16 err; |
| 816 | |
| 817 | err = s5k5baf_get_cfg_error(state); |
| 818 | if (state->error) |
| 819 | return; |
| 820 | |
| 821 | switch (err) { |
| 822 | case 0: |
| 823 | state->apply_cfg = 1; |
| 824 | return; |
| 825 | case CFG_ERROR_RANGE: |
| 826 | s5k5baf_hw_find_min_fiv(state); |
| 827 | if (!state->error) |
| 828 | state->apply_cfg = 1; |
| 829 | return; |
| 830 | default: |
| 831 | v4l2_err(&state->sd, |
| 832 | "error setting format: %d\n", err); |
| 833 | state->error = -EINVAL; |
| 834 | } |
| 835 | } |
| 836 | |
| 837 | static void s5k5baf_rescale(struct v4l2_rect *r, const struct v4l2_rect *v, |
| 838 | const struct v4l2_rect *n, |
| 839 | const struct v4l2_rect *d) |
| 840 | { |
| 841 | r->left = v->left * n->width / d->width; |
| 842 | r->top = v->top * n->height / d->height; |
| 843 | r->width = v->width * n->width / d->width; |
| 844 | r->height = v->height * n->height / d->height; |
| 845 | } |
| 846 | |
| 847 | static int s5k5baf_hw_set_crop_rects(struct s5k5baf *state) |
| 848 | { |
| 849 | struct v4l2_rect *p, r; |
| 850 | u16 err; |
| 851 | int ret; |
| 852 | |
| 853 | p = &state->crop_sink; |
| 854 | s5k5baf_write_seq(state, REG_G_PREVREQ_IN_WIDTH, p->width, p->height, |
| 855 | p->left, p->top); |
| 856 | |
| 857 | s5k5baf_rescale(&r, &state->crop_source, &state->crop_sink, |
| 858 | &state->compose); |
| 859 | s5k5baf_write_seq(state, REG_G_PREVZOOM_IN_WIDTH, r.width, r.height, |
| 860 | r.left, r.top); |
| 861 | |
| 862 | s5k5baf_synchronize(state, 500, REG_G_INPUTS_CHANGE_REQ); |
| 863 | s5k5baf_synchronize(state, 500, REG_G_PREV_CFG_BYPASS_CHANGED); |
| 864 | err = s5k5baf_get_cfg_error(state); |
| 865 | ret = s5k5baf_clear_error(state); |
| 866 | if (ret < 0) |
| 867 | return ret; |
| 868 | |
| 869 | switch (err) { |
| 870 | case 0: |
| 871 | break; |
| 872 | case CFG_ERROR_RANGE: |
| 873 | /* retry crop with frame interval set to max */ |
| 874 | s5k5baf_hw_set_fiv(state, S5K5BAF_MAX_FR_TIME); |
| 875 | err = s5k5baf_get_cfg_error(state); |
| 876 | ret = s5k5baf_clear_error(state); |
| 877 | if (ret < 0) |
| 878 | return ret; |
| 879 | if (err) { |
| 880 | v4l2_err(&state->sd, |
| 881 | "crop error on max frame interval: %d\n", err); |
| 882 | state->error = -EINVAL; |
| 883 | } |
| 884 | s5k5baf_hw_set_fiv(state, state->req_fiv); |
| 885 | s5k5baf_hw_validate_cfg(state); |
| 886 | break; |
| 887 | default: |
| 888 | v4l2_err(&state->sd, "crop error: %d\n", err); |
| 889 | return -EINVAL; |
| 890 | } |
| 891 | |
| 892 | if (!state->apply_cfg) |
| 893 | return 0; |
| 894 | |
| 895 | p = &state->crop_source; |
| 896 | s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0), p->width, p->height); |
| 897 | s5k5baf_hw_set_fiv(state, state->req_fiv); |
| 898 | s5k5baf_hw_validate_cfg(state); |
| 899 | |
| 900 | return s5k5baf_clear_error(state); |
| 901 | } |
| 902 | |
| 903 | static void s5k5baf_hw_set_config(struct s5k5baf *state) |
| 904 | { |
| 905 | u16 reg_fmt = s5k5baf_formats[state->pixfmt].reg_p_fmt; |
| 906 | struct v4l2_rect *r = &state->crop_source; |
| 907 | |
| 908 | s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0), |
| 909 | r->width, r->height, reg_fmt, |
| 910 | PCLK_MAX_FREQ >> 2, PCLK_MIN_FREQ >> 2, |
| 911 | PVI_MASK_MIPI, CLK_MIPI_INDEX, |
| 912 | FR_RATE_FIXED, FR_RATE_Q_DYNAMIC, |
| 913 | state->req_fiv, S5K5BAF_MIN_FR_TIME); |
| 914 | s5k5baf_hw_sync_cfg(state); |
| 915 | s5k5baf_hw_validate_cfg(state); |
| 916 | } |
| 917 | |
| 918 | |
| 919 | static void s5k5baf_hw_set_test_pattern(struct s5k5baf *state, int id) |
| 920 | { |
| 921 | s5k5baf_i2c_write(state, REG_PATTERN_WIDTH, 800); |
| 922 | s5k5baf_i2c_write(state, REG_PATTERN_HEIGHT, 511); |
| 923 | s5k5baf_i2c_write(state, REG_PATTERN_PARAM, 0); |
| 924 | s5k5baf_i2c_write(state, REG_PATTERN_SET, id); |
| 925 | } |
| 926 | |
| 927 | static void s5k5baf_gpio_assert(struct s5k5baf *state, int id) |
| 928 | { |
| 929 | struct s5k5baf_gpio *gpio = &state->gpios[id]; |
| 930 | |
| 931 | gpio_set_value(gpio->gpio, gpio->level); |
| 932 | } |
| 933 | |
| 934 | static void s5k5baf_gpio_deassert(struct s5k5baf *state, int id) |
| 935 | { |
| 936 | struct s5k5baf_gpio *gpio = &state->gpios[id]; |
| 937 | |
| 938 | gpio_set_value(gpio->gpio, !gpio->level); |
| 939 | } |
| 940 | |
| 941 | static int s5k5baf_power_on(struct s5k5baf *state) |
| 942 | { |
| 943 | int ret; |
| 944 | |
| 945 | ret = regulator_bulk_enable(S5K5BAF_NUM_SUPPLIES, state->supplies); |
| 946 | if (ret < 0) |
| 947 | goto err; |
| 948 | |
| 949 | ret = clk_set_rate(state->clock, state->mclk_frequency); |
| 950 | if (ret < 0) |
| 951 | goto err_reg_dis; |
| 952 | |
| 953 | ret = clk_prepare_enable(state->clock); |
| 954 | if (ret < 0) |
| 955 | goto err_reg_dis; |
| 956 | |
| 957 | v4l2_dbg(1, debug, &state->sd, "clock frequency: %ld\n", |
| 958 | clk_get_rate(state->clock)); |
| 959 | |
| 960 | s5k5baf_gpio_deassert(state, STBY); |
| 961 | usleep_range(50, 100); |
| 962 | s5k5baf_gpio_deassert(state, RST); |
| 963 | return 0; |
| 964 | |
| 965 | err_reg_dis: |
| 966 | regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES, state->supplies); |
| 967 | err: |
| 968 | v4l2_err(&state->sd, "%s() failed (%d)\n", __func__, ret); |
| 969 | return ret; |
| 970 | } |
| 971 | |
| 972 | static int s5k5baf_power_off(struct s5k5baf *state) |
| 973 | { |
| 974 | int ret; |
| 975 | |
| 976 | state->streaming = 0; |
| 977 | state->apply_cfg = 0; |
| 978 | state->apply_crop = 0; |
| 979 | |
| 980 | s5k5baf_gpio_assert(state, RST); |
| 981 | s5k5baf_gpio_assert(state, STBY); |
| 982 | |
| 983 | if (!IS_ERR(state->clock)) |
| 984 | clk_disable_unprepare(state->clock); |
| 985 | |
| 986 | ret = regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES, |
| 987 | state->supplies); |
| 988 | if (ret < 0) |
| 989 | v4l2_err(&state->sd, "failed to disable regulators\n"); |
| 990 | |
| 991 | return 0; |
| 992 | } |
| 993 | |
| 994 | static void s5k5baf_hw_init(struct s5k5baf *state) |
| 995 | { |
| 996 | s5k5baf_i2c_write(state, AHB_MSB_ADDR_PTR, PAGE_IF_HW); |
| 997 | s5k5baf_i2c_write(state, REG_CLEAR_HOST_INT, 0); |
| 998 | s5k5baf_i2c_write(state, REG_SW_LOAD_COMPLETE, 1); |
| 999 | s5k5baf_i2c_write(state, REG_CMDRD_PAGE, PAGE_IF_SW); |
| 1000 | s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW); |
| 1001 | } |
| 1002 | |
| 1003 | /* |
| 1004 | * V4L2 subdev core and video operations |
| 1005 | */ |
| 1006 | |
| 1007 | static void s5k5baf_initialize_data(struct s5k5baf *state) |
| 1008 | { |
| 1009 | state->pixfmt = 0; |
| 1010 | state->req_fiv = 10000 / 15; |
| 1011 | state->fiv = state->req_fiv; |
| 1012 | state->valid_auto_alg = 0; |
| 1013 | } |
| 1014 | |
| 1015 | static int s5k5baf_load_setfile(struct s5k5baf *state) |
| 1016 | { |
| 1017 | struct i2c_client *c = v4l2_get_subdevdata(&state->sd); |
| 1018 | const struct firmware *fw; |
| 1019 | int ret; |
| 1020 | |
| 1021 | ret = request_firmware(&fw, S5K5BAF_FW_FILENAME, &c->dev); |
| 1022 | if (ret < 0) { |
| 1023 | dev_warn(&c->dev, "firmware file (%s) not loaded\n", |
| 1024 | S5K5BAF_FW_FILENAME); |
| 1025 | return ret; |
| 1026 | } |
| 1027 | |
| 1028 | ret = s5k5baf_fw_parse(&c->dev, &state->fw, fw->size / 2, |
| 1029 | (u16 *)fw->data); |
| 1030 | |
| 1031 | release_firmware(fw); |
| 1032 | |
| 1033 | return ret; |
| 1034 | } |
| 1035 | |
| 1036 | static int s5k5baf_set_power(struct v4l2_subdev *sd, int on) |
| 1037 | { |
| 1038 | struct s5k5baf *state = to_s5k5baf(sd); |
| 1039 | int ret = 0; |
| 1040 | |
| 1041 | mutex_lock(&state->lock); |
| 1042 | |
| 1043 | if (!on != state->power) |
| 1044 | goto out; |
| 1045 | |
| 1046 | if (on) { |
| 1047 | if (state->fw == NULL) |
| 1048 | s5k5baf_load_setfile(state); |
| 1049 | |
| 1050 | s5k5baf_initialize_data(state); |
| 1051 | ret = s5k5baf_power_on(state); |
| 1052 | if (ret < 0) |
| 1053 | goto out; |
| 1054 | |
| 1055 | s5k5baf_hw_init(state); |
| 1056 | s5k5baf_hw_patch(state); |
| 1057 | s5k5baf_i2c_write(state, REG_SET_HOST_INT, 1); |
| 1058 | s5k5baf_hw_set_clocks(state); |
| 1059 | |
| 1060 | ret = s5k5baf_hw_set_video_bus(state); |
| 1061 | if (ret < 0) |
| 1062 | goto out; |
| 1063 | |
| 1064 | s5k5baf_hw_set_cis(state); |
| 1065 | s5k5baf_hw_set_ccm(state); |
| 1066 | |
| 1067 | ret = s5k5baf_clear_error(state); |
| 1068 | if (!ret) |
| 1069 | state->power++; |
| 1070 | } else { |
| 1071 | s5k5baf_power_off(state); |
| 1072 | state->power--; |
| 1073 | } |
| 1074 | |
| 1075 | out: |
| 1076 | mutex_unlock(&state->lock); |
| 1077 | |
| 1078 | if (!ret && on) |
| 1079 | ret = v4l2_ctrl_handler_setup(&state->ctrls.handler); |
| 1080 | |
| 1081 | return ret; |
| 1082 | } |
| 1083 | |
| 1084 | static void s5k5baf_hw_set_stream(struct s5k5baf *state, int enable) |
| 1085 | { |
| 1086 | s5k5baf_write_seq(state, REG_G_ENABLE_PREV, enable, 1); |
| 1087 | } |
| 1088 | |
| 1089 | static int s5k5baf_s_stream(struct v4l2_subdev *sd, int on) |
| 1090 | { |
| 1091 | struct s5k5baf *state = to_s5k5baf(sd); |
| 1092 | int ret; |
| 1093 | |
| 1094 | mutex_lock(&state->lock); |
| 1095 | |
| 1096 | if (state->streaming == !!on) { |
| 1097 | ret = 0; |
| 1098 | goto out; |
| 1099 | } |
| 1100 | |
| 1101 | if (on) { |
| 1102 | s5k5baf_hw_set_config(state); |
| 1103 | ret = s5k5baf_hw_set_crop_rects(state); |
| 1104 | if (ret < 0) |
| 1105 | goto out; |
| 1106 | s5k5baf_hw_set_stream(state, 1); |
| 1107 | s5k5baf_i2c_write(state, 0xb0cc, 0x000b); |
| 1108 | } else { |
| 1109 | s5k5baf_hw_set_stream(state, 0); |
| 1110 | } |
| 1111 | ret = s5k5baf_clear_error(state); |
| 1112 | if (!ret) |
| 1113 | state->streaming = !state->streaming; |
| 1114 | |
| 1115 | out: |
| 1116 | mutex_unlock(&state->lock); |
| 1117 | |
| 1118 | return ret; |
| 1119 | } |
| 1120 | |
| 1121 | static int s5k5baf_g_frame_interval(struct v4l2_subdev *sd, |
| 1122 | struct v4l2_subdev_frame_interval *fi) |
| 1123 | { |
| 1124 | struct s5k5baf *state = to_s5k5baf(sd); |
| 1125 | |
| 1126 | mutex_lock(&state->lock); |
| 1127 | fi->interval.numerator = state->fiv; |
| 1128 | fi->interval.denominator = 10000; |
| 1129 | mutex_unlock(&state->lock); |
| 1130 | |
| 1131 | return 0; |
| 1132 | } |
| 1133 | |
| 1134 | static void s5k5baf_set_frame_interval(struct s5k5baf *state, |
| 1135 | struct v4l2_subdev_frame_interval *fi) |
| 1136 | { |
| 1137 | struct v4l2_fract *i = &fi->interval; |
| 1138 | |
| 1139 | if (fi->interval.denominator == 0) |
| 1140 | state->req_fiv = S5K5BAF_MAX_FR_TIME; |
| 1141 | else |
| 1142 | state->req_fiv = clamp_t(u32, |
| 1143 | i->numerator * 10000 / i->denominator, |
| 1144 | S5K5BAF_MIN_FR_TIME, |
| 1145 | S5K5BAF_MAX_FR_TIME); |
| 1146 | |
| 1147 | state->fiv = state->req_fiv; |
| 1148 | if (state->apply_cfg) { |
| 1149 | s5k5baf_hw_set_fiv(state, state->req_fiv); |
| 1150 | s5k5baf_hw_validate_cfg(state); |
| 1151 | } |
| 1152 | *i = (struct v4l2_fract){ state->fiv, 10000 }; |
| 1153 | if (state->fiv == state->req_fiv) |
| 1154 | v4l2_info(&state->sd, "frame interval changed to %d00us\n", |
| 1155 | state->fiv); |
| 1156 | } |
| 1157 | |
| 1158 | static int s5k5baf_s_frame_interval(struct v4l2_subdev *sd, |
| 1159 | struct v4l2_subdev_frame_interval *fi) |
| 1160 | { |
| 1161 | struct s5k5baf *state = to_s5k5baf(sd); |
| 1162 | |
| 1163 | mutex_lock(&state->lock); |
| 1164 | s5k5baf_set_frame_interval(state, fi); |
| 1165 | mutex_unlock(&state->lock); |
| 1166 | return 0; |
| 1167 | } |
| 1168 | |
| 1169 | /* |
| 1170 | * V4L2 subdev pad level and video operations |
| 1171 | */ |
| 1172 | static int s5k5baf_enum_frame_interval(struct v4l2_subdev *sd, |
| 1173 | struct v4l2_subdev_fh *fh, |
| 1174 | struct v4l2_subdev_frame_interval_enum *fie) |
| 1175 | { |
| 1176 | if (fie->index > S5K5BAF_MAX_FR_TIME - S5K5BAF_MIN_FR_TIME || |
| 1177 | fie->pad != PAD_CIS) |
| 1178 | return -EINVAL; |
| 1179 | |
| 1180 | v4l_bound_align_image(&fie->width, S5K5BAF_WIN_WIDTH_MIN, |
| 1181 | S5K5BAF_CIS_WIDTH, 1, |
| 1182 | &fie->height, S5K5BAF_WIN_HEIGHT_MIN, |
| 1183 | S5K5BAF_CIS_HEIGHT, 1, 0); |
| 1184 | |
| 1185 | fie->interval.numerator = S5K5BAF_MIN_FR_TIME + fie->index; |
| 1186 | fie->interval.denominator = 10000; |
| 1187 | |
| 1188 | return 0; |
| 1189 | } |
| 1190 | |
| 1191 | static int s5k5baf_enum_mbus_code(struct v4l2_subdev *sd, |
| 1192 | struct v4l2_subdev_fh *fh, |
| 1193 | struct v4l2_subdev_mbus_code_enum *code) |
| 1194 | { |
| 1195 | if (code->pad == PAD_CIS) { |
| 1196 | if (code->index > 0) |
| 1197 | return -EINVAL; |
| 1198 | code->code = V4L2_MBUS_FMT_FIXED; |
| 1199 | return 0; |
| 1200 | } |
| 1201 | |
| 1202 | if (code->index >= ARRAY_SIZE(s5k5baf_formats)) |
| 1203 | return -EINVAL; |
| 1204 | |
| 1205 | code->code = s5k5baf_formats[code->index].code; |
| 1206 | return 0; |
| 1207 | } |
| 1208 | |
| 1209 | static int s5k5baf_enum_frame_size(struct v4l2_subdev *sd, |
| 1210 | struct v4l2_subdev_fh *fh, |
| 1211 | struct v4l2_subdev_frame_size_enum *fse) |
| 1212 | { |
| 1213 | int i; |
| 1214 | |
| 1215 | if (fse->index > 0) |
| 1216 | return -EINVAL; |
| 1217 | |
| 1218 | if (fse->pad == PAD_CIS) { |
| 1219 | fse->code = V4L2_MBUS_FMT_FIXED; |
| 1220 | fse->min_width = S5K5BAF_CIS_WIDTH; |
| 1221 | fse->max_width = S5K5BAF_CIS_WIDTH; |
| 1222 | fse->min_height = S5K5BAF_CIS_HEIGHT; |
| 1223 | fse->max_height = S5K5BAF_CIS_HEIGHT; |
| 1224 | return 0; |
| 1225 | } |
| 1226 | |
| 1227 | i = ARRAY_SIZE(s5k5baf_formats); |
| 1228 | while (--i) |
| 1229 | if (fse->code == s5k5baf_formats[i].code) |
| 1230 | break; |
| 1231 | fse->code = s5k5baf_formats[i].code; |
| 1232 | fse->min_width = S5K5BAF_WIN_WIDTH_MIN; |
| 1233 | fse->max_width = S5K5BAF_CIS_WIDTH; |
| 1234 | fse->max_height = S5K5BAF_WIN_HEIGHT_MIN; |
| 1235 | fse->min_height = S5K5BAF_CIS_HEIGHT; |
| 1236 | |
| 1237 | return 0; |
| 1238 | } |
| 1239 | |
| 1240 | static void s5k5baf_try_cis_format(struct v4l2_mbus_framefmt *mf) |
| 1241 | { |
| 1242 | mf->width = S5K5BAF_CIS_WIDTH; |
| 1243 | mf->height = S5K5BAF_CIS_HEIGHT; |
| 1244 | mf->code = V4L2_MBUS_FMT_FIXED; |
| 1245 | mf->colorspace = V4L2_COLORSPACE_JPEG; |
| 1246 | mf->field = V4L2_FIELD_NONE; |
| 1247 | } |
| 1248 | |
| 1249 | static int s5k5baf_try_isp_format(struct v4l2_mbus_framefmt *mf) |
| 1250 | { |
| 1251 | int pixfmt; |
| 1252 | |
| 1253 | v4l_bound_align_image(&mf->width, S5K5BAF_WIN_WIDTH_MIN, |
| 1254 | S5K5BAF_CIS_WIDTH, 1, |
| 1255 | &mf->height, S5K5BAF_WIN_HEIGHT_MIN, |
| 1256 | S5K5BAF_CIS_HEIGHT, 1, 0); |
| 1257 | |
| 1258 | pixfmt = s5k5baf_find_pixfmt(mf); |
| 1259 | |
| 1260 | mf->colorspace = s5k5baf_formats[pixfmt].colorspace; |
| 1261 | mf->code = s5k5baf_formats[pixfmt].code; |
| 1262 | mf->field = V4L2_FIELD_NONE; |
| 1263 | |
| 1264 | return pixfmt; |
| 1265 | } |
| 1266 | |
| 1267 | static int s5k5baf_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, |
| 1268 | struct v4l2_subdev_format *fmt) |
| 1269 | { |
| 1270 | struct s5k5baf *state = to_s5k5baf(sd); |
| 1271 | const struct s5k5baf_pixfmt *pixfmt; |
| 1272 | struct v4l2_mbus_framefmt *mf; |
| 1273 | |
| 1274 | if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { |
| 1275 | mf = v4l2_subdev_get_try_format(fh, fmt->pad); |
| 1276 | fmt->format = *mf; |
| 1277 | return 0; |
| 1278 | } |
| 1279 | |
| 1280 | mf = &fmt->format; |
| 1281 | if (fmt->pad == PAD_CIS) { |
| 1282 | s5k5baf_try_cis_format(mf); |
| 1283 | return 0; |
| 1284 | } |
| 1285 | mf->field = V4L2_FIELD_NONE; |
| 1286 | mutex_lock(&state->lock); |
| 1287 | pixfmt = &s5k5baf_formats[state->pixfmt]; |
| 1288 | mf->width = state->crop_source.width; |
| 1289 | mf->height = state->crop_source.height; |
| 1290 | mf->code = pixfmt->code; |
| 1291 | mf->colorspace = pixfmt->colorspace; |
| 1292 | mutex_unlock(&state->lock); |
| 1293 | |
| 1294 | return 0; |
| 1295 | } |
| 1296 | |
| 1297 | static int s5k5baf_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, |
| 1298 | struct v4l2_subdev_format *fmt) |
| 1299 | { |
| 1300 | struct v4l2_mbus_framefmt *mf = &fmt->format; |
| 1301 | struct s5k5baf *state = to_s5k5baf(sd); |
| 1302 | const struct s5k5baf_pixfmt *pixfmt; |
| 1303 | int ret = 0; |
| 1304 | |
| 1305 | if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { |
| 1306 | *v4l2_subdev_get_try_format(fh, fmt->pad) = *mf; |
| 1307 | return 0; |
| 1308 | } |
| 1309 | |
| 1310 | if (fmt->pad == PAD_CIS) { |
| 1311 | s5k5baf_try_cis_format(mf); |
| 1312 | return 0; |
| 1313 | } |
| 1314 | |
| 1315 | mutex_lock(&state->lock); |
| 1316 | |
| 1317 | if (state->streaming) { |
| 1318 | mutex_unlock(&state->lock); |
| 1319 | return -EBUSY; |
| 1320 | } |
| 1321 | |
| 1322 | state->pixfmt = s5k5baf_try_isp_format(mf); |
| 1323 | pixfmt = &s5k5baf_formats[state->pixfmt]; |
| 1324 | mf->code = pixfmt->code; |
| 1325 | mf->colorspace = pixfmt->colorspace; |
| 1326 | mf->width = state->crop_source.width; |
| 1327 | mf->height = state->crop_source.height; |
| 1328 | |
| 1329 | mutex_unlock(&state->lock); |
| 1330 | return ret; |
| 1331 | } |
| 1332 | |
| 1333 | enum selection_rect { R_CIS, R_CROP_SINK, R_COMPOSE, R_CROP_SOURCE, R_INVALID }; |
| 1334 | |
| 1335 | static enum selection_rect s5k5baf_get_sel_rect(u32 pad, u32 target) |
| 1336 | { |
| 1337 | switch (target) { |
| 1338 | case V4L2_SEL_TGT_CROP_BOUNDS: |
| 1339 | return pad ? R_COMPOSE : R_CIS; |
| 1340 | case V4L2_SEL_TGT_CROP: |
| 1341 | return pad ? R_CROP_SOURCE : R_CROP_SINK; |
| 1342 | case V4L2_SEL_TGT_COMPOSE_BOUNDS: |
| 1343 | return pad ? R_INVALID : R_CROP_SINK; |
| 1344 | case V4L2_SEL_TGT_COMPOSE: |
| 1345 | return pad ? R_INVALID : R_COMPOSE; |
| 1346 | default: |
| 1347 | return R_INVALID; |
| 1348 | } |
| 1349 | } |
| 1350 | |
| 1351 | static int s5k5baf_is_bound_target(u32 target) |
| 1352 | { |
| 1353 | return (target == V4L2_SEL_TGT_CROP_BOUNDS || |
| 1354 | target == V4L2_SEL_TGT_COMPOSE_BOUNDS); |
| 1355 | } |
| 1356 | |
| 1357 | static int s5k5baf_get_selection(struct v4l2_subdev *sd, |
| 1358 | struct v4l2_subdev_fh *fh, |
| 1359 | struct v4l2_subdev_selection *sel) |
| 1360 | { |
| 1361 | static enum selection_rect rtype; |
| 1362 | struct s5k5baf *state = to_s5k5baf(sd); |
| 1363 | |
| 1364 | rtype = s5k5baf_get_sel_rect(sel->pad, sel->target); |
| 1365 | |
| 1366 | switch (rtype) { |
| 1367 | case R_INVALID: |
| 1368 | return -EINVAL; |
| 1369 | case R_CIS: |
| 1370 | sel->r = s5k5baf_cis_rect; |
| 1371 | return 0; |
| 1372 | default: |
| 1373 | break; |
| 1374 | } |
| 1375 | |
| 1376 | if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { |
| 1377 | if (rtype == R_COMPOSE) |
| 1378 | sel->r = *v4l2_subdev_get_try_compose(fh, sel->pad); |
| 1379 | else |
| 1380 | sel->r = *v4l2_subdev_get_try_crop(fh, sel->pad); |
| 1381 | return 0; |
| 1382 | } |
| 1383 | |
| 1384 | mutex_lock(&state->lock); |
| 1385 | switch (rtype) { |
| 1386 | case R_CROP_SINK: |
| 1387 | sel->r = state->crop_sink; |
| 1388 | break; |
| 1389 | case R_COMPOSE: |
| 1390 | sel->r = state->compose; |
| 1391 | break; |
| 1392 | case R_CROP_SOURCE: |
| 1393 | sel->r = state->crop_source; |
| 1394 | break; |
| 1395 | default: |
| 1396 | break; |
| 1397 | } |
| 1398 | if (s5k5baf_is_bound_target(sel->target)) { |
| 1399 | sel->r.left = 0; |
| 1400 | sel->r.top = 0; |
| 1401 | } |
| 1402 | mutex_unlock(&state->lock); |
| 1403 | |
| 1404 | return 0; |
| 1405 | } |
| 1406 | |
| 1407 | /* bounds range [start, start+len) to [0, max) and aligns to 2 */ |
| 1408 | static void s5k5baf_bound_range(u32 *start, u32 *len, u32 max) |
| 1409 | { |
| 1410 | if (*len > max) |
| 1411 | *len = max; |
| 1412 | if (*start + *len > max) |
| 1413 | *start = max - *len; |
| 1414 | *start &= ~1; |
| 1415 | *len &= ~1; |
| 1416 | if (*len < S5K5BAF_WIN_WIDTH_MIN) |
| 1417 | *len = S5K5BAF_WIN_WIDTH_MIN; |
| 1418 | } |
| 1419 | |
| 1420 | static void s5k5baf_bound_rect(struct v4l2_rect *r, u32 width, u32 height) |
| 1421 | { |
| 1422 | s5k5baf_bound_range(&r->left, &r->width, width); |
| 1423 | s5k5baf_bound_range(&r->top, &r->height, height); |
| 1424 | } |
| 1425 | |
| 1426 | static void s5k5baf_set_rect_and_adjust(struct v4l2_rect **rects, |
| 1427 | enum selection_rect first, |
| 1428 | struct v4l2_rect *v) |
| 1429 | { |
| 1430 | struct v4l2_rect *r, *br; |
| 1431 | enum selection_rect i = first; |
| 1432 | |
| 1433 | *rects[first] = *v; |
| 1434 | do { |
| 1435 | r = rects[i]; |
| 1436 | br = rects[i - 1]; |
| 1437 | s5k5baf_bound_rect(r, br->width, br->height); |
| 1438 | } while (++i != R_INVALID); |
| 1439 | *v = *rects[first]; |
| 1440 | } |
| 1441 | |
| 1442 | static bool s5k5baf_cmp_rect(const struct v4l2_rect *r1, |
| 1443 | const struct v4l2_rect *r2) |
| 1444 | { |
| 1445 | return !memcmp(r1, r2, sizeof(*r1)); |
| 1446 | } |
| 1447 | |
| 1448 | static int s5k5baf_set_selection(struct v4l2_subdev *sd, |
| 1449 | struct v4l2_subdev_fh *fh, |
| 1450 | struct v4l2_subdev_selection *sel) |
| 1451 | { |
| 1452 | static enum selection_rect rtype; |
| 1453 | struct s5k5baf *state = to_s5k5baf(sd); |
| 1454 | struct v4l2_rect **rects; |
| 1455 | int ret = 0; |
| 1456 | |
| 1457 | rtype = s5k5baf_get_sel_rect(sel->pad, sel->target); |
| 1458 | if (rtype == R_INVALID || s5k5baf_is_bound_target(sel->target)) |
| 1459 | return -EINVAL; |
| 1460 | |
| 1461 | /* allow only scaling on compose */ |
| 1462 | if (rtype == R_COMPOSE) { |
| 1463 | sel->r.left = 0; |
| 1464 | sel->r.top = 0; |
| 1465 | } |
| 1466 | |
| 1467 | if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { |
| 1468 | rects = (struct v4l2_rect * []) { |
| 1469 | &s5k5baf_cis_rect, |
| 1470 | v4l2_subdev_get_try_crop(fh, PAD_CIS), |
| 1471 | v4l2_subdev_get_try_compose(fh, PAD_CIS), |
| 1472 | v4l2_subdev_get_try_crop(fh, PAD_OUT) |
| 1473 | }; |
| 1474 | s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r); |
| 1475 | return 0; |
| 1476 | } |
| 1477 | |
| 1478 | rects = (struct v4l2_rect * []) { |
| 1479 | &s5k5baf_cis_rect, |
| 1480 | &state->crop_sink, |
| 1481 | &state->compose, |
| 1482 | &state->crop_source |
| 1483 | }; |
| 1484 | mutex_lock(&state->lock); |
| 1485 | if (state->streaming) { |
| 1486 | /* adjust sel->r to avoid output resolution change */ |
| 1487 | if (rtype < R_CROP_SOURCE) { |
| 1488 | if (sel->r.width < state->crop_source.width) |
| 1489 | sel->r.width = state->crop_source.width; |
| 1490 | if (sel->r.height < state->crop_source.height) |
| 1491 | sel->r.height = state->crop_source.height; |
| 1492 | } else { |
| 1493 | sel->r.width = state->crop_source.width; |
| 1494 | sel->r.height = state->crop_source.height; |
| 1495 | } |
| 1496 | } |
| 1497 | s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r); |
| 1498 | if (!s5k5baf_cmp_rect(&state->crop_sink, &s5k5baf_cis_rect) || |
| 1499 | !s5k5baf_cmp_rect(&state->compose, &s5k5baf_cis_rect)) |
| 1500 | state->apply_crop = 1; |
| 1501 | if (state->streaming) |
| 1502 | ret = s5k5baf_hw_set_crop_rects(state); |
| 1503 | mutex_unlock(&state->lock); |
| 1504 | |
| 1505 | return ret; |
| 1506 | } |
| 1507 | |
| 1508 | static const struct v4l2_subdev_pad_ops s5k5baf_cis_pad_ops = { |
| 1509 | .enum_mbus_code = s5k5baf_enum_mbus_code, |
| 1510 | .enum_frame_size = s5k5baf_enum_frame_size, |
| 1511 | .get_fmt = s5k5baf_get_fmt, |
| 1512 | .set_fmt = s5k5baf_set_fmt, |
| 1513 | }; |
| 1514 | |
| 1515 | static const struct v4l2_subdev_pad_ops s5k5baf_pad_ops = { |
| 1516 | .enum_mbus_code = s5k5baf_enum_mbus_code, |
| 1517 | .enum_frame_size = s5k5baf_enum_frame_size, |
| 1518 | .enum_frame_interval = s5k5baf_enum_frame_interval, |
| 1519 | .get_fmt = s5k5baf_get_fmt, |
| 1520 | .set_fmt = s5k5baf_set_fmt, |
| 1521 | .get_selection = s5k5baf_get_selection, |
| 1522 | .set_selection = s5k5baf_set_selection, |
| 1523 | }; |
| 1524 | |
| 1525 | static const struct v4l2_subdev_video_ops s5k5baf_video_ops = { |
| 1526 | .g_frame_interval = s5k5baf_g_frame_interval, |
| 1527 | .s_frame_interval = s5k5baf_s_frame_interval, |
| 1528 | .s_stream = s5k5baf_s_stream, |
| 1529 | }; |
| 1530 | |
| 1531 | /* |
| 1532 | * V4L2 subdev controls |
| 1533 | */ |
| 1534 | |
| 1535 | static int s5k5baf_s_ctrl(struct v4l2_ctrl *ctrl) |
| 1536 | { |
| 1537 | struct v4l2_subdev *sd = ctrl_to_sd(ctrl); |
| 1538 | struct s5k5baf *state = to_s5k5baf(sd); |
| 1539 | int ret; |
| 1540 | |
| 1541 | v4l2_dbg(1, debug, sd, "ctrl: %s, value: %d\n", ctrl->name, ctrl->val); |
| 1542 | |
| 1543 | mutex_lock(&state->lock); |
| 1544 | |
| 1545 | if (state->power == 0) |
| 1546 | goto unlock; |
| 1547 | |
| 1548 | switch (ctrl->id) { |
| 1549 | case V4L2_CID_AUTO_WHITE_BALANCE: |
| 1550 | s5k5baf_hw_set_awb(state, ctrl->val); |
| 1551 | break; |
| 1552 | |
| 1553 | case V4L2_CID_BRIGHTNESS: |
| 1554 | s5k5baf_write(state, REG_USER_BRIGHTNESS, ctrl->val); |
| 1555 | break; |
| 1556 | |
| 1557 | case V4L2_CID_COLORFX: |
| 1558 | s5k5baf_hw_set_colorfx(state, ctrl->val); |
| 1559 | break; |
| 1560 | |
| 1561 | case V4L2_CID_CONTRAST: |
| 1562 | s5k5baf_write(state, REG_USER_CONTRAST, ctrl->val); |
| 1563 | break; |
| 1564 | |
| 1565 | case V4L2_CID_EXPOSURE_AUTO: |
| 1566 | s5k5baf_hw_set_auto_exposure(state, ctrl->val); |
| 1567 | break; |
| 1568 | |
| 1569 | case V4L2_CID_HFLIP: |
| 1570 | s5k5baf_hw_set_mirror(state); |
| 1571 | break; |
| 1572 | |
| 1573 | case V4L2_CID_POWER_LINE_FREQUENCY: |
| 1574 | s5k5baf_hw_set_anti_flicker(state, ctrl->val); |
| 1575 | break; |
| 1576 | |
| 1577 | case V4L2_CID_SATURATION: |
| 1578 | s5k5baf_write(state, REG_USER_SATURATION, ctrl->val); |
| 1579 | break; |
| 1580 | |
| 1581 | case V4L2_CID_SHARPNESS: |
| 1582 | s5k5baf_write(state, REG_USER_SHARPBLUR, ctrl->val); |
| 1583 | break; |
| 1584 | |
| 1585 | case V4L2_CID_WHITE_BALANCE_TEMPERATURE: |
| 1586 | s5k5baf_write(state, REG_P_COLORTEMP(0), ctrl->val); |
| 1587 | if (state->apply_cfg) |
| 1588 | s5k5baf_hw_sync_cfg(state); |
| 1589 | break; |
| 1590 | |
| 1591 | case V4L2_CID_TEST_PATTERN: |
| 1592 | s5k5baf_hw_set_test_pattern(state, ctrl->val); |
| 1593 | break; |
| 1594 | } |
| 1595 | unlock: |
| 1596 | ret = s5k5baf_clear_error(state); |
| 1597 | mutex_unlock(&state->lock); |
| 1598 | return ret; |
| 1599 | } |
| 1600 | |
| 1601 | static const struct v4l2_ctrl_ops s5k5baf_ctrl_ops = { |
| 1602 | .s_ctrl = s5k5baf_s_ctrl, |
| 1603 | }; |
| 1604 | |
| 1605 | static const char * const s5k5baf_test_pattern_menu[] = { |
| 1606 | "Disabled", |
| 1607 | "Blank", |
| 1608 | "Bars", |
| 1609 | "Gradients", |
| 1610 | "Textile", |
| 1611 | "Textile2", |
| 1612 | "Squares" |
| 1613 | }; |
| 1614 | |
| 1615 | static int s5k5baf_initialize_ctrls(struct s5k5baf *state) |
| 1616 | { |
| 1617 | const struct v4l2_ctrl_ops *ops = &s5k5baf_ctrl_ops; |
| 1618 | struct s5k5baf_ctrls *ctrls = &state->ctrls; |
| 1619 | struct v4l2_ctrl_handler *hdl = &ctrls->handler; |
| 1620 | int ret; |
| 1621 | |
| 1622 | ret = v4l2_ctrl_handler_init(hdl, 16); |
| 1623 | if (ret < 0) { |
| 1624 | v4l2_err(&state->sd, "cannot init ctrl handler (%d)\n", ret); |
| 1625 | return ret; |
| 1626 | } |
| 1627 | |
| 1628 | /* Auto white balance cluster */ |
| 1629 | ctrls->awb = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_WHITE_BALANCE, |
| 1630 | 0, 1, 1, 1); |
| 1631 | ctrls->gain_red = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE, |
| 1632 | 0, 255, 1, S5K5BAF_GAIN_RED_DEF); |
| 1633 | ctrls->gain_blue = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE, |
| 1634 | 0, 255, 1, S5K5BAF_GAIN_BLUE_DEF); |
| 1635 | v4l2_ctrl_auto_cluster(3, &ctrls->awb, 0, false); |
| 1636 | |
| 1637 | ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP, 0, 1, 1, 0); |
| 1638 | ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP, 0, 1, 1, 0); |
| 1639 | v4l2_ctrl_cluster(2, &ctrls->hflip); |
| 1640 | |
| 1641 | ctrls->auto_exp = v4l2_ctrl_new_std_menu(hdl, ops, |
| 1642 | V4L2_CID_EXPOSURE_AUTO, |
| 1643 | V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO); |
| 1644 | /* Exposure time: x 1 us */ |
| 1645 | ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE, |
| 1646 | 0, 6000000U, 1, 100000U); |
| 1647 | /* Total gain: 256 <=> 1x */ |
| 1648 | ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN, |
| 1649 | 0, 256, 1, 256); |
| 1650 | v4l2_ctrl_auto_cluster(3, &ctrls->auto_exp, 0, false); |
| 1651 | |
| 1652 | v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_POWER_LINE_FREQUENCY, |
| 1653 | V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0, |
| 1654 | V4L2_CID_POWER_LINE_FREQUENCY_AUTO); |
| 1655 | |
| 1656 | v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_COLORFX, |
| 1657 | V4L2_COLORFX_SKY_BLUE, ~0x6f, V4L2_COLORFX_NONE); |
| 1658 | |
| 1659 | v4l2_ctrl_new_std(hdl, ops, V4L2_CID_WHITE_BALANCE_TEMPERATURE, |
| 1660 | 0, 256, 1, 0); |
| 1661 | |
| 1662 | v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, -127, 127, 1, 0); |
| 1663 | v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -127, 127, 1, 0); |
| 1664 | v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -127, 127, 1, 0); |
| 1665 | v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS, -127, 127, 1, 0); |
| 1666 | |
| 1667 | v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN, |
| 1668 | ARRAY_SIZE(s5k5baf_test_pattern_menu) - 1, |
| 1669 | 0, 0, s5k5baf_test_pattern_menu); |
| 1670 | |
| 1671 | if (hdl->error) { |
| 1672 | v4l2_err(&state->sd, "error creating controls (%d)\n", |
| 1673 | hdl->error); |
| 1674 | ret = hdl->error; |
| 1675 | v4l2_ctrl_handler_free(hdl); |
| 1676 | return ret; |
| 1677 | } |
| 1678 | |
| 1679 | state->sd.ctrl_handler = hdl; |
| 1680 | return 0; |
| 1681 | } |
| 1682 | |
| 1683 | /* |
| 1684 | * V4L2 subdev internal operations |
| 1685 | */ |
| 1686 | static int s5k5baf_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) |
| 1687 | { |
| 1688 | struct v4l2_mbus_framefmt *mf; |
| 1689 | |
| 1690 | mf = v4l2_subdev_get_try_format(fh, PAD_CIS); |
| 1691 | s5k5baf_try_cis_format(mf); |
| 1692 | |
| 1693 | if (s5k5baf_is_cis_subdev(sd)) |
| 1694 | return 0; |
| 1695 | |
| 1696 | mf = v4l2_subdev_get_try_format(fh, PAD_OUT); |
| 1697 | mf->colorspace = s5k5baf_formats[0].colorspace; |
| 1698 | mf->code = s5k5baf_formats[0].code; |
| 1699 | mf->width = s5k5baf_cis_rect.width; |
| 1700 | mf->height = s5k5baf_cis_rect.height; |
| 1701 | mf->field = V4L2_FIELD_NONE; |
| 1702 | |
| 1703 | *v4l2_subdev_get_try_crop(fh, PAD_CIS) = s5k5baf_cis_rect; |
| 1704 | *v4l2_subdev_get_try_compose(fh, PAD_CIS) = s5k5baf_cis_rect; |
| 1705 | *v4l2_subdev_get_try_crop(fh, PAD_OUT) = s5k5baf_cis_rect; |
| 1706 | |
| 1707 | return 0; |
| 1708 | } |
| 1709 | |
| 1710 | static int s5k5baf_check_fw_revision(struct s5k5baf *state) |
| 1711 | { |
| 1712 | u16 api_ver = 0, fw_rev = 0, s_id = 0; |
| 1713 | int ret; |
| 1714 | |
| 1715 | api_ver = s5k5baf_read(state, REG_FW_APIVER); |
| 1716 | fw_rev = s5k5baf_read(state, REG_FW_REVISION) & 0xff; |
| 1717 | s_id = s5k5baf_read(state, REG_FW_SENSOR_ID); |
| 1718 | ret = s5k5baf_clear_error(state); |
| 1719 | if (ret < 0) |
| 1720 | return ret; |
| 1721 | |
| 1722 | v4l2_info(&state->sd, "FW API=%#x, revision=%#x sensor_id=%#x\n", |
| 1723 | api_ver, fw_rev, s_id); |
| 1724 | |
| 1725 | if (api_ver != S5K5BAF_FW_APIVER) { |
| 1726 | v4l2_err(&state->sd, "FW API version not supported\n"); |
| 1727 | return -ENODEV; |
| 1728 | } |
| 1729 | |
| 1730 | return 0; |
| 1731 | } |
| 1732 | |
| 1733 | static int s5k5baf_registered(struct v4l2_subdev *sd) |
| 1734 | { |
| 1735 | struct s5k5baf *state = to_s5k5baf(sd); |
| 1736 | int ret; |
| 1737 | |
| 1738 | ret = v4l2_device_register_subdev(sd->v4l2_dev, &state->cis_sd); |
| 1739 | if (ret < 0) |
| 1740 | v4l2_err(sd, "failed to register subdev %s\n", |
| 1741 | state->cis_sd.name); |
| 1742 | else |
| 1743 | ret = media_entity_create_link(&state->cis_sd.entity, PAD_CIS, |
| 1744 | &state->sd.entity, PAD_CIS, |
| 1745 | MEDIA_LNK_FL_IMMUTABLE | |
| 1746 | MEDIA_LNK_FL_ENABLED); |
| 1747 | return ret; |
| 1748 | } |
| 1749 | |
| 1750 | static void s5k5baf_unregistered(struct v4l2_subdev *sd) |
| 1751 | { |
| 1752 | struct s5k5baf *state = to_s5k5baf(sd); |
| 1753 | v4l2_device_unregister_subdev(&state->cis_sd); |
| 1754 | } |
| 1755 | |
| 1756 | static const struct v4l2_subdev_ops s5k5baf_cis_subdev_ops = { |
| 1757 | .pad = &s5k5baf_cis_pad_ops, |
| 1758 | }; |
| 1759 | |
| 1760 | static const struct v4l2_subdev_internal_ops s5k5baf_cis_subdev_internal_ops = { |
| 1761 | .open = s5k5baf_open, |
| 1762 | }; |
| 1763 | |
| 1764 | static const struct v4l2_subdev_internal_ops s5k5baf_subdev_internal_ops = { |
| 1765 | .registered = s5k5baf_registered, |
| 1766 | .unregistered = s5k5baf_unregistered, |
| 1767 | .open = s5k5baf_open, |
| 1768 | }; |
| 1769 | |
| 1770 | static const struct v4l2_subdev_core_ops s5k5baf_core_ops = { |
| 1771 | .s_power = s5k5baf_set_power, |
| 1772 | .log_status = v4l2_ctrl_subdev_log_status, |
| 1773 | }; |
| 1774 | |
| 1775 | static const struct v4l2_subdev_ops s5k5baf_subdev_ops = { |
| 1776 | .core = &s5k5baf_core_ops, |
| 1777 | .pad = &s5k5baf_pad_ops, |
| 1778 | .video = &s5k5baf_video_ops, |
| 1779 | }; |
| 1780 | |
| 1781 | static int s5k5baf_configure_gpios(struct s5k5baf *state) |
| 1782 | { |
| 1783 | static const char const *name[] = { "S5K5BAF_STBY", "S5K5BAF_RST" }; |
| 1784 | struct i2c_client *c = v4l2_get_subdevdata(&state->sd); |
| 1785 | struct s5k5baf_gpio *g = state->gpios; |
| 1786 | int ret, i; |
| 1787 | |
| 1788 | for (i = 0; i < NUM_GPIOS; ++i) { |
| 1789 | int flags = GPIOF_DIR_OUT; |
| 1790 | if (g[i].level) |
| 1791 | flags |= GPIOF_INIT_HIGH; |
| 1792 | ret = devm_gpio_request_one(&c->dev, g[i].gpio, flags, name[i]); |
| 1793 | if (ret < 0) { |
| 1794 | v4l2_err(c, "failed to request gpio %s\n", name[i]); |
| 1795 | return ret; |
| 1796 | } |
| 1797 | } |
| 1798 | return 0; |
| 1799 | } |
| 1800 | |
| 1801 | static int s5k5baf_parse_gpios(struct s5k5baf_gpio *gpios, struct device *dev) |
| 1802 | { |
| 1803 | static const char * const names[] = { |
| 1804 | "stbyn-gpios", |
| 1805 | "rstn-gpios", |
| 1806 | }; |
| 1807 | struct device_node *node = dev->of_node; |
| 1808 | enum of_gpio_flags flags; |
| 1809 | int ret, i; |
| 1810 | |
| 1811 | for (i = 0; i < NUM_GPIOS; ++i) { |
| 1812 | ret = of_get_named_gpio_flags(node, names[i], 0, &flags); |
| 1813 | if (ret < 0) { |
| 1814 | dev_err(dev, "no %s GPIO pin provided\n", names[i]); |
| 1815 | return ret; |
| 1816 | } |
| 1817 | gpios[i].gpio = ret; |
| 1818 | gpios[i].level = !(flags & OF_GPIO_ACTIVE_LOW); |
| 1819 | } |
| 1820 | |
| 1821 | return 0; |
| 1822 | } |
| 1823 | |
| 1824 | static int s5k5baf_parse_device_node(struct s5k5baf *state, struct device *dev) |
| 1825 | { |
| 1826 | struct device_node *node = dev->of_node; |
| 1827 | struct device_node *node_ep; |
| 1828 | struct v4l2_of_endpoint ep; |
| 1829 | int ret; |
| 1830 | |
| 1831 | if (!node) { |
| 1832 | dev_err(dev, "no device-tree node provided\n"); |
| 1833 | return -EINVAL; |
| 1834 | } |
| 1835 | |
| 1836 | ret = of_property_read_u32(node, "clock-frequency", |
| 1837 | &state->mclk_frequency); |
| 1838 | if (ret < 0) { |
| 1839 | state->mclk_frequency = S5K5BAF_DEFAULT_MCLK_FREQ; |
| 1840 | dev_info(dev, "using default %u Hz clock frequency\n", |
| 1841 | state->mclk_frequency); |
| 1842 | } |
| 1843 | |
| 1844 | ret = s5k5baf_parse_gpios(state->gpios, dev); |
| 1845 | if (ret < 0) |
| 1846 | return ret; |
| 1847 | |
| 1848 | node_ep = v4l2_of_get_next_endpoint(node, NULL); |
| 1849 | if (!node_ep) { |
| 1850 | dev_err(dev, "no endpoint defined at node %s\n", |
| 1851 | node->full_name); |
| 1852 | return -EINVAL; |
| 1853 | } |
| 1854 | |
| 1855 | v4l2_of_parse_endpoint(node_ep, &ep); |
| 1856 | of_node_put(node_ep); |
| 1857 | state->bus_type = ep.bus_type; |
| 1858 | |
| 1859 | switch (state->bus_type) { |
| 1860 | case V4L2_MBUS_CSI2: |
| 1861 | state->nlanes = ep.bus.mipi_csi2.num_data_lanes; |
| 1862 | break; |
| 1863 | case V4L2_MBUS_PARALLEL: |
| 1864 | break; |
| 1865 | default: |
| 1866 | dev_err(dev, "unsupported bus in endpoint defined at node %s\n", |
| 1867 | node->full_name); |
| 1868 | return -EINVAL; |
| 1869 | } |
| 1870 | |
| 1871 | return 0; |
| 1872 | } |
| 1873 | |
| 1874 | static int s5k5baf_configure_subdevs(struct s5k5baf *state, |
| 1875 | struct i2c_client *c) |
| 1876 | { |
| 1877 | struct v4l2_subdev *sd; |
| 1878 | int ret; |
| 1879 | |
| 1880 | sd = &state->cis_sd; |
| 1881 | v4l2_subdev_init(sd, &s5k5baf_cis_subdev_ops); |
| 1882 | sd->owner = THIS_MODULE; |
| 1883 | v4l2_set_subdevdata(sd, state); |
| 1884 | snprintf(sd->name, sizeof(sd->name), "S5K5BAF-CIS %d-%04x", |
| 1885 | i2c_adapter_id(c->adapter), c->addr); |
| 1886 | |
| 1887 | sd->internal_ops = &s5k5baf_cis_subdev_internal_ops; |
| 1888 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
| 1889 | |
| 1890 | state->cis_pad.flags = MEDIA_PAD_FL_SOURCE; |
| 1891 | sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR; |
| 1892 | ret = media_entity_init(&sd->entity, NUM_CIS_PADS, &state->cis_pad, 0); |
| 1893 | if (ret < 0) |
| 1894 | goto err; |
| 1895 | |
| 1896 | sd = &state->sd; |
| 1897 | v4l2_i2c_subdev_init(sd, c, &s5k5baf_subdev_ops); |
| 1898 | snprintf(sd->name, sizeof(sd->name), "S5K5BAF-ISP %d-%04x", |
| 1899 | i2c_adapter_id(c->adapter), c->addr); |
| 1900 | |
| 1901 | sd->internal_ops = &s5k5baf_subdev_internal_ops; |
| 1902 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
| 1903 | |
| 1904 | state->pads[PAD_CIS].flags = MEDIA_PAD_FL_SINK; |
| 1905 | state->pads[PAD_OUT].flags = MEDIA_PAD_FL_SOURCE; |
| 1906 | sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV; |
| 1907 | ret = media_entity_init(&sd->entity, NUM_ISP_PADS, state->pads, 0); |
| 1908 | |
| 1909 | if (!ret) |
| 1910 | return 0; |
| 1911 | |
| 1912 | media_entity_cleanup(&state->cis_sd.entity); |
| 1913 | err: |
| 1914 | dev_err(&c->dev, "cannot init media entity %s\n", sd->name); |
| 1915 | return ret; |
| 1916 | } |
| 1917 | |
| 1918 | static int s5k5baf_configure_regulators(struct s5k5baf *state) |
| 1919 | { |
| 1920 | struct i2c_client *c = v4l2_get_subdevdata(&state->sd); |
| 1921 | int ret; |
| 1922 | int i; |
| 1923 | |
| 1924 | for (i = 0; i < S5K5BAF_NUM_SUPPLIES; i++) |
| 1925 | state->supplies[i].supply = s5k5baf_supply_names[i]; |
| 1926 | |
| 1927 | ret = devm_regulator_bulk_get(&c->dev, S5K5BAF_NUM_SUPPLIES, |
| 1928 | state->supplies); |
| 1929 | if (ret < 0) |
| 1930 | v4l2_err(c, "failed to get regulators\n"); |
| 1931 | return ret; |
| 1932 | } |
| 1933 | |
| 1934 | static int s5k5baf_probe(struct i2c_client *c, |
| 1935 | const struct i2c_device_id *id) |
| 1936 | { |
| 1937 | struct s5k5baf *state; |
| 1938 | int ret; |
| 1939 | |
| 1940 | state = devm_kzalloc(&c->dev, sizeof(*state), GFP_KERNEL); |
| 1941 | if (!state) |
| 1942 | return -ENOMEM; |
| 1943 | |
| 1944 | mutex_init(&state->lock); |
| 1945 | state->crop_sink = s5k5baf_cis_rect; |
| 1946 | state->compose = s5k5baf_cis_rect; |
| 1947 | state->crop_source = s5k5baf_cis_rect; |
| 1948 | |
| 1949 | ret = s5k5baf_parse_device_node(state, &c->dev); |
| 1950 | if (ret < 0) |
| 1951 | return ret; |
| 1952 | |
| 1953 | ret = s5k5baf_configure_subdevs(state, c); |
| 1954 | if (ret < 0) |
| 1955 | return ret; |
| 1956 | |
| 1957 | ret = s5k5baf_configure_gpios(state); |
| 1958 | if (ret < 0) |
| 1959 | goto err_me; |
| 1960 | |
| 1961 | ret = s5k5baf_configure_regulators(state); |
| 1962 | if (ret < 0) |
| 1963 | goto err_me; |
| 1964 | |
| 1965 | state->clock = devm_clk_get(state->sd.dev, S5K5BAF_CLK_NAME); |
| 1966 | if (IS_ERR(state->clock)) { |
| 1967 | ret = -EPROBE_DEFER; |
| 1968 | goto err_me; |
| 1969 | } |
| 1970 | |
| 1971 | ret = s5k5baf_power_on(state); |
| 1972 | if (ret < 0) { |
| 1973 | ret = -EPROBE_DEFER; |
| 1974 | goto err_me; |
| 1975 | } |
| 1976 | s5k5baf_hw_init(state); |
| 1977 | ret = s5k5baf_check_fw_revision(state); |
| 1978 | |
| 1979 | s5k5baf_power_off(state); |
| 1980 | if (ret < 0) |
| 1981 | goto err_me; |
| 1982 | |
| 1983 | ret = s5k5baf_initialize_ctrls(state); |
| 1984 | if (ret < 0) |
| 1985 | goto err_me; |
| 1986 | |
| 1987 | ret = v4l2_async_register_subdev(&state->sd); |
| 1988 | if (ret < 0) |
| 1989 | goto err_ctrl; |
| 1990 | |
| 1991 | return 0; |
| 1992 | |
| 1993 | err_ctrl: |
| 1994 | v4l2_ctrl_handler_free(state->sd.ctrl_handler); |
| 1995 | err_me: |
| 1996 | media_entity_cleanup(&state->sd.entity); |
| 1997 | media_entity_cleanup(&state->cis_sd.entity); |
| 1998 | return ret; |
| 1999 | } |
| 2000 | |
| 2001 | static int s5k5baf_remove(struct i2c_client *c) |
| 2002 | { |
| 2003 | struct v4l2_subdev *sd = i2c_get_clientdata(c); |
| 2004 | struct s5k5baf *state = to_s5k5baf(sd); |
| 2005 | |
| 2006 | v4l2_async_unregister_subdev(sd); |
| 2007 | v4l2_ctrl_handler_free(sd->ctrl_handler); |
| 2008 | media_entity_cleanup(&sd->entity); |
| 2009 | |
| 2010 | sd = &state->cis_sd; |
| 2011 | v4l2_device_unregister_subdev(sd); |
| 2012 | media_entity_cleanup(&sd->entity); |
| 2013 | |
| 2014 | return 0; |
| 2015 | } |
| 2016 | |
| 2017 | static const struct i2c_device_id s5k5baf_id[] = { |
| 2018 | { S5K5BAF_DRIVER_NAME, 0 }, |
| 2019 | { }, |
| 2020 | }; |
| 2021 | MODULE_DEVICE_TABLE(i2c, s5k5baf_id); |
| 2022 | |
| 2023 | static const struct of_device_id s5k5baf_of_match[] = { |
| 2024 | { .compatible = "samsung,s5k5baf" }, |
| 2025 | { } |
| 2026 | }; |
| 2027 | MODULE_DEVICE_TABLE(of, s5k5baf_of_match); |
| 2028 | |
| 2029 | static struct i2c_driver s5k5baf_i2c_driver = { |
| 2030 | .driver = { |
| 2031 | .of_match_table = s5k5baf_of_match, |
| 2032 | .name = S5K5BAF_DRIVER_NAME |
| 2033 | }, |
| 2034 | .probe = s5k5baf_probe, |
| 2035 | .remove = s5k5baf_remove, |
| 2036 | .id_table = s5k5baf_id, |
| 2037 | }; |
| 2038 | |
| 2039 | module_i2c_driver(s5k5baf_i2c_driver); |
| 2040 | |
| 2041 | MODULE_DESCRIPTION("Samsung S5K5BAF(X) UXGA camera driver"); |
| 2042 | MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); |
| 2043 | MODULE_LICENSE("GPL v2"); |