blob: 0a806924b90671e212ebad90f7680fe873109a2f [file] [log] [blame]
Grant Likelyca632f52011-06-06 01:16:30 -06001/*
Jassi Brar230d42d2009-11-30 07:39:42 +00002 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/workqueue.h>
Mark Brownc2573122011-11-10 10:57:32 +000023#include <linux/interrupt.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000024#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/dma-mapping.h>
Arnd Bergmann78843722013-04-11 22:42:03 +020027#include <linux/dmaengine.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000028#include <linux/platform_device.h>
Mark Brownb97b6622011-12-04 00:58:06 +000029#include <linux/pm_runtime.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000030#include <linux/spi/spi.h>
Thomas Abraham1c20c202012-07-13 07:15:14 +090031#include <linux/gpio.h>
Thomas Abraham2b908072012-07-13 07:15:15 +090032#include <linux/of.h>
33#include <linux/of_gpio.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000034
Arnd Bergmann436d42c2012-08-24 15:22:12 +020035#include <linux/platform_data/spi-s3c64xx.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000036
Mark Brown563b4442013-04-18 18:06:05 +010037#ifdef CONFIG_S3C_DMA
Arnd Bergmann78843722013-04-11 22:42:03 +020038#include <mach/dma.h>
39#endif
40
Thomas Abrahama5238e32012-07-13 07:15:14 +090041#define MAX_SPI_PORTS 3
Girish K S7e995552013-05-20 12:21:32 +053042#define S3C64XX_SPI_QUIRK_POLL (1 << 0)
Thomas Abrahama5238e32012-07-13 07:15:14 +090043
Jassi Brar230d42d2009-11-30 07:39:42 +000044/* Registers and bit-fields */
45
46#define S3C64XX_SPI_CH_CFG 0x00
47#define S3C64XX_SPI_CLK_CFG 0x04
48#define S3C64XX_SPI_MODE_CFG 0x08
49#define S3C64XX_SPI_SLAVE_SEL 0x0C
50#define S3C64XX_SPI_INT_EN 0x10
51#define S3C64XX_SPI_STATUS 0x14
52#define S3C64XX_SPI_TX_DATA 0x18
53#define S3C64XX_SPI_RX_DATA 0x1C
54#define S3C64XX_SPI_PACKET_CNT 0x20
55#define S3C64XX_SPI_PENDING_CLR 0x24
56#define S3C64XX_SPI_SWAP_CFG 0x28
57#define S3C64XX_SPI_FB_CLK 0x2C
58
59#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
60#define S3C64XX_SPI_CH_SW_RST (1<<5)
61#define S3C64XX_SPI_CH_SLAVE (1<<4)
62#define S3C64XX_SPI_CPOL_L (1<<3)
63#define S3C64XX_SPI_CPHA_B (1<<2)
64#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
65#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
66
67#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
68#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
69#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
Jingoo Han75bf3362013-01-31 15:25:01 +090070#define S3C64XX_SPI_PSR_MASK 0xff
Jassi Brar230d42d2009-11-30 07:39:42 +000071
72#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
73#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
74#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
75#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
76#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
77#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
78#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
79#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
80#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
81#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
82#define S3C64XX_SPI_MODE_4BURST (1<<0)
83
84#define S3C64XX_SPI_SLAVE_AUTO (1<<1)
85#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
86
Jassi Brar230d42d2009-11-30 07:39:42 +000087#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
88#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
89#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
90#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
91#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
92#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
93#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
94
95#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
96#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
97#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
98#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
99#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
100#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
101
102#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
103
104#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
105#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
106#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
107#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
108#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
109
110#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
111#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
112#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
113#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
114#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
115#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
116#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
117#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
118
119#define S3C64XX_SPI_FBCLK_MSK (3<<0)
120
Thomas Abrahama5238e32012-07-13 07:15:14 +0900121#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
122#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
123 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
124#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
125#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
126 FIFO_LVL_MASK(i))
Jassi Brar230d42d2009-11-30 07:39:42 +0000127
128#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
129#define S3C64XX_SPI_TRAILCNT_OFF 19
130
131#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
132
133#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
Girish K S7e995552013-05-20 12:21:32 +0530134#define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
Jassi Brar230d42d2009-11-30 07:39:42 +0000135
Jassi Brar230d42d2009-11-30 07:39:42 +0000136#define RXBUSY (1<<2)
137#define TXBUSY (1<<3)
138
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900139struct s3c64xx_spi_dma_data {
Arnd Bergmann78843722013-04-11 22:42:03 +0200140 struct dma_chan *ch;
Arnd Bergmannc10356b2012-04-30 16:31:27 +0000141 enum dma_transfer_direction direction;
Arnd Bergmann78843722013-04-11 22:42:03 +0200142 unsigned int dmach;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900143};
144
Jassi Brar230d42d2009-11-30 07:39:42 +0000145/**
Thomas Abrahama5238e32012-07-13 07:15:14 +0900146 * struct s3c64xx_spi_info - SPI Controller hardware info
147 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
148 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
149 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
150 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
151 * @clk_from_cmu: True, if the controller does not include a clock mux and
152 * prescaler unit.
153 *
154 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
155 * differ in some aspects such as the size of the fifo and spi bus clock
156 * setup. Such differences are specified to the driver using this structure
157 * which is provided as driver data to the driver.
158 */
159struct s3c64xx_spi_port_config {
160 int fifo_lvl_mask[MAX_SPI_PORTS];
161 int rx_lvl_offset;
162 int tx_st_done;
Girish K S7e995552013-05-20 12:21:32 +0530163 int quirks;
Thomas Abrahama5238e32012-07-13 07:15:14 +0900164 bool high_speed;
165 bool clk_from_cmu;
166};
167
168/**
Jassi Brar230d42d2009-11-30 07:39:42 +0000169 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
170 * @clk: Pointer to the spi clock.
Jassi Brarb0d5d6e2010-01-20 13:49:44 -0700171 * @src_clk: Pointer to the clock used to generate SPI signals.
Jassi Brar230d42d2009-11-30 07:39:42 +0000172 * @master: Pointer to the SPI Protocol master.
Jassi Brar230d42d2009-11-30 07:39:42 +0000173 * @cntrlr_info: Platform specific data for the controller this driver manages.
174 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
Jassi Brar230d42d2009-11-30 07:39:42 +0000175 * @queue: To log SPI xfer requests.
176 * @lock: Controller specific lock.
177 * @state: Set of FLAGS to indicate status.
178 * @rx_dmach: Controller's DMA channel for Rx.
179 * @tx_dmach: Controller's DMA channel for Tx.
180 * @sfr_start: BUS address of SPI controller regs.
181 * @regs: Pointer to ioremap'ed controller registers.
Mark Brownc2573122011-11-10 10:57:32 +0000182 * @irq: interrupt
Jassi Brar230d42d2009-11-30 07:39:42 +0000183 * @xfer_completion: To indicate completion of xfer task.
184 * @cur_mode: Stores the active configuration of the controller.
185 * @cur_bpw: Stores the active bits per word settings.
186 * @cur_speed: Stores the active xfer clock speed.
187 */
188struct s3c64xx_spi_driver_data {
189 void __iomem *regs;
190 struct clk *clk;
Jassi Brarb0d5d6e2010-01-20 13:49:44 -0700191 struct clk *src_clk;
Jassi Brar230d42d2009-11-30 07:39:42 +0000192 struct platform_device *pdev;
193 struct spi_master *master;
Jassi Brarad7de722010-01-20 13:49:44 -0700194 struct s3c64xx_spi_info *cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000195 struct spi_device *tgl_spi;
Jassi Brar230d42d2009-11-30 07:39:42 +0000196 struct list_head queue;
197 spinlock_t lock;
Jassi Brar230d42d2009-11-30 07:39:42 +0000198 unsigned long sfr_start;
199 struct completion xfer_completion;
200 unsigned state;
201 unsigned cur_mode, cur_bpw;
202 unsigned cur_speed;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900203 struct s3c64xx_spi_dma_data rx_dma;
204 struct s3c64xx_spi_dma_data tx_dma;
Mark Brown563b4442013-04-18 18:06:05 +0100205#ifdef CONFIG_S3C_DMA
Boojin Kim39d3e802011-09-02 09:44:41 +0900206 struct samsung_dma_ops *ops;
Arnd Bergmann78843722013-04-11 22:42:03 +0200207#endif
Thomas Abrahama5238e32012-07-13 07:15:14 +0900208 struct s3c64xx_spi_port_config *port_conf;
209 unsigned int port_id;
Thomas Abraham2b908072012-07-13 07:15:15 +0900210 unsigned long gpios[4];
Jassi Brar230d42d2009-11-30 07:39:42 +0000211};
212
Jassi Brar230d42d2009-11-30 07:39:42 +0000213static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
214{
Jassi Brar230d42d2009-11-30 07:39:42 +0000215 void __iomem *regs = sdd->regs;
216 unsigned long loops;
217 u32 val;
218
219 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
220
221 val = readl(regs + S3C64XX_SPI_CH_CFG);
Kyoungil Kim7d859ff2012-05-23 21:29:51 +0900222 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
223 writel(val, regs + S3C64XX_SPI_CH_CFG);
224
225 val = readl(regs + S3C64XX_SPI_CH_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000226 val |= S3C64XX_SPI_CH_SW_RST;
227 val &= ~S3C64XX_SPI_CH_HS_EN;
228 writel(val, regs + S3C64XX_SPI_CH_CFG);
229
230 /* Flush TxFIFO*/
231 loops = msecs_to_loops(1);
232 do {
233 val = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900234 } while (TX_FIFO_LVL(val, sdd) && loops--);
Jassi Brar230d42d2009-11-30 07:39:42 +0000235
Mark Brownbe7852a2010-08-23 17:40:56 +0100236 if (loops == 0)
237 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
238
Jassi Brar230d42d2009-11-30 07:39:42 +0000239 /* Flush RxFIFO*/
240 loops = msecs_to_loops(1);
241 do {
242 val = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900243 if (RX_FIFO_LVL(val, sdd))
Jassi Brar230d42d2009-11-30 07:39:42 +0000244 readl(regs + S3C64XX_SPI_RX_DATA);
245 else
246 break;
247 } while (loops--);
248
Mark Brownbe7852a2010-08-23 17:40:56 +0100249 if (loops == 0)
250 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
251
Jassi Brar230d42d2009-11-30 07:39:42 +0000252 val = readl(regs + S3C64XX_SPI_CH_CFG);
253 val &= ~S3C64XX_SPI_CH_SW_RST;
254 writel(val, regs + S3C64XX_SPI_CH_CFG);
255
256 val = readl(regs + S3C64XX_SPI_MODE_CFG);
257 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
258 writel(val, regs + S3C64XX_SPI_MODE_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000259}
260
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900261static void s3c64xx_spi_dmacb(void *data)
Boojin Kim39d3e802011-09-02 09:44:41 +0900262{
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900263 struct s3c64xx_spi_driver_data *sdd;
264 struct s3c64xx_spi_dma_data *dma = data;
Boojin Kim39d3e802011-09-02 09:44:41 +0900265 unsigned long flags;
266
Kyoungil Kim054ebcc2012-03-10 09:48:46 +0900267 if (dma->direction == DMA_DEV_TO_MEM)
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900268 sdd = container_of(data,
269 struct s3c64xx_spi_driver_data, rx_dma);
270 else
271 sdd = container_of(data,
272 struct s3c64xx_spi_driver_data, tx_dma);
273
Boojin Kim39d3e802011-09-02 09:44:41 +0900274 spin_lock_irqsave(&sdd->lock, flags);
275
Kyoungil Kim054ebcc2012-03-10 09:48:46 +0900276 if (dma->direction == DMA_DEV_TO_MEM) {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900277 sdd->state &= ~RXBUSY;
278 if (!(sdd->state & TXBUSY))
279 complete(&sdd->xfer_completion);
280 } else {
281 sdd->state &= ~TXBUSY;
282 if (!(sdd->state & RXBUSY))
283 complete(&sdd->xfer_completion);
284 }
Boojin Kim39d3e802011-09-02 09:44:41 +0900285
286 spin_unlock_irqrestore(&sdd->lock, flags);
287}
288
Mark Brown563b4442013-04-18 18:06:05 +0100289#ifdef CONFIG_S3C_DMA
Arnd Bergmann78843722013-04-11 22:42:03 +0200290/* FIXME: remove this section once arch/arm/mach-s3c64xx uses dmaengine */
291
292static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
293 .name = "samsung-spi-dma",
294};
295
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900296static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
297 unsigned len, dma_addr_t buf)
Boojin Kim39d3e802011-09-02 09:44:41 +0900298{
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900299 struct s3c64xx_spi_driver_data *sdd;
Boojin Kim4969c322012-06-19 13:27:03 +0900300 struct samsung_dma_prep info;
301 struct samsung_dma_config config;
Boojin Kim39d3e802011-09-02 09:44:41 +0900302
Boojin Kim4969c322012-06-19 13:27:03 +0900303 if (dma->direction == DMA_DEV_TO_MEM) {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900304 sdd = container_of((void *)dma,
305 struct s3c64xx_spi_driver_data, rx_dma);
Boojin Kim4969c322012-06-19 13:27:03 +0900306 config.direction = sdd->rx_dma.direction;
307 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
308 config.width = sdd->cur_bpw / 8;
Arnd Bergmann78843722013-04-11 22:42:03 +0200309 sdd->ops->config((enum dma_ch)sdd->rx_dma.ch, &config);
Boojin Kim4969c322012-06-19 13:27:03 +0900310 } else {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900311 sdd = container_of((void *)dma,
312 struct s3c64xx_spi_driver_data, tx_dma);
Boojin Kim4969c322012-06-19 13:27:03 +0900313 config.direction = sdd->tx_dma.direction;
314 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
315 config.width = sdd->cur_bpw / 8;
Arnd Bergmann78843722013-04-11 22:42:03 +0200316 sdd->ops->config((enum dma_ch)sdd->tx_dma.ch, &config);
Boojin Kim4969c322012-06-19 13:27:03 +0900317 }
Boojin Kim39d3e802011-09-02 09:44:41 +0900318
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900319 info.cap = DMA_SLAVE;
320 info.len = len;
321 info.fp = s3c64xx_spi_dmacb;
322 info.fp_param = dma;
323 info.direction = dma->direction;
324 info.buf = buf;
Boojin Kim39d3e802011-09-02 09:44:41 +0900325
Arnd Bergmann78843722013-04-11 22:42:03 +0200326 sdd->ops->prepare((enum dma_ch)dma->ch, &info);
327 sdd->ops->trigger((enum dma_ch)dma->ch);
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900328}
329
330static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
331{
Boojin Kim4969c322012-06-19 13:27:03 +0900332 struct samsung_dma_req req;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +0530333 struct device *dev = &sdd->pdev->dev;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900334
335 sdd->ops = samsung_dma_get_ops();
336
Boojin Kim4969c322012-06-19 13:27:03 +0900337 req.cap = DMA_SLAVE;
338 req.client = &s3c64xx_spi_dma_client;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900339
Arnd Bergmann78843722013-04-11 22:42:03 +0200340 sdd->rx_dma.ch = (void *)sdd->ops->request(sdd->rx_dma.dmach, &req, dev, "rx");
341 sdd->tx_dma.ch = (void *)sdd->ops->request(sdd->tx_dma.dmach, &req, dev, "tx");
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900342
343 return 1;
Boojin Kim39d3e802011-09-02 09:44:41 +0900344}
345
Arnd Bergmann78843722013-04-11 22:42:03 +0200346static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
347{
348 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
349
Girish K S7e995552013-05-20 12:21:32 +0530350 /*
351 * If DMA resource was not available during
352 * probe, no need to continue with dma requests
353 * else Acquire DMA channels
354 */
355 while (!is_polling(sdd) && !acquire_dma(sdd))
Arnd Bergmann78843722013-04-11 22:42:03 +0200356 usleep_range(10000, 11000);
357
358 pm_runtime_get_sync(&sdd->pdev->dev);
359
360 return 0;
361}
362
363static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
364{
365 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
366
367 /* Free DMA channels */
Girish K S7e995552013-05-20 12:21:32 +0530368 if (!is_polling(sdd)) {
369 sdd->ops->release((enum dma_ch)sdd->rx_dma.ch,
370 &s3c64xx_spi_dma_client);
371 sdd->ops->release((enum dma_ch)sdd->tx_dma.ch,
372 &s3c64xx_spi_dma_client);
373 }
Arnd Bergmann78843722013-04-11 22:42:03 +0200374 pm_runtime_put(&sdd->pdev->dev);
375
376 return 0;
377}
378
379static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
380 struct s3c64xx_spi_dma_data *dma)
381{
382 sdd->ops->stop((enum dma_ch)dma->ch);
383}
384#else
385
386static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
387 unsigned len, dma_addr_t buf)
388{
389 struct s3c64xx_spi_driver_data *sdd;
390 struct dma_slave_config config;
391 struct scatterlist sg;
392 struct dma_async_tx_descriptor *desc;
393
394 if (dma->direction == DMA_DEV_TO_MEM) {
395 sdd = container_of((void *)dma,
396 struct s3c64xx_spi_driver_data, rx_dma);
397 config.direction = dma->direction;
398 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
399 config.src_addr_width = sdd->cur_bpw / 8;
400 config.src_maxburst = 1;
401 dmaengine_slave_config(dma->ch, &config);
402 } else {
403 sdd = container_of((void *)dma,
404 struct s3c64xx_spi_driver_data, tx_dma);
405 config.direction = dma->direction;
406 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
407 config.dst_addr_width = sdd->cur_bpw / 8;
408 config.dst_maxburst = 1;
409 dmaengine_slave_config(dma->ch, &config);
410 }
411
412 sg_init_table(&sg, 1);
413 sg_dma_len(&sg) = len;
414 sg_set_page(&sg, pfn_to_page(PFN_DOWN(buf)),
415 len, offset_in_page(buf));
416 sg_dma_address(&sg) = buf;
417
418 desc = dmaengine_prep_slave_sg(dma->ch,
419 &sg, 1, dma->direction, DMA_PREP_INTERRUPT);
420
421 desc->callback = s3c64xx_spi_dmacb;
422 desc->callback_param = dma;
423
424 dmaengine_submit(desc);
425 dma_async_issue_pending(dma->ch);
426}
427
428static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
429{
430 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
431 dma_filter_fn filter = sdd->cntrlr_info->filter;
432 struct device *dev = &sdd->pdev->dev;
433 dma_cap_mask_t mask;
Mark Brownfb9d0442013-04-18 18:12:00 +0100434 int ret;
Arnd Bergmann78843722013-04-11 22:42:03 +0200435
436 dma_cap_zero(mask);
437 dma_cap_set(DMA_SLAVE, mask);
438
439 /* Acquire DMA channels */
440 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
441 (void*)sdd->rx_dma.dmach, dev, "rx");
Mark Brownfb9d0442013-04-18 18:12:00 +0100442 if (!sdd->rx_dma.ch) {
443 dev_err(dev, "Failed to get RX DMA channel\n");
444 ret = -EBUSY;
445 goto out;
446 }
447
Arnd Bergmann78843722013-04-11 22:42:03 +0200448 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
449 (void*)sdd->tx_dma.dmach, dev, "tx");
Mark Brownfb9d0442013-04-18 18:12:00 +0100450 if (!sdd->tx_dma.ch) {
451 dev_err(dev, "Failed to get TX DMA channel\n");
452 ret = -EBUSY;
453 goto out_rx;
454 }
455
456 ret = pm_runtime_get_sync(&sdd->pdev->dev);
457 if (ret != 0) {
458 dev_err(dev, "Failed to enable device: %d\n", ret);
459 goto out_tx;
460 }
Arnd Bergmann78843722013-04-11 22:42:03 +0200461
462 return 0;
Mark Brownfb9d0442013-04-18 18:12:00 +0100463
464out_tx:
465 dma_release_channel(sdd->tx_dma.ch);
466out_rx:
467 dma_release_channel(sdd->rx_dma.ch);
468out:
469 return ret;
Arnd Bergmann78843722013-04-11 22:42:03 +0200470}
471
472static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
473{
474 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
475
476 /* Free DMA channels */
Girish K S7e995552013-05-20 12:21:32 +0530477 if (!is_polling(sdd)) {
478 dma_release_channel(sdd->rx_dma.ch);
479 dma_release_channel(sdd->tx_dma.ch);
480 }
Arnd Bergmann78843722013-04-11 22:42:03 +0200481
482 pm_runtime_put(&sdd->pdev->dev);
483 return 0;
484}
485
486static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
487 struct s3c64xx_spi_dma_data *dma)
488{
489 dmaengine_terminate_all(dma->ch);
490}
491#endif
492
Jassi Brar230d42d2009-11-30 07:39:42 +0000493static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
494 struct spi_device *spi,
495 struct spi_transfer *xfer, int dma_mode)
496{
Jassi Brar230d42d2009-11-30 07:39:42 +0000497 void __iomem *regs = sdd->regs;
498 u32 modecfg, chcfg;
499
500 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
501 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
502
503 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
504 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
505
506 if (dma_mode) {
507 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
508 } else {
509 /* Always shift in data in FIFO, even if xfer is Tx only,
510 * this helps setting PCKT_CNT value for generating clocks
511 * as exactly needed.
512 */
513 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
514 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
515 | S3C64XX_SPI_PACKET_CNT_EN,
516 regs + S3C64XX_SPI_PACKET_CNT);
517 }
518
519 if (xfer->tx_buf != NULL) {
520 sdd->state |= TXBUSY;
521 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
522 if (dma_mode) {
523 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900524 prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000525 } else {
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900526 switch (sdd->cur_bpw) {
527 case 32:
528 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
529 xfer->tx_buf, xfer->len / 4);
530 break;
531 case 16:
532 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
533 xfer->tx_buf, xfer->len / 2);
534 break;
535 default:
536 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
537 xfer->tx_buf, xfer->len);
538 break;
539 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000540 }
541 }
542
543 if (xfer->rx_buf != NULL) {
544 sdd->state |= RXBUSY;
545
Thomas Abrahama5238e32012-07-13 07:15:14 +0900546 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
Jassi Brar230d42d2009-11-30 07:39:42 +0000547 && !(sdd->cur_mode & SPI_CPHA))
548 chcfg |= S3C64XX_SPI_CH_HS_EN;
549
550 if (dma_mode) {
551 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
552 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
553 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
554 | S3C64XX_SPI_PACKET_CNT_EN,
555 regs + S3C64XX_SPI_PACKET_CNT);
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900556 prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000557 }
558 }
559
560 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
561 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
562}
563
564static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
565 struct spi_device *spi)
566{
567 struct s3c64xx_spi_csinfo *cs;
568
569 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
570 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
571 /* Deselect the last toggled device */
572 cs = sdd->tgl_spi->controller_data;
Thomas Abraham1c20c202012-07-13 07:15:14 +0900573 gpio_set_value(cs->line,
574 spi->mode & SPI_CS_HIGH ? 0 : 1);
Jassi Brar230d42d2009-11-30 07:39:42 +0000575 }
576 sdd->tgl_spi = NULL;
577 }
578
579 cs = spi->controller_data;
Thomas Abraham1c20c202012-07-13 07:15:14 +0900580 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
Girish K S7e995552013-05-20 12:21:32 +0530581
582 /* Start the signals */
583 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
584}
585
586static u32 wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
587 int timeout_ms)
588{
589 void __iomem *regs = sdd->regs;
590 unsigned long val = 1;
591 u32 status;
592
593 /* max fifo depth available */
594 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
595
596 if (timeout_ms)
597 val = msecs_to_loops(timeout_ms);
598
599 do {
600 status = readl(regs + S3C64XX_SPI_STATUS);
601 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
602
603 /* return the actual received data length */
604 return RX_FIFO_LVL(status, sdd);
Jassi Brar230d42d2009-11-30 07:39:42 +0000605}
606
607static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
608 struct spi_transfer *xfer, int dma_mode)
609{
Jassi Brar230d42d2009-11-30 07:39:42 +0000610 void __iomem *regs = sdd->regs;
611 unsigned long val;
612 int ms;
613
614 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
615 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
Mark Brown9d8f86b2010-09-07 16:37:52 +0100616 ms += 10; /* some tolerance */
Jassi Brar230d42d2009-11-30 07:39:42 +0000617
618 if (dma_mode) {
619 val = msecs_to_jiffies(ms) + 10;
620 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
621 } else {
Jassi Brarc3f139b2010-09-03 10:36:46 +0900622 u32 status;
Jassi Brar230d42d2009-11-30 07:39:42 +0000623 val = msecs_to_loops(ms);
624 do {
Jassi Brarc3f139b2010-09-03 10:36:46 +0900625 status = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900626 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
Jassi Brar230d42d2009-11-30 07:39:42 +0000627 }
628
Jassi Brar230d42d2009-11-30 07:39:42 +0000629 if (dma_mode) {
630 u32 status;
631
632 /*
Girish K S7e995552013-05-20 12:21:32 +0530633 * If the previous xfer was completed within timeout, then
634 * proceed further else return -EIO.
Jassi Brar230d42d2009-11-30 07:39:42 +0000635 * DmaTx returns after simply writing data in the FIFO,
636 * w/o waiting for real transmission on the bus to finish.
637 * DmaRx returns only after Dma read data from FIFO which
638 * needs bus transmission to finish, so we don't worry if
639 * Xfer involved Rx(with or without Tx).
640 */
Girish K S7e995552013-05-20 12:21:32 +0530641 if (val && !xfer->rx_buf) {
Jassi Brar230d42d2009-11-30 07:39:42 +0000642 val = msecs_to_loops(10);
643 status = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900644 while ((TX_FIFO_LVL(status, sdd)
645 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
Jassi Brar230d42d2009-11-30 07:39:42 +0000646 && --val) {
647 cpu_relax();
648 status = readl(regs + S3C64XX_SPI_STATUS);
649 }
650
Jassi Brar230d42d2009-11-30 07:39:42 +0000651 }
Girish K S7e995552013-05-20 12:21:32 +0530652
653 /* If timed out while checking rx/tx status return error */
654 if (!val)
655 return -EIO;
Jassi Brar230d42d2009-11-30 07:39:42 +0000656 } else {
Girish K S7e995552013-05-20 12:21:32 +0530657 int loops;
658 u32 cpy_len;
659 u8 *buf;
660
Jassi Brar230d42d2009-11-30 07:39:42 +0000661 /* If it was only Tx */
Girish K S7e995552013-05-20 12:21:32 +0530662 if (!xfer->rx_buf) {
Jassi Brar230d42d2009-11-30 07:39:42 +0000663 sdd->state &= ~TXBUSY;
664 return 0;
665 }
666
Girish K S7e995552013-05-20 12:21:32 +0530667 /*
668 * If the receive length is bigger than the controller fifo
669 * size, calculate the loops and read the fifo as many times.
670 * loops = length / max fifo size (calculated by using the
671 * fifo mask).
672 * For any size less than the fifo size the below code is
673 * executed atleast once.
674 */
675 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
676 buf = xfer->rx_buf;
677 do {
678 /* wait for data to be received in the fifo */
679 cpy_len = wait_for_timeout(sdd, (loops ? ms : 0));
680
681 switch (sdd->cur_bpw) {
682 case 32:
683 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
684 buf, cpy_len / 4);
685 break;
686 case 16:
687 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
688 buf, cpy_len / 2);
689 break;
690 default:
691 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
692 buf, cpy_len);
693 break;
694 }
695
696 buf = buf + cpy_len;
697 } while (loops--);
Jassi Brar230d42d2009-11-30 07:39:42 +0000698 sdd->state &= ~RXBUSY;
699 }
700
701 return 0;
702}
703
704static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
705 struct spi_device *spi)
706{
707 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
708
709 if (sdd->tgl_spi == spi)
710 sdd->tgl_spi = NULL;
711
Thomas Abraham1c20c202012-07-13 07:15:14 +0900712 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
Girish K S7e995552013-05-20 12:21:32 +0530713
714 /* Quiese the signals */
715 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Jassi Brar230d42d2009-11-30 07:39:42 +0000716}
717
718static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
719{
Jassi Brar230d42d2009-11-30 07:39:42 +0000720 void __iomem *regs = sdd->regs;
721 u32 val;
722
723 /* Disable Clock */
Thomas Abrahama5238e32012-07-13 07:15:14 +0900724 if (sdd->port_conf->clk_from_cmu) {
Thomas Abraham9f667bf2012-10-03 08:30:12 +0900725 clk_disable_unprepare(sdd->src_clk);
Jassi Brarb42a81c2010-09-29 17:31:33 +0900726 } else {
727 val = readl(regs + S3C64XX_SPI_CLK_CFG);
728 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
729 writel(val, regs + S3C64XX_SPI_CLK_CFG);
730 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000731
732 /* Set Polarity and Phase */
733 val = readl(regs + S3C64XX_SPI_CH_CFG);
734 val &= ~(S3C64XX_SPI_CH_SLAVE |
735 S3C64XX_SPI_CPOL_L |
736 S3C64XX_SPI_CPHA_B);
737
738 if (sdd->cur_mode & SPI_CPOL)
739 val |= S3C64XX_SPI_CPOL_L;
740
741 if (sdd->cur_mode & SPI_CPHA)
742 val |= S3C64XX_SPI_CPHA_B;
743
744 writel(val, regs + S3C64XX_SPI_CH_CFG);
745
746 /* Set Channel & DMA Mode */
747 val = readl(regs + S3C64XX_SPI_MODE_CFG);
748 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
749 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
750
751 switch (sdd->cur_bpw) {
752 case 32:
753 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900754 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
Jassi Brar230d42d2009-11-30 07:39:42 +0000755 break;
756 case 16:
757 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900758 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
Jassi Brar230d42d2009-11-30 07:39:42 +0000759 break;
760 default:
761 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900762 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
Jassi Brar230d42d2009-11-30 07:39:42 +0000763 break;
764 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000765
766 writel(val, regs + S3C64XX_SPI_MODE_CFG);
767
Thomas Abrahama5238e32012-07-13 07:15:14 +0900768 if (sdd->port_conf->clk_from_cmu) {
Jassi Brarb42a81c2010-09-29 17:31:33 +0900769 /* Configure Clock */
770 /* There is half-multiplier before the SPI */
771 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
772 /* Enable Clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +0900773 clk_prepare_enable(sdd->src_clk);
Jassi Brarb42a81c2010-09-29 17:31:33 +0900774 } else {
775 /* Configure Clock */
776 val = readl(regs + S3C64XX_SPI_CLK_CFG);
777 val &= ~S3C64XX_SPI_PSR_MASK;
778 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
779 & S3C64XX_SPI_PSR_MASK);
780 writel(val, regs + S3C64XX_SPI_CLK_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000781
Jassi Brarb42a81c2010-09-29 17:31:33 +0900782 /* Enable Clock */
783 val = readl(regs + S3C64XX_SPI_CLK_CFG);
784 val |= S3C64XX_SPI_ENCLK_ENABLE;
785 writel(val, regs + S3C64XX_SPI_CLK_CFG);
786 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000787}
788
Jassi Brar230d42d2009-11-30 07:39:42 +0000789#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
790
791static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
792 struct spi_message *msg)
793{
794 struct device *dev = &sdd->pdev->dev;
795 struct spi_transfer *xfer;
796
Girish K S7e995552013-05-20 12:21:32 +0530797 if (is_polling(sdd) || msg->is_dma_mapped)
Jassi Brar230d42d2009-11-30 07:39:42 +0000798 return 0;
799
800 /* First mark all xfer unmapped */
801 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
802 xfer->rx_dma = XFER_DMAADDR_INVALID;
803 xfer->tx_dma = XFER_DMAADDR_INVALID;
804 }
805
806 /* Map until end or first fail */
807 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
808
Thomas Abrahama5238e32012-07-13 07:15:14 +0900809 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
Jassi Brare02ddd42010-09-29 17:31:31 +0900810 continue;
811
Jassi Brar230d42d2009-11-30 07:39:42 +0000812 if (xfer->tx_buf != NULL) {
Jassi Brar251ee472010-09-03 10:36:26 +0900813 xfer->tx_dma = dma_map_single(dev,
814 (void *)xfer->tx_buf, xfer->len,
815 DMA_TO_DEVICE);
Jassi Brar230d42d2009-11-30 07:39:42 +0000816 if (dma_mapping_error(dev, xfer->tx_dma)) {
817 dev_err(dev, "dma_map_single Tx failed\n");
818 xfer->tx_dma = XFER_DMAADDR_INVALID;
819 return -ENOMEM;
820 }
821 }
822
823 if (xfer->rx_buf != NULL) {
824 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
825 xfer->len, DMA_FROM_DEVICE);
826 if (dma_mapping_error(dev, xfer->rx_dma)) {
827 dev_err(dev, "dma_map_single Rx failed\n");
828 dma_unmap_single(dev, xfer->tx_dma,
829 xfer->len, DMA_TO_DEVICE);
830 xfer->tx_dma = XFER_DMAADDR_INVALID;
831 xfer->rx_dma = XFER_DMAADDR_INVALID;
832 return -ENOMEM;
833 }
834 }
835 }
836
837 return 0;
838}
839
840static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
841 struct spi_message *msg)
842{
843 struct device *dev = &sdd->pdev->dev;
844 struct spi_transfer *xfer;
845
Girish K S7e995552013-05-20 12:21:32 +0530846 if (is_polling(sdd) || msg->is_dma_mapped)
Jassi Brar230d42d2009-11-30 07:39:42 +0000847 return;
848
849 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
850
Thomas Abrahama5238e32012-07-13 07:15:14 +0900851 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
Jassi Brare02ddd42010-09-29 17:31:31 +0900852 continue;
853
Jassi Brar230d42d2009-11-30 07:39:42 +0000854 if (xfer->rx_buf != NULL
855 && xfer->rx_dma != XFER_DMAADDR_INVALID)
856 dma_unmap_single(dev, xfer->rx_dma,
857 xfer->len, DMA_FROM_DEVICE);
858
859 if (xfer->tx_buf != NULL
860 && xfer->tx_dma != XFER_DMAADDR_INVALID)
861 dma_unmap_single(dev, xfer->tx_dma,
862 xfer->len, DMA_TO_DEVICE);
863 }
864}
865
Mark Brownad2a99a2012-02-15 14:48:32 -0800866static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
867 struct spi_message *msg)
Jassi Brar230d42d2009-11-30 07:39:42 +0000868{
Mark Brownad2a99a2012-02-15 14:48:32 -0800869 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +0000870 struct spi_device *spi = msg->spi;
871 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
872 struct spi_transfer *xfer;
873 int status = 0, cs_toggle = 0;
874 u32 speed;
875 u8 bpw;
876
877 /* If Master's(controller) state differs from that needed by Slave */
878 if (sdd->cur_speed != spi->max_speed_hz
879 || sdd->cur_mode != spi->mode
880 || sdd->cur_bpw != spi->bits_per_word) {
881 sdd->cur_bpw = spi->bits_per_word;
882 sdd->cur_speed = spi->max_speed_hz;
883 sdd->cur_mode = spi->mode;
884 s3c64xx_spi_config(sdd);
885 }
886
887 /* Map all the transfers if needed */
888 if (s3c64xx_spi_map_mssg(sdd, msg)) {
889 dev_err(&spi->dev,
890 "Xfer: Unable to map message buffers!\n");
891 status = -ENOMEM;
892 goto out;
893 }
894
895 /* Configure feedback delay */
896 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
897
898 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
899
900 unsigned long flags;
901 int use_dma;
902
903 INIT_COMPLETION(sdd->xfer_completion);
904
905 /* Only BPW and Speed may change across transfers */
Laxman Dewangan766ed702012-12-18 14:25:43 +0530906 bpw = xfer->bits_per_word;
Jassi Brar230d42d2009-11-30 07:39:42 +0000907 speed = xfer->speed_hz ? : spi->max_speed_hz;
908
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900909 if (xfer->len % (bpw / 8)) {
910 dev_err(&spi->dev,
911 "Xfer length(%u) not a multiple of word size(%u)\n",
912 xfer->len, bpw / 8);
913 status = -EIO;
914 goto out;
915 }
916
Jassi Brar230d42d2009-11-30 07:39:42 +0000917 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
918 sdd->cur_bpw = bpw;
919 sdd->cur_speed = speed;
920 s3c64xx_spi_config(sdd);
921 }
922
923 /* Polling method for xfers not bigger than FIFO capacity */
Arnd Bergmann78843722013-04-11 22:42:03 +0200924 use_dma = 0;
Girish K S7e995552013-05-20 12:21:32 +0530925 if (!is_polling(sdd) &&
926 (sdd->rx_dma.ch && sdd->tx_dma.ch &&
927 (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
Jassi Brar230d42d2009-11-30 07:39:42 +0000928 use_dma = 1;
929
930 spin_lock_irqsave(&sdd->lock, flags);
931
932 /* Pending only which is to be done */
933 sdd->state &= ~RXBUSY;
934 sdd->state &= ~TXBUSY;
935
936 enable_datapath(sdd, spi, xfer, use_dma);
937
938 /* Slave Select */
939 enable_cs(sdd, spi);
940
Jassi Brar230d42d2009-11-30 07:39:42 +0000941 spin_unlock_irqrestore(&sdd->lock, flags);
942
943 status = wait_for_xfer(sdd, xfer, use_dma);
944
Jassi Brar230d42d2009-11-30 07:39:42 +0000945 if (status) {
Jingoo Han75bf3362013-01-31 15:25:01 +0900946 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
Jassi Brar230d42d2009-11-30 07:39:42 +0000947 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
948 (sdd->state & RXBUSY) ? 'f' : 'p',
949 (sdd->state & TXBUSY) ? 'f' : 'p',
950 xfer->len);
951
952 if (use_dma) {
953 if (xfer->tx_buf != NULL
954 && (sdd->state & TXBUSY))
Arnd Bergmann78843722013-04-11 22:42:03 +0200955 s3c64xx_spi_dma_stop(sdd, &sdd->tx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000956 if (xfer->rx_buf != NULL
957 && (sdd->state & RXBUSY))
Arnd Bergmann78843722013-04-11 22:42:03 +0200958 s3c64xx_spi_dma_stop(sdd, &sdd->rx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000959 }
960
961 goto out;
962 }
963
964 if (xfer->delay_usecs)
965 udelay(xfer->delay_usecs);
966
967 if (xfer->cs_change) {
968 /* Hint that the next mssg is gonna be
969 for the same device */
970 if (list_is_last(&xfer->transfer_list,
971 &msg->transfers))
972 cs_toggle = 1;
Jassi Brar230d42d2009-11-30 07:39:42 +0000973 }
974
975 msg->actual_length += xfer->len;
976
977 flush_fifo(sdd);
978 }
979
980out:
981 if (!cs_toggle || status)
982 disable_cs(sdd, spi);
983 else
984 sdd->tgl_spi = spi;
985
986 s3c64xx_spi_unmap_mssg(sdd, msg);
987
988 msg->status = status;
989
Mark Brownad2a99a2012-02-15 14:48:32 -0800990 spi_finalize_current_message(master);
991
992 return 0;
Jassi Brar230d42d2009-11-30 07:39:42 +0000993}
994
Thomas Abraham2b908072012-07-13 07:15:15 +0900995static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
Thomas Abraham2b908072012-07-13 07:15:15 +0900996 struct spi_device *spi)
997{
998 struct s3c64xx_spi_csinfo *cs;
Arnd Bergmann4732cc62012-08-04 11:18:20 +0000999 struct device_node *slave_np, *data_np = NULL;
Thomas Abraham2b908072012-07-13 07:15:15 +09001000 u32 fb_delay = 0;
1001
1002 slave_np = spi->dev.of_node;
1003 if (!slave_np) {
1004 dev_err(&spi->dev, "device node not found\n");
1005 return ERR_PTR(-EINVAL);
1006 }
1007
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +01001008 data_np = of_get_child_by_name(slave_np, "controller-data");
Thomas Abraham2b908072012-07-13 07:15:15 +09001009 if (!data_np) {
1010 dev_err(&spi->dev, "child node 'controller-data' not found\n");
1011 return ERR_PTR(-EINVAL);
1012 }
1013
1014 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
1015 if (!cs) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001016 dev_err(&spi->dev, "could not allocate memory for controller data\n");
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +01001017 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +09001018 return ERR_PTR(-ENOMEM);
1019 }
1020
1021 cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
1022 if (!gpio_is_valid(cs->line)) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001023 dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
Thomas Abraham2b908072012-07-13 07:15:15 +09001024 kfree(cs);
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +01001025 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +09001026 return ERR_PTR(-EINVAL);
1027 }
1028
1029 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
1030 cs->fb_delay = fb_delay;
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +01001031 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +09001032 return cs;
1033}
1034
Jassi Brar230d42d2009-11-30 07:39:42 +00001035/*
1036 * Here we only check the validity of requested configuration
1037 * and save the configuration in a local data-structure.
1038 * The controller is actually configured only just before we
1039 * get a message to transfer.
1040 */
1041static int s3c64xx_spi_setup(struct spi_device *spi)
1042{
1043 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
1044 struct s3c64xx_spi_driver_data *sdd;
Jassi Brarad7de722010-01-20 13:49:44 -07001045 struct s3c64xx_spi_info *sci;
Jassi Brar230d42d2009-11-30 07:39:42 +00001046 struct spi_message *msg;
Jassi Brar230d42d2009-11-30 07:39:42 +00001047 unsigned long flags;
Thomas Abraham2b908072012-07-13 07:15:15 +09001048 int err;
Jassi Brar230d42d2009-11-30 07:39:42 +00001049
Thomas Abraham2b908072012-07-13 07:15:15 +09001050 sdd = spi_master_get_devdata(spi->master);
1051 if (!cs && spi->dev.of_node) {
Matthias Brugger5c725b32013-03-26 10:27:35 +01001052 cs = s3c64xx_get_slave_ctrldata(spi);
Thomas Abraham2b908072012-07-13 07:15:15 +09001053 spi->controller_data = cs;
1054 }
1055
1056 if (IS_ERR_OR_NULL(cs)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001057 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
1058 return -ENODEV;
1059 }
1060
Thomas Abraham1c20c202012-07-13 07:15:14 +09001061 if (!spi_get_ctldata(spi)) {
Mark Brown707214d2012-07-19 14:36:16 +09001062 err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
1063 dev_name(&spi->dev));
Thomas Abraham1c20c202012-07-13 07:15:14 +09001064 if (err) {
Mark Brown49f3eac2012-07-19 14:36:13 +09001065 dev_err(&spi->dev,
1066 "Failed to get /CS gpio [%d]: %d\n",
1067 cs->line, err);
Thomas Abraham2b908072012-07-13 07:15:15 +09001068 goto err_gpio_req;
Thomas Abraham1c20c202012-07-13 07:15:14 +09001069 }
1070 spi_set_ctldata(spi, cs);
1071 }
1072
Jassi Brar230d42d2009-11-30 07:39:42 +00001073 sci = sdd->cntrlr_info;
1074
1075 spin_lock_irqsave(&sdd->lock, flags);
1076
1077 list_for_each_entry(msg, &sdd->queue, queue) {
1078 /* Is some mssg is already queued for this device */
1079 if (msg->spi == spi) {
1080 dev_err(&spi->dev,
1081 "setup: attempt while mssg in queue!\n");
1082 spin_unlock_irqrestore(&sdd->lock, flags);
Thomas Abraham2b908072012-07-13 07:15:15 +09001083 err = -EBUSY;
1084 goto err_msgq;
Jassi Brar230d42d2009-11-30 07:39:42 +00001085 }
1086 }
1087
Jassi Brar230d42d2009-11-30 07:39:42 +00001088 spin_unlock_irqrestore(&sdd->lock, flags);
1089
Mark Brownb97b6622011-12-04 00:58:06 +00001090 pm_runtime_get_sync(&sdd->pdev->dev);
1091
Jassi Brar230d42d2009-11-30 07:39:42 +00001092 /* Check if we can provide the requested rate */
Thomas Abrahama5238e32012-07-13 07:15:14 +09001093 if (!sdd->port_conf->clk_from_cmu) {
Jassi Brarb42a81c2010-09-29 17:31:33 +09001094 u32 psr, speed;
Jassi Brar230d42d2009-11-30 07:39:42 +00001095
Jassi Brarb42a81c2010-09-29 17:31:33 +09001096 /* Max possible */
1097 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
Jassi Brar230d42d2009-11-30 07:39:42 +00001098
Jassi Brarb42a81c2010-09-29 17:31:33 +09001099 if (spi->max_speed_hz > speed)
1100 spi->max_speed_hz = speed;
Jassi Brar230d42d2009-11-30 07:39:42 +00001101
Jassi Brarb42a81c2010-09-29 17:31:33 +09001102 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
1103 psr &= S3C64XX_SPI_PSR_MASK;
1104 if (psr == S3C64XX_SPI_PSR_MASK)
1105 psr--;
1106
1107 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
1108 if (spi->max_speed_hz < speed) {
1109 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
1110 psr++;
1111 } else {
1112 err = -EINVAL;
1113 goto setup_exit;
1114 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001115 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001116
Jassi Brarb42a81c2010-09-29 17:31:33 +09001117 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
Thomas Abraham2b908072012-07-13 07:15:15 +09001118 if (spi->max_speed_hz >= speed) {
Jassi Brarb42a81c2010-09-29 17:31:33 +09001119 spi->max_speed_hz = speed;
Thomas Abraham2b908072012-07-13 07:15:15 +09001120 } else {
Mark Browne1b0f0d2012-12-20 18:27:31 +00001121 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
1122 spi->max_speed_hz);
Jassi Brarb42a81c2010-09-29 17:31:33 +09001123 err = -EINVAL;
Thomas Abraham2b908072012-07-13 07:15:15 +09001124 goto setup_exit;
1125 }
Jassi Brarb42a81c2010-09-29 17:31:33 +09001126 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001127
Mark Brownb97b6622011-12-04 00:58:06 +00001128 pm_runtime_put(&sdd->pdev->dev);
Thomas Abraham2b908072012-07-13 07:15:15 +09001129 disable_cs(sdd, spi);
1130 return 0;
Mark Brownb97b6622011-12-04 00:58:06 +00001131
Jassi Brar230d42d2009-11-30 07:39:42 +00001132setup_exit:
Jassi Brar230d42d2009-11-30 07:39:42 +00001133 /* setup() returns with device de-selected */
1134 disable_cs(sdd, spi);
1135
Thomas Abraham2b908072012-07-13 07:15:15 +09001136err_msgq:
1137 gpio_free(cs->line);
1138 spi_set_ctldata(spi, NULL);
1139
1140err_gpio_req:
Sylwester Nawrocki5bee3b92012-09-13 16:31:30 +02001141 if (spi->dev.of_node)
1142 kfree(cs);
Thomas Abraham2b908072012-07-13 07:15:15 +09001143
Jassi Brar230d42d2009-11-30 07:39:42 +00001144 return err;
1145}
1146
Thomas Abraham1c20c202012-07-13 07:15:14 +09001147static void s3c64xx_spi_cleanup(struct spi_device *spi)
1148{
1149 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
1150
Thomas Abraham2b908072012-07-13 07:15:15 +09001151 if (cs) {
Thomas Abraham1c20c202012-07-13 07:15:14 +09001152 gpio_free(cs->line);
Thomas Abraham2b908072012-07-13 07:15:15 +09001153 if (spi->dev.of_node)
1154 kfree(cs);
1155 }
Thomas Abraham1c20c202012-07-13 07:15:14 +09001156 spi_set_ctldata(spi, NULL);
1157}
1158
Mark Brownc2573122011-11-10 10:57:32 +00001159static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
1160{
1161 struct s3c64xx_spi_driver_data *sdd = data;
1162 struct spi_master *spi = sdd->master;
Girish K S375981f2013-03-13 12:13:30 +05301163 unsigned int val, clr = 0;
Mark Brownc2573122011-11-10 10:57:32 +00001164
Girish K S375981f2013-03-13 12:13:30 +05301165 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
Mark Brownc2573122011-11-10 10:57:32 +00001166
Girish K S375981f2013-03-13 12:13:30 +05301167 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
1168 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001169 dev_err(&spi->dev, "RX overrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301170 }
1171 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
1172 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001173 dev_err(&spi->dev, "RX underrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301174 }
1175 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
1176 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001177 dev_err(&spi->dev, "TX overrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301178 }
1179 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
1180 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001181 dev_err(&spi->dev, "TX underrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301182 }
1183
1184 /* Clear the pending irq by setting and then clearing it */
1185 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1186 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
Mark Brownc2573122011-11-10 10:57:32 +00001187
1188 return IRQ_HANDLED;
1189}
1190
Jassi Brar230d42d2009-11-30 07:39:42 +00001191static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1192{
Jassi Brarad7de722010-01-20 13:49:44 -07001193 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +00001194 void __iomem *regs = sdd->regs;
1195 unsigned int val;
1196
1197 sdd->cur_speed = 0;
1198
Mark Brown5fc3e832012-07-19 14:36:23 +09001199 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Jassi Brar230d42d2009-11-30 07:39:42 +00001200
1201 /* Disable Interrupts - we use Polling if not DMA mode */
1202 writel(0, regs + S3C64XX_SPI_INT_EN);
1203
Thomas Abrahama5238e32012-07-13 07:15:14 +09001204 if (!sdd->port_conf->clk_from_cmu)
Jassi Brarb42a81c2010-09-29 17:31:33 +09001205 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
Jassi Brar230d42d2009-11-30 07:39:42 +00001206 regs + S3C64XX_SPI_CLK_CFG);
1207 writel(0, regs + S3C64XX_SPI_MODE_CFG);
1208 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1209
Girish K S375981f2013-03-13 12:13:30 +05301210 /* Clear any irq pending bits, should set and clear the bits */
1211 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1212 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1213 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1214 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1215 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1216 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
Jassi Brar230d42d2009-11-30 07:39:42 +00001217
1218 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1219
1220 val = readl(regs + S3C64XX_SPI_MODE_CFG);
1221 val &= ~S3C64XX_SPI_MODE_4BURST;
1222 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1223 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1224 writel(val, regs + S3C64XX_SPI_MODE_CFG);
1225
1226 flush_fifo(sdd);
1227}
1228
Thomas Abraham2b908072012-07-13 07:15:15 +09001229#ifdef CONFIG_OF
Jingoo Han75bf3362013-01-31 15:25:01 +09001230static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
Thomas Abraham2b908072012-07-13 07:15:15 +09001231{
1232 struct s3c64xx_spi_info *sci;
1233 u32 temp;
1234
1235 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1236 if (!sci) {
1237 dev_err(dev, "memory allocation for spi_info failed\n");
1238 return ERR_PTR(-ENOMEM);
1239 }
1240
1241 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001242 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
Thomas Abraham2b908072012-07-13 07:15:15 +09001243 sci->src_clk_nr = 0;
1244 } else {
1245 sci->src_clk_nr = temp;
1246 }
1247
1248 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001249 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
Thomas Abraham2b908072012-07-13 07:15:15 +09001250 sci->num_cs = 1;
1251 } else {
1252 sci->num_cs = temp;
1253 }
1254
1255 return sci;
1256}
1257#else
1258static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1259{
1260 return dev->platform_data;
1261}
Thomas Abraham2b908072012-07-13 07:15:15 +09001262#endif
1263
1264static const struct of_device_id s3c64xx_spi_dt_match[];
1265
Thomas Abrahama5238e32012-07-13 07:15:14 +09001266static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1267 struct platform_device *pdev)
1268{
Thomas Abraham2b908072012-07-13 07:15:15 +09001269#ifdef CONFIG_OF
1270 if (pdev->dev.of_node) {
1271 const struct of_device_id *match;
1272 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1273 return (struct s3c64xx_spi_port_config *)match->data;
1274 }
1275#endif
Thomas Abrahama5238e32012-07-13 07:15:14 +09001276 return (struct s3c64xx_spi_port_config *)
1277 platform_get_device_id(pdev)->driver_data;
1278}
1279
Grant Likely2deff8d2013-02-05 13:27:35 +00001280static int s3c64xx_spi_probe(struct platform_device *pdev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001281{
Thomas Abraham2b908072012-07-13 07:15:15 +09001282 struct resource *mem_res;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301283 struct resource *res;
Jassi Brar230d42d2009-11-30 07:39:42 +00001284 struct s3c64xx_spi_driver_data *sdd;
Thomas Abraham2b908072012-07-13 07:15:15 +09001285 struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
Jassi Brar230d42d2009-11-30 07:39:42 +00001286 struct spi_master *master;
Mark Brownc2573122011-11-10 10:57:32 +00001287 int ret, irq;
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001288 char clk_name[16];
Jassi Brar230d42d2009-11-30 07:39:42 +00001289
Thomas Abraham2b908072012-07-13 07:15:15 +09001290 if (!sci && pdev->dev.of_node) {
1291 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1292 if (IS_ERR(sci))
1293 return PTR_ERR(sci);
Jassi Brar230d42d2009-11-30 07:39:42 +00001294 }
1295
Thomas Abraham2b908072012-07-13 07:15:15 +09001296 if (!sci) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001297 dev_err(&pdev->dev, "platform_data missing!\n");
1298 return -ENODEV;
1299 }
1300
Jassi Brar230d42d2009-11-30 07:39:42 +00001301 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1302 if (mem_res == NULL) {
1303 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1304 return -ENXIO;
1305 }
1306
Mark Brownc2573122011-11-10 10:57:32 +00001307 irq = platform_get_irq(pdev, 0);
1308 if (irq < 0) {
1309 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1310 return irq;
1311 }
1312
Jassi Brar230d42d2009-11-30 07:39:42 +00001313 master = spi_alloc_master(&pdev->dev,
1314 sizeof(struct s3c64xx_spi_driver_data));
1315 if (master == NULL) {
1316 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1317 return -ENOMEM;
1318 }
1319
Jassi Brar230d42d2009-11-30 07:39:42 +00001320 platform_set_drvdata(pdev, master);
1321
1322 sdd = spi_master_get_devdata(master);
Thomas Abrahama5238e32012-07-13 07:15:14 +09001323 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001324 sdd->master = master;
1325 sdd->cntrlr_info = sci;
1326 sdd->pdev = pdev;
1327 sdd->sfr_start = mem_res->start;
Thomas Abraham2b908072012-07-13 07:15:15 +09001328 if (pdev->dev.of_node) {
1329 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1330 if (ret < 0) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001331 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1332 ret);
Thomas Abraham2b908072012-07-13 07:15:15 +09001333 goto err0;
1334 }
1335 sdd->port_id = ret;
1336 } else {
1337 sdd->port_id = pdev->id;
1338 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001339
1340 sdd->cur_bpw = 8;
1341
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301342 if (!sdd->pdev->dev.of_node) {
1343 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1344 if (!res) {
Girish K S7e995552013-05-20 12:21:32 +05301345 dev_warn(&pdev->dev, "Unable to get SPI tx dma "
1346 "resource. Switching to poll mode\n");
1347 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1348 } else
1349 sdd->tx_dma.dmach = res->start;
Thomas Abraham2b908072012-07-13 07:15:15 +09001350
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301351 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1352 if (!res) {
Girish K S7e995552013-05-20 12:21:32 +05301353 dev_warn(&pdev->dev, "Unable to get SPI rx dma "
1354 "resource. Switching to poll mode\n");
1355 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1356 } else
1357 sdd->rx_dma.dmach = res->start;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301358 }
1359
1360 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1361 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
Thomas Abraham2b908072012-07-13 07:15:15 +09001362
1363 master->dev.of_node = pdev->dev.of_node;
Thomas Abrahama5238e32012-07-13 07:15:14 +09001364 master->bus_num = sdd->port_id;
Jassi Brar230d42d2009-11-30 07:39:42 +00001365 master->setup = s3c64xx_spi_setup;
Thomas Abraham1c20c202012-07-13 07:15:14 +09001366 master->cleanup = s3c64xx_spi_cleanup;
Mark Brownad2a99a2012-02-15 14:48:32 -08001367 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1368 master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1369 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
Jassi Brar230d42d2009-11-30 07:39:42 +00001370 master->num_chipselect = sci->num_cs;
1371 master->dma_alignment = 8;
Mark Browne761f422013-04-01 14:17:37 +01001372 master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
Jassi Brar230d42d2009-11-30 07:39:42 +00001373 /* the spi->mode bits understood by this driver: */
1374 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1375
Thierry Redingb0ee5602013-01-21 11:09:18 +01001376 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1377 if (IS_ERR(sdd->regs)) {
1378 ret = PTR_ERR(sdd->regs);
Jingoo Han4eb77002013-01-10 11:04:21 +09001379 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001380 }
1381
Thomas Abraham00ab5392013-04-15 20:42:57 -07001382 if (sci->cfg_gpio && sci->cfg_gpio()) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001383 dev_err(&pdev->dev, "Unable to config gpio\n");
1384 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001385 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001386 }
1387
1388 /* Setup clocks */
Jingoo Han4eb77002013-01-10 11:04:21 +09001389 sdd->clk = devm_clk_get(&pdev->dev, "spi");
Jassi Brar230d42d2009-11-30 07:39:42 +00001390 if (IS_ERR(sdd->clk)) {
1391 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1392 ret = PTR_ERR(sdd->clk);
Thomas Abraham00ab5392013-04-15 20:42:57 -07001393 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001394 }
1395
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001396 if (clk_prepare_enable(sdd->clk)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001397 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1398 ret = -EBUSY;
Thomas Abraham00ab5392013-04-15 20:42:57 -07001399 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001400 }
1401
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001402 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
Jingoo Han4eb77002013-01-10 11:04:21 +09001403 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001404 if (IS_ERR(sdd->src_clk)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001405 dev_err(&pdev->dev,
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001406 "Unable to acquire clock '%s'\n", clk_name);
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001407 ret = PTR_ERR(sdd->src_clk);
Jingoo Han4eb77002013-01-10 11:04:21 +09001408 goto err2;
Jassi Brar230d42d2009-11-30 07:39:42 +00001409 }
1410
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001411 if (clk_prepare_enable(sdd->src_clk)) {
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001412 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
Jassi Brar230d42d2009-11-30 07:39:42 +00001413 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001414 goto err2;
Jassi Brar230d42d2009-11-30 07:39:42 +00001415 }
1416
Jassi Brar230d42d2009-11-30 07:39:42 +00001417 /* Setup Deufult Mode */
Thomas Abrahama5238e32012-07-13 07:15:14 +09001418 s3c64xx_spi_hwinit(sdd, sdd->port_id);
Jassi Brar230d42d2009-11-30 07:39:42 +00001419
1420 spin_lock_init(&sdd->lock);
1421 init_completion(&sdd->xfer_completion);
Jassi Brar230d42d2009-11-30 07:39:42 +00001422 INIT_LIST_HEAD(&sdd->queue);
1423
Jingoo Han4eb77002013-01-10 11:04:21 +09001424 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1425 "spi-s3c64xx", sdd);
Mark Brownc2573122011-11-10 10:57:32 +00001426 if (ret != 0) {
1427 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1428 irq, ret);
Jingoo Han4eb77002013-01-10 11:04:21 +09001429 goto err3;
Mark Brownc2573122011-11-10 10:57:32 +00001430 }
1431
1432 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1433 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1434 sdd->regs + S3C64XX_SPI_INT_EN);
1435
Jassi Brar230d42d2009-11-30 07:39:42 +00001436 if (spi_register_master(master)) {
1437 dev_err(&pdev->dev, "cannot register SPI master\n");
1438 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001439 goto err3;
Jassi Brar230d42d2009-11-30 07:39:42 +00001440 }
1441
Jingoo Han75bf3362013-01-31 15:25:01 +09001442 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
Thomas Abrahama5238e32012-07-13 07:15:14 +09001443 sdd->port_id, master->num_chipselect);
Joe Perches8a349d42010-02-02 07:22:13 +00001444 dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
Jassi Brar230d42d2009-11-30 07:39:42 +00001445 mem_res->end, mem_res->start,
Boojin Kim82ab8cd2011-09-02 09:44:42 +09001446 sdd->rx_dma.dmach, sdd->tx_dma.dmach);
Jassi Brar230d42d2009-11-30 07:39:42 +00001447
Mark Brownb97b6622011-12-04 00:58:06 +00001448 pm_runtime_enable(&pdev->dev);
1449
Jassi Brar230d42d2009-11-30 07:39:42 +00001450 return 0;
1451
Jassi Brar230d42d2009-11-30 07:39:42 +00001452err3:
Jingoo Han4eb77002013-01-10 11:04:21 +09001453 clk_disable_unprepare(sdd->src_clk);
1454err2:
1455 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001456err0:
1457 platform_set_drvdata(pdev, NULL);
1458 spi_master_put(master);
1459
1460 return ret;
1461}
1462
1463static int s3c64xx_spi_remove(struct platform_device *pdev)
1464{
1465 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1466 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001467
Mark Brownb97b6622011-12-04 00:58:06 +00001468 pm_runtime_disable(&pdev->dev);
1469
Jassi Brar230d42d2009-11-30 07:39:42 +00001470 spi_unregister_master(master);
1471
Mark Brownc2573122011-11-10 10:57:32 +00001472 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1473
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001474 clk_disable_unprepare(sdd->src_clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001475
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001476 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001477
Jassi Brar230d42d2009-11-30 07:39:42 +00001478 platform_set_drvdata(pdev, NULL);
1479 spi_master_put(master);
1480
1481 return 0;
1482}
1483
Jingoo Han997230d2013-03-22 02:09:08 +00001484#ifdef CONFIG_PM_SLEEP
Mark Browne25d0bf2011-12-04 00:36:18 +00001485static int s3c64xx_spi_suspend(struct device *dev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001486{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001487 struct spi_master *master = dev_get_drvdata(dev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001488 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001489
Mark Brownad2a99a2012-02-15 14:48:32 -08001490 spi_master_suspend(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001491
1492 /* Disable the clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001493 clk_disable_unprepare(sdd->src_clk);
1494 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001495
1496 sdd->cur_speed = 0; /* Output Clock is stopped */
1497
1498 return 0;
1499}
1500
Mark Browne25d0bf2011-12-04 00:36:18 +00001501static int s3c64xx_spi_resume(struct device *dev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001502{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001503 struct spi_master *master = dev_get_drvdata(dev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001504 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brarad7de722010-01-20 13:49:44 -07001505 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +00001506
Thomas Abraham00ab5392013-04-15 20:42:57 -07001507 if (sci->cfg_gpio)
Thomas Abraham2b908072012-07-13 07:15:15 +09001508 sci->cfg_gpio();
Jassi Brar230d42d2009-11-30 07:39:42 +00001509
1510 /* Enable the clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001511 clk_prepare_enable(sdd->src_clk);
1512 clk_prepare_enable(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001513
Thomas Abrahama5238e32012-07-13 07:15:14 +09001514 s3c64xx_spi_hwinit(sdd, sdd->port_id);
Jassi Brar230d42d2009-11-30 07:39:42 +00001515
Mark Brownad2a99a2012-02-15 14:48:32 -08001516 spi_master_resume(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001517
1518 return 0;
1519}
Jingoo Han997230d2013-03-22 02:09:08 +00001520#endif /* CONFIG_PM_SLEEP */
Jassi Brar230d42d2009-11-30 07:39:42 +00001521
Mark Brownb97b6622011-12-04 00:58:06 +00001522#ifdef CONFIG_PM_RUNTIME
1523static int s3c64xx_spi_runtime_suspend(struct device *dev)
1524{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001525 struct spi_master *master = dev_get_drvdata(dev);
Mark Brownb97b6622011-12-04 00:58:06 +00001526 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1527
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001528 clk_disable_unprepare(sdd->clk);
1529 clk_disable_unprepare(sdd->src_clk);
Mark Brownb97b6622011-12-04 00:58:06 +00001530
1531 return 0;
1532}
1533
1534static int s3c64xx_spi_runtime_resume(struct device *dev)
1535{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001536 struct spi_master *master = dev_get_drvdata(dev);
Mark Brownb97b6622011-12-04 00:58:06 +00001537 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1538
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001539 clk_prepare_enable(sdd->src_clk);
1540 clk_prepare_enable(sdd->clk);
Mark Brownb97b6622011-12-04 00:58:06 +00001541
1542 return 0;
1543}
1544#endif /* CONFIG_PM_RUNTIME */
1545
Mark Browne25d0bf2011-12-04 00:36:18 +00001546static const struct dev_pm_ops s3c64xx_spi_pm = {
1547 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
Mark Brownb97b6622011-12-04 00:58:06 +00001548 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1549 s3c64xx_spi_runtime_resume, NULL)
Mark Browne25d0bf2011-12-04 00:36:18 +00001550};
1551
Sachin Kamat10ce0472012-08-03 10:08:12 +05301552static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001553 .fifo_lvl_mask = { 0x7f },
1554 .rx_lvl_offset = 13,
1555 .tx_st_done = 21,
1556 .high_speed = true,
1557};
1558
Sachin Kamat10ce0472012-08-03 10:08:12 +05301559static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001560 .fifo_lvl_mask = { 0x7f, 0x7F },
1561 .rx_lvl_offset = 13,
1562 .tx_st_done = 21,
1563};
1564
Sachin Kamat10ce0472012-08-03 10:08:12 +05301565static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001566 .fifo_lvl_mask = { 0x1ff, 0x7F },
1567 .rx_lvl_offset = 15,
1568 .tx_st_done = 25,
1569};
1570
Sachin Kamat10ce0472012-08-03 10:08:12 +05301571static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001572 .fifo_lvl_mask = { 0x7f, 0x7F },
1573 .rx_lvl_offset = 13,
1574 .tx_st_done = 21,
1575 .high_speed = true,
1576};
1577
Sachin Kamat10ce0472012-08-03 10:08:12 +05301578static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001579 .fifo_lvl_mask = { 0x1ff, 0x7F },
1580 .rx_lvl_offset = 15,
1581 .tx_st_done = 25,
1582 .high_speed = true,
1583};
1584
Sachin Kamat10ce0472012-08-03 10:08:12 +05301585static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001586 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1587 .rx_lvl_offset = 15,
1588 .tx_st_done = 25,
1589 .high_speed = true,
1590 .clk_from_cmu = true,
1591};
1592
1593static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1594 {
1595 .name = "s3c2443-spi",
1596 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1597 }, {
1598 .name = "s3c6410-spi",
1599 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1600 }, {
1601 .name = "s5p64x0-spi",
1602 .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config,
1603 }, {
1604 .name = "s5pc100-spi",
1605 .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config,
1606 }, {
1607 .name = "s5pv210-spi",
1608 .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config,
1609 }, {
1610 .name = "exynos4210-spi",
1611 .driver_data = (kernel_ulong_t)&exynos4_spi_port_config,
1612 },
1613 { },
1614};
1615
Thomas Abraham2b908072012-07-13 07:15:15 +09001616#ifdef CONFIG_OF
1617static const struct of_device_id s3c64xx_spi_dt_match[] = {
1618 { .compatible = "samsung,exynos4210-spi",
1619 .data = (void *)&exynos4_spi_port_config,
1620 },
1621 { },
1622};
1623MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1624#endif /* CONFIG_OF */
1625
Jassi Brar230d42d2009-11-30 07:39:42 +00001626static struct platform_driver s3c64xx_spi_driver = {
1627 .driver = {
1628 .name = "s3c64xx-spi",
1629 .owner = THIS_MODULE,
Mark Browne25d0bf2011-12-04 00:36:18 +00001630 .pm = &s3c64xx_spi_pm,
Thomas Abraham2b908072012-07-13 07:15:15 +09001631 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
Jassi Brar230d42d2009-11-30 07:39:42 +00001632 },
1633 .remove = s3c64xx_spi_remove,
Thomas Abrahama5238e32012-07-13 07:15:14 +09001634 .id_table = s3c64xx_spi_driver_ids,
Jassi Brar230d42d2009-11-30 07:39:42 +00001635};
1636MODULE_ALIAS("platform:s3c64xx-spi");
1637
1638static int __init s3c64xx_spi_init(void)
1639{
1640 return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1641}
Mark Brownd2a787f2010-09-07 11:29:17 +01001642subsys_initcall(s3c64xx_spi_init);
Jassi Brar230d42d2009-11-30 07:39:42 +00001643
1644static void __exit s3c64xx_spi_exit(void)
1645{
1646 platform_driver_unregister(&s3c64xx_spi_driver);
1647}
1648module_exit(s3c64xx_spi_exit);
1649
1650MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1651MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1652MODULE_LICENSE("GPL");