Haojian Zhuang | 2f7e8fa | 2009-12-04 09:41:28 -0500 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-mmp/mmp2.c |
| 3 | * |
| 4 | * code name MMP2 |
| 5 | * |
| 6 | * Copyright (C) 2009 Marvell International Ltd. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/io.h> |
| 17 | |
Haojian Zhuang | 66b1964 | 2010-04-28 10:59:45 -0400 | [diff] [blame] | 18 | #include <asm/hardware/cache-tauros2.h> |
| 19 | |
Haojian Zhuang | 2f7e8fa | 2009-12-04 09:41:28 -0500 | [diff] [blame] | 20 | #include <mach/addr-map.h> |
| 21 | #include <mach/regs-apbc.h> |
| 22 | #include <mach/regs-apmu.h> |
| 23 | #include <mach/cputype.h> |
| 24 | #include <mach/irqs.h> |
| 25 | #include <mach/mfp.h> |
Haojian Zhuang | 16144bf | 2010-01-25 06:03:54 -0500 | [diff] [blame] | 26 | #include <mach/gpio.h> |
Haojian Zhuang | 2f7e8fa | 2009-12-04 09:41:28 -0500 | [diff] [blame] | 27 | #include <mach/devices.h> |
| 28 | |
| 29 | #include "common.h" |
| 30 | #include "clock.h" |
| 31 | |
| 32 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) |
| 33 | |
Haojian Zhuang | 16144bf | 2010-01-25 06:03:54 -0500 | [diff] [blame] | 34 | #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c) |
| 35 | |
Haojian Zhuang | 247b459 | 2010-01-25 06:03:25 -0500 | [diff] [blame] | 36 | static struct mfp_addr_map mmp2_addr_map[] __initdata = { |
| 37 | MFP_ADDR(PMIC_INT, 0x2c4), |
| 38 | |
| 39 | MFP_ADDR_END, |
| 40 | }; |
| 41 | |
Haojian Zhuang | df0c382 | 2010-02-03 10:01:18 -0500 | [diff] [blame] | 42 | void mmp2_clear_pmic_int(void) |
| 43 | { |
| 44 | unsigned long mfpr_pmic, data; |
| 45 | |
| 46 | mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4; |
| 47 | data = __raw_readl(mfpr_pmic); |
| 48 | __raw_writel(data | (1 << 6), mfpr_pmic); |
| 49 | __raw_writel(data, mfpr_pmic); |
| 50 | } |
| 51 | |
Haojian Zhuang | 16144bf | 2010-01-25 06:03:54 -0500 | [diff] [blame] | 52 | static void __init mmp2_init_gpio(void) |
| 53 | { |
| 54 | int i; |
| 55 | |
| 56 | /* enable GPIO clock */ |
| 57 | __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_MMP2_GPIO); |
| 58 | |
| 59 | /* unmask GPIO edge detection for all 6 banks -- APMASKx */ |
| 60 | for (i = 0; i < 6; i++) |
| 61 | __raw_writel(0xffffffff, APMASK(i)); |
| 62 | |
| 63 | pxa_init_gpio(IRQ_MMP2_GPIO, 0, 167, NULL); |
| 64 | } |
| 65 | |
| 66 | void __init mmp2_init_irq(void) |
| 67 | { |
| 68 | mmp2_init_icu(); |
| 69 | mmp2_init_gpio(); |
| 70 | } |
| 71 | |
Haojian Zhuang | 2f7e8fa | 2009-12-04 09:41:28 -0500 | [diff] [blame] | 72 | /* APB peripheral clocks */ |
| 73 | static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); |
| 74 | static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); |
| 75 | static APBC_CLK(uart3, MMP2_UART3, 1, 26000000); |
| 76 | static APBC_CLK(uart4, MMP2_UART4, 1, 26000000); |
| 77 | static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000); |
| 78 | static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000); |
| 79 | static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000); |
| 80 | static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); |
| 81 | static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); |
| 82 | static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); |
| 83 | static APBC_CLK(rtc, MMP2_RTC, 0, 32768); |
| 84 | |
| 85 | static APMU_CLK(nand, NAND, 0xbf, 100000000); |
| 86 | |
| 87 | static struct clk_lookup mmp2_clkregs[] = { |
| 88 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), |
| 89 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), |
| 90 | INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), |
| 91 | INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), |
| 92 | INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), |
| 93 | INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), |
| 94 | INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), |
| 95 | INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), |
| 96 | INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), |
| 97 | INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), |
| 98 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), |
| 99 | }; |
| 100 | |
| 101 | static int __init mmp2_init(void) |
| 102 | { |
| 103 | if (cpu_is_mmp2()) { |
Haojian Zhuang | 66b1964 | 2010-04-28 10:59:45 -0400 | [diff] [blame] | 104 | #ifdef CONFIG_CACHE_TAUROS2 |
| 105 | tauros2_init(); |
| 106 | #endif |
Haojian Zhuang | 2f7e8fa | 2009-12-04 09:41:28 -0500 | [diff] [blame] | 107 | mfp_init_base(MFPR_VIRT_BASE); |
Haojian Zhuang | 247b459 | 2010-01-25 06:03:25 -0500 | [diff] [blame] | 108 | mfp_init_addr(mmp2_addr_map); |
Haojian Zhuang | e598863 | 2010-04-28 10:48:24 -0400 | [diff] [blame] | 109 | clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); |
Haojian Zhuang | 2f7e8fa | 2009-12-04 09:41:28 -0500 | [diff] [blame] | 110 | } |
| 111 | |
| 112 | return 0; |
| 113 | } |
| 114 | postcore_initcall(mmp2_init); |
| 115 | |
| 116 | /* on-chip devices */ |
| 117 | MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5); |
| 118 | MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21); |
| 119 | MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23); |
| 120 | MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19); |
| 121 | MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70); |
| 122 | MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70); |
| 123 | MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70); |
| 124 | MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70); |
| 125 | MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70); |
| 126 | MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70); |
| 127 | MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29); |
| 128 | |