Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | * |
| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 4 | * redistributing this file, you may do so under either license. |
| 5 | * |
| 6 | * GPL LICENSE SUMMARY |
| 7 | * |
Emmanuel Grumbach | 51368bf | 2013-12-30 13:15:54 +0200 | [diff] [blame] | 8 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
Johannes Berg | 8b4139d | 2014-07-24 14:05:26 +0200 | [diff] [blame] | 9 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
Ian Schram | 01ebd06 | 2007-10-25 17:15:22 +0800 | [diff] [blame] | 12 | * it under the terms of version 2 of the GNU General Public License as |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 13 | * published by the Free Software Foundation. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, but |
| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 18 | * General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, |
| 23 | * USA |
| 24 | * |
| 25 | * The full GNU General Public License is included in this distribution |
Emmanuel Grumbach | 410dc5a | 2013-02-18 09:22:28 +0200 | [diff] [blame] | 26 | * in the file called COPYING. |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 27 | * |
| 28 | * Contact Information: |
Winkler, Tomas | 759ef89 | 2008-12-09 11:28:58 -0800 | [diff] [blame] | 29 | * Intel Linux Wireless <ilw@linux.intel.com> |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 31 | * |
| 32 | * BSD LICENSE |
| 33 | * |
Emmanuel Grumbach | 51368bf | 2013-12-30 13:15:54 +0200 | [diff] [blame] | 34 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
Johannes Berg | 8b4139d | 2014-07-24 14:05:26 +0200 | [diff] [blame] | 35 | * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 36 | * All rights reserved. |
| 37 | * |
| 38 | * Redistribution and use in source and binary forms, with or without |
| 39 | * modification, are permitted provided that the following conditions |
| 40 | * are met: |
| 41 | * |
| 42 | * * Redistributions of source code must retain the above copyright |
| 43 | * notice, this list of conditions and the following disclaimer. |
| 44 | * * Redistributions in binary form must reproduce the above copyright |
| 45 | * notice, this list of conditions and the following disclaimer in |
| 46 | * the documentation and/or other materials provided with the |
| 47 | * distribution. |
| 48 | * * Neither the name Intel Corporation nor the names of its |
| 49 | * contributors may be used to endorse or promote products derived |
| 50 | * from this software without specific prior written permission. |
| 51 | * |
| 52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 63 | *****************************************************************************/ |
| 64 | |
| 65 | #ifndef __iwl_prph_h__ |
| 66 | #define __iwl_prph_h__ |
| 67 | |
Ben Cahill | e385144 | 2007-11-29 11:10:07 +0800 | [diff] [blame] | 68 | /* |
| 69 | * Registers in this file are internal, not PCI bus memory mapped. |
| 70 | * Driver accesses these via HBUS_TARG_PRPH_* registers. |
| 71 | */ |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 72 | #define PRPH_BASE (0x00000) |
| 73 | #define PRPH_END (0xFFFFF) |
| 74 | |
| 75 | /* APMG (power management) constants */ |
| 76 | #define APMG_BASE (PRPH_BASE + 0x3000) |
| 77 | #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000) |
| 78 | #define APMG_CLK_EN_REG (APMG_BASE + 0x0004) |
| 79 | #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008) |
| 80 | #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c) |
| 81 | #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010) |
| 82 | #define APMG_RFKILL_REG (APMG_BASE + 0x0014) |
| 83 | #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c) |
| 84 | #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020) |
Wey-Yi Guy | 02c06e4 | 2009-07-17 09:30:14 -0700 | [diff] [blame] | 85 | #define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058) |
| 86 | #define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C) |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 87 | |
Wey-Yi Guy | 50619ac | 2010-12-07 08:06:31 -0800 | [diff] [blame] | 88 | #define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 89 | #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) |
| 90 | #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) |
| 91 | |
Tomas Winkler | 4c43e0d | 2008-08-04 16:00:39 +0800 | [diff] [blame] | 92 | #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) |
| 93 | #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) |
| 94 | #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) |
| 95 | #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) |
Tomas Winkler | 4c43e0d | 2008-08-04 16:00:39 +0800 | [diff] [blame] | 96 | #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) |
Wey-Yi Guy | 02c06e4 | 2009-07-17 09:30:14 -0700 | [diff] [blame] | 97 | #define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ |
| 98 | #define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 99 | |
Alexander Bondar | a812cba | 2014-02-18 16:45:00 +0100 | [diff] [blame] | 100 | #define APMG_PCIDEV_STT_VAL_PERSIST_DIS (0x00000200) |
| 101 | #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) |
Emmanuel Grumbach | b7aaeae | 2014-12-07 19:44:30 +0200 | [diff] [blame] | 102 | #define APMG_PCIDEV_STT_VAL_WAKE_ME (0x00004000) |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 103 | |
Emmanuel Grumbach | 889b169 | 2013-07-25 13:14:34 +0300 | [diff] [blame] | 104 | #define APMG_RTC_INT_STT_RFKILL (0x10000000) |
| 105 | |
Johannes Berg | 99cd471 | 2013-01-24 13:52:01 +0100 | [diff] [blame] | 106 | /* Device system time */ |
| 107 | #define DEVICE_SYSTEM_TIME_REG 0xA0206C |
| 108 | |
Alexander Bondar | 119663c | 2013-10-17 14:26:50 +0200 | [diff] [blame] | 109 | /* Device NMI register */ |
| 110 | #define DEVICE_SET_NMI_REG 0x00a01c30 |
Emmanuel Grumbach | 6639658 | 2015-01-07 16:44:06 +0200 | [diff] [blame] | 111 | #define DEVICE_SET_NMI_VAL_HW BIT(0) |
| 112 | #define DEVICE_SET_NMI_VAL_DRV BIT(7) |
Emmanuel Grumbach | 5dd9c68 | 2015-03-05 13:06:13 +0200 | [diff] [blame] | 113 | #define DEVICE_SET_NMI_8000_REG 0x00a01c24 |
| 114 | #define DEVICE_SET_NMI_8000_VAL 0x1000000 |
Alexander Bondar | 119663c | 2013-10-17 14:26:50 +0200 | [diff] [blame] | 115 | |
Alexander Bondar | a812cba | 2014-02-18 16:45:00 +0100 | [diff] [blame] | 116 | /* Shared registers (0x0..0x3ff, via target indirect or periphery */ |
| 117 | #define SHR_BASE 0x00a10000 |
| 118 | |
| 119 | /* Shared GP1 register */ |
| 120 | #define SHR_APMG_GP1_REG 0x01dc |
| 121 | #define SHR_APMG_GP1_REG_PRPH (SHR_BASE + SHR_APMG_GP1_REG) |
| 122 | #define SHR_APMG_GP1_WF_XTAL_LP_EN 0x00000004 |
| 123 | #define SHR_APMG_GP1_CHICKEN_BIT_SELECT 0x80000000 |
| 124 | |
| 125 | /* Shared DL_CFG register */ |
| 126 | #define SHR_APMG_DL_CFG_REG 0x01c4 |
| 127 | #define SHR_APMG_DL_CFG_REG_PRPH (SHR_BASE + SHR_APMG_DL_CFG_REG) |
| 128 | #define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK 0x000000c0 |
| 129 | #define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL 0x00000080 |
| 130 | #define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP 0x00000100 |
| 131 | |
| 132 | /* Shared APMG_XTAL_CFG register */ |
| 133 | #define SHR_APMG_XTAL_CFG_REG 0x1c0 |
| 134 | #define SHR_APMG_XTAL_CFG_XTAL_ON_REQ 0x80000000 |
| 135 | |
Eran Harary | e12ba84 | 2013-12-02 12:18:10 +0200 | [diff] [blame] | 136 | /* |
| 137 | * Device reset for family 8000 |
| 138 | * write to bit 24 in order to reset the CPU |
| 139 | */ |
| 140 | #define RELEASE_CPU_RESET (0x300C) |
| 141 | #define RELEASE_CPU_RESET_BIT BIT(24) |
| 142 | |
Eytan Lifshitz | 9ee718a | 2013-05-19 19:14:41 +0300 | [diff] [blame] | 143 | /***************************************************************************** |
| 144 | * 7000/3000 series SHR DTS addresses * |
| 145 | *****************************************************************************/ |
| 146 | |
| 147 | #define SHR_MISC_WFM_DTS_EN (0x00a10024) |
| 148 | #define DTSC_CFG_MODE (0x00a10604) |
| 149 | #define DTSC_VREF_AVG (0x00a10648) |
| 150 | #define DTSC_VREF5_AVG (0x00a1064c) |
| 151 | #define DTSC_CFG_MODE_PERIODIC (0x2) |
| 152 | #define DTSC_PTAT_AVG (0x00a10650) |
| 153 | |
| 154 | |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 155 | /** |
Emmanuel Grumbach | 038669e | 2008-04-23 17:15:04 -0700 | [diff] [blame] | 156 | * Tx Scheduler |
| 157 | * |
Tomas Winkler | a96a27f | 2008-10-23 23:48:56 -0700 | [diff] [blame] | 158 | * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs |
Emmanuel Grumbach | 038669e | 2008-04-23 17:15:04 -0700 | [diff] [blame] | 159 | * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in |
| 160 | * host DRAM. It steers each frame's Tx command (which contains the frame |
| 161 | * data) into one of up to 7 prioritized Tx DMA FIFO channels within the |
| 162 | * device. A queue maps to only one (selectable by driver) Tx DMA channel, |
| 163 | * but one DMA channel may take input from several queues. |
| 164 | * |
Wey-Yi Guy | 8ff84a2 | 2011-04-01 16:29:52 -0700 | [diff] [blame] | 165 | * Tx DMA FIFOs have dedicated purposes. |
Emmanuel Grumbach | 038669e | 2008-04-23 17:15:04 -0700 | [diff] [blame] | 166 | * |
Johannes Berg | edc1a3a | 2010-02-24 01:57:19 -0800 | [diff] [blame] | 167 | * For 5000 series and up, they are used differently |
Johannes Berg | 6819886 | 2009-11-06 14:52:53 -0800 | [diff] [blame] | 168 | * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): |
| 169 | * |
| 170 | * 0 -- EDCA BK (background) frames, lowest priority |
| 171 | * 1 -- EDCA BE (best effort) frames, normal priority |
| 172 | * 2 -- EDCA VI (video) frames, higher priority |
| 173 | * 3 -- EDCA VO (voice) and management frames, highest priority |
Johannes Berg | edc1a3a | 2010-02-24 01:57:19 -0800 | [diff] [blame] | 174 | * 4 -- unused |
| 175 | * 5 -- unused |
| 176 | * 6 -- unused |
Johannes Berg | 6819886 | 2009-11-06 14:52:53 -0800 | [diff] [blame] | 177 | * 7 -- Commands |
| 178 | * |
Emmanuel Grumbach | 038669e | 2008-04-23 17:15:04 -0700 | [diff] [blame] | 179 | * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. |
Johannes Berg | 6819886 | 2009-11-06 14:52:53 -0800 | [diff] [blame] | 180 | * In addition, driver can map the remaining queues to Tx DMA/FIFO |
| 181 | * channels 0-3 to support 11n aggregation via EDCA DMA channels. |
Emmanuel Grumbach | 038669e | 2008-04-23 17:15:04 -0700 | [diff] [blame] | 182 | * |
| 183 | * The driver sets up each queue to work in one of two modes: |
| 184 | * |
| 185 | * 1) Scheduler-Ack, in which the scheduler automatically supports a |
| 186 | * block-ack (BA) window of up to 64 TFDs. In this mode, each queue |
| 187 | * contains TFDs for a unique combination of Recipient Address (RA) |
| 188 | * and Traffic Identifier (TID), that is, traffic of a given |
| 189 | * Quality-Of-Service (QOS) priority, destined for a single station. |
| 190 | * |
| 191 | * In scheduler-ack mode, the scheduler keeps track of the Tx status of |
| 192 | * each frame within the BA window, including whether it's been transmitted, |
| 193 | * and whether it's been acknowledged by the receiving station. The device |
| 194 | * automatically processes block-acks received from the receiving STA, |
| 195 | * and reschedules un-acked frames to be retransmitted (successful |
| 196 | * Tx completion may end up being out-of-order). |
| 197 | * |
| 198 | * The driver must maintain the queue's Byte Count table in host DRAM |
Wey-Yi Guy | 8ff84a2 | 2011-04-01 16:29:52 -0700 | [diff] [blame] | 199 | * for this mode. |
Emmanuel Grumbach | 038669e | 2008-04-23 17:15:04 -0700 | [diff] [blame] | 200 | * This mode does not support fragmentation. |
| 201 | * |
| 202 | * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. |
| 203 | * The device may automatically retry Tx, but will retry only one frame |
| 204 | * at a time, until receiving ACK from receiving station, or reaching |
| 205 | * retry limit and giving up. |
| 206 | * |
Johannes Berg | 13bb948 | 2010-08-23 10:46:33 +0200 | [diff] [blame] | 207 | * The command queue (#4/#9) must use this mode! |
Emmanuel Grumbach | 038669e | 2008-04-23 17:15:04 -0700 | [diff] [blame] | 208 | * This mode does not require use of the Byte Count table in host DRAM. |
| 209 | * |
| 210 | * Driver controls scheduler operation via 3 means: |
| 211 | * 1) Scheduler registers |
Wey-Yi Guy | 8ff84a2 | 2011-04-01 16:29:52 -0700 | [diff] [blame] | 212 | * 2) Shared scheduler data base in internal SRAM |
Emmanuel Grumbach | 038669e | 2008-04-23 17:15:04 -0700 | [diff] [blame] | 213 | * 3) Shared data in host DRAM |
| 214 | * |
| 215 | * Initialization: |
| 216 | * |
| 217 | * When loading, driver should allocate memory for: |
| 218 | * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. |
| 219 | * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory |
| 220 | * (1024 bytes for each queue). |
| 221 | * |
| 222 | * After receiving "Alive" response from uCode, driver must initialize |
Johannes Berg | 13bb948 | 2010-08-23 10:46:33 +0200 | [diff] [blame] | 223 | * the scheduler (especially for queue #4/#9, the command queue, otherwise |
Emmanuel Grumbach | 038669e | 2008-04-23 17:15:04 -0700 | [diff] [blame] | 224 | * the driver can't issue commands!): |
Ben Cahill | e385144 | 2007-11-29 11:10:07 +0800 | [diff] [blame] | 225 | */ |
Wey-Yi Guy | f86af7b | 2011-06-28 08:01:12 -0700 | [diff] [blame] | 226 | #define SCD_MEM_LOWER_BOUND (0x0000) |
Emmanuel Grumbach | 67dc320 | 2007-10-25 17:15:38 +0800 | [diff] [blame] | 227 | |
Emmanuel Grumbach | 038669e | 2008-04-23 17:15:04 -0700 | [diff] [blame] | 228 | /** |
| 229 | * Max Tx window size is the max number of contiguous TFDs that the scheduler |
| 230 | * can keep track of at one time when creating block-ack chains of frames. |
| 231 | * Note that "64" matches the number of ack bits in a block-ack packet. |
Emmanuel Grumbach | 038669e | 2008-04-23 17:15:04 -0700 | [diff] [blame] | 232 | */ |
| 233 | #define SCD_WIN_SIZE 64 |
| 234 | #define SCD_FRAME_LIMIT 64 |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 235 | |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 236 | #define SCD_TXFIFO_POS_TID (0) |
| 237 | #define SCD_TXFIFO_POS_RA (4) |
| 238 | #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) |
Emmanuel Grumbach | 038669e | 2008-04-23 17:15:04 -0700 | [diff] [blame] | 239 | |
Wey-Yi Guy | f4388ad | 2010-04-12 18:32:11 -0700 | [diff] [blame] | 240 | /* agn SCD */ |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 241 | #define SCD_QUEUE_STTS_REG_POS_TXF (0) |
| 242 | #define SCD_QUEUE_STTS_REG_POS_ACTIVE (3) |
| 243 | #define SCD_QUEUE_STTS_REG_POS_WSL (4) |
| 244 | #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) |
Emmanuel Grumbach | cde5b48 | 2012-05-28 16:55:34 +0300 | [diff] [blame] | 245 | #define SCD_QUEUE_STTS_REG_MSK (0x017F0000) |
Ron Rindjunsky | 99da1b4 | 2008-05-15 13:54:13 +0800 | [diff] [blame] | 246 | |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 247 | #define SCD_QUEUE_CTX_REG1_CREDIT_POS (8) |
| 248 | #define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) |
| 249 | #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) |
| 250 | #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) |
| 251 | #define SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) |
| 252 | #define SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) |
| 253 | #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) |
| 254 | #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) |
Emmanuel Grumbach | cb6bb12 | 2015-01-25 10:36:31 +0200 | [diff] [blame] | 255 | #define SCD_GP_CTRL_ENABLE_31_QUEUES BIT(0) |
Ron Rindjunsky | 99da1b4 | 2008-05-15 13:54:13 +0800 | [diff] [blame] | 256 | |
Wey-Yi Guy | f86af7b | 2011-06-28 08:01:12 -0700 | [diff] [blame] | 257 | /* Context Data */ |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 258 | #define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600) |
| 259 | #define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0) |
Wey-Yi Guy | f86af7b | 2011-06-28 08:01:12 -0700 | [diff] [blame] | 260 | |
| 261 | /* Tx status */ |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 262 | #define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0) |
| 263 | #define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0) |
Wey-Yi Guy | f86af7b | 2011-06-28 08:01:12 -0700 | [diff] [blame] | 264 | |
| 265 | /* Translation Data */ |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 266 | #define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0) |
| 267 | #define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808) |
Ron Rindjunsky | 99da1b4 | 2008-05-15 13:54:13 +0800 | [diff] [blame] | 268 | |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 269 | #define SCD_CONTEXT_QUEUE_OFFSET(x)\ |
| 270 | (SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) |
Ron Rindjunsky | 99da1b4 | 2008-05-15 13:54:13 +0800 | [diff] [blame] | 271 | |
Emmanuel Grumbach | 986ea6c | 2012-09-30 16:25:43 +0200 | [diff] [blame] | 272 | #define SCD_TX_STTS_QUEUE_OFFSET(x)\ |
| 273 | (SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) |
| 274 | |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 275 | #define SCD_TRANS_TBL_OFFSET_QUEUE(x) \ |
| 276 | ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) |
Ron Rindjunsky | 99da1b4 | 2008-05-15 13:54:13 +0800 | [diff] [blame] | 277 | |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 278 | #define SCD_BASE (PRPH_BASE + 0xa02c00) |
Emmanuel Grumbach | b559e66 | 2007-10-25 17:15:40 +0800 | [diff] [blame] | 279 | |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 280 | #define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0) |
| 281 | #define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8) |
| 282 | #define SCD_AIT (SCD_BASE + 0x0c) |
| 283 | #define SCD_TXFACT (SCD_BASE + 0x10) |
| 284 | #define SCD_ACTIVE (SCD_BASE + 0x14) |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 285 | #define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8) |
Emmanuel Grumbach | d012d04 | 2012-06-06 13:55:02 +0200 | [diff] [blame] | 286 | #define SCD_CHAINEXT_EN (SCD_BASE + 0x244) |
Emmanuel Grumbach | b3c2ce1 | 2011-07-07 15:50:10 +0300 | [diff] [blame] | 287 | #define SCD_AGGR_SEL (SCD_BASE + 0x248) |
| 288 | #define SCD_INTERRUPT_MASK (SCD_BASE + 0x108) |
Emmanuel Grumbach | cb6bb12 | 2015-01-25 10:36:31 +0200 | [diff] [blame] | 289 | #define SCD_GP_CTRL (SCD_BASE + 0x1a8) |
Avri Altman | 002a9e2 | 2014-07-24 19:25:10 +0300 | [diff] [blame] | 290 | #define SCD_EN_CTRL (SCD_BASE + 0x254) |
Johannes Berg | 5ef4acd | 2012-04-23 14:17:50 -0700 | [diff] [blame] | 291 | |
Emmanuel Grumbach | 038669e | 2008-04-23 17:15:04 -0700 | [diff] [blame] | 292 | /*********************** END TX SCHEDULER *************************************/ |
| 293 | |
Emmanuel Grumbach | 2d93aee | 2013-12-24 14:15:41 +0200 | [diff] [blame] | 294 | /* Oscillator clock */ |
| 295 | #define OSC_CLK (0xa04068) |
| 296 | #define OSC_CLK_FORCE_CONTROL (0x8) |
| 297 | |
Eran Harary | dcab8ec | 2014-10-19 12:20:14 +0200 | [diff] [blame] | 298 | #define FH_UCODE_LOAD_STATUS (0x1AF0) |
Eran Harary | 189fa2f | 2014-01-23 16:26:32 +0200 | [diff] [blame] | 299 | #define CSR_UCODE_LOAD_STATUS_ADDR (0x1E70) |
| 300 | enum secure_load_status_reg { |
| 301 | LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001, |
| 302 | LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003, |
| 303 | LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007, |
| 304 | LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, |
| 305 | LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, |
| 306 | }; |
| 307 | |
| 308 | #define LMPM_SECURE_INSPECTOR_CODE_ADDR (0x1E38) |
| 309 | #define LMPM_SECURE_INSPECTOR_DATA_ADDR (0x1E3C) |
| 310 | #define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78) |
| 311 | #define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C) |
| 312 | |
| 313 | #define LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE (0x400000) |
| 314 | #define LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE (0x402000) |
Eran Harary | dcab8ec | 2014-10-19 12:20:14 +0200 | [diff] [blame] | 315 | #define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000) |
| 316 | #define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400) |
Eran Harary | 189fa2f | 2014-01-23 16:26:32 +0200 | [diff] [blame] | 317 | |
Emmanuel Grumbach | 7b445f3 | 2014-03-20 11:08:19 +0200 | [diff] [blame] | 318 | /* Rx FIFO */ |
| 319 | #define RXF_SIZE_ADDR (0xa00c88) |
Liad Kaufman | 04fd2c2 | 2014-12-15 17:54:16 +0200 | [diff] [blame] | 320 | #define RXF_RD_D_SPACE (0xa00c40) |
| 321 | #define RXF_RD_WR_PTR (0xa00c50) |
| 322 | #define RXF_RD_RD_PTR (0xa00c54) |
| 323 | #define RXF_RD_FENCE_PTR (0xa00c4c) |
| 324 | #define RXF_SET_FENCE_MODE (0xa00c14) |
| 325 | #define RXF_LD_WR2FENCE (0xa00c1c) |
| 326 | #define RXF_FIFO_RD_FENCE_INC (0xa00c68) |
Emmanuel Grumbach | 7b445f3 | 2014-03-20 11:08:19 +0200 | [diff] [blame] | 327 | #define RXF_SIZE_BYTE_CND_POS (7) |
| 328 | #define RXF_SIZE_BYTE_CNT_MSK (0x3ff << RXF_SIZE_BYTE_CND_POS) |
Liad Kaufman | 04fd2c2 | 2014-12-15 17:54:16 +0200 | [diff] [blame] | 329 | #define RXF_DIFF_FROM_PREV (0x200) |
Emmanuel Grumbach | 7b445f3 | 2014-03-20 11:08:19 +0200 | [diff] [blame] | 330 | |
| 331 | #define RXF_LD_FENCE_OFFSET_ADDR (0xa00c10) |
| 332 | #define RXF_FIFO_RD_FENCE_ADDR (0xa00c0c) |
| 333 | |
Liad Kaufman | 04fd2c2 | 2014-12-15 17:54:16 +0200 | [diff] [blame] | 334 | /* Tx FIFO */ |
| 335 | #define TXF_FIFO_ITEM_CNT (0xa00438) |
| 336 | #define TXF_WR_PTR (0xa00414) |
| 337 | #define TXF_RD_PTR (0xa00410) |
| 338 | #define TXF_FENCE_PTR (0xa00418) |
| 339 | #define TXF_LOCK_FENCE (0xa00424) |
| 340 | #define TXF_LARC_NUM (0xa0043c) |
| 341 | #define TXF_READ_MODIFY_DATA (0xa00448) |
| 342 | #define TXF_READ_MODIFY_ADDR (0xa0044c) |
| 343 | |
Emmanuel Grumbach | c2d2020 | 2014-06-01 08:05:52 +0300 | [diff] [blame] | 344 | /* FW monitor */ |
Emmanuel Grumbach | 8c23f95 | 2014-12-04 10:07:47 +0200 | [diff] [blame] | 345 | #define MON_BUFF_SAMPLE_CTL (0xa03c00) |
Emmanuel Grumbach | c2d2020 | 2014-06-01 08:05:52 +0300 | [diff] [blame] | 346 | #define MON_BUFF_BASE_ADDR (0xa03c3c) |
| 347 | #define MON_BUFF_END_ADDR (0xa03c40) |
| 348 | #define MON_BUFF_WRPTR (0xa03c44) |
| 349 | #define MON_BUFF_CYCLE_CNT (0xa03c48) |
| 350 | |
Emmanuel Grumbach | 8c23f95 | 2014-12-04 10:07:47 +0200 | [diff] [blame] | 351 | #define DBGC_IN_SAMPLE (0xa03c00) |
Emmanuel Grumbach | 8c23f95 | 2014-12-04 10:07:47 +0200 | [diff] [blame] | 352 | |
Eran Harary | 8ba2d7a | 2015-02-08 11:41:43 +0200 | [diff] [blame] | 353 | /* enable the ID buf for read */ |
| 354 | #define WFPM_PS_CTL_CLR 0xA0300C |
| 355 | #define WFMP_MAC_ADDR_0 0xA03080 |
| 356 | #define WFMP_MAC_ADDR_1 0xA03084 |
| 357 | #define LMPM_PMG_EN 0xA01CEC |
| 358 | #define RADIO_REG_SYS_MANUAL_DFT_0 0xAD4078 |
| 359 | #define RFIC_REG_RD 0xAD0470 |
Eran Harary | 7a42baa | 2015-02-25 14:24:51 +0200 | [diff] [blame] | 360 | #define WFPM_CTRL_REG 0xA03030 |
| 361 | enum { |
| 362 | ENABLE_WFPM = BIT(31), |
Eran Harary | 16bc119 | 2015-03-03 13:53:28 +0200 | [diff] [blame] | 363 | WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK = 0x80000000, |
Eran Harary | 7a42baa | 2015-02-25 14:24:51 +0200 | [diff] [blame] | 364 | }; |
| 365 | |
| 366 | #define AUX_MISC_REG 0xA200B0 |
| 367 | enum { |
| 368 | HW_STEP_LOCATION_BITS = 24, |
| 369 | }; |
Eran Harary | 8ba2d7a | 2015-02-08 11:41:43 +0200 | [diff] [blame] | 370 | |
Eran Harary | 16bc119 | 2015-03-03 13:53:28 +0200 | [diff] [blame] | 371 | #define AUX_MISC_MASTER1_EN 0xA20818 |
| 372 | enum aux_misc_master1_en { |
| 373 | AUX_MISC_MASTER1_EN_SBE_MSK = 0x1, |
| 374 | }; |
| 375 | |
| 376 | #define AUX_MISC_MASTER1_SMPHR_STATUS 0xA20800 |
| 377 | #define RSA_ENABLE 0xA24B08 |
| 378 | #define PREG_AUX_BUS_WPROT_0 0xA04CC0 |
| 379 | |
Arik Nemtsov | fe45773 | 2014-11-17 15:46:37 +0200 | [diff] [blame] | 380 | /* FW chicken bits */ |
| 381 | #define LMPM_CHICK 0xA01FF8 |
| 382 | enum { |
| 383 | LMPM_CHICK_EXTENDED_ADDR_SPACE = BIT(0), |
| 384 | }; |
| 385 | |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 386 | #endif /* __iwl_prph_h__ */ |