blob: 801afaf2d449655bcc6acc45dac5d8655a850008 [file] [log] [blame]
Lee Jones6e877fe2014-07-09 12:41:12 +01001/*
2 * Copyright (C) 2014 STMicroelectronics – All Rights Reserved
3 *
4 * STMicroelectronics PHY driver MiPHY365 (for SoC STiH416).
5 *
6 * Authors: Alexandre Torgue <alexandre.torgue@st.com>
7 * Lee Jones <lee.jones@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2, as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/platform_device.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_platform.h>
Lee Jones7ebdb522014-07-09 12:41:13 +010021#include <linux/of_address.h>
Lee Jones6e877fe2014-07-09 12:41:12 +010022#include <linux/clk.h>
23#include <linux/phy/phy.h>
24#include <linux/delay.h>
25#include <linux/mfd/syscon.h>
26#include <linux/regmap.h>
27
28#include <dt-bindings/phy/phy-miphy365x.h>
29
30#define HFC_TIMEOUT 100
31
Lee Jones7ebdb522014-07-09 12:41:13 +010032#define SYSCFG_SELECT_SATA_MASK BIT(1)
33#define SYSCFG_SELECT_SATA_POS 1
Lee Jones6e877fe2014-07-09 12:41:12 +010034
35/* MiPHY365x register definitions */
36#define RESET_REG 0x00
37#define RST_PLL BIT(1)
38#define RST_PLL_CAL BIT(2)
39#define RST_RX BIT(4)
40#define RST_MACRO BIT(7)
41
42#define STATUS_REG 0x01
43#define IDLL_RDY BIT(0)
44#define PLL_RDY BIT(1)
45#define DES_BIT_LOCK BIT(2)
46#define DES_SYMBOL_LOCK BIT(3)
47
48#define CTRL_REG 0x02
49#define TERM_EN BIT(0)
50#define PCI_EN BIT(2)
51#define DES_BIT_LOCK_EN BIT(3)
52#define TX_POL BIT(5)
53
54#define INT_CTRL_REG 0x03
55
56#define BOUNDARY1_REG 0x10
57#define SPDSEL_SEL BIT(0)
58
59#define BOUNDARY3_REG 0x12
60#define TX_SPDSEL_GEN1_VAL 0
61#define TX_SPDSEL_GEN2_VAL 0x01
62#define TX_SPDSEL_GEN3_VAL 0x02
63#define RX_SPDSEL_GEN1_VAL 0
64#define RX_SPDSEL_GEN2_VAL (0x01 << 3)
65#define RX_SPDSEL_GEN3_VAL (0x02 << 3)
66
67#define PCIE_REG 0x16
68
69#define BUF_SEL_REG 0x20
70#define CONF_GEN_SEL_GEN3 0x02
71#define CONF_GEN_SEL_GEN2 0x01
72#define PD_VDDTFILTER BIT(4)
73
74#define TXBUF1_REG 0x21
75#define SWING_VAL 0x04
76#define SWING_VAL_GEN1 0x03
77#define PREEMPH_VAL (0x3 << 5)
78
79#define TXBUF2_REG 0x22
80#define TXSLEW_VAL 0x2
81#define TXSLEW_VAL_GEN1 0x4
82
83#define RXBUF_OFFSET_CTRL_REG 0x23
84
85#define RXBUF_REG 0x25
86#define SDTHRES_VAL 0x01
87#define EQ_ON3 (0x03 << 4)
88#define EQ_ON1 (0x01 << 4)
89
90#define COMP_CTRL1_REG 0x40
91#define START_COMSR BIT(0)
92#define START_COMZC BIT(1)
93#define COMSR_DONE BIT(2)
94#define COMZC_DONE BIT(3)
95#define COMP_AUTO_LOAD BIT(4)
96
97#define COMP_CTRL2_REG 0x41
98#define COMP_2MHZ_RAT_GEN1 0x1e
99#define COMP_2MHZ_RAT 0xf
100
101#define COMP_CTRL3_REG 0x42
102#define COMSR_COMP_REF 0x33
103
104#define COMP_IDLL_REG 0x47
105#define COMZC_IDLL 0x2a
106
107#define PLL_CTRL1_REG 0x50
108#define PLL_START_CAL BIT(0)
109#define BUF_EN BIT(2)
110#define SYNCHRO_TX BIT(3)
111#define SSC_EN BIT(6)
112#define CONFIG_PLL BIT(7)
113
114#define PLL_CTRL2_REG 0x51
115#define BYPASS_PLL_CAL BIT(1)
116
117#define PLL_RAT_REG 0x52
118
119#define PLL_SSC_STEP_MSB_REG 0x56
120#define PLL_SSC_STEP_MSB_VAL 0x03
121
122#define PLL_SSC_STEP_LSB_REG 0x57
123#define PLL_SSC_STEP_LSB_VAL 0x63
124
125#define PLL_SSC_PER_MSB_REG 0x58
126#define PLL_SSC_PER_MSB_VAL 0
127
128#define PLL_SSC_PER_LSB_REG 0x59
129#define PLL_SSC_PER_LSB_VAL 0xf1
130
131#define IDLL_TEST_REG 0x72
132#define START_CLK_HF BIT(6)
133
134#define DES_BITLOCK_REG 0x86
135#define BIT_LOCK_LEVEL 0x01
136#define BIT_LOCK_CNT_512 (0x03 << 5)
137
Lee Jones6e877fe2014-07-09 12:41:12 +0100138struct miphy365x_phy {
139 struct phy *phy;
140 void __iomem *base;
Lee Jones7ebdb522014-07-09 12:41:13 +0100141 bool pcie_tx_pol_inv;
142 bool sata_tx_pol_inv;
143 u32 sata_gen;
144 u64 ctrlreg;
Lee Jones6e877fe2014-07-09 12:41:12 +0100145 u8 type;
Lee Jones6e877fe2014-07-09 12:41:12 +0100146};
147
148struct miphy365x_dev {
149 struct device *dev;
150 struct regmap *regmap;
151 struct mutex miphy_mutex;
Lee Jones7ebdb522014-07-09 12:41:13 +0100152 struct miphy365x_phy **phys;
Lee Jones6e877fe2014-07-09 12:41:12 +0100153};
154
155/*
156 * These values are represented in Device tree. They are considered to be ABI
157 * and although they can be extended any existing values must not change.
158 */
159enum miphy_sata_gen {
160 SATA_GEN1 = 1,
161 SATA_GEN2,
162 SATA_GEN3
163};
164
165static u8 rx_tx_spd[] = {
Lee Jonesa6cc1b92014-08-28 14:59:50 +0100166 0, /* GEN0 doesn't exist. */
Lee Jones6e877fe2014-07-09 12:41:12 +0100167 TX_SPDSEL_GEN1_VAL | RX_SPDSEL_GEN1_VAL,
168 TX_SPDSEL_GEN2_VAL | RX_SPDSEL_GEN2_VAL,
169 TX_SPDSEL_GEN3_VAL | RX_SPDSEL_GEN3_VAL
170};
171
172/*
173 * This function selects the system configuration,
174 * either two SATA, one SATA and one PCIe, or two PCIe lanes.
175 */
176static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
177 struct miphy365x_dev *miphy_dev)
178{
Lee Jones7ebdb522014-07-09 12:41:13 +0100179 bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
Lee Jones6e877fe2014-07-09 12:41:12 +0100180
Lee Jones7ebdb522014-07-09 12:41:13 +0100181 return regmap_update_bits(miphy_dev->regmap,
182 (unsigned int)miphy_phy->ctrlreg,
183 SYSCFG_SELECT_SATA_MASK,
184 sata << SYSCFG_SELECT_SATA_POS);
Lee Jones6e877fe2014-07-09 12:41:12 +0100185}
186
187static int miphy365x_init_pcie_port(struct miphy365x_phy *miphy_phy,
188 struct miphy365x_dev *miphy_dev)
189{
190 u8 val;
191
192 if (miphy_phy->pcie_tx_pol_inv) {
193 /* Invert Tx polarity and clear pci_txdetect_pol bit */
194 val = TERM_EN | PCI_EN | DES_BIT_LOCK_EN | TX_POL;
195 writeb_relaxed(val, miphy_phy->base + CTRL_REG);
196 writeb_relaxed(0x00, miphy_phy->base + PCIE_REG);
197 }
198
199 return 0;
200}
201
202static inline int miphy365x_hfc_not_rdy(struct miphy365x_phy *miphy_phy,
203 struct miphy365x_dev *miphy_dev)
204{
205 unsigned long timeout = jiffies + msecs_to_jiffies(HFC_TIMEOUT);
206 u8 mask = IDLL_RDY | PLL_RDY;
207 u8 regval;
208
209 do {
210 regval = readb_relaxed(miphy_phy->base + STATUS_REG);
211 if (!(regval & mask))
212 return 0;
213
214 usleep_range(2000, 2500);
215 } while (time_before(jiffies, timeout));
216
217 dev_err(miphy_dev->dev, "HFC ready timeout!\n");
218 return -EBUSY;
219}
220
221static inline int miphy365x_rdy(struct miphy365x_phy *miphy_phy,
222 struct miphy365x_dev *miphy_dev)
223{
224 unsigned long timeout = jiffies + msecs_to_jiffies(HFC_TIMEOUT);
225 u8 mask = IDLL_RDY | PLL_RDY;
226 u8 regval;
227
228 do {
229 regval = readb_relaxed(miphy_phy->base + STATUS_REG);
230 if ((regval & mask) == mask)
231 return 0;
232
233 usleep_range(2000, 2500);
234 } while (time_before(jiffies, timeout));
235
236 dev_err(miphy_dev->dev, "PHY not ready timeout!\n");
237 return -EBUSY;
238}
239
240static inline void miphy365x_set_comp(struct miphy365x_phy *miphy_phy,
241 struct miphy365x_dev *miphy_dev)
242{
243 u8 val, mask;
244
Lee Jones7ebdb522014-07-09 12:41:13 +0100245 if (miphy_phy->sata_gen == SATA_GEN1)
Lee Jones6e877fe2014-07-09 12:41:12 +0100246 writeb_relaxed(COMP_2MHZ_RAT_GEN1,
247 miphy_phy->base + COMP_CTRL2_REG);
248 else
249 writeb_relaxed(COMP_2MHZ_RAT,
250 miphy_phy->base + COMP_CTRL2_REG);
251
Lee Jones7ebdb522014-07-09 12:41:13 +0100252 if (miphy_phy->sata_gen != SATA_GEN3) {
Lee Jones6e877fe2014-07-09 12:41:12 +0100253 writeb_relaxed(COMSR_COMP_REF,
254 miphy_phy->base + COMP_CTRL3_REG);
255 /*
256 * Force VCO current to value defined by address 0x5A
257 * and disable PCIe100Mref bit
258 * Enable auto load compensation for pll_i_bias
259 */
260 writeb_relaxed(BYPASS_PLL_CAL, miphy_phy->base + PLL_CTRL2_REG);
261 writeb_relaxed(COMZC_IDLL, miphy_phy->base + COMP_IDLL_REG);
262 }
263
264 /*
265 * Force restart compensation and enable auto load
266 * for Comzc_Tx, Comzc_Rx and Comsr on macro
267 */
268 val = START_COMSR | START_COMZC | COMP_AUTO_LOAD;
269 writeb_relaxed(val, miphy_phy->base + COMP_CTRL1_REG);
270
271 mask = COMSR_DONE | COMZC_DONE;
272 while ((readb_relaxed(miphy_phy->base + COMP_CTRL1_REG) & mask) != mask)
273 cpu_relax();
274}
275
276static inline void miphy365x_set_ssc(struct miphy365x_phy *miphy_phy,
277 struct miphy365x_dev *miphy_dev)
278{
279 u8 val;
280
281 /*
282 * SSC Settings. SSC will be enabled through Link
283 * SSC Ampl. = 0.4%
284 * SSC Freq = 31KHz
285 */
286 writeb_relaxed(PLL_SSC_STEP_MSB_VAL,
287 miphy_phy->base + PLL_SSC_STEP_MSB_REG);
288 writeb_relaxed(PLL_SSC_STEP_LSB_VAL,
289 miphy_phy->base + PLL_SSC_STEP_LSB_REG);
290 writeb_relaxed(PLL_SSC_PER_MSB_VAL,
291 miphy_phy->base + PLL_SSC_PER_MSB_REG);
292 writeb_relaxed(PLL_SSC_PER_LSB_VAL,
293 miphy_phy->base + PLL_SSC_PER_LSB_REG);
294
295 /* SSC Settings complete */
Lee Jones7ebdb522014-07-09 12:41:13 +0100296 if (miphy_phy->sata_gen == SATA_GEN1) {
Lee Jones6e877fe2014-07-09 12:41:12 +0100297 val = PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL;
298 writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
299 } else {
300 val = SSC_EN | PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL;
301 writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
302 }
303}
304
305static int miphy365x_init_sata_port(struct miphy365x_phy *miphy_phy,
306 struct miphy365x_dev *miphy_dev)
307{
308 int ret;
309 u8 val;
310
311 /*
312 * Force PHY macro reset, PLL calibration reset, PLL reset
313 * and assert Deserializer Reset
314 */
315 val = RST_PLL | RST_PLL_CAL | RST_RX | RST_MACRO;
316 writeb_relaxed(val, miphy_phy->base + RESET_REG);
317
Lee Jones7ebdb522014-07-09 12:41:13 +0100318 if (miphy_phy->sata_tx_pol_inv)
Lee Jones6e877fe2014-07-09 12:41:12 +0100319 writeb_relaxed(TX_POL, miphy_phy->base + CTRL_REG);
320
321 /*
322 * Force macro1 to use rx_lspd, tx_lspd
323 * Force Rx_Clock on first I-DLL phase
324 * Force Des in HP mode on macro, rx_lspd, tx_lspd for Gen2/3
325 */
326 writeb_relaxed(SPDSEL_SEL, miphy_phy->base + BOUNDARY1_REG);
327 writeb_relaxed(START_CLK_HF, miphy_phy->base + IDLL_TEST_REG);
Lee Jones7ebdb522014-07-09 12:41:13 +0100328 val = rx_tx_spd[miphy_phy->sata_gen];
Lee Jones6e877fe2014-07-09 12:41:12 +0100329 writeb_relaxed(val, miphy_phy->base + BOUNDARY3_REG);
330
331 /* Wait for HFC_READY = 0 */
332 ret = miphy365x_hfc_not_rdy(miphy_phy, miphy_dev);
333 if (ret)
334 return ret;
335
336 /* Compensation Recalibration */
337 miphy365x_set_comp(miphy_phy, miphy_dev);
338
Lee Jones7ebdb522014-07-09 12:41:13 +0100339 switch (miphy_phy->sata_gen) {
Lee Jones6e877fe2014-07-09 12:41:12 +0100340 case SATA_GEN3:
341 /*
342 * TX Swing target 550-600mv peak to peak diff
343 * Tx Slew target 90-110ps rising/falling time
344 * Rx Eq ON3, Sigdet threshold SDTH1
345 */
346 val = PD_VDDTFILTER | CONF_GEN_SEL_GEN3;
347 writeb_relaxed(val, miphy_phy->base + BUF_SEL_REG);
348 val = SWING_VAL | PREEMPH_VAL;
349 writeb_relaxed(val, miphy_phy->base + TXBUF1_REG);
350 writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);
351 writeb_relaxed(0x00, miphy_phy->base + RXBUF_OFFSET_CTRL_REG);
352 val = SDTHRES_VAL | EQ_ON3;
353 writeb_relaxed(val, miphy_phy->base + RXBUF_REG);
354 break;
355 case SATA_GEN2:
356 /*
357 * conf gen sel=0x1 to program Gen2 banked registers
358 * VDDT filter ON
359 * Tx Swing target 550-600mV peak-to-peak diff
360 * Tx Slew target 90-110 ps rising/falling time
361 * RX Equalization ON1, Sigdet threshold SDTH1
362 */
363 writeb_relaxed(CONF_GEN_SEL_GEN2,
364 miphy_phy->base + BUF_SEL_REG);
365 writeb_relaxed(SWING_VAL, miphy_phy->base + TXBUF1_REG);
366 writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);
367 val = SDTHRES_VAL | EQ_ON1;
368 writeb_relaxed(val, miphy_phy->base + RXBUF_REG);
369 break;
370 case SATA_GEN1:
371 /*
372 * conf gen sel = 00b to program Gen1 banked registers
373 * VDDT filter ON
374 * Tx Swing target 500-550mV peak-to-peak diff
375 * Tx Slew target120-140 ps rising/falling time
376 */
377 writeb_relaxed(PD_VDDTFILTER, miphy_phy->base + BUF_SEL_REG);
378 writeb_relaxed(SWING_VAL_GEN1, miphy_phy->base + TXBUF1_REG);
379 writeb_relaxed(TXSLEW_VAL_GEN1, miphy_phy->base + TXBUF2_REG);
380 break;
381 default:
382 break;
383 }
384
385 /* Force Macro1 in partial mode & release pll cal reset */
386 writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
387 usleep_range(100, 150);
388
389 miphy365x_set_ssc(miphy_phy, miphy_dev);
390
391 /* Wait for phy_ready */
392 ret = miphy365x_rdy(miphy_phy, miphy_dev);
393 if (ret)
394 return ret;
395
396 /*
397 * Enable macro1 to use rx_lspd & tx_lspd
398 * Release Rx_Clock on first I-DLL phase on macro1
399 * Assert deserializer reset
400 * des_bit_lock_en is set
401 * bit lock detection strength
402 * Deassert deserializer reset
403 */
404 writeb_relaxed(0x00, miphy_phy->base + BOUNDARY1_REG);
405 writeb_relaxed(0x00, miphy_phy->base + IDLL_TEST_REG);
406 writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
Lee Jones7ebdb522014-07-09 12:41:13 +0100407 val = miphy_phy->sata_tx_pol_inv ?
Lee Jones6e877fe2014-07-09 12:41:12 +0100408 (TX_POL | DES_BIT_LOCK_EN) : DES_BIT_LOCK_EN;
409 writeb_relaxed(val, miphy_phy->base + CTRL_REG);
410
411 val = BIT_LOCK_CNT_512 | BIT_LOCK_LEVEL;
412 writeb_relaxed(val, miphy_phy->base + DES_BITLOCK_REG);
413 writeb_relaxed(0x00, miphy_phy->base + RESET_REG);
414
415 return 0;
416}
417
418static int miphy365x_init(struct phy *phy)
419{
420 struct miphy365x_phy *miphy_phy = phy_get_drvdata(phy);
421 struct miphy365x_dev *miphy_dev = dev_get_drvdata(phy->dev.parent);
422 int ret = 0;
423
424 mutex_lock(&miphy_dev->miphy_mutex);
425
426 ret = miphy365x_set_path(miphy_phy, miphy_dev);
427 if (ret) {
428 mutex_unlock(&miphy_dev->miphy_mutex);
429 return ret;
430 }
431
432 /* Initialise Miphy for PCIe or SATA */
433 if (miphy_phy->type == MIPHY_TYPE_PCIE)
434 ret = miphy365x_init_pcie_port(miphy_phy, miphy_dev);
435 else
436 ret = miphy365x_init_sata_port(miphy_phy, miphy_dev);
437
438 mutex_unlock(&miphy_dev->miphy_mutex);
439
440 return ret;
441}
442
Lee Jones7ebdb522014-07-09 12:41:13 +0100443int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
444 int index)
445{
446 struct device_node *phynode = miphy_phy->phy->dev.of_node;
447 const char *name;
448 const __be32 *taddr;
449 int type = miphy_phy->type;
450 int ret;
451
452 ret = of_property_read_string_index(phynode, "reg-names", index, &name);
453 if (ret) {
454 dev_err(dev, "no reg-names property not found\n");
455 return ret;
456 }
457
458 if (!strncmp(name, "syscfg", 6)) {
459 taddr = of_get_address(phynode, index, NULL, NULL);
460 if (!taddr) {
461 dev_err(dev, "failed to fetch syscfg address\n");
462 return -EINVAL;
463 }
464
465 miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
466 if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
467 dev_err(dev, "failed to translate syscfg address\n");
468 return -EINVAL;
469 }
470
471 return 0;
472 }
473
474 if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
475 (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
476 return 0;
477
478 miphy_phy->base = of_iomap(phynode, index);
479 if (!miphy_phy->base) {
480 dev_err(dev, "Failed to map %s\n", phynode->full_name);
481 return -EINVAL;
482 }
483
484 return 0;
485}
486
Lee Jones6e877fe2014-07-09 12:41:12 +0100487static struct phy *miphy365x_xlate(struct device *dev,
488 struct of_phandle_args *args)
489{
Lee Jones7ebdb522014-07-09 12:41:13 +0100490 struct miphy365x_dev *miphy_dev = dev_get_drvdata(dev);
491 struct miphy365x_phy *miphy_phy = NULL;
492 struct device_node *phynode = args->np;
493 int ret, index;
Lee Jones6e877fe2014-07-09 12:41:12 +0100494
Lee Jones7ebdb522014-07-09 12:41:13 +0100495 if (!of_device_is_available(phynode)) {
496 dev_warn(dev, "Requested PHY is disabled\n");
497 return ERR_PTR(-ENODEV);
498 }
499
500 if (args->args_count != 1) {
Lee Jones6e877fe2014-07-09 12:41:12 +0100501 dev_err(dev, "Invalid number of cells in 'phy' property\n");
502 return ERR_PTR(-EINVAL);
503 }
504
Lee Jones7ebdb522014-07-09 12:41:13 +0100505 for (index = 0; index < of_get_child_count(dev->of_node); index++)
506 if (phynode == miphy_dev->phys[index]->phy->dev.of_node) {
507 miphy_phy = miphy_dev->phys[index];
508 break;
509 }
510
511 if (!miphy_phy) {
512 dev_err(dev, "Failed to find appropriate phy\n");
Lee Jones6e877fe2014-07-09 12:41:12 +0100513 return ERR_PTR(-EINVAL);
514 }
515
Lee Jones7ebdb522014-07-09 12:41:13 +0100516 miphy_phy->type = args->args[0];
Lee Jones6e877fe2014-07-09 12:41:12 +0100517
Lee Jones7ebdb522014-07-09 12:41:13 +0100518 if (!(miphy_phy->type == MIPHY_TYPE_SATA ||
519 miphy_phy->type == MIPHY_TYPE_PCIE)) {
520 dev_err(dev, "Unsupported device type: %d\n", miphy_phy->type);
Lee Jones6e877fe2014-07-09 12:41:12 +0100521 return ERR_PTR(-EINVAL);
522 }
523
Lee Jones7ebdb522014-07-09 12:41:13 +0100524 /* Each port handles SATA and PCIE - third entry is always sysconf. */
525 for (index = 0; index < 3; index++) {
526 ret = miphy365x_get_addr(dev, miphy_phy, index);
527 if (ret < 0)
528 return ERR_PTR(ret);
529 }
Lee Jones6e877fe2014-07-09 12:41:12 +0100530
Lee Jones7ebdb522014-07-09 12:41:13 +0100531 return miphy_phy->phy;
Lee Jones6e877fe2014-07-09 12:41:12 +0100532}
533
534static struct phy_ops miphy365x_ops = {
535 .init = miphy365x_init,
536 .owner = THIS_MODULE,
537};
538
Lee Jones7ebdb522014-07-09 12:41:13 +0100539static int miphy365x_of_probe(struct device_node *phynode,
540 struct miphy365x_phy *miphy_phy)
Lee Jones6e877fe2014-07-09 12:41:12 +0100541{
Lee Jones7ebdb522014-07-09 12:41:13 +0100542 of_property_read_u32(phynode, "st,sata-gen", &miphy_phy->sata_gen);
543 if (!miphy_phy->sata_gen)
544 miphy_phy->sata_gen = SATA_GEN1;
Lee Jones6e877fe2014-07-09 12:41:12 +0100545
Lee Jones7ebdb522014-07-09 12:41:13 +0100546 miphy_phy->pcie_tx_pol_inv =
547 of_property_read_bool(phynode, "st,pcie-tx-pol-inv");
Lee Jones6e877fe2014-07-09 12:41:12 +0100548
Lee Jones7ebdb522014-07-09 12:41:13 +0100549 miphy_phy->sata_tx_pol_inv =
550 of_property_read_bool(phynode, "st,sata-tx-pol-inv");
Lee Jones6e877fe2014-07-09 12:41:12 +0100551
552 return 0;
553}
554
555static int miphy365x_probe(struct platform_device *pdev)
556{
Lee Jones7ebdb522014-07-09 12:41:13 +0100557 struct device_node *child, *np = pdev->dev.of_node;
558 struct miphy365x_dev *miphy_dev;
Lee Jones6e877fe2014-07-09 12:41:12 +0100559 struct phy_provider *provider;
Lee Jones7ebdb522014-07-09 12:41:13 +0100560 struct phy *phy;
561 int chancount, port = 0;
Lee Jones6e877fe2014-07-09 12:41:12 +0100562 int ret;
563
Lee Jones7ebdb522014-07-09 12:41:13 +0100564 miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);
565 if (!miphy_dev)
Lee Jones6e877fe2014-07-09 12:41:12 +0100566 return -ENOMEM;
567
Lee Jones7ebdb522014-07-09 12:41:13 +0100568 chancount = of_get_child_count(np);
569 miphy_dev->phys = devm_kzalloc(&pdev->dev, sizeof(phy) * chancount,
570 GFP_KERNEL);
571 if (!miphy_dev->phys)
572 return -ENOMEM;
Lee Jones6e877fe2014-07-09 12:41:12 +0100573
Lee Jones7ebdb522014-07-09 12:41:13 +0100574 miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
575 if (IS_ERR(miphy_dev->regmap)) {
576 dev_err(miphy_dev->dev, "No syscfg phandle specified\n");
577 return PTR_ERR(miphy_dev->regmap);
578 }
Lee Jones6e877fe2014-07-09 12:41:12 +0100579
Lee Jones7ebdb522014-07-09 12:41:13 +0100580 miphy_dev->dev = &pdev->dev;
Lee Jones6e877fe2014-07-09 12:41:12 +0100581
Lee Jones7ebdb522014-07-09 12:41:13 +0100582 dev_set_drvdata(&pdev->dev, miphy_dev);
Lee Jones6e877fe2014-07-09 12:41:12 +0100583
Lee Jones7ebdb522014-07-09 12:41:13 +0100584 mutex_init(&miphy_dev->miphy_mutex);
Lee Jones6e877fe2014-07-09 12:41:12 +0100585
Lee Jones7ebdb522014-07-09 12:41:13 +0100586 for_each_child_of_node(np, child) {
587 struct miphy365x_phy *miphy_phy;
588
589 miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),
590 GFP_KERNEL);
591 if (!miphy_phy)
592 return -ENOMEM;
593
594 miphy_dev->phys[port] = miphy_phy;
595
596 phy = devm_phy_create(&pdev->dev, child, &miphy365x_ops, NULL);
Lee Jones6e877fe2014-07-09 12:41:12 +0100597 if (IS_ERR(phy)) {
Lee Jones7ebdb522014-07-09 12:41:13 +0100598 dev_err(&pdev->dev, "failed to create PHY\n");
Lee Jones6e877fe2014-07-09 12:41:12 +0100599 return PTR_ERR(phy);
600 }
601
Lee Jones7ebdb522014-07-09 12:41:13 +0100602 miphy_dev->phys[port]->phy = phy;
Lee Jones6e877fe2014-07-09 12:41:12 +0100603
Lee Jones7ebdb522014-07-09 12:41:13 +0100604 ret = miphy365x_of_probe(child, miphy_phy);
Lee Jones6e877fe2014-07-09 12:41:12 +0100605 if (ret)
606 return ret;
607
Lee Jones7ebdb522014-07-09 12:41:13 +0100608 phy_set_drvdata(phy, miphy_dev->phys[port]);
609 port++;
Lee Jones6e877fe2014-07-09 12:41:12 +0100610 }
611
Lee Jones7ebdb522014-07-09 12:41:13 +0100612 provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
Lee Jones6e877fe2014-07-09 12:41:12 +0100613 if (IS_ERR(provider))
614 return PTR_ERR(provider);
615
616 return 0;
617}
618
619static const struct of_device_id miphy365x_of_match[] = {
620 { .compatible = "st,miphy365x-phy", },
621 { },
622};
623MODULE_DEVICE_TABLE(of, miphy365x_of_match);
624
625static struct platform_driver miphy365x_driver = {
626 .probe = miphy365x_probe,
627 .driver = {
628 .name = "miphy365x-phy",
Lee Jones6e877fe2014-07-09 12:41:12 +0100629 .of_match_table = miphy365x_of_match,
630 }
631};
632module_platform_driver(miphy365x_driver);
633
634MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
635MODULE_DESCRIPTION("STMicroelectronics miphy365x driver");
636MODULE_LICENSE("GPL v2");